From 7630884c55c77baf3cb399b67146f1f5bd5b18df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= Date: Tue, 6 Jan 2026 20:01:25 +0100 Subject: [PATCH 01/20] Avoid `unsafe fn` in remaining x86 tests --- .../stdarch/crates/core_arch/src/x86/avx.rs | 231 +++-- .../stdarch/crates/core_arch/src/x86/avx2.rs | 374 ++++--- .../crates/core_arch/src/x86/avx512bf16.rs | 279 ++--- .../crates/core_arch/src/x86/avx512bw.rs | 314 +++--- .../crates/core_arch/src/x86/avx512dq.rs | 52 +- .../crates/core_arch/src/x86/avx512f.rs | 966 +++++++++++------- .../crates/core_arch/src/x86/avx512fp16.rs | 99 +- .../crates/core_arch/src/x86/avx512vbmi2.rs | 124 ++- .../crates/core_arch/src/x86/avxneconvert.rs | 56 +- .../stdarch/crates/core_arch/src/x86/f16c.rs | 2 +- .../stdarch/crates/core_arch/src/x86/fxsr.rs | 10 +- .../stdarch/crates/core_arch/src/x86/gfni.rs | 210 ++-- .../stdarch/crates/core_arch/src/x86/kl.rs | 88 +- .../stdarch/crates/core_arch/src/x86/rtm.rs | 34 +- .../stdarch/crates/core_arch/src/x86/sse.rs | 60 +- .../stdarch/crates/core_arch/src/x86/sse2.rs | 178 ++-- .../stdarch/crates/core_arch/src/x86/sse3.rs | 8 +- .../stdarch/crates/core_arch/src/x86/sse41.rs | 12 +- .../stdarch/crates/core_arch/src/x86/sse42.rs | 3 +- .../stdarch/crates/core_arch/src/x86/sse4a.rs | 12 +- .../stdarch/crates/core_arch/src/x86/xsave.rs | 36 +- .../crates/core_arch/src/x86_64/amx.rs | 858 ++++++++-------- .../crates/core_arch/src/x86_64/avx512f.rs | 659 +++++++----- .../crates/core_arch/src/x86_64/fxsr.rs | 10 +- .../crates/core_arch/src/x86_64/sse2.rs | 6 +- .../crates/core_arch/src/x86_64/xsave.rs | 30 +- 26 files changed, 2693 insertions(+), 2018 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs index e0e01ae6d0346..c406d537bc1cb 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx.rs @@ -3369,6 +3369,7 @@ unsafe extern "C" { #[cfg(test)] mod tests { use crate::core_arch::assert_eq_const as assert_eq; + use crate::core_arch::simd::*; use crate::hint::black_box; use crate::ptr; use stdarch_test::simd_test; @@ -3464,7 +3465,7 @@ mod tests { } #[simd_test(enable = "avx")] - unsafe fn test_mm256_max_pd() { + fn test_mm256_max_pd() { let a = _mm256_setr_pd(1., 4., 5., 8.); let b = _mm256_setr_pd(2., 3., 6., 7.); let r = _mm256_max_pd(a, b); @@ -3474,23 +3475,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0)); let x = _mm256_max_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0)); - let wu: [u64; 4] = transmute(w); - let xu: [u64; 4] = transmute(x); - assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]); - assert_eq!(xu, [0u64; 4]); + let wu = _mm256_castpd_si256(w).as_u64x4(); + let xu = _mm256_castpd_si256(x).as_u64x4(); + assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64)); + assert_eq!(xu, u64x4::splat(0u64)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_max_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0)); let z = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN)); - let yf: [f64; 4] = transmute(y); - let zf: [f64; 4] = transmute(z); - assert_eq!(yf, [0.0; 4]); + assert_eq_m256d(y, _mm256_set1_pd(0.0)); + let zf = *z.as_f64x4().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_max_ps() { + fn test_mm256_max_ps() { let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.); let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.); let r = _mm256_max_ps(a, b); @@ -3500,23 +3500,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0)); let x = _mm256_max_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0)); - let wu: [u32; 8] = transmute(w); - let xu: [u32; 8] = transmute(x); - assert_eq!(wu, [0x8000_0000u32; 8]); - assert_eq!(xu, [0u32; 8]); + let wu = _mm256_castps_si256(w).as_u32x8(); + let xu = _mm256_castps_si256(x).as_u32x8(); + assert_eq!(wu, u32x8::splat(0x8000_0000u32)); + assert_eq!(xu, u32x8::splat(0u32)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_max_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0)); let z = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN)); - let yf: [f32; 8] = transmute(y); - let zf: [f32; 8] = transmute(z); - assert_eq!(yf, [0.0; 8]); + assert_eq_m256(y, _mm256_set1_ps(0.0)); + let zf = *z.as_f32x8().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_min_pd() { + fn test_mm256_min_pd() { let a = _mm256_setr_pd(1., 4., 5., 8.); let b = _mm256_setr_pd(2., 3., 6., 7.); let r = _mm256_min_pd(a, b); @@ -3526,23 +3525,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0)); let x = _mm256_min_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0)); - let wu: [u64; 4] = transmute(w); - let xu: [u64; 4] = transmute(x); - assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]); - assert_eq!(xu, [0u64; 4]); + let wu = _mm256_castpd_si256(w).as_u64x4(); + let xu = _mm256_castpd_si256(x).as_u64x4(); + assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64)); + assert_eq!(xu, u64x4::splat(0u64)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_min_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0)); let z = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN)); - let yf: [f64; 4] = transmute(y); - let zf: [f64; 4] = transmute(z); - assert_eq!(yf, [0.0; 4]); + assert_eq_m256d(y, _mm256_set1_pd(0.0)); + let zf = *z.as_f64x4().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_min_ps() { + fn test_mm256_min_ps() { let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.); let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.); let r = _mm256_min_ps(a, b); @@ -3552,18 +3550,17 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0)); let x = _mm256_min_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0)); - let wu: [u32; 8] = transmute(w); - let xu: [u32; 8] = transmute(x); - assert_eq!(wu, [0x8000_0000u32; 8]); - assert_eq!(xu, [0u32; 8]); + let wu = _mm256_castps_si256(w).as_u32x8(); + let xu = _mm256_castps_si256(x).as_u32x8(); + assert_eq!(wu, u32x8::splat(0x8000_0000u32)); + assert_eq!(xu, u32x8::splat(0u32)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_min_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0)); let z = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN)); - let yf: [f32; 8] = transmute(y); - let zf: [f32; 8] = transmute(z); - assert_eq!(yf, [0.0; 8]); + assert_eq_m256(y, _mm256_set1_ps(0.0)); + let zf = *z.as_f32x8().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } @@ -4247,183 +4244,203 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_pd() { + const fn test_mm256_load_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let p = ptr::addr_of!(a) as *const f64; - let r = _mm256_load_pd(p); + let r = unsafe { _mm256_load_pd(p) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_pd() { + const fn test_mm256_store_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut r = _mm256_undefined_pd(); - _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a); + unsafe { + _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a); + } assert_eq_m256d(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_ps() { + const fn test_mm256_load_ps() { let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); let p = ptr::addr_of!(a) as *const f32; - let r = _mm256_load_ps(p); + let r = unsafe { _mm256_load_ps(p) }; let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_ps() { + const fn test_mm256_store_ps() { let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); let mut r = _mm256_undefined_ps(); - _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a); + unsafe { + _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a); + } assert_eq_m256(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_pd() { + const fn test_mm256_loadu_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); - let r = _mm256_loadu_pd(black_box(p)); + let r = unsafe { _mm256_loadu_pd(black_box(p)) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_pd() { + const fn test_mm256_storeu_pd() { let a = _mm256_set1_pd(9.); let mut r = _mm256_undefined_pd(); - _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a); + unsafe { + _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a); + } assert_eq_m256d(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_ps() { + const fn test_mm256_loadu_ps() { let a = &[4., 3., 2., 5., 8., 9., 64., 50.]; let p = a.as_ptr(); - let r = _mm256_loadu_ps(black_box(p)); + let r = unsafe { _mm256_loadu_ps(black_box(p)) }; let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_ps() { + const fn test_mm256_storeu_ps() { let a = _mm256_set1_ps(9.); let mut r = _mm256_undefined_ps(); - _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a); + unsafe { + _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a); + } assert_eq_m256(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_si256() { + const fn test_mm256_load_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let p = ptr::addr_of!(a); - let r = _mm256_load_si256(p); + let r = unsafe { _mm256_load_si256(p) }; let e = _mm256_setr_epi64x(1, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_si256() { + const fn test_mm256_store_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); - _mm256_store_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_store_si256(ptr::addr_of_mut!(r), a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_si256() { + const fn test_mm256_loadu_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let p = ptr::addr_of!(a); - let r = _mm256_loadu_si256(black_box(p)); + let r = unsafe { _mm256_loadu_si256(black_box(p)) }; let e = _mm256_setr_epi64x(1, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_si256() { + const fn test_mm256_storeu_si256() { let a = _mm256_set1_epi8(9); let mut r = _mm256_undefined_si256(); - _mm256_storeu_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_storeu_si256(ptr::addr_of_mut!(r), a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskload_pd() { + const fn test_mm256_maskload_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let mask = _mm256_setr_epi64x(0, !0, 0, !0); - let r = _mm256_maskload_pd(black_box(p), mask); + let r = unsafe { _mm256_maskload_pd(black_box(p), mask) }; let e = _mm256_setr_pd(0., 2., 0., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskstore_pd() { + const fn test_mm256_maskstore_pd() { let mut r = _mm256_set1_pd(0.); let mask = _mm256_setr_epi64x(0, !0, 0, !0); let a = _mm256_setr_pd(1., 2., 3., 4.); - _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + unsafe { + _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + } let e = _mm256_setr_pd(0., 2., 0., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskload_pd() { + const fn test_mm_maskload_pd() { let a = &[1.0f64, 2.]; let p = a.as_ptr(); let mask = _mm_setr_epi64x(0, !0); - let r = _mm_maskload_pd(black_box(p), mask); + let r = unsafe { _mm_maskload_pd(black_box(p), mask) }; let e = _mm_setr_pd(0., 2.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskstore_pd() { + const fn test_mm_maskstore_pd() { let mut r = _mm_set1_pd(0.); let mask = _mm_setr_epi64x(0, !0); let a = _mm_setr_pd(1., 2.); - _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + unsafe { + _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + } let e = _mm_setr_pd(0., 2.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskload_ps() { + const fn test_mm256_maskload_ps() { let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0); - let r = _mm256_maskload_ps(black_box(p), mask); + let r = unsafe { _mm256_maskload_ps(black_box(p), mask) }; let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskstore_ps() { + const fn test_mm256_maskstore_ps() { let mut r = _mm256_set1_ps(0.); let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0); let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); - _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + unsafe { + _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + } let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskload_ps() { + const fn test_mm_maskload_ps() { let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let mask = _mm_setr_epi32(0, !0, 0, !0); - let r = _mm_maskload_ps(black_box(p), mask); + let r = unsafe { _mm_maskload_ps(black_box(p), mask) }; let e = _mm_setr_ps(0., 2., 0., 4.); assert_eq_m128(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskstore_ps() { + const fn test_mm_maskstore_ps() { let mut r = _mm_set1_ps(0.); let mask = _mm_setr_epi32(0, !0, 0, !0); let a = _mm_setr_ps(1., 2., 3., 4.); - _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + unsafe { + _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + } let e = _mm_setr_ps(0., 2., 0., 4.); assert_eq_m128(r, e); } @@ -4453,7 +4470,7 @@ mod tests { } #[simd_test(enable = "avx")] - unsafe fn test_mm256_lddqu_si256() { + fn test_mm256_lddqu_si256() { #[rustfmt::skip] let a = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -4462,7 +4479,7 @@ mod tests { 25, 26, 27, 28, 29, 30, 31, 32, ); let p = ptr::addr_of!(a); - let r = _mm256_lddqu_si256(black_box(p)); + let r = unsafe { _mm256_lddqu_si256(black_box(p)) }; #[rustfmt::skip] let e = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -4475,17 +4492,19 @@ mod tests { #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_si256() { + fn test_mm256_stream_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); - _mm256_stream_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_stream_si256(ptr::addr_of_mut!(r), a); + } _mm_sfence(); assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_pd() { + fn test_mm256_stream_pd() { #[repr(align(32))] struct Memory { pub data: [f64; 4], @@ -4493,7 +4512,9 @@ mod tests { let a = _mm256_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 4] }; - _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..4 { assert_eq!(mem.data[i], get_m256d(a, i)); @@ -4502,7 +4523,7 @@ mod tests { #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_ps() { + fn test_mm256_stream_ps() { #[repr(align(32))] struct Memory { pub data: [f32; 8], @@ -4510,7 +4531,9 @@ mod tests { let a = _mm256_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 8] }; - _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m256(a, i)); @@ -5147,29 +5170,29 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128() { + const fn test_mm256_loadu2_m128() { let hi = &[5., 6., 7., 8.]; let hiaddr = hi.as_ptr(); let lo = &[1., 2., 3., 4.]; let loaddr = lo.as_ptr(); - let r = _mm256_loadu2_m128(hiaddr, loaddr); + let r = unsafe { _mm256_loadu2_m128(hiaddr, loaddr) }; let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128d() { + const fn test_mm256_loadu2_m128d() { let hi = &[3., 4.]; let hiaddr = hi.as_ptr(); let lo = &[1., 2.]; let loaddr = lo.as_ptr(); - let r = _mm256_loadu2_m128d(hiaddr, loaddr); + let r = unsafe { _mm256_loadu2_m128d(hiaddr, loaddr) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128i() { + const fn test_mm256_loadu2_m128i() { #[rustfmt::skip] let hi = _mm_setr_epi8( 17, 18, 19, 20, 21, 22, 23, 24, @@ -5180,7 +5203,9 @@ mod tests { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, ); - let r = _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _); + let r = unsafe { + _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _) + }; #[rustfmt::skip] let e = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -5192,35 +5217,39 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128() { + const fn test_mm256_storeu2_m128() { let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); let mut hi = _mm_undefined_ps(); let mut lo = _mm_undefined_ps(); - _mm256_storeu2_m128( - ptr::addr_of_mut!(hi) as *mut f32, - ptr::addr_of_mut!(lo) as *mut f32, - a, - ); + unsafe { + _mm256_storeu2_m128( + ptr::addr_of_mut!(hi) as *mut f32, + ptr::addr_of_mut!(lo) as *mut f32, + a, + ); + } assert_eq_m128(hi, _mm_setr_ps(5., 6., 7., 8.)); assert_eq_m128(lo, _mm_setr_ps(1., 2., 3., 4.)); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128d() { + const fn test_mm256_storeu2_m128d() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut hi = _mm_undefined_pd(); let mut lo = _mm_undefined_pd(); - _mm256_storeu2_m128d( - ptr::addr_of_mut!(hi) as *mut f64, - ptr::addr_of_mut!(lo) as *mut f64, - a, - ); + unsafe { + _mm256_storeu2_m128d( + ptr::addr_of_mut!(hi) as *mut f64, + ptr::addr_of_mut!(lo) as *mut f64, + a, + ); + } assert_eq_m128d(hi, _mm_setr_pd(3., 4.)); assert_eq_m128d(lo, _mm_setr_pd(1., 2.)); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128i() { + const fn test_mm256_storeu2_m128i() { #[rustfmt::skip] let a = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -5230,7 +5259,9 @@ mod tests { ); let mut hi = _mm_undefined_si128(); let mut lo = _mm_undefined_si128(); - _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a); + unsafe { + _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a); + } #[rustfmt::skip] let e_hi = _mm_setr_epi8( 17, 18, 19, 20, 21, 22, 23, 24, diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs index 6f56e937c6db6..6a39a0aaf8feb 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs @@ -4672,81 +4672,89 @@ mod tests { } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskload_epi32() { + const fn test_mm_maskload_epi32() { let nums = [1, 2, 3, 4]; let a = &nums as *const i32; let mask = _mm_setr_epi32(-1, 0, 0, -1); - let r = _mm_maskload_epi32(a, mask); + let r = unsafe { _mm_maskload_epi32(a, mask) }; let e = _mm_setr_epi32(1, 0, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskload_epi32() { + const fn test_mm256_maskload_epi32() { let nums = [1, 2, 3, 4, 5, 6, 7, 8]; let a = &nums as *const i32; let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0); - let r = _mm256_maskload_epi32(a, mask); + let r = unsafe { _mm256_maskload_epi32(a, mask) }; let e = _mm256_setr_epi32(1, 0, 0, 4, 0, 6, 7, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskload_epi64() { + const fn test_mm_maskload_epi64() { let nums = [1_i64, 2_i64]; let a = &nums as *const i64; let mask = _mm_setr_epi64x(0, -1); - let r = _mm_maskload_epi64(a, mask); + let r = unsafe { _mm_maskload_epi64(a, mask) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskload_epi64() { + const fn test_mm256_maskload_epi64() { let nums = [1_i64, 2_i64, 3_i64, 4_i64]; let a = &nums as *const i64; let mask = _mm256_setr_epi64x(0, -1, -1, 0); - let r = _mm256_maskload_epi64(a, mask); + let r = unsafe { _mm256_maskload_epi64(a, mask) }; let e = _mm256_setr_epi64x(0, 2, 3, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskstore_epi32() { + const fn test_mm_maskstore_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut arr = [-1, -1, -1, -1]; let mask = _mm_setr_epi32(-1, 0, 0, -1); - _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a); + unsafe { + _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a); + } let e = [1, -1, -1, 4]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskstore_epi32() { + const fn test_mm256_maskstore_epi32() { let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8); let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1]; let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0); - _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a); + unsafe { + _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a); + } let e = [1, -1, -1, 42, -1, 6, 7, -1]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskstore_epi64() { + const fn test_mm_maskstore_epi64() { let a = _mm_setr_epi64x(1_i64, 2_i64); let mut arr = [-1_i64, -1_i64]; let mask = _mm_setr_epi64x(0, -1); - _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a); + unsafe { + _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a); + } let e = [-1, 2]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskstore_epi64() { + const fn test_mm256_maskstore_epi64() { let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64); let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64]; let mask = _mm256_setr_epi64x(0, -1, -1, 0); - _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a); + unsafe { + _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a); + } let e = [-1, 2, 3, -1]; assert_eq!(arr, e); } @@ -5301,9 +5309,9 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_stream_load_si256() { + fn test_mm256_stream_load_si256() { let a = _mm256_set_epi64x(5, 6, 7, 8); - let r = _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _) }; assert_eq_m256i(a, r); } @@ -5506,88 +5514,98 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_epi32() { + fn test_mm_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_epi32() { + fn test_mm_mask_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_mask_i32gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm_setr_epi32(-1, -1, -1, 0), - ); + let r = unsafe { + _mm_mask_i32gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm_setr_epi32(-1, -1, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_epi32() { + fn test_mm256_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = - _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); + let r = unsafe { + _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)) + }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_epi32() { + fn test_mm256_mask_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_mask_i32gather_epi32::<4>( - _mm256_set1_epi32(256), - arr.as_ptr(), - _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), - _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0), - ); + let r = unsafe { + _mm256_mask_i32gather_epi32::<4>( + _mm256_set1_epi32(256), + arr.as_ptr(), + _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), + _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 64, 256, 256, 256, 256, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_ps() { + fn test_mm_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_ps() { + fn test_mm_mask_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_mask_i32gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i32gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_ps() { + fn test_mm256_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = - _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); + let r = unsafe { + _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)) + }; assert_eq_m256(r, _mm256_setr_ps(0.0, 16.0, 32.0, 48.0, 1.0, 2.0, 3.0, 4.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_ps() { + fn test_mm256_mask_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_mask_i32gather_ps::<4>( - _mm256_set1_ps(256.0), - arr.as_ptr(), - _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), - _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i32gather_ps::<4>( + _mm256_set1_ps(256.0), + arr.as_ptr(), + _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), + _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0), + ) + }; assert_eq_m256( r, _mm256_setr_ps(0.0, 16.0, 64.0, 256.0, 256.0, 256.0, 256.0, 256.0), @@ -5595,254 +5613,282 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_epi64() { + fn test_mm_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)); + let r = unsafe { _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) }; assert_eq_m128i(r, _mm_setr_epi64x(0, 16)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_epi64() { + fn test_mm_mask_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_mask_i32gather_epi64::<8>( - _mm_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi32(16, 16, 16, 16), - _mm_setr_epi64x(-1, 0), - ); + let r = unsafe { + _mm_mask_i32gather_epi64::<8>( + _mm_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi32(16, 16, 16, 16), + _mm_setr_epi64x(-1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi64x(16, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_epi64() { + fn test_mm256_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_epi64() { + fn test_mm256_mask_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_mask_i32gather_epi64::<8>( - _mm256_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm256_setr_epi64x(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i32gather_epi64::<8>( + _mm256_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm256_setr_epi64x(-1, -1, -1, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_pd() { + fn test_mm_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)); + let r = unsafe { _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) }; assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_pd() { + fn test_mm_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_mask_i32gather_pd::<8>( - _mm_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi32(16, 16, 16, 16), - _mm_setr_pd(-1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i32gather_pd::<8>( + _mm_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi32(16, 16, 16, 16), + _mm_setr_pd(-1.0, 0.0), + ) + }; assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_pd() { + fn test_mm256_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_pd() { + fn test_mm256_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_mask_i32gather_pd::<8>( - _mm256_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i32gather_pd::<8>( + _mm256_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_epi32() { + fn test_mm_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 0, 0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_epi32() { + fn test_mm_mask_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_mask_i64gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm_setr_epi64x(0, 16), - _mm_setr_epi32(-1, 0, -1, 0), - ); + let r = unsafe { + _mm_mask_i64gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm_setr_epi64x(0, 16), + _mm_setr_epi32(-1, 0, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 256, 0, 0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_epi32() { + fn test_mm256_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_epi32() { + fn test_mm256_mask_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_mask_i64gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm_setr_epi32(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i64gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm_setr_epi32(-1, -1, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_ps() { + fn test_mm_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 0.0, 0.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_ps() { + fn test_mm_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_mask_i64gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm_setr_epi64x(0, 16), - _mm_setr_ps(-1.0, 0.0, -1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i64gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm_setr_epi64x(0, 16), + _mm_setr_ps(-1.0, 0.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 256.0, 0.0, 0.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_ps() { + fn test_mm256_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_ps() { + fn test_mm256_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_mask_i64gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i64gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_epi64() { + fn test_mm_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128i(r, _mm_setr_epi64x(0, 16)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_epi64() { + fn test_mm_mask_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_mask_i64gather_epi64::<8>( - _mm_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi64x(16, 16), - _mm_setr_epi64x(-1, 0), - ); + let r = unsafe { + _mm_mask_i64gather_epi64::<8>( + _mm_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi64x(16, 16), + _mm_setr_epi64x(-1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi64x(16, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_epi64() { + fn test_mm256_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_epi64() { + fn test_mm256_mask_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_mask_i64gather_epi64::<8>( - _mm256_set1_epi64x(256), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm256_setr_epi64x(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i64gather_epi64::<8>( + _mm256_set1_epi64x(256), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm256_setr_epi64x(-1, -1, -1, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_pd() { + fn test_mm_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_pd() { + fn test_mm_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_mask_i64gather_pd::<8>( - _mm_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi64x(16, 16), - _mm_setr_pd(-1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i64gather_pd::<8>( + _mm_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi64x(16, 16), + _mm_setr_pd(-1.0, 0.0), + ) + }; assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_pd() { + fn test_mm256_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_pd() { + fn test_mm256_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_mask_i64gather_pd::<8>( - _mm256_set1_pd(256.0), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i64gather_pd::<8>( + _mm256_set1_pd(256.0), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0)); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs index 83dbc540a0c8a..66eef063eed8b 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs @@ -593,7 +593,7 @@ pub fn _mm_cvtness_sbh(a: f32) -> bf16 { #[cfg(test)] mod tests { - use crate::core_arch::simd::u16x4; + use crate::core_arch::simd::{f32x4, f32x8, f32x16, u16x4, u16x8, u16x16, u16x32}; use crate::{ core_arch::x86::*, mem::{transmute, transmute_copy}, @@ -601,13 +601,13 @@ mod tests { use stdarch_test::simd_test; #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_cvtne2ps_pbh() { + fn test_mm_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let c: __m128bh = _mm_cvtne2ps_pbh(a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -623,7 +623,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_cvtne2ps_pbh() { + fn test_mm_mask_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; #[rustfmt::skip] @@ -637,12 +637,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m128bh = transmute(src_array); - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let src = u16x8::from_array(src_array).as_m128bh(); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0b1111_1111; let c: __m128bh = _mm_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -657,20 +657,20 @@ mod tests { assert_eq!(result, expected_result); let k = 0b0000_0000; let c = _mm_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_cvtne2ps_pbh() { + fn test_mm_maskz_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0b1111_1111; let c: __m128bh = _mm_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -685,7 +685,7 @@ mod tests { assert_eq!(result, expected_result); let k = 0b0011_1100; let c = _mm_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0, @@ -701,7 +701,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_cvtne2ps_pbh() { + fn test_mm256_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -723,10 +723,10 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let c: __m256bh = _mm256_cvtne2ps_pbh(a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -750,7 +750,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_cvtne2ps_pbh() { + fn test_mm256_mask_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -790,12 +790,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m256bh = transmute(src_array); - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let src = u16x16::from_array(src_array).as_m256bh(); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -818,13 +818,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_cvtne2ps_pbh() { + fn test_mm256_maskz_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -846,11 +846,11 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -873,7 +873,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0b0110_1100_0011_0110; let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0, @@ -897,7 +897,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_cvtne2ps_pbh() { + fn test_mm512_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -935,10 +935,10 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let c: __m512bh = _mm512_cvtne2ps_pbh(a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -978,7 +978,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_cvtne2ps_pbh() { + fn test_mm512_mask_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1050,12 +1050,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m512bh = transmute(src_array); - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let src = u16x32::from_array(src_array).as_m512bh(); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let k: __mmask32 = 0xffffffff; let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -1094,13 +1094,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask32 = 0; let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_cvtne2ps_pbh() { + fn test_mm512_maskz_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1138,11 +1138,11 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let k: __mmask32 = 0xffffffff; let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -1181,7 +1181,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask32 = 0b1100_1010_1001_0110_1010_0011_0101_0110; let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0, @@ -1221,7 +1221,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_cvtneps_pbh() { + fn test_mm256_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1233,9 +1233,9 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m256 = transmute(a_array); + let a = f32x8::from_array(a_array).as_m256(); let c: __m128bh = _mm256_cvtneps_pbh(a); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1251,7 +1251,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_cvtneps_pbh() { + fn test_mm256_mask_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1273,11 +1273,11 @@ mod tests { 0b1_10001000_1111010, 0b1_10001000_0010000, ]; - let src: __m128bh = transmute(src_array); - let a: __m256 = transmute(a_array); + let src = u16x8::from_array(src_array).as_m128bh(); + let a = f32x8::from_array(a_array).as_m256(); let k: __mmask8 = 0xff; let b = _mm256_mask_cvtneps_pbh(src, k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1292,13 +1292,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0x0; let b: __m128bh = _mm256_mask_cvtneps_pbh(src, k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); let expected_result: [u16; 8] = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_cvtneps_pbh() { + fn test_mm256_maskz_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1310,10 +1310,10 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m256 = transmute(a_array); + let a = f32x8::from_array(a_array).as_m256(); let k: __mmask8 = 0xff; let b = _mm256_maskz_cvtneps_pbh(k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1328,14 +1328,14 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0x6; let b: __m128bh = _mm256_maskz_cvtneps_pbh(k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); let expected_result: [u16; 8] = [0, 0b0_10000010_0101000, 0b0_10000000_1110000, 0, 0, 0, 0, 0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_cvtneps_pbh() { + fn test_mm512_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1355,9 +1355,9 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m512 = transmute(a_array); + let a = f32x16::from_array(a_array).as_m512(); let c: __m256bh = _mm512_cvtneps_pbh(a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1381,7 +1381,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_cvtneps_pbh() { + fn test_mm512_mask_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1419,11 +1419,11 @@ mod tests { 0b1_10001000_1111010, 0b1_10001000_0010000, ]; - let src: __m256bh = transmute(src_array); - let a: __m512 = transmute(a_array); + let src = u16x16::from_array(src_array).as_m256bh(); + let a = f32x16::from_array(a_array).as_m512(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1446,13 +1446,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_cvtneps_pbh() { + fn test_mm512_maskz_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1472,10 +1472,10 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m512 = transmute(a_array); + let a = f32x16::from_array(a_array).as_m512(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1498,7 +1498,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0x653a; let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0, @@ -1522,74 +1522,74 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_dpbf16_ps() { + fn test_mm_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_dpbf16_ps(src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_dpbf16_ps() { + fn test_mm_mask_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0xf3; - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_dpbf16_ps() { + fn test_mm_maskz_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0xf3; - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 0.0, 0.0]; assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [0.0, 0.0, 0.0, 0.0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_dpbf16_ps() { + fn test_mm256_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1597,16 +1597,16 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_dpbf16_ps(src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1615,7 +1615,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_dpbf16_ps() { + fn test_mm256_mask_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1623,17 +1623,17 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); let k: __mmask8 = 0x33; #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, @@ -1641,7 +1641,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1649,7 +1649,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, @@ -1658,7 +1658,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_dpbf16_ps() { + fn test_mm256_maskz_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1666,17 +1666,17 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); let k: __mmask8 = 0x33; #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, @@ -1684,7 +1684,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1692,13 +1692,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); let expected_result: [f32; 8] = [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_dpbf16_ps() { + fn test_mm512_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1708,16 +1708,17 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); - let src: __m512 = transmute([ + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]) + .as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_dpbf16_ps(src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1727,7 +1728,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_dpbf16_ps() { + fn test_mm512_mask_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1737,18 +1738,18 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); let k: __mmask16 = 0x3333; #[rustfmt::skip] - let src: __m512 = transmute([ + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, @@ -1757,7 +1758,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0xffff; let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1766,7 +1767,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, @@ -1776,7 +1777,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_dpbf16_ps() { + fn test_mm512_maskz_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1786,18 +1787,18 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); let k: __mmask16 = 0x3333; #[rustfmt::skip] - let src: __m512 = transmute([ + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, @@ -1806,7 +1807,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0xffff; let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1815,7 +1816,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, @@ -1943,28 +1944,28 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_cvtneps_pbh() { + fn test_mm_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - let r: u16x4 = transmute_copy(&_mm_cvtneps_pbh(a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_pbh(a)) }; let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_cvtneps_pbh() { + fn test_mm_mask_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let src = __m128bh([5, 6, 7, 8, !0, !0, !0, !0]); let k = 0b1010; - let r: u16x4 = transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)) }; let e = u16x4::new(5, BF16_TWO, 7, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_cvtneps_pbh() { + fn test_mm_maskz_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let k = 0b1010; - let r: u16x4 = transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)) }; let e = u16x4::new(0, BF16_TWO, 0, BF16_FOUR); assert_eq!(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index 6b4b88621efd3..8e074fdcfa486 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -17098,37 +17098,37 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_loadu_epi16() { + const fn test_mm512_loadu_epi16() { #[rustfmt::skip] let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm512_loadu_epi16(&a[0]); + let r = unsafe { _mm512_loadu_epi16(&a[0]) }; #[rustfmt::skip] let e = _mm512_set_epi16(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_loadu_epi16() { + const fn test_mm256_loadu_epi16() { let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let r = _mm256_loadu_epi16(&a[0]); + let r = unsafe { _mm256_loadu_epi16(&a[0]) }; let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_loadu_epi16() { + const fn test_mm_loadu_epi16() { let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let r = _mm_loadu_epi16(&a[0]); + let r = unsafe { _mm_loadu_epi16(&a[0]) }; let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_loadu_epi8() { + const fn test_mm512_loadu_epi8() { #[rustfmt::skip] let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm512_loadu_epi8(&a[0]); + let r = unsafe { _mm512_loadu_epi8(&a[0]) }; #[rustfmt::skip] let e = _mm512_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); @@ -17136,73 +17136,85 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_loadu_epi8() { + const fn test_mm256_loadu_epi8() { #[rustfmt::skip] let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm256_loadu_epi8(&a[0]); + let r = unsafe { _mm256_loadu_epi8(&a[0]) }; #[rustfmt::skip] let e = _mm256_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_loadu_epi8() { + const fn test_mm_loadu_epi8() { let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let r = _mm_loadu_epi8(&a[0]); + let r = unsafe { _mm_loadu_epi8(&a[0]) }; let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_storeu_epi16() { + const fn test_mm512_storeu_epi16() { let a = _mm512_set1_epi16(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_storeu_epi16() { + const fn test_mm256_storeu_epi16() { let a = _mm256_set1_epi16(9); let mut r = _mm256_set1_epi32(0); - _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_storeu_epi16() { + const fn test_mm_storeu_epi16() { let a = _mm_set1_epi16(9); let mut r = _mm_set1_epi32(0); - _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_storeu_epi8() { + const fn test_mm512_storeu_epi8() { let a = _mm512_set1_epi8(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_storeu_epi8() { + const fn test_mm256_storeu_epi8() { let a = _mm256_set1_epi8(9); let mut r = _mm256_set1_epi32(0); - _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_storeu_epi8() { + const fn test_mm_storeu_epi8() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi32(0); - _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_loadu_epi16() { + const fn test_mm512_mask_loadu_epi16() { let src = _mm512_set1_epi16(42); let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17210,52 +17222,54 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm512_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_maskz_loadu_epi16() { + const fn test_mm512_maskz_loadu_epi16() { let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm512_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi16(m, black_box(p)) }; let e = &[ 0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_storeu_epi16() { + const fn test_mm512_mask_storeu_epi16() { let mut r = [42_i16; 32]; let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; - let a = _mm512_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm512_loadu_epi16(a.as_ptr()) }; let m = 0b10101010_11001100_11101000_11001010; - _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a); + } let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); - assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; + assert_eq_m512i(unsafe { _mm512_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_loadu_epi8() { + const fn test_mm512_mask_loadu_epi8() { let src = _mm512_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17264,18 +17278,18 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - let r = _mm512_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_maskz_loadu_epi8() { + const fn test_mm512_maskz_loadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, @@ -17283,77 +17297,81 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - let r = _mm512_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi8(m, black_box(p)) }; let e = &[ 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_storeu_epi8() { + const fn test_mm512_mask_storeu_epi8() { let mut r = [42_i8; 64]; let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, ]; - let a = _mm512_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm512_loadu_epi8(a.as_ptr()) }; let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a); + } let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); - assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; + assert_eq_m512i(unsafe { _mm512_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi16() { + const fn test_mm256_mask_loadu_epi16() { let src = _mm256_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm256_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi16() { + const fn test_mm256_maskz_loadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi16(m, black_box(p)) }; let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16]; - let e = _mm256_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi16() { + const fn test_mm256_mask_storeu_epi16() { let mut r = [42_i16; 16]; let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let a = _mm256_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm256_loadu_epi16(a.as_ptr()) }; let m = 0b11101000_11001010; - _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a); + } let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm256_loadu_epi16(e.as_ptr()); - assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; + assert_eq_m256i(unsafe { _mm256_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi8() { + const fn test_mm256_mask_loadu_epi8() { let src = _mm256_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17361,122 +17379,124 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm256_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi8() { + const fn test_mm256_maskz_loadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm256_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi8(m, black_box(p)) }; let e = &[ 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi8() { + const fn test_mm256_mask_storeu_epi8() { let mut r = [42_i8; 32]; let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; - let a = _mm256_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm256_loadu_epi8(a.as_ptr()) }; let m = 0b10101010_11001100_11101000_11001010; - _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a); + } let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); - assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; + assert_eq_m256i(unsafe { _mm256_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi16() { + const fn test_mm_mask_loadu_epi16() { let src = _mm_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi16() { + const fn test_mm_maskz_loadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi16(m, black_box(p)) }; let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi16() { + const fn test_mm_mask_storeu_epi16() { let mut r = [42_i16; 8]; let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; - let a = _mm_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm_loadu_epi16(a.as_ptr()) }; let m = 0b11001010; - _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a) }; let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); - assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; + assert_eq_m128i(unsafe { _mm_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi8() { + const fn test_mm_mask_loadu_epi8() { let src = _mm_set1_epi8(42); let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi8() { + const fn test_mm_maskz_loadu_epi8() { let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi8(m, black_box(p)) }; let e = &[0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16]; - let e = _mm_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi8() { + const fn test_mm_mask_storeu_epi8() { let mut r = [42_i8; 16]; let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let a = _mm_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm_loadu_epi8(a.as_ptr()) }; let m = 0b11101000_11001010; - _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm_loadu_epi8(e.as_ptr()); - assert_eq_m128i(_mm_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; + assert_eq_m128i(unsafe { _mm_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw")] @@ -20714,36 +20734,40 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_store_mask64() { + const fn test_store_mask64() { let a: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; let mut r = 0; - _store_mask64(&mut r, a); + unsafe { + _store_mask64(&mut r, a); + } assert_eq!(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_store_mask32() { + const fn test_store_mask32() { let a: __mmask32 = 0b11111111_00000000_11111111_00000000; let mut r = 0; - _store_mask32(&mut r, a); + unsafe { + _store_mask32(&mut r, a); + } assert_eq!(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_load_mask64() { + const fn test_load_mask64() { let p: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; - let r = _load_mask64(&p); + let r = unsafe { _load_mask64(&p) }; let e: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; assert_eq!(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_load_mask32() { + const fn test_load_mask32() { let p: __mmask32 = 0b11111111_00000000_11111111_00000000; - let r = _load_mask32(&p); + let r = unsafe { _load_mask32(&p) }; let e: __mmask32 = 0b11111111_00000000_11111111_00000000; assert_eq!(r, e); } @@ -21163,21 +21187,21 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_kortest_mask32_u8() { + const fn test_kortest_mask32_u8() { let a: __mmask32 = 0b0110100101101001_0110100101101001; let b: __mmask32 = 0b1011011010110110_1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask32_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask32_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_kortest_mask64_u8() { + const fn test_kortest_mask64_u8() { let a: __mmask64 = 0b0110100101101001_0110100101101001; let b: __mmask64 = 0b1011011010110110_1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask64_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask64_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 0); } @@ -21299,11 +21323,11 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_ktest_mask32_u8() { + const fn test_ktest_mask32_u8() { let a: __mmask32 = 0b0110100100111100_0110100100111100; let b: __mmask32 = 0b1001011011000011_1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask32_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask32_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -21325,11 +21349,11 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_ktest_mask64_u8() { + const fn test_ktest_mask64_u8() { let a: __mmask64 = 0b0110100100111100_0110100100111100; let b: __mmask64 = 0b1001011011000011_1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask64_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask64_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -21951,32 +21975,38 @@ mod tests { } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtsepi16_storeu_epi8() { + fn test_mm512_mask_cvtsepi16_storeu_epi8() { let a = _mm512_set1_epi16(i16::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtsepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(i8::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi16_storeu_epi8() { + fn test_mm256_mask_cvtsepi16_storeu_epi8() { let a = _mm256_set1_epi16(i16::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtsepi16_storeu_epi8() { + fn test_mm_mask_cvtsepi16_storeu_epi8() { let a = _mm_set1_epi16(i16::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, @@ -21986,63 +22016,75 @@ mod tests { } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtepi16_storeu_epi8() { + fn test_mm512_mask_cvtepi16_storeu_epi8() { let a = _mm512_set1_epi16(8); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtepi16_storeu_epi8() { + fn test_mm256_mask_cvtepi16_storeu_epi8() { let a = _mm256_set1_epi16(8); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtepi16_storeu_epi8() { + fn test_mm_mask_cvtepi16_storeu_epi8() { let a = _mm_set1_epi16(8); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtusepi16_storeu_epi8() { + fn test_mm512_mask_cvtusepi16_storeu_epi8() { let a = _mm512_set1_epi16(i16::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtusepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(u8::MAX as i8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi16_storeu_epi8() { + fn test_mm256_mask_cvtusepi16_storeu_epi8() { let a = _mm256_set1_epi16(i16::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(u8::MAX as i8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtusepi16_storeu_epi8() { + fn test_mm_mask_cvtusepi16_storeu_epi8() { let a = _mm_set1_epi16(i16::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs index ebe75cd22d8e5..9e1a4c0b29558 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs @@ -7401,27 +7401,25 @@ unsafe extern "C" { mod tests { use super::*; use crate::core_arch::assert_eq_const as assert_eq; + use crate::core_arch::x86::*; use stdarch_test::simd_test; - use crate::core_arch::x86::*; - use crate::mem::transmute; - - const OPRND1_64: f64 = unsafe { transmute(0x3333333333333333_u64) }; - const OPRND2_64: f64 = unsafe { transmute(0x5555555555555555_u64) }; + const OPRND1_64: f64 = f64::from_bits(0x3333333333333333); + const OPRND2_64: f64 = f64::from_bits(0x5555555555555555); - const AND_64: f64 = unsafe { transmute(0x1111111111111111_u64) }; - const ANDN_64: f64 = unsafe { transmute(0x4444444444444444_u64) }; - const OR_64: f64 = unsafe { transmute(0x7777777777777777_u64) }; - const XOR_64: f64 = unsafe { transmute(0x6666666666666666_u64) }; + const AND_64: f64 = f64::from_bits(0x1111111111111111); + const ANDN_64: f64 = f64::from_bits(0x4444444444444444); + const OR_64: f64 = f64::from_bits(0x7777777777777777); + const XOR_64: f64 = f64::from_bits(0x6666666666666666); - const OPRND1_32: f32 = unsafe { transmute(0x33333333_u32) }; - const OPRND2_32: f32 = unsafe { transmute(0x55555555_u32) }; + const OPRND1_32: f32 = f32::from_bits(0x33333333); + const OPRND2_32: f32 = f32::from_bits(0x55555555); - const AND_32: f32 = unsafe { transmute(0x11111111_u32) }; - const ANDN_32: f32 = unsafe { transmute(0x44444444_u32) }; - const OR_32: f32 = unsafe { transmute(0x77777777_u32) }; - const XOR_32: f32 = unsafe { transmute(0x66666666_u32) }; + const AND_32: f32 = f32::from_bits(0x11111111); + const ANDN_32: f32 = f32::from_bits(0x44444444); + const OR_32: f32 = f32::from_bits(0x77777777); + const XOR_32: f32 = f32::from_bits(0x66666666); #[simd_test(enable = "avx512dq,avx512vl")] const fn test_mm_mask_and_pd() { @@ -10023,11 +10021,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_kortest_mask8_u8() { + const fn test_kortest_mask8_u8() { let a: __mmask8 = 0b01101001; let b: __mmask8 = 0b10110110; let mut all_ones: u8 = 0; - let r = _kortest_mask8_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask8_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } @@ -10049,7 +10047,7 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_kshiftli_mask8() { + const fn test_kshiftli_mask8() { let a: __mmask8 = 0b01101001; let r = _kshiftli_mask8::<3>(a); let e: __mmask8 = 0b01001000; @@ -10089,11 +10087,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_ktest_mask8_u8() { + const fn test_ktest_mask8_u8() { let a: __mmask8 = 0b01101001; let b: __mmask8 = 0b10010110; let mut and_not: u8 = 0; - let r = _ktest_mask8_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask8_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -10115,11 +10113,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_ktest_mask16_u8() { + const fn test_ktest_mask16_u8() { let a: __mmask16 = 0b0110100100111100; let b: __mmask16 = 0b1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask16_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask16_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -10141,18 +10139,20 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_load_mask8() { + const fn test_load_mask8() { let a: __mmask8 = 0b01101001; - let r = _load_mask8(&a); + let r = unsafe { _load_mask8(&a) }; let e: __mmask8 = 0b01101001; assert_eq!(r, e); } #[simd_test(enable = "avx512dq")] - const unsafe fn test_store_mask8() { + const fn test_store_mask8() { let a: __mmask8 = 0b01101001; let mut r = 0; - _store_mask8(&mut r, a); + unsafe { + _store_mask8(&mut r, a); + } let e: __mmask8 = 0b01101001; assert_eq!(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs index 76b7539383839..3730496e1ec34 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -48062,9 +48062,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm512_ternarylogic_epi32() { let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101); let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b110); let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b111); @@ -48077,7 +48075,7 @@ mod tests { let r = _mm512_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm512_set4_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m512i(r, e); - assert_eq_m512i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m512i(r, _mm512_xor_si512(_mm512_xor_si512(a, b), c)); // Majority (2 or more bits set). let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -48110,9 +48108,7 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm256_ternarylogic_epi32() { let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d); let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101); @@ -48127,7 +48123,7 @@ mod tests { let r = _mm256_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm256_set4_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m256i(r, e); - assert_eq_m256i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m256i(r, _mm256_xor_si256(_mm256_xor_si256(a, b), c)); // Majority (2 or more bits set). let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -48160,9 +48156,7 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm_ternarylogic_epi32() { let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101); let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b110); let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b111); @@ -48175,7 +48169,7 @@ mod tests { let r = _mm_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm_setr_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m128i(r, e); - assert_eq_m128i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m128i(r, _mm_xor_si128(_mm_xor_si128(a, b), c)); // Majority (2 or more bits set). let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -51447,20 +51441,20 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_ps() { + fn test_mm512_i32gather_ps() { let arr: [f32; 256] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); - let r = _mm512_i32gather_ps::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_ps::<4>(index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512(r, _mm512_setr_ps(0., 16., 32., 48., 64., 80., 96., 112., 120., 128., 136., 144., 152., 160., 168., 176.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_ps() { + fn test_mm512_mask_i32gather_ps() { let arr: [f32; 256] = core::array::from_fn(|i| i as f32); let src = _mm512_set1_ps(2.); let mask = 0b10101010_10101010; @@ -51468,27 +51462,27 @@ mod tests { let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512(r, _mm512_setr_ps(2., 16., 2., 48., 2., 80., 2., 112., 2., 128., 2., 144., 2., 160., 2., 176.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_epi32() { + fn test_mm512_i32gather_epi32() { let arr: [i32; 256] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); - let r = _mm512_i32gather_epi32::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_epi32::<4>(index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512i(r, _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_epi32() { + fn test_mm512_mask_i32gather_epi32() { let arr: [i32; 256] = core::array::from_fn(|i| i as i32); let src = _mm512_set1_epi32(2); let mask = 0b10101010_10101010; @@ -51496,7 +51490,7 @@ mod tests { 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, ); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i( r, _mm512_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112, 2, 144, 2, 176, 2, 208, 2, 240), @@ -51504,7 +51498,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_ps() { + fn test_mm512_i32scatter_ps() { let mut arr = [0f32; 256]; #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, @@ -51513,7 +51507,9 @@ mod tests { 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ); // A multiplier of 4 is word-addressing - _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f32; 256]; for i in 0..16 { expected[i * 16] = (i + 1) as f32; @@ -51522,7 +51518,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_ps() { + fn test_mm512_mask_i32scatter_ps() { let mut arr = [0f32; 256]; let mask = 0b10101010_10101010; #[rustfmt::skip] @@ -51532,7 +51528,9 @@ mod tests { 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ); // A multiplier of 4 is word-addressing - _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f32; 256]; for i in 0..8 { expected[i * 32 + 16] = 2. * (i + 1) as f32; @@ -51541,7 +51539,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_epi32() { + fn test_mm512_i32scatter_epi32() { let mut arr = [0i32; 256]; #[rustfmt::skip] @@ -51549,7 +51547,9 @@ mod tests { 128, 144, 160, 176, 192, 208, 224, 240); let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); // A multiplier of 4 is word-addressing - _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i32; 256]; for i in 0..16 { expected[i * 16] = (i + 1) as i32; @@ -51558,7 +51558,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_epi32() { + fn test_mm512_mask_i32scatter_epi32() { let mut arr = [0i32; 256]; let mask = 0b10101010_10101010; #[rustfmt::skip] @@ -51566,7 +51566,9 @@ mod tests { 128, 144, 160, 176, 192, 208, 224, 240); let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); // A multiplier of 4 is word-addressing - _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i32; 256]; for i in 0..8 { expected[i * 32 + 16] = 2 * (i + 1) as i32; @@ -52850,29 +52852,31 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_pd() { + const fn test_mm512_loadu_pd() { let a = &[4., 3., 2., 5., 8., 9., 64., 50.]; let p = a.as_ptr(); - let r = _mm512_loadu_pd(black_box(p)); + let r = unsafe { _mm512_loadu_pd(black_box(p)) }; let e = _mm512_setr_pd(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_pd() { + const fn test_mm512_storeu_pd() { let a = _mm512_set1_pd(9.); let mut r = _mm512_undefined_pd(); - _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a); + unsafe { + _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a); + } assert_eq_m512d(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_ps() { + const fn test_mm512_loadu_ps() { let a = &[ 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ]; let p = a.as_ptr(); - let r = _mm512_loadu_ps(black_box(p)); + let r = unsafe { _mm512_loadu_ps(black_box(p)) }; let e = _mm512_setr_ps( 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ); @@ -52880,36 +52884,38 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_ps() { + const fn test_mm512_storeu_ps() { let a = _mm512_set1_ps(9.); let mut r = _mm512_undefined_ps(); - _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a); + unsafe { + _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a); + } assert_eq_m512(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_epi32() { + const fn test_mm512_mask_loadu_epi32() { let src = _mm512_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_epi32() { + const fn test_mm512_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_epi32() { + const fn test_mm512_mask_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -52920,13 +52926,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_epi32(src, m, black_box(p)) }; let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_epi32() { + const fn test_mm512_maskz_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -52936,23 +52942,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_epi32(m, black_box(p)) }; let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_epi32() { + const fn test_mm512_mask_storeu_epi32() { let mut r = [42_i32; 16]; let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let m = 0b11101000_11001010; - _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); - assert_eq_m512i(_mm512_loadu_epi32(r.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_epi32() { + const fn test_mm512_mask_store_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], @@ -52960,34 +52968,36 @@ mod tests { let mut r = Align { data: [42; 16] }; let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let m = 0b11101000_11001010; - _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); - assert_eq_m512i(_mm512_load_epi32(r.data.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_epi64() { + const fn test_mm512_mask_loadu_epi64() { let src = _mm512_set1_epi64(42); let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_epi64() { + const fn test_mm512_maskz_loadu_epi64() { let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_epi64() { + const fn test_mm512_mask_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -52998,13 +53008,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_epi64(src, m, black_box(p)) }; let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_epi64() { + const fn test_mm512_maskz_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -53014,23 +53024,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_epi64(m, black_box(p)) }; let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_epi64() { + const fn test_mm512_mask_storeu_epi64() { let mut r = [42_i64; 8]; let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m512i(_mm512_loadu_epi64(r.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_epi64() { + const fn test_mm512_mask_store_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], @@ -53039,13 +53051,15 @@ mod tests { let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; let p = r.data.as_mut_ptr(); - _mm512_mask_store_epi64(p, m, a); + unsafe { + _mm512_mask_store_epi64(p, m, a); + } let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m512i(_mm512_load_epi64(r.data.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_ps() { + const fn test_mm512_mask_loadu_ps() { let src = _mm512_set1_ps(42.0); let a = &[ 1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, @@ -53053,7 +53067,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, @@ -53062,14 +53076,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_ps() { + const fn test_mm512_maskz_loadu_ps() { let a = &[ 1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_ps(m, black_box(p)) }; let e = _mm512_setr_ps( 0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0, ); @@ -53077,7 +53091,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_ps() { + const fn test_mm512_mask_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -53091,7 +53105,7 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_ps(src, m, black_box(p)) }; let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, @@ -53100,7 +53114,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_ps() { + const fn test_mm512_maskz_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -53113,7 +53127,7 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_ps(m, black_box(p)) }; let e = _mm512_setr_ps( 0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0, ); @@ -53121,22 +53135,24 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_ps() { + const fn test_mm512_mask_storeu_ps() { let mut r = [42_f32; 16]; let a = _mm512_setr_ps( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let m = 0b11101000_11001010; - _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, ); - assert_eq_m512(_mm512_loadu_ps(r.as_ptr()), e); + assert_eq_m512(unsafe { _mm512_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_ps() { + const fn test_mm512_mask_store_ps() { #[repr(align(64))] struct Align { data: [f32; 16], @@ -53146,37 +53162,39 @@ mod tests { 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let m = 0b11101000_11001010; - _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, ); - assert_eq_m512(_mm512_load_ps(r.data.as_ptr()), e); + assert_eq_m512(unsafe { _mm512_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_pd() { + const fn test_mm512_mask_loadu_pd() { let src = _mm512_set1_pd(42.0); let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_pd() { + const fn test_mm512_maskz_loadu_pd() { let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_pd(m, black_box(p)) }; let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_pd() { + const fn test_mm512_mask_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -53187,13 +53205,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_pd(src, m, black_box(p)) }; let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_pd() { + const fn test_mm512_maskz_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -53203,23 +53221,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_pd(m, black_box(p)) }; let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_pd() { + const fn test_mm512_mask_storeu_pd() { let mut r = [42_f64; 8]; let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m512d(_mm512_loadu_pd(r.as_ptr()), e); + assert_eq_m512d(unsafe { _mm512_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_pd() { + const fn test_mm512_mask_store_pd() { #[repr(align(64))] struct Align { data: [f64; 8], @@ -53227,34 +53247,36 @@ mod tests { let mut r = Align { data: [42.0; 8] }; let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m512d(_mm512_load_pd(r.data.as_ptr()), e); + assert_eq_m512d(unsafe { _mm512_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi32() { + const fn test_mm256_mask_loadu_epi32() { let src = _mm256_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi32() { + const fn test_mm256_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_epi32() { + const fn test_mm256_mask_load_epi32() { #[repr(align(32))] struct Align { data: [i32; 8], // 32 bytes @@ -53265,13 +53287,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_epi32(src, m, black_box(p)) }; let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_epi32() { + const fn test_mm256_maskz_load_epi32() { #[repr(align(32))] struct Align { data: [i32; 8], // 32 bytes @@ -53281,23 +53303,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_epi32(m, black_box(p)) }; let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi32() { + const fn test_mm256_mask_storeu_epi32() { let mut r = [42_i32; 8]; let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m256i(_mm256_loadu_epi32(r.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_epi32() { + const fn test_mm256_mask_store_epi32() { #[repr(align(64))] struct Align { data: [i32; 8], @@ -53305,34 +53329,36 @@ mod tests { let mut r = Align { data: [42; 8] }; let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m256i(_mm256_load_epi32(r.data.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi64() { + const fn test_mm256_mask_loadu_epi64() { let src = _mm256_set1_epi64x(42); let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm256_setr_epi64x(42, 2, 42, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi64() { + const fn test_mm256_maskz_loadu_epi64() { let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm256_setr_epi64x(0, 2, 0, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_epi64() { + const fn test_mm256_mask_load_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], // 32 bytes @@ -53343,13 +53369,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_epi64(src, m, black_box(p)) }; let e = _mm256_setr_epi64x(42, 2, 42, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_epi64() { + const fn test_mm256_maskz_load_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], // 32 bytes @@ -53359,23 +53385,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_epi64(m, black_box(p)) }; let e = _mm256_setr_epi64x(0, 2, 0, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi64() { + const fn test_mm256_mask_storeu_epi64() { let mut r = [42_i64; 4]; let a = _mm256_setr_epi64x(1, 2, 3, 4); let m = 0b1010; - _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi64x(42, 2, 42, 4); - assert_eq_m256i(_mm256_loadu_epi64(r.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_epi64() { + const fn test_mm256_mask_store_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], @@ -53383,34 +53411,36 @@ mod tests { let mut r = Align { data: [42; 4] }; let a = _mm256_setr_epi64x(1, 2, 3, 4); let m = 0b1010; - _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi64x(42, 2, 42, 4); - assert_eq_m256i(_mm256_load_epi64(r.data.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_ps() { + const fn test_mm256_mask_loadu_ps() { let src = _mm256_set1_ps(42.0); let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_ps() { + const fn test_mm256_maskz_loadu_ps() { let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_ps(m, black_box(p)) }; let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_ps() { + const fn test_mm256_mask_load_ps() { #[repr(align(32))] struct Align { data: [f32; 8], // 32 bytes @@ -53421,13 +53451,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_ps(src, m, black_box(p)) }; let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_ps() { + const fn test_mm256_maskz_load_ps() { #[repr(align(32))] struct Align { data: [f32; 8], // 32 bytes @@ -53437,23 +53467,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_ps(m, black_box(p)) }; let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_ps() { + const fn test_mm256_mask_storeu_ps() { let mut r = [42_f32; 8]; let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m256(_mm256_loadu_ps(r.as_ptr()), e); + assert_eq_m256(unsafe { _mm256_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_ps() { + const fn test_mm256_mask_store_ps() { #[repr(align(32))] struct Align { data: [f32; 8], @@ -53461,34 +53493,36 @@ mod tests { let mut r = Align { data: [42.0; 8] }; let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m256(_mm256_load_ps(r.data.as_ptr()), e); + assert_eq_m256(unsafe { _mm256_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_pd() { + const fn test_mm256_mask_loadu_pd() { let src = _mm256_set1_pd(42.0); let a = &[1.0_f64, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_pd() { + const fn test_mm256_maskz_loadu_pd() { let a = &[1.0_f64, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_pd(m, black_box(p)) }; let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_pd() { + const fn test_mm256_mask_load_pd() { #[repr(align(32))] struct Align { data: [f64; 4], // 32 bytes @@ -53499,13 +53533,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_pd(src, m, black_box(p)) }; let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_pd() { + const fn test_mm256_maskz_load_pd() { #[repr(align(32))] struct Align { data: [f64; 4], // 32 bytes @@ -53515,23 +53549,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_pd(m, black_box(p)) }; let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_pd() { + const fn test_mm256_mask_storeu_pd() { let mut r = [42_f64; 4]; let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); - assert_eq_m256d(_mm256_loadu_pd(r.as_ptr()), e); + assert_eq_m256d(unsafe { _mm256_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_pd() { + const fn test_mm256_mask_store_pd() { #[repr(align(32))] struct Align { data: [f64; 4], @@ -53539,34 +53575,36 @@ mod tests { let mut r = Align { data: [42.0; 4] }; let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); - assert_eq_m256d(_mm256_load_pd(r.data.as_ptr()), e); + assert_eq_m256d(unsafe { _mm256_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi32() { + const fn test_mm_mask_loadu_epi32() { let src = _mm_set1_epi32(42); let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm_setr_epi32(42, 2, 42, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi32() { + const fn test_mm_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm_setr_epi32(0, 2, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_epi32() { + const fn test_mm_mask_load_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 32 bytes @@ -53577,13 +53615,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_epi32(src, m, black_box(p)) }; let e = _mm_setr_epi32(42, 2, 42, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_epi32() { + const fn test_mm_maskz_load_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 16 bytes @@ -53593,23 +53631,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_load_epi32(m, black_box(p)) }; let e = _mm_setr_epi32(0, 2, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi32() { + const fn test_mm_mask_storeu_epi32() { let mut r = [42_i32; 4]; let a = _mm_setr_epi32(1, 2, 3, 4); let m = 0b1010; - _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm_setr_epi32(42, 2, 42, 4); - assert_eq_m128i(_mm_loadu_epi32(r.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_epi32() { + const fn test_mm_mask_store_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 16 bytes @@ -53617,34 +53657,36 @@ mod tests { let mut r = Align { data: [42; 4] }; let a = _mm_setr_epi32(1, 2, 3, 4); let m = 0b1010; - _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_epi32(42, 2, 42, 4); - assert_eq_m128i(_mm_load_epi32(r.data.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi64() { + const fn test_mm_mask_loadu_epi64() { let src = _mm_set1_epi64x(42); let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm_setr_epi64x(42, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi64() { + const fn test_mm_maskz_loadu_epi64() { let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_epi64() { + const fn test_mm_mask_load_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53653,13 +53695,13 @@ mod tests { let a = Align { data: [1_i64, 2] }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_epi64(src, m, black_box(p)) }; let e = _mm_setr_epi64x(42, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_epi64() { + const fn test_mm_maskz_load_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53667,23 +53709,25 @@ mod tests { let a = Align { data: [1_i64, 2] }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_load_epi64(m, black_box(p)) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi64() { + const fn test_mm_mask_storeu_epi64() { let mut r = [42_i64; 2]; let a = _mm_setr_epi64x(1, 2); let m = 0b10; - _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm_setr_epi64x(42, 2); - assert_eq_m128i(_mm_loadu_epi64(r.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_epi64() { + const fn test_mm_mask_store_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53691,34 +53735,36 @@ mod tests { let mut r = Align { data: [42; 2] }; let a = _mm_setr_epi64x(1, 2); let m = 0b10; - _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_epi64x(42, 2); - assert_eq_m128i(_mm_load_epi64(r.data.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_ps() { + const fn test_mm_mask_loadu_ps() { let src = _mm_set1_ps(42.0); let a = &[1.0_f32, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_ps() { + const fn test_mm_maskz_loadu_ps() { let a = &[1.0_f32, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_ps(m, black_box(p)) }; let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_ps() { + const fn test_mm_mask_load_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53729,13 +53775,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_ps(src, m, black_box(p)) }; let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_ps() { + const fn test_mm_maskz_load_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53745,23 +53791,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_load_ps(m, black_box(p)) }; let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_ps() { + const fn test_mm_mask_storeu_ps() { let mut r = [42_f32; 4]; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); - assert_eq_m128(_mm_loadu_ps(r.as_ptr()), e); + assert_eq_m128(unsafe { _mm_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_ps() { + const fn test_mm_mask_store_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53769,34 +53817,36 @@ mod tests { let mut r = Align { data: [42.0; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); - assert_eq_m128(_mm_load_ps(r.data.as_ptr()), e); + assert_eq_m128(unsafe { _mm_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_pd() { + const fn test_mm_mask_loadu_pd() { let src = _mm_set1_pd(42.0); let a = &[1.0_f64, 2.0]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm_setr_pd(42.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_pd() { + const fn test_mm_maskz_loadu_pd() { let a = &[1.0_f64, 2.0]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_pd(m, black_box(p)) }; let e = _mm_setr_pd(0.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_pd() { + const fn test_mm_mask_load_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53807,13 +53857,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_pd(src, m, black_box(p)) }; let e = _mm_setr_pd(42.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_pd() { + const fn test_mm_maskz_load_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53823,77 +53873,79 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_load_pd(m, black_box(p)) }; let e = _mm_setr_pd(0.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_load_ss() { + fn test_mm_mask_load_ss() { #[repr(align(16))] struct Align { data: f32, } let src = _mm_set_ss(2.0); let mem = Align { data: 1.0 }; - let r = _mm_mask_load_ss(src, 0b1, &mem.data); + let r = unsafe { _mm_mask_load_ss(src, 0b1, &mem.data) }; assert_eq_m128(r, _mm_set_ss(1.0)); - let r = _mm_mask_load_ss(src, 0b0, &mem.data); + let r = unsafe { _mm_mask_load_ss(src, 0b0, &mem.data) }; assert_eq_m128(r, _mm_set_ss(2.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_maskz_load_ss() { + fn test_mm_maskz_load_ss() { #[repr(align(16))] struct Align { data: f32, } let mem = Align { data: 1.0 }; - let r = _mm_maskz_load_ss(0b1, &mem.data); + let r = unsafe { _mm_maskz_load_ss(0b1, &mem.data) }; assert_eq_m128(r, _mm_set_ss(1.0)); - let r = _mm_maskz_load_ss(0b0, &mem.data); + let r = unsafe { _mm_maskz_load_ss(0b0, &mem.data) }; assert_eq_m128(r, _mm_set_ss(0.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_load_sd() { + fn test_mm_mask_load_sd() { #[repr(align(16))] struct Align { data: f64, } let src = _mm_set_sd(2.0); let mem = Align { data: 1.0 }; - let r = _mm_mask_load_sd(src, 0b1, &mem.data); + let r = unsafe { _mm_mask_load_sd(src, 0b1, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(1.0)); - let r = _mm_mask_load_sd(src, 0b0, &mem.data); + let r = unsafe { _mm_mask_load_sd(src, 0b0, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(2.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_maskz_load_sd() { + fn test_mm_maskz_load_sd() { #[repr(align(16))] struct Align { data: f64, } let mem = Align { data: 1.0 }; - let r = _mm_maskz_load_sd(0b1, &mem.data); + let r = unsafe { _mm_maskz_load_sd(0b1, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(1.0)); - let r = _mm_maskz_load_sd(0b0, &mem.data); + let r = unsafe { _mm_maskz_load_sd(0b0, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(0.0)); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_pd() { + const fn test_mm_mask_storeu_pd() { let mut r = [42_f64; 2]; let a = _mm_setr_pd(1.0, 2.0); let m = 0b10; - _mm_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm_setr_pd(42.0, 2.0); - assert_eq_m128d(_mm_loadu_pd(r.as_ptr()), e); + assert_eq_m128d(unsafe { _mm_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_pd() { + const fn test_mm_mask_store_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53901,36 +53953,46 @@ mod tests { let mut r = Align { data: [42.0; 2] }; let a = _mm_setr_pd(1.0, 2.0); let m = 0b10; - _mm_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_pd(42.0, 2.0); - assert_eq_m128d(_mm_load_pd(r.data.as_ptr()), e); + assert_eq_m128d(unsafe { _mm_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_store_ss() { + fn test_mm_mask_store_ss() { #[repr(align(16))] struct Align { data: f32, } let a = _mm_set_ss(2.0); let mut mem = Align { data: 1.0 }; - _mm_mask_store_ss(&mut mem.data, 0b1, a); + unsafe { + _mm_mask_store_ss(&mut mem.data, 0b1, a); + } assert_eq!(mem.data, 2.0); - _mm_mask_store_ss(&mut mem.data, 0b0, a); + unsafe { + _mm_mask_store_ss(&mut mem.data, 0b0, a); + } assert_eq!(mem.data, 2.0); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_store_sd() { + fn test_mm_mask_store_sd() { #[repr(align(16))] struct Align { data: f64, } let a = _mm_set_sd(2.0); let mut mem = Align { data: 1.0 }; - _mm_mask_store_sd(&mut mem.data, 0b1, a); + unsafe { + _mm_mask_store_sd(&mut mem.data, 0b1, a); + } assert_eq!(mem.data, 2.0); - _mm_mask_store_sd(&mut mem.data, 0b0, a); + unsafe { + _mm_mask_store_sd(&mut mem.data, 0b0, a); + } assert_eq!(mem.data, 2.0); } @@ -57931,11 +57993,11 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_kortest_mask16_u8() { + const fn test_kortest_mask16_u8() { let a: __mmask16 = 0b0110100101101001; let b: __mmask16 = 0b1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask16_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask16_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } @@ -57997,18 +58059,20 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_load_mask16() { + const fn test_load_mask16() { let a: __mmask16 = 0b1001011011000011; - let r = _load_mask16(&a); + let r = unsafe { _load_mask16(&a) }; let e: __mmask16 = 0b1001011011000011; assert_eq!(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_store_mask16() { + const fn test_store_mask16() { let a: __mmask16 = 0b0110100100111100; let mut r = 0; - _store_mask16(&mut r, a); + unsafe { + _store_mask16(&mut r, a); + } let e: __mmask16 = 0b0110100100111100; assert_eq!(r, e); } @@ -58189,7 +58253,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_ps() { + fn test_mm512_stream_ps() { #[repr(align(64))] struct Memory { pub data: [f32; 16], // 64 bytes @@ -58197,7 +58261,9 @@ mod tests { let a = _mm512_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 16] }; - _mm512_stream_ps(&mut mem.data[0] as *mut f32, a); + unsafe { + _mm512_stream_ps(&mut mem.data[0] as *mut f32, a); + } _mm_sfence(); for i in 0..16 { assert_eq!(mem.data[i], get_m512(a, i)); @@ -58206,7 +58272,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_pd() { + fn test_mm512_stream_pd() { #[repr(align(64))] struct Memory { pub data: [f64; 8], @@ -58214,7 +58280,9 @@ mod tests { let a = _mm512_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 8] }; - _mm512_stream_pd(&mut mem.data[0] as *mut f64, a); + unsafe { + _mm512_stream_pd(&mut mem.data[0] as *mut f64, a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m512d(a, i)); @@ -58223,7 +58291,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_si512() { + fn test_mm512_stream_si512() { #[repr(align(64))] struct Memory { pub data: [i64; 8], @@ -58231,7 +58299,9 @@ mod tests { let a = _mm512_set1_epi32(7); let mut mem = Memory { data: [-1; 8] }; - _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a); + unsafe { + _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m512i(a, i)); @@ -58239,9 +58309,9 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_stream_load_si512() { + fn test_mm512_stream_load_si512() { let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); - let r = _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _) }; assert_eq_m512i(a, r); } @@ -58558,75 +58628,103 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_epi32() { + fn test_mm512_mask_compressstoreu_epi32() { let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let mut r = [0_i32; 16]; - _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 16]); - _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a); + unsafe { + _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi32() { + fn test_mm256_mask_compressstoreu_epi32() { let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let mut r = [0_i32; 8]; - _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 8]); - _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi32() { + fn test_mm_mask_compressstoreu_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = [0_i32; 4]; - _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 4]); - _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1, 2, 4, 0]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_epi64() { + fn test_mm512_mask_compressstoreu_epi64() { let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let mut r = [0_i64; 8]; - _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 8]); - _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi64() { + fn test_mm256_mask_compressstoreu_epi64() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = [0_i64; 4]; - _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 4]); - _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1, 2, 4, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi64() { + fn test_mm_mask_compressstoreu_epi64() { let a = _mm_setr_epi64x(1, 2); let mut r = [0_i64; 2]; - _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 2]); - _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a); + unsafe { + _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a); + } assert_eq!(&r, &[2, 0]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_ps() { + fn test_mm512_mask_compressstoreu_ps() { let a = _mm512_setr_ps( 1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32, 9_f32, 10_f32, 11_f32, 12_f32, 13_f32, 14_f32, 15_f32, 16_f32, ); let mut r = [0_f32; 16]; - _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_f32; 16]); - _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a); + unsafe { + _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a); + } assert_eq!( &r, &[ @@ -58637,12 +58735,16 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_ps() { + fn test_mm256_mask_compressstoreu_ps() { let a = _mm256_setr_ps(1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32); let mut r = [0_f32; 8]; - _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_f32; 8]); - _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!( &r, &[2_f32, 4_f32, 7_f32, 8_f32, 0_f32, 0_f32, 0_f32, 0_f32] @@ -58650,47 +58752,63 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_ps() { + fn test_mm_mask_compressstoreu_ps() { let a = _mm_setr_ps(1_f32, 2_f32, 3_f32, 4_f32); let mut r = [0.; 4]; - _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 4]); - _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1_f32, 2_f32, 4_f32, 0_f32]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_pd() { + fn test_mm512_mask_compressstoreu_pd() { let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); let mut r = [0.; 8]; - _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 8]); - _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2., 4., 7., 8., 0., 0., 0., 0.]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_pd() { + fn test_mm256_mask_compressstoreu_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut r = [0.; 4]; - _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 4]); - _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1., 2., 4., 0.]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_pd() { + fn test_mm_mask_compressstoreu_pd() { let a = _mm_setr_pd(1., 2.); let mut r = [0.; 2]; - _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 2]); - _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a); + unsafe { + _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a); + } assert_eq!(&r, &[2., 0.]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expand_epi32() { + fn test_mm512_mask_expand_epi32() { let src = _mm512_set1_epi32(200); let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); let r = _mm512_mask_expand_epi32(src, 0, a); @@ -58826,109 +58944,135 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_epi32() { + const fn test_mm512_loadu_epi32() { let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50]; let p = a.as_ptr(); - let r = _mm512_loadu_epi32(black_box(p)); + let r = unsafe { _mm512_loadu_epi32(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_loadu_epi32() { + const fn test_mm256_loadu_epi32() { let a = &[4, 3, 2, 5, 8, 9, 64, 50]; let p = a.as_ptr(); - let r = _mm256_loadu_epi32(black_box(p)); + let r = unsafe { _mm256_loadu_epi32(black_box(p)) }; let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_loadu_epi32() { + const fn test_mm_loadu_epi32() { let a = &[4, 3, 2, 5]; let p = a.as_ptr(); - let r = _mm_loadu_epi32(black_box(p)); + let r = unsafe { _mm_loadu_epi32(black_box(p)) }; let e = _mm_setr_epi32(4, 3, 2, 5); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi32_storeu_epi16() { + fn test_mm512_mask_cvtepi32_storeu_epi16() { let a = _mm512_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + } let e = _mm256_set1_epi16(9); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi32_storeu_epi16() { + fn test_mm256_mask_cvtepi32_storeu_epi16() { let a = _mm256_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi32_storeu_epi16() { + fn test_mm_mask_cvtepi32_storeu_epi16() { let a = _mm_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi32_storeu_epi16() { + fn test_mm512_mask_cvtsepi32_storeu_epi16() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtsepi32_storeu_epi16( + &mut r as *mut _ as *mut i16, + 0b11111111_11111111, + a, + ); + } let e = _mm256_set1_epi16(i16::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi32_storeu_epi16() { + fn test_mm256_mask_cvtsepi32_storeu_epi16() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi32_storeu_epi16() { + fn test_mm_mask_cvtsepi32_storeu_epi16() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi32_storeu_epi16() { + fn test_mm512_mask_cvtusepi32_storeu_epi16() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtusepi32_storeu_epi16( + &mut r as *mut _ as *mut i16, + 0b11111111_11111111, + a, + ); + } let e = _mm256_set1_epi16(u16::MAX as i16); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi32_storeu_epi16() { + fn test_mm256_mask_cvtusepi32_storeu_epi16() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi32_storeu_epi16() { + fn test_mm_mask_cvtusepi32_storeu_epi16() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16( 0, 0, @@ -58943,46 +59087,56 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi32_storeu_epi8() { + fn test_mm512_mask_cvtepi32_storeu_epi8() { let a = _mm512_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi32_storeu_epi8() { + fn test_mm256_mask_cvtepi32_storeu_epi8() { let a = _mm256_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi32_storeu_epi8() { + fn test_mm_mask_cvtepi32_storeu_epi8() { let a = _mm_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi32_storeu_epi8() { + fn test_mm512_mask_cvtsepi32_storeu_epi8() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi32_storeu_epi8() { + fn test_mm256_mask_cvtsepi32_storeu_epi8() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -58994,10 +59148,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi32_storeu_epi8() { + fn test_mm_mask_cvtsepi32_storeu_epi8() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59009,19 +59165,23 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi32_storeu_epi8() { + fn test_mm512_mask_cvtusepi32_storeu_epi8() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(u8::MAX as i8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi32_storeu_epi8() { + fn test_mm256_mask_cvtusepi32_storeu_epi8() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59033,10 +59193,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi32_storeu_epi8() { + fn test_mm_mask_cvtusepi32_storeu_epi8() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59048,48 +59210,56 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_epi32() { + const fn test_mm512_storeu_epi32() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_storeu_epi32() { + const fn test_mm256_storeu_epi32() { let a = _mm256_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_storeu_epi32() { + const fn test_mm_storeu_epi32() { let a = _mm_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_si512() { + const fn test_mm512_loadu_si512() { let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50]; let p = a.as_ptr().cast(); - let r = _mm512_loadu_si512(black_box(p)); + let r = unsafe { _mm512_loadu_si512(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_si512() { + const fn test_mm512_storeu_si512() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_si512(&mut r as *mut _, a); + unsafe { + _mm512_storeu_si512(&mut r as *mut _, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_si512() { + const fn test_mm512_load_si512() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -59098,21 +59268,23 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50], }; let p = (a.data).as_ptr().cast(); - let r = _mm512_load_si512(black_box(p)); + let r = unsafe { _mm512_load_si512(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_si512() { + const fn test_mm512_store_si512() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_store_si512(&mut r as *mut _, a); + unsafe { + _mm512_store_si512(&mut r as *mut _, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_epi32() { + const fn test_mm512_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -59121,13 +59293,13 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50], }; let p = (a.data).as_ptr(); - let r = _mm512_load_epi32(black_box(p)); + let r = unsafe { _mm512_load_epi32(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_load_epi32() { + const fn test_mm256_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 8], @@ -59136,50 +59308,56 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50], }; let p = (a.data).as_ptr(); - let r = _mm256_load_epi32(black_box(p)); + let r = unsafe { _mm256_load_epi32(black_box(p)) }; let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_load_epi32() { + const fn test_mm_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 4], } let a = Align { data: [4, 3, 2, 5] }; let p = (a.data).as_ptr(); - let r = _mm_load_epi32(black_box(p)); + let r = unsafe { _mm_load_epi32(black_box(p)) }; let e = _mm_setr_epi32(4, 3, 2, 5); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_epi32() { + const fn test_mm512_store_epi32() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm512_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_store_epi32() { + const fn test_mm256_store_epi32() { let a = _mm256_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm256_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm256_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_store_epi32() { + const fn test_mm_store_epi32() { let a = _mm_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_ps() { + const fn test_mm512_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -59190,7 +59368,7 @@ mod tests { ], }; let p = (a.data).as_ptr(); - let r = _mm512_load_ps(black_box(p)); + let r = unsafe { _mm512_load_ps(black_box(p)) }; let e = _mm512_setr_ps( 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ); @@ -59198,10 +59376,12 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_ps() { + const fn test_mm512_store_ps() { let a = _mm512_set1_ps(9.); let mut r = _mm512_undefined_ps(); - _mm512_store_ps(&mut r as *mut _ as *mut f32, a); + unsafe { + _mm512_store_ps(&mut r as *mut _ as *mut f32, a); + } assert_eq_m512(r, a); } @@ -62191,140 +62371,140 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_epi32() { + fn test_mm512_mask_expandloadu_epi32() { let src = _mm512_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm512_set_epi32(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_epi32() { + fn test_mm512_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm512_set_epi32(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi32() { + fn test_mm256_mask_expandloadu_epi32() { let src = _mm256_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm256_set_epi32(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi32() { + fn test_mm256_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm256_set_epi32(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi32() { + fn test_mm_mask_expandloadu_epi32() { let src = _mm_set1_epi32(42); let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11111000; - let r = _mm_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm_set_epi32(1, 42, 42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi32() { + fn test_mm_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11111000; - let r = _mm_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm_set_epi32(1, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_epi64() { + fn test_mm512_mask_expandloadu_epi64() { let src = _mm512_set1_epi64(42); let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm512_set_epi64(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_epi64() { + fn test_mm512_maskz_expandloadu_epi64() { let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm512_set_epi64(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi64() { + fn test_mm256_mask_expandloadu_epi64() { let src = _mm256_set1_epi64x(42); let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm256_set_epi64x(1, 42, 42, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi64() { + fn test_mm256_maskz_expandloadu_epi64() { let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm256_set_epi64x(1, 0, 0, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi64() { + fn test_mm_mask_expandloadu_epi64() { let src = _mm_set1_epi64x(42); let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm_set_epi64x(42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi64() { + fn test_mm_maskz_expandloadu_epi64() { let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm_set_epi64x(0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_ps() { + fn test_mm512_mask_expandloadu_ps() { let src = _mm512_set1_ps(42.); let a = &[ 1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm512_set_ps( 8., 7., 6., 42., 5., 42., 42., 42., 4., 3., 42., 42., 2., 42., 1., 42., ); @@ -62332,13 +62512,13 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_ps() { + fn test_mm512_maskz_expandloadu_ps() { let a = &[ 1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm512_set_ps( 8., 7., 6., 0., 5., 0., 0., 0., 4., 3., 0., 0., 2., 0., 1., 0., ); @@ -62346,106 +62526,106 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_ps() { + fn test_mm256_mask_expandloadu_ps() { let src = _mm256_set1_ps(42.); let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm256_set_ps(4., 3., 2., 42., 1., 42., 42., 42.); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_ps() { + fn test_mm256_maskz_expandloadu_ps() { let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm256_set_ps(4., 3., 2., 0., 1., 0., 0., 0.); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_ps() { + fn test_mm_mask_expandloadu_ps() { let src = _mm_set1_ps(42.); let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm_set_ps(1., 42., 42., 42.); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_ps() { + fn test_mm_maskz_expandloadu_ps() { let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm_set_ps(1., 0., 0., 0.); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_pd() { + fn test_mm512_mask_expandloadu_pd() { let src = _mm512_set1_pd(42.); let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm512_set_pd(4., 3., 2., 42., 1., 42., 42., 42.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_pd() { + fn test_mm512_maskz_expandloadu_pd() { let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm512_set_pd(4., 3., 2., 0., 1., 0., 0., 0.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_pd() { + fn test_mm256_mask_expandloadu_pd() { let src = _mm256_set1_pd(42.); let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm256_set_pd(1., 42., 42., 42.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_pd() { + fn test_mm256_maskz_expandloadu_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm256_set_pd(1., 0., 0., 0.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_pd() { + fn test_mm_mask_expandloadu_pd() { let src = _mm_set1_pd(42.); let a = &[1.0f64, 2.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm_set_pd(42., 42.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_pd() { + fn test_mm_maskz_expandloadu_pd() { let a = &[1.0f64, 2.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm_set_pd(0., 0.); assert_eq_m128d(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 57d47c0bb010a..f581711a3c99c 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -16932,7 +16932,6 @@ unsafe extern "C" { mod tests { use crate::core_arch::assert_eq_const as assert_eq; use crate::core_arch::x86::*; - use crate::mem::transmute; use crate::ptr::{addr_of, addr_of_mut}; use stdarch_test::simd_test; @@ -17569,72 +17568,72 @@ mod tests { } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_load_ph() { + const fn test_mm_load_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); - let b = _mm_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm_load_ph(addr_of!(a).cast()) }; assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_load_ph() { + const fn test_mm256_load_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); - let b = _mm256_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm256_load_ph(addr_of!(a).cast()) }; assert_eq_m256h(a, b); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_load_ph() { + const fn test_mm512_load_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); - let b = _mm512_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm512_load_ph(addr_of!(a).cast()) }; assert_eq_m512h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_load_sh() { + const fn test_mm_load_sh() { let a = _mm_set_sh(1.0); - let b = _mm_load_sh(addr_of!(a).cast()); + let b = unsafe { _mm_load_sh(addr_of!(a).cast()) }; assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_mask_load_sh() { + fn test_mm_mask_load_sh() { let a = _mm_set_sh(1.0); let src = _mm_set_sh(2.); - let b = _mm_mask_load_sh(src, 1, addr_of!(a).cast()); + let b = unsafe { _mm_mask_load_sh(src, 1, addr_of!(a).cast()) }; assert_eq_m128h(a, b); - let b = _mm_mask_load_sh(src, 0, addr_of!(a).cast()); + let b = unsafe { _mm_mask_load_sh(src, 0, addr_of!(a).cast()) }; assert_eq_m128h(src, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_maskz_load_sh() { + fn test_mm_maskz_load_sh() { let a = _mm_set_sh(1.0); - let b = _mm_maskz_load_sh(1, addr_of!(a).cast()); + let b = unsafe { _mm_maskz_load_sh(1, addr_of!(a).cast()) }; assert_eq_m128h(a, b); - let b = _mm_maskz_load_sh(0, addr_of!(a).cast()); + let b = unsafe { _mm_maskz_load_sh(0, addr_of!(a).cast()) }; assert_eq_m128h(_mm_setzero_ph(), b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_loadu_ph() { + const fn test_mm_loadu_ph() { let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; - let r = _mm_loadu_ph(array.as_ptr()); + let r = unsafe { _mm_loadu_ph(array.as_ptr()) }; let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); assert_eq_m128h(r, e); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_loadu_ph() { + const fn test_mm256_loadu_ph() { let array = [ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]; - let r = _mm256_loadu_ph(array.as_ptr()); + let r = unsafe { _mm256_loadu_ph(array.as_ptr()) }; let e = _mm256_setr_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); @@ -17642,13 +17641,13 @@ mod tests { } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_loadu_ph() { + const fn test_mm512_loadu_ph() { let array = [ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ]; - let r = _mm512_loadu_ph(array.as_ptr()); + let r = unsafe { _mm512_loadu_ph(array.as_ptr()) }; let e = _mm512_setr_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, @@ -17686,81 +17685,99 @@ mod tests { } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_store_ph() { + const fn test_mm_store_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let mut b = _mm_setzero_ph(); - _mm_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_store_ph() { + const fn test_mm256_store_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let mut b = _mm256_setzero_ph(); - _mm256_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm256_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m256h(a, b); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_store_ph() { + const fn test_mm512_store_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); let mut b = _mm512_setzero_ph(); - _mm512_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm512_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m512h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_store_sh() { + const fn test_mm_store_sh() { let a = _mm_set_sh(1.0); let mut b = _mm_setzero_ph(); - _mm_store_sh(addr_of_mut!(b).cast(), a); + unsafe { + _mm_store_sh(addr_of_mut!(b).cast(), a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_mask_store_sh() { + fn test_mm_mask_store_sh() { let a = _mm_set_sh(1.0); let mut b = _mm_setzero_ph(); - _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a); + unsafe { + _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a); + } assert_eq_m128h(_mm_setzero_ph(), b); - _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a); + unsafe { + _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_storeu_ph() { + const fn test_mm_storeu_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let mut array = [0.0; 8]; - _mm_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m128h(a, _mm_loadu_ph(array.as_ptr())); + unsafe { + _mm_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m128h(a, unsafe { _mm_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_storeu_ph() { + const fn test_mm256_storeu_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let mut array = [0.0; 16]; - _mm256_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m256h(a, _mm256_loadu_ph(array.as_ptr())); + unsafe { + _mm256_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m256h(a, unsafe { _mm256_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_storeu_ph() { + const fn test_mm512_storeu_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); let mut array = [0.0; 32]; - _mm512_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m512h(a, _mm512_loadu_ph(array.as_ptr())); + unsafe { + _mm512_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m512h(a, unsafe { _mm512_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16,avx512vl")] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs index 26cef5814e9cc..78a50b90c8614 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs @@ -3932,7 +3932,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_expandloadu_epi16() { + fn test_mm512_mask_expandloadu_epi16() { let src = _mm512_set1_epi16(42); let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -3940,7 +3940,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm512_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm512_set_epi16( 16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42, 42, 42, 42, 42, 42, 4, 3, 2, 1, @@ -3949,14 +3949,14 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_maskz_expandloadu_epi16() { + fn test_mm512_maskz_expandloadu_epi16() { let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm512_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm512_set_epi16( 16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 2, 1, @@ -3965,49 +3965,49 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi16() { + fn test_mm256_mask_expandloadu_epi16() { let src = _mm256_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm256_set_epi16(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi16() { + fn test_mm256_maskz_expandloadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm256_set_epi16(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi16() { + fn test_mm_mask_expandloadu_epi16() { let src = _mm_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm_set_epi16(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi16() { + fn test_mm_maskz_expandloadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm_set_epi16(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_expandloadu_epi8() { + fn test_mm512_mask_expandloadu_epi8() { let src = _mm512_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -4016,7 +4016,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101; - let r = _mm512_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm512_set_epi8( 32, 31, 30, 42, 29, 42, 42, 42, 28, 27, 42, 42, 26, 42, 25, 42, 24, 23, 22, 21, 42, 42, 42, 42, 42, 42, 42, 42, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 42, 42, 42, 42, @@ -4026,7 +4026,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_maskz_expandloadu_epi8() { + fn test_mm512_maskz_expandloadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, @@ -4034,7 +4034,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101; - let r = _mm512_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm512_set_epi8( 32, 31, 30, 0, 29, 0, 0, 0, 28, 27, 0, 0, 26, 0, 25, 0, 24, 23, 22, 21, 0, 0, 0, 0, 0, 0, 0, 0, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, @@ -4044,7 +4044,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi8() { + fn test_mm256_mask_expandloadu_epi8() { let src = _mm256_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -4052,7 +4052,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm256_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm256_set_epi8( 16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42, 42, 42, 42, 42, 42, 4, 3, 2, 1, @@ -4061,14 +4061,14 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi8() { + fn test_mm256_maskz_expandloadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm256_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm256_set_epi8( 16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 2, 1, @@ -4077,36 +4077,44 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi8() { + fn test_mm_mask_expandloadu_epi8() { let src = _mm_set1_epi8(42); let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm_set_epi8(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi8() { + fn test_mm_maskz_expandloadu_epi8() { let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm_set_epi8(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_compressstoreu_epi16() { + fn test_mm512_mask_compressstoreu_epi16() { let a = _mm512_set_epi16( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i16; 32]; - _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 32]); - _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a); + unsafe { + _mm512_mask_compressstoreu_epi16( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000, + a, + ); + } assert_eq!( &r, &[ @@ -4117,40 +4125,52 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi16() { + fn test_mm256_mask_compressstoreu_epi16() { let a = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i16; 16]; - _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 16]); - _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a); + unsafe { + _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi16() { + fn test_mm_mask_compressstoreu_epi16() { let a = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i16; 8]; - _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 8]); - _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a); + unsafe { + _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a); + } assert_eq!(&r, &[5, 6, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_compressstoreu_epi8() { + fn test_mm512_mask_compressstoreu_epi8() { let a = _mm512_set_epi8( 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i8; 64]; - _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 64]); - _mm512_mask_compressstoreu_epi8( - r.as_mut_ptr(), - 0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111, - a, - ); + unsafe { + _mm512_mask_compressstoreu_epi8( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111, + a, + ); + } assert_eq!( &r, &[ @@ -4162,15 +4182,23 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi8() { + fn test_mm256_mask_compressstoreu_epi8() { let a = _mm256_set_epi8( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i8; 32]; - _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 32]); - _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a); + unsafe { + _mm256_mask_compressstoreu_epi8( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000, + a, + ); + } assert_eq!( &r, &[ @@ -4181,12 +4209,16 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi8() { + fn test_mm_mask_compressstoreu_epi8() { let a = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i8; 16]; - _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 16]); - _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a); + unsafe { + _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } } diff --git a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs index a53d6d97e8a0c..91b6be2b09d78 100644 --- a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -242,127 +242,127 @@ mod tests { const BF16_EIGHT: u16 = 0b0_10000010_0000000; #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_bcstnebf16_ps() { + fn test_mm_bcstnebf16_ps() { let a = bf16::from_bits(BF16_ONE); - let r = _mm_bcstnebf16_ps(addr_of!(a)); + let r = unsafe { _mm_bcstnebf16_ps(addr_of!(a)) }; let e = _mm_set_ps(1., 1., 1., 1.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_bcstnebf16_ps() { + fn test_mm256_bcstnebf16_ps() { let a = bf16::from_bits(BF16_ONE); - let r = _mm256_bcstnebf16_ps(addr_of!(a)); + let r = unsafe { _mm256_bcstnebf16_ps(addr_of!(a)) }; let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_bcstnesh_ps() { + fn test_mm_bcstnesh_ps() { let a = 1.0_f16; - let r = _mm_bcstnesh_ps(addr_of!(a)); + let r = unsafe { _mm_bcstnesh_ps(addr_of!(a)) }; let e = _mm_set_ps(1., 1., 1., 1.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_bcstnesh_ps() { + fn test_mm256_bcstnesh_ps() { let a = 1.0_f16; - let r = _mm256_bcstnesh_ps(addr_of!(a)); + let r = unsafe { _mm256_bcstnesh_ps(addr_of!(a)) }; let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneebf16_ps() { + fn test_mm_cvtneebf16_ps() { let a = __m128bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm_cvtneebf16_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneebf16_ps(addr_of!(a)) }; let e = _mm_setr_ps(1., 3., 5., 7.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneebf16_ps() { + fn test_mm256_cvtneebf16_ps() { let a = __m256bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm256_cvtneebf16_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneebf16_ps(addr_of!(a)) }; let e = _mm256_setr_ps(1., 3., 5., 7., 1., 3., 5., 7.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneeph_ps() { + fn test_mm_cvtneeph_ps() { let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]); - let r = _mm_cvtneeph_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneeph_ps(addr_of!(a)) }; let e = _mm_setr_ps(1., 3., 5., 7.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneeph_ps() { + fn test_mm256_cvtneeph_ps() { let a = __m256h([ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]); - let r = _mm256_cvtneeph_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneeph_ps(addr_of!(a)) }; let e = _mm256_setr_ps(1., 3., 5., 7., 9., 11., 13., 15.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneobf16_ps() { + fn test_mm_cvtneobf16_ps() { let a = __m128bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm_cvtneobf16_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneobf16_ps(addr_of!(a)) }; let e = _mm_setr_ps(2., 4., 6., 8.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneobf16_ps() { + fn test_mm256_cvtneobf16_ps() { let a = __m256bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm256_cvtneobf16_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneobf16_ps(addr_of!(a)) }; let e = _mm256_setr_ps(2., 4., 6., 8., 2., 4., 6., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneoph_ps() { + fn test_mm_cvtneoph_ps() { let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]); - let r = _mm_cvtneoph_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneoph_ps(addr_of!(a)) }; let e = _mm_setr_ps(2., 4., 6., 8.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneoph_ps() { + fn test_mm256_cvtneoph_ps() { let a = __m256h([ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]); - let r = _mm256_cvtneoph_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneoph_ps(addr_of!(a)) }; let e = _mm256_setr_ps(2., 4., 6., 8., 10., 12., 14., 16.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneps_avx_pbh() { + fn test_mm_cvtneps_avx_pbh() { let a = _mm_setr_ps(1., 2., 3., 4.); - let r: u16x4 = transmute_copy(&_mm_cvtneps_avx_pbh(a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_avx_pbh(a)) }; let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneps_avx_pbh() { + fn test_mm256_cvtneps_avx_pbh() { let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); - let r: u16x8 = transmute(_mm256_cvtneps_avx_pbh(a)); + let r: u16x8 = _mm256_cvtneps_avx_pbh(a).as_u16x8(); let e = u16x8::new( BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ); diff --git a/library/stdarch/crates/core_arch/src/x86/f16c.rs b/library/stdarch/crates/core_arch/src/x86/f16c.rs index 0a26a9ff8d255..a0bb992bb9d4c 100644 --- a/library/stdarch/crates/core_arch/src/x86/f16c.rs +++ b/library/stdarch/crates/core_arch/src/x86/f16c.rs @@ -106,7 +106,7 @@ pub fn _mm256_cvtps_ph(a: __m256) -> __m128i { #[cfg(test)] mod tests { use crate::core_arch::assert_eq_const as assert_eq; - use crate::{core_arch::x86::*, mem::transmute}; + use crate::core_arch::x86::*; use stdarch_test::simd_test; const F16_ONE: i16 = 0x3c00; diff --git a/library/stdarch/crates/core_arch/src/x86/fxsr.rs b/library/stdarch/crates/core_arch/src/x86/fxsr.rs index 71fd52ca14963..08619efe7c9ef 100644 --- a/library/stdarch/crates/core_arch/src/x86/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86/fxsr.rs @@ -77,12 +77,14 @@ mod tests { #[simd_test(enable = "fxsr")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_fxsave() { + fn test_fxsave() { let mut a = FxsaveArea::new(); let mut b = FxsaveArea::new(); - fxsr::_fxsave(a.ptr()); - fxsr::_fxrstor(a.ptr()); - fxsr::_fxsave(b.ptr()); + unsafe { + fxsr::_fxsave(a.ptr()); + fxsr::_fxrstor(a.ptr()); + fxsr::_fxsave(b.ptr()); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs index 681b8ae330d49..e9ee27a7b823b 100644 --- a/library/stdarch/crates/core_arch/src/x86/gfni.rs +++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs @@ -898,25 +898,25 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8mul_epi8() { + fn test_mm512_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); - let expected = load_m512i_word(&expected, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; + let expected = unsafe { load_m512i_word(&expected, i) }; let result = _mm512_gf2p8mul_epi8(left, right); assert_eq_m512i(result, expected); } } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8mul_epi8() { + fn test_mm512_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; let result_zero = _mm512_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m512i(result_zero, _mm512_setzero_si512()); let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00; @@ -930,12 +930,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8mul_epi8() { + fn test_mm512_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; let result_left = _mm512_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m512i(result_left, left); let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00; @@ -948,25 +948,25 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8mul_epi8() { + fn test_mm256_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); - let expected = load_m256i_word(&expected, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; + let expected = unsafe { load_m256i_word(&expected, i) }; let result = _mm256_gf2p8mul_epi8(left, right); assert_eq_m256i(result, expected); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8mul_epi8() { + fn test_mm256_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; let result_zero = _mm256_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m256i(result_zero, _mm256_setzero_si256()); let mask_bytes: __mmask32 = 0x0F_F0_FF_00; @@ -980,12 +980,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8mul_epi8() { + fn test_mm256_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; let result_left = _mm256_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m256i(result_left, left); let mask_bytes: __mmask32 = 0x0F_F0_FF_00; @@ -998,25 +998,25 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8mul_epi8() { + fn test_mm_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); - let expected = load_m128i_word(&expected, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; + let expected = unsafe { load_m128i_word(&expected, i) }; let result = _mm_gf2p8mul_epi8(left, right); assert_eq_m128i(result, expected); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8mul_epi8() { + fn test_mm_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; let result_zero = _mm_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m128i(result_zero, _mm_setzero_si128()); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1030,12 +1030,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8mul_epi8() { + fn test_mm_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; let result_left = _mm_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m128i(result_left, left); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1048,7 +1048,7 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8affine_epi64_epi8() { + fn test_mm512_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1061,20 +1061,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let data = load_m512i_word(&bytes, i); + let data = unsafe { load_m512i_word(&bytes, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m512i(result, data); let result = _mm512_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m512i(result, constant_reference); - let data = load_m512i_word(&more_bytes, i); + let data = unsafe { load_m512i_word(&more_bytes, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m512i(result, data); let result = _mm512_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m512i(result, constant_reference); - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); - let reference = load_m512i_word(&references, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; + let reference = unsafe { load_m512i_word(&references, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m512i(result, reference); @@ -1082,13 +1082,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8affine_epi64_epi8() { + fn test_mm512_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; let result_zero = _mm512_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m512i(result_zero, _mm512_setzero_si512()); @@ -1104,13 +1104,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8affine_epi64_epi8() { + fn test_mm512_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&vectors, i); - let right = load_m512i_word(&matrices, i); + let left = unsafe { load_m512i_word(&vectors, i) }; + let right = unsafe { load_m512i_word(&matrices, i) }; let result_left = _mm512_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m512i(result_left, left); @@ -1125,7 +1125,7 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8affine_epi64_epi8() { + fn test_mm256_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1138,20 +1138,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let data = load_m256i_word(&bytes, i); + let data = unsafe { load_m256i_word(&bytes, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m256i(result, data); let result = _mm256_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m256i(result, constant_reference); - let data = load_m256i_word(&more_bytes, i); + let data = unsafe { load_m256i_word(&more_bytes, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m256i(result, data); let result = _mm256_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m256i(result, constant_reference); - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); - let reference = load_m256i_word(&references, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; + let reference = unsafe { load_m256i_word(&references, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m256i(result, reference); @@ -1159,13 +1159,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8affine_epi64_epi8() { + fn test_mm256_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; let result_zero = _mm256_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m256i(result_zero, _mm256_setzero_si256()); @@ -1181,13 +1181,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8affine_epi64_epi8() { + fn test_mm256_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&vectors, i); - let right = load_m256i_word(&matrices, i); + let left = unsafe { load_m256i_word(&vectors, i) }; + let right = unsafe { load_m256i_word(&matrices, i) }; let result_left = _mm256_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m256i(result_left, left); @@ -1202,7 +1202,7 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8affine_epi64_epi8() { + fn test_mm_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1215,20 +1215,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let data = load_m128i_word(&bytes, i); + let data = unsafe { load_m128i_word(&bytes, i) }; let result = _mm_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m128i(result, data); let result = _mm_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m128i(result, constant_reference); - let data = load_m128i_word(&more_bytes, i); + let data = unsafe { load_m128i_word(&more_bytes, i) }; let result = _mm_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m128i(result, data); let result = _mm_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m128i(result, constant_reference); - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); - let reference = load_m128i_word(&references, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; + let reference = unsafe { load_m128i_word(&references, i) }; let result = _mm_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m128i(result, reference); @@ -1236,13 +1236,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8affine_epi64_epi8() { + fn test_mm_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; let result_zero = _mm_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m128i(result_zero, _mm_setzero_si128()); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1257,13 +1257,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8affine_epi64_epi8() { + fn test_mm_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&vectors, i); - let right = load_m128i_word(&matrices, i); + let left = unsafe { load_m128i_word(&vectors, i) }; + let right = unsafe { load_m128i_word(&matrices, i) }; let result_left = _mm_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m128i(result_left, left); @@ -1278,7 +1278,7 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8affineinv_epi64_epi8() { + fn test_mm512_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1288,8 +1288,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_512 { - let input = load_m512i_word(&inputs, i); - let reference = load_m512i_word(&results, i); + let input = unsafe { load_m512i_word(&inputs, i) }; + let reference = unsafe { load_m512i_word(&results, i) }; let result = _mm512_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm512_gf2p8mul_epi8(result, input); assert_eq_m512i(remultiplied, reference); @@ -1300,8 +1300,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let vector = load_m512i_word(&vectors, i); - let matrix = load_m512i_word(&matrices, i); + let vector = unsafe { load_m512i_word(&vectors, i) }; + let matrix = unsafe { load_m512i_word(&matrices, i) }; let inv_vec = _mm512_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm512_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1314,21 +1314,21 @@ mod tests { let sbox_matrix = _mm512_set1_epi64(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_512 { - let reference = load_m512i_word(&AES_S_BOX, i); - let input = load_m512i_word(&inputs, i); + let reference = unsafe { load_m512i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m512i_word(&inputs, i) }; let result = _mm512_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m512i(result, reference); } } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; let result_zero = _mm512_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m512i(result_zero, _mm512_setzero_si512()); @@ -1344,13 +1344,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm512_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&vectors, i); - let right = load_m512i_word(&matrices, i); + let left = unsafe { load_m512i_word(&vectors, i) }; + let right = unsafe { load_m512i_word(&matrices, i) }; let result_left = _mm512_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m512i(result_left, left); @@ -1366,7 +1366,7 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8affineinv_epi64_epi8() { + fn test_mm256_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1376,8 +1376,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_256 { - let input = load_m256i_word(&inputs, i); - let reference = load_m256i_word(&results, i); + let input = unsafe { load_m256i_word(&inputs, i) }; + let reference = unsafe { load_m256i_word(&results, i) }; let result = _mm256_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm256_gf2p8mul_epi8(result, input); assert_eq_m256i(remultiplied, reference); @@ -1388,8 +1388,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let vector = load_m256i_word(&vectors, i); - let matrix = load_m256i_word(&matrices, i); + let vector = unsafe { load_m256i_word(&vectors, i) }; + let matrix = unsafe { load_m256i_word(&matrices, i) }; let inv_vec = _mm256_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm256_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1402,21 +1402,21 @@ mod tests { let sbox_matrix = _mm256_set1_epi64x(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_256 { - let reference = load_m256i_word(&AES_S_BOX, i); - let input = load_m256i_word(&inputs, i); + let reference = unsafe { load_m256i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m256i_word(&inputs, i) }; let result = _mm256_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m256i(result, reference); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; let result_zero = _mm256_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m256i(result_zero, _mm256_setzero_si256()); @@ -1432,13 +1432,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm256_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&vectors, i); - let right = load_m256i_word(&matrices, i); + let left = unsafe { load_m256i_word(&vectors, i) }; + let right = unsafe { load_m256i_word(&matrices, i) }; let result_left = _mm256_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m256i(result_left, left); @@ -1454,7 +1454,7 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8affineinv_epi64_epi8() { + fn test_mm_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1464,8 +1464,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_128 { - let input = load_m128i_word(&inputs, i); - let reference = load_m128i_word(&results, i); + let input = unsafe { load_m128i_word(&inputs, i) }; + let reference = unsafe { load_m128i_word(&results, i) }; let result = _mm_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm_gf2p8mul_epi8(result, input); assert_eq_m128i(remultiplied, reference); @@ -1476,8 +1476,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let vector = load_m128i_word(&vectors, i); - let matrix = load_m128i_word(&matrices, i); + let vector = unsafe { load_m128i_word(&vectors, i) }; + let matrix = unsafe { load_m128i_word(&matrices, i) }; let inv_vec = _mm_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1490,21 +1490,21 @@ mod tests { let sbox_matrix = _mm_set1_epi64x(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_128 { - let reference = load_m128i_word(&AES_S_BOX, i); - let input = load_m128i_word(&inputs, i); + let reference = unsafe { load_m128i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m128i_word(&inputs, i) }; let result = _mm_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m128i(result, reference); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; let result_zero = _mm_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m128i(result_zero, _mm_setzero_si128()); @@ -1520,13 +1520,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&vectors, i); - let right = load_m128i_word(&matrices, i); + let left = unsafe { load_m128i_word(&vectors, i) }; + let right = unsafe { load_m128i_word(&matrices, i) }; let result_left = _mm_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m128i(result_left, left); diff --git a/library/stdarch/crates/core_arch/src/x86/kl.rs b/library/stdarch/crates/core_arch/src/x86/kl.rs index 26e5a46c62934..7cb52847f50d1 100644 --- a/library/stdarch/crates/core_arch/src/x86/kl.rs +++ b/library/stdarch/crates/core_arch/src/x86/kl.rs @@ -352,45 +352,47 @@ mod tests { use stdarch_test::simd_test; #[target_feature(enable = "kl")] - unsafe fn encodekey128() -> [u8; 48] { + fn encodekey128() -> [u8; 48] { let mut handle = [0; 48]; - let _ = _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()); + let _ = unsafe { _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()) }; handle } #[target_feature(enable = "kl")] - unsafe fn encodekey256() -> [u8; 64] { + fn encodekey256() -> [u8; 64] { let mut handle = [0; 64]; - let _ = _mm_encodekey256_u32( - 0, - _mm_setzero_si128(), - _mm_setzero_si128(), - handle.as_mut_ptr(), - ); + let _ = unsafe { + _mm_encodekey256_u32( + 0, + _mm_setzero_si128(), + _mm_setzero_si128(), + handle.as_mut_ptr(), + ) + }; handle } #[simd_test(enable = "kl")] - unsafe fn test_mm_encodekey128_u32() { + fn test_mm_encodekey128_u32() { encodekey128(); } #[simd_test(enable = "kl")] - unsafe fn test_mm_encodekey256_u32() { + fn test_mm_encodekey256_u32() { encodekey256(); } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesenc128kl_u8() { + fn test_mm_aesenc128kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -398,16 +400,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesdec128kl_u8() { + fn test_mm_aesdec128kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -415,16 +417,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesenc256kl_u8() { + fn test_mm_aesenc256kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -432,16 +434,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesdec256kl_u8() { + fn test_mm_aesdec256kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -449,16 +451,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesencwide128kl_u8() { + fn test_mm_aesencwide128kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -468,16 +474,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesdecwide128kl_u8() { + fn test_mm_aesdecwide128kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -487,16 +497,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesencwide256kl_u8() { + fn test_mm_aesencwide256kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -506,16 +520,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesdecwide256kl_u8() { + fn test_mm_aesdecwide256kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs index b37e7571eb8f7..c88bd6592d784 100644 --- a/library/stdarch/crates/core_arch/src/x86/rtm.rs +++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs @@ -120,13 +120,15 @@ mod tests { use crate::core_arch::x86::*; #[simd_test(enable = "rtm")] - unsafe fn test_xbegin() { + fn test_xbegin() { let mut x = 0; for _ in 0..10 { - let code = _xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { x += 1; - _xend(); + unsafe { + _xend(); + } assert_eq!(x, 1); break; } @@ -135,19 +137,23 @@ mod tests { } #[simd_test(enable = "rtm")] - unsafe fn test_xabort() { + fn test_xabort() { const ABORT_CODE: u32 = 42; // aborting outside a transactional region does nothing - _xabort::(); + unsafe { + _xabort::(); + } for _ in 0..10 { let mut x = 0; - let code = rtm::_xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { x += 1; - rtm::_xabort::(); + unsafe { + _xabort::(); + } } else if code & _XABORT_EXPLICIT != 0 { - let test_abort_code = rtm::_xabort_code(code); + let test_abort_code = _xabort_code(code); assert_eq!(test_abort_code, ABORT_CODE); } assert_eq!(x, 0); @@ -155,14 +161,16 @@ mod tests { } #[simd_test(enable = "rtm")] - unsafe fn test_xtest() { - assert_eq!(_xtest(), 0); + fn test_xtest() { + assert_eq!(unsafe { _xtest() }, 0); for _ in 0..10 { - let code = rtm::_xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { - let in_tx = _xtest(); - rtm::_xend(); + let in_tx = unsafe { _xtest() }; + unsafe { + _xend(); + } // putting the assert inside the transaction would abort the transaction on fail // without any output/panic/etc diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs index f167e8381d272..1812721db4d30 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse.rs @@ -3147,21 +3147,21 @@ mod tests { } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load_ss() { + const fn test_mm_load_ss() { let a = 42.0f32; - let r = _mm_load_ss(ptr::addr_of!(a)); + let r = unsafe { _mm_load_ss(ptr::addr_of!(a)) }; assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load1_ps() { + const fn test_mm_load1_ps() { let a = 42.0f32; - let r = _mm_load1_ps(ptr::addr_of!(a)); + let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) }; assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load_ps() { + const fn test_mm_load_ps() { let vals = Memory { data: [1.0f32, 2.0, 3.0, 4.0], }; @@ -3169,21 +3169,21 @@ mod tests { // guaranteed to be aligned to 16 bytes let p = vals.data.as_ptr(); - let r = _mm_load_ps(p); + let r = unsafe { _mm_load_ps(p) }; let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_loadu_ps() { + const fn test_mm_loadu_ps() { let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; - let p = vals.as_ptr().add(3); - let r = _mm_loadu_ps(black_box(p)); + let p = unsafe { vals.as_ptr().add(3) }; + let r = unsafe { _mm_loadu_ps(black_box(p)) }; assert_eq_m128(r, _mm_setr_ps(4.0, 5.0, 6.0, 7.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_loadr_ps() { + const fn test_mm_loadr_ps() { let vals = Memory { data: [1.0f32, 2.0, 3.0, 4.0], }; @@ -3191,16 +3191,18 @@ mod tests { // guaranteed to be aligned to 16 bytes let p = vals.data.as_ptr(); - let r = _mm_loadr_ps(p); + let r = unsafe { _mm_loadr_ps(p) }; let e = _mm_setr_ps(4.0, 3.0, 2.0, 1.0); assert_eq_m128(r, e); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store_ss() { + const fn test_mm_store_ss() { let mut vals = [0.0f32; 8]; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - _mm_store_ss(vals.as_mut_ptr().add(1), a); + unsafe { + _mm_store_ss(vals.as_mut_ptr().add(1), a); + } assert_eq!(vals[0], 0.0); assert_eq!(vals[1], 1.0); @@ -3208,46 +3210,52 @@ mod tests { } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store1_ps() { + const fn test_mm_store1_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_store1_ps(p, *black_box(&a)); + unsafe { + _mm_store1_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store_ps() { + const fn test_mm_store_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_store_ps(p, *black_box(&a)); + unsafe { + _mm_store_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_storer_ps() { + const fn test_mm_storer_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_storer_ps(p, *black_box(&a)); + unsafe { + _mm_storer_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [4.0, 3.0, 2.0, 1.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_storeu_ps() { + const fn test_mm_storeu_ps() { #[repr(align(16))] struct Memory8 { data: [f32; 8], @@ -3258,9 +3266,11 @@ mod tests { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be *not* aligned to 16 bytes - let p = vals.data.as_mut_ptr().offset(1); + let p = unsafe { vals.data.as_mut_ptr().offset(1) }; - _mm_storeu_ps(p, *black_box(&a)); + unsafe { + _mm_storeu_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]); } @@ -3315,11 +3325,13 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_ps() { + fn test_mm_stream_ps() { let a = _mm_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 4] }; - _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..4 { assert_eq!(mem.data[i], get_m128(a, i)); diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs index fc010e8467bbd..c58e1b86a4707 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs @@ -3291,9 +3291,11 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_clflush() { + fn test_mm_clflush() { let x = 0_u8; - _mm_clflush(ptr::addr_of!(x)); + unsafe { + _mm_clflush(ptr::addr_of!(x)); + } } #[simd_test(enable = "sse2")] @@ -3725,7 +3727,7 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_sll_epi16() { + fn test_mm_sll_epi16() { let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF); let r = _mm_sll_epi16(a, _mm_set_epi64x(0, 4)); assert_eq_m128i( @@ -4071,7 +4073,7 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_cvtps_epi32() { + fn test_mm_cvtps_epi32() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let r = _mm_cvtps_epi32(a); assert_eq_m128i(r, _mm_setr_epi32(1, 2, 3, 4)); @@ -4178,23 +4180,23 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadl_epi64() { + const fn test_mm_loadl_epi64() { let a = _mm_setr_epi64x(6, 5); - let r = _mm_loadl_epi64(ptr::addr_of!(a)); + let r = unsafe { _mm_loadl_epi64(ptr::addr_of!(a)) }; assert_eq_m128i(r, _mm_setr_epi64x(6, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_si128() { + const fn test_mm_load_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_load_si128(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_load_si128(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si128() { + const fn test_mm_loadu_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_loadu_si128(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si128(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } @@ -4202,7 +4204,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_maskmoveu_si128() { + fn test_mm_maskmoveu_si128() { let a = _mm_set1_epi8(9); #[rustfmt::skip] let mask = _mm_set_epi8( @@ -4210,33 +4212,41 @@ mod tests { 0, 0, 0, 0, 0, 0, 0, 0, ); let mut r = _mm_set1_epi8(0); - _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8); + unsafe { + _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8); + } _mm_sfence(); let e = _mm_set_epi8(0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_si128() { + const fn test_mm_store_si128() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi8(0); - _mm_store_si128(&mut r, a); + unsafe { + _mm_store_si128(&mut r, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si128() { + const fn test_mm_storeu_si128() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi8(0); - _mm_storeu_si128(&mut r, a); + unsafe { + _mm_storeu_si128(&mut r, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storel_epi64() { + const fn test_mm_storel_epi64() { let a = _mm_setr_epi64x(2, 9); let mut r = _mm_set1_epi8(0); - _mm_storel_epi64(&mut r, a); + unsafe { + _mm_storel_epi64(&mut r, a); + } assert_eq_m128i(r, _mm_setr_epi64x(2, 0)); } @@ -4244,10 +4254,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si128() { + fn test_mm_stream_si128() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = _mm_undefined_si128(); - _mm_stream_si128(ptr::addr_of_mut!(r), a); + unsafe { + _mm_stream_si128(ptr::addr_of_mut!(r), a); + } _mm_sfence(); assert_eq_m128i(r, a); } @@ -4256,10 +4268,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si32() { + fn test_mm_stream_si32() { let a: i32 = 7; let mut mem = boxed::Box::::new(-1); - _mm_stream_si32(ptr::addr_of_mut!(*mem), a); + unsafe { + _mm_stream_si32(ptr::addr_of_mut!(*mem), a); + } _mm_sfence(); assert_eq!(a, *mem); } @@ -4909,40 +4923,40 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_pd() { + const fn test_mm_load_pd() { let mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], }; let vals = &mem.data; let d = vals.as_ptr(); - let r = _mm_load_pd(d); + let r = unsafe { _mm_load_pd(d) }; assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_sd() { + const fn test_mm_load_sd() { let a = 1.; let expected = _mm_setr_pd(a, 0.); - let r = _mm_load_sd(&a); + let r = unsafe { _mm_load_sd(&a) }; assert_eq_m128d(r, expected); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadh_pd() { + const fn test_mm_loadh_pd() { let a = _mm_setr_pd(1., 2.); let b = 3.; let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.); - let r = _mm_loadh_pd(a, &b); + let r = unsafe { _mm_loadh_pd(a, &b) }; assert_eq_m128d(r, expected); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadl_pd() { + const fn test_mm_loadl_pd() { let a = _mm_setr_pd(1., 2.); let b = 3.; let expected = _mm_setr_pd(3., get_m128d(a, 1)); - let r = _mm_loadl_pd(a, &b); + let r = unsafe { _mm_loadl_pd(a, &b) }; assert_eq_m128d(r, expected); } @@ -4950,7 +4964,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_pd() { + fn test_mm_stream_pd() { #[repr(align(128))] struct Memory { pub data: [f64; 2], @@ -4958,7 +4972,9 @@ mod tests { let a = _mm_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 2] }; - _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..2 { assert_eq!(mem.data[i], get_m128d(a, i)); @@ -4966,132 +4982,154 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_sd() { + const fn test_mm_store_sd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_store_sd(&mut dest, a); + unsafe { + _mm_store_sd(&mut dest, a); + } assert_eq!(dest, _mm_cvtsd_f64(a)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_pd() { + const fn test_mm_store_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store_pd(d, *black_box(&a)); + unsafe { + _mm_store_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 2.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_pd() { + const fn test_mm_storeu_pd() { // guaranteed to be aligned to 16 bytes let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); // so p is *not* aligned to 16 bytes - let p = vals.as_mut_ptr().offset(1); - _mm_storeu_pd(p, *black_box(&a)); + unsafe { + let p = vals.as_mut_ptr().offset(1); + _mm_storeu_pd(p, *black_box(&a)); + } assert_eq!(*vals, [0.0, 1.0, 2.0, 0.0]); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si16() { + const fn test_mm_storeu_si16() { let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8); let mut r = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16); - _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi16(1, 10, 11, 12, 13, 14, 15, 16); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si32() { + const fn test_mm_storeu_si32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = _mm_setr_epi32(5, 6, 7, 8); - _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi32(1, 6, 7, 8); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si64() { + const fn test_mm_storeu_si64() { let a = _mm_setr_epi64x(1, 2); let mut r = _mm_setr_epi64x(3, 4); - _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi64x(1, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store1_pd() { + const fn test_mm_store1_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store1_pd(d, *black_box(&a)); + unsafe { + _mm_store1_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_pd1() { + const fn test_mm_store_pd1() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store_pd1(d, *black_box(&a)); + unsafe { + _mm_store_pd1(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storer_pd() { + const fn test_mm_storer_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_storer_pd(d, *black_box(&a)); + unsafe { + _mm_storer_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 2.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeh_pd() { + const fn test_mm_storeh_pd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_storeh_pd(&mut dest, a); + unsafe { + _mm_storeh_pd(&mut dest, a); + } assert_eq!(dest, get_m128d(a, 1)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storel_pd() { + const fn test_mm_storel_pd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_storel_pd(&mut dest, a); + unsafe { + _mm_storel_pd(&mut dest, a); + } assert_eq!(dest, _mm_cvtsd_f64(a)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadr_pd() { + const fn test_mm_loadr_pd() { let mut mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], }; let vals = &mut mem.data; let d = vals.as_ptr(); - let r = _mm_loadr_pd(d); + let r = unsafe { _mm_loadr_pd(d) }; assert_eq_m128d(r, _mm_setr_pd(2.0, 1.0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_pd() { + const fn test_mm_loadu_pd() { // guaranteed to be aligned to 16 bytes let mut mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], @@ -5099,31 +5137,31 @@ mod tests { let vals = &mut mem.data; // so this will *not* be aligned to 16 bytes - let d = vals.as_ptr().offset(1); + let d = unsafe { vals.as_ptr().offset(1) }; - let r = _mm_loadu_pd(d); + let r = unsafe { _mm_loadu_pd(d) }; let e = _mm_setr_pd(2.0, 3.0); assert_eq_m128d(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si16() { + const fn test_mm_loadu_si16() { let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8); - let r = _mm_loadu_si16(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si16(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si32() { + const fn test_mm_loadu_si32() { let a = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm_loadu_si32(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si32(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi32(1, 0, 0, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si64() { + const fn test_mm_loadu_si64() { let a = _mm_setr_epi64x(5, 6); - let r = _mm_loadu_si64(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si64(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi64x(5, 0)); } @@ -5302,16 +5340,16 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load1_pd() { + const fn test_mm_load1_pd() { let d = -5.0; - let r = _mm_load1_pd(&d); + let r = unsafe { _mm_load1_pd(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_pd1() { + const fn test_mm_load_pd1() { let d = -5.0; - let r = _mm_load_pd1(&d); + let r = unsafe { _mm_load_pd1(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } diff --git a/library/stdarch/crates/core_arch/src/x86/sse3.rs b/library/stdarch/crates/core_arch/src/x86/sse3.rs index 68817856f44ab..e4c75702544d9 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse3.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse3.rs @@ -239,7 +239,7 @@ mod tests { } #[simd_test(enable = "sse3")] - unsafe fn test_mm_lddqu_si128() { + fn test_mm_lddqu_si128() { #[rustfmt::skip] let a = _mm_setr_epi8( 1, 2, 3, 4, @@ -247,7 +247,7 @@ mod tests { 9, 10, 11, 12, 13, 14, 15, 16, ); - let r = _mm_lddqu_si128(&a); + let r = unsafe { _mm_lddqu_si128(&a) }; assert_eq_m128i(a, r); } @@ -273,9 +273,9 @@ mod tests { } #[simd_test(enable = "sse3")] - const unsafe fn test_mm_loaddup_pd() { + const fn test_mm_loaddup_pd() { let d = -5.0; - let r = _mm_loaddup_pd(&d); + let r = unsafe { _mm_loaddup_pd(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } } diff --git a/library/stdarch/crates/core_arch/src/x86/sse41.rs b/library/stdarch/crates/core_arch/src/x86/sse41.rs index a499bf898b809..7ad4306f36f21 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse41.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse41.rs @@ -1219,20 +1219,20 @@ mod tests { } #[simd_test(enable = "sse4.1")] - const unsafe fn test_mm_blendv_pd() { + const fn test_mm_blendv_pd() { let a = _mm_set1_pd(0.0); let b = _mm_set1_pd(1.0); - let mask = transmute(_mm_setr_epi64x(0, -1)); + let mask = _mm_castsi128_pd(_mm_setr_epi64x(0, -1)); let r = _mm_blendv_pd(a, b, mask); let e = _mm_setr_pd(0.0, 1.0); assert_eq_m128d(r, e); } #[simd_test(enable = "sse4.1")] - const unsafe fn test_mm_blendv_ps() { + const fn test_mm_blendv_ps() { let a = _mm_set1_ps(0.0); let b = _mm_set1_ps(1.0); - let mask = transmute(_mm_setr_epi32(0, -1, 0, -1)); + let mask = _mm_castsi128_ps(_mm_setr_epi32(0, -1, 0, -1)); let r = _mm_blendv_ps(a, b, mask); let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0); assert_eq_m128(r, e); @@ -1949,9 +1949,9 @@ mod tests { } #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_stream_load_si128() { + fn test_mm_stream_load_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } } diff --git a/library/stdarch/crates/core_arch/src/x86/sse42.rs b/library/stdarch/crates/core_arch/src/x86/sse42.rs index 65d1fe4d62339..55e22592637f1 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse42.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse42.rs @@ -613,6 +613,7 @@ mod tests { use crate::core_arch::assert_eq_const as assert_eq; use stdarch_test::simd_test; + use crate::core_arch::simd::*; use crate::core_arch::x86::*; use std::ptr; @@ -625,7 +626,7 @@ mod tests { assert!(s.len() <= 16); let mut array = [0u8; 16]; array[..s.len()].copy_from_slice(s); - unsafe { transmute(array) } + u8x16::from_array(array).as_m128i() } #[simd_test(enable = "sse4.2")] diff --git a/library/stdarch/crates/core_arch/src/x86/sse4a.rs b/library/stdarch/crates/core_arch/src/x86/sse4a.rs index 020baeff152d9..f36b879a030e3 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse4a.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse4a.rs @@ -206,7 +206,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_sd() { + fn test_mm_stream_sd() { let mut mem = MemoryF64 { data: [1.0_f64, 2.0], }; @@ -216,7 +216,9 @@ mod tests { let x = _mm_setr_pd(3.0, 4.0); - _mm_stream_sd(d, x); + unsafe { + _mm_stream_sd(d, x); + } _mm_sfence(); } assert_eq!(mem.data[0], 3.0); @@ -232,7 +234,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_ss() { + fn test_mm_stream_ss() { let mut mem = MemoryF32 { data: [1.0_f32, 2.0, 3.0, 4.0], }; @@ -242,7 +244,9 @@ mod tests { let x = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); - _mm_stream_ss(d, x); + unsafe { + _mm_stream_ss(d, x); + } _mm_sfence(); } assert_eq!(mem.data[0], 5.0); diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs index 653eb28c42680..e22d3580ff463 100644 --- a/library/stdarch/crates/core_arch/src/x86/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs @@ -197,47 +197,53 @@ mod tests { #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsave() { + fn test_xsave() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsave(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsave(b.ptr(), m); + unsafe { + _xsave(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsave(b.ptr(), m); + } } #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xgetbv() { + fn test_xgetbv() { let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK; - let xcr: u64 = _xgetbv(xcr_n); - let xcr_cpy: u64 = _xgetbv(xcr_n); + let xcr: u64 = unsafe { _xgetbv(xcr_n) }; + let xcr_cpy: u64 = unsafe { _xgetbv(xcr_n) }; assert_eq!(xcr, xcr_cpy); } #[simd_test(enable = "xsave,xsaveopt")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsaveopt() { + fn test_xsaveopt() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsaveopt(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsaveopt(b.ptr(), m); + unsafe { + _xsaveopt(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsaveopt(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsavec")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsavec() { + fn test_xsavec() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsavec(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsavec(b.ptr(), m); + unsafe { + _xsavec(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsavec(b.ptr(), m); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/amx.rs b/library/stdarch/crates/core_arch/src/x86_64/amx.rs index f372f7066d510..4e20e014cf20a 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/amx.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/amx.rs @@ -581,267 +581,297 @@ mod tests { } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_loadconfig() { - let config = __tilecfg::default(); - _tile_loadconfig(config.as_ptr()); - _tile_release(); + fn test_tile_loadconfig() { + unsafe { + let config = __tilecfg::default(); + _tile_loadconfig(config.as_ptr()); + _tile_release(); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_storeconfig() { - let config = __tilecfg::new(1, 0, [32; 8], [8; 8]); - _tile_loadconfig(config.as_ptr()); - let mut _config = __tilecfg::default(); - _tile_storeconfig(_config.as_mut_ptr()); - _tile_release(); - assert_eq!(config, _config); + fn test_tile_storeconfig() { + unsafe { + let config = __tilecfg::new(1, 0, [32; 8], [8; 8]); + _tile_loadconfig(config.as_ptr()); + let mut _config = __tilecfg::default(); + _tile_storeconfig(_config.as_mut_ptr()); + _tile_release(); + assert_eq!(config, _config); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_zero() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[0; 64]; 16]); + fn test_tile_zero() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mut out = [[1_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[0; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_stored() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[0; 64]; 16]); + fn test_tile_stored() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mut out = [[1_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[0; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_loadd() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_loadd::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_loadd() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_loadd::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_stream_loadd() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_stream_loadd() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_release() { - _tile_release(); + fn test_tile_release() { + unsafe { + _tile_release(); + } } #[simd_test(enable = "amx-bf16,avx512f")] - unsafe fn test_tile_dpbf16ps() { - _init_amx(); - let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits(); - let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits(); - let ones: [u8; 1024] = transmute([bf16_1; 512]); - let twos: [u8; 1024] = transmute([bf16_2; 512]); - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbf16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_dpbf16ps() { + unsafe { + _init_amx(); + let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits(); + let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits(); + let ones: [u8; 1024] = transmute([bf16_1; 512]); + let twos: [u8; 1024] = transmute([bf16_2; 512]); + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbf16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbssd() { - _init_amx(); - let ones = [-1_i8; 1024]; - let twos = [-2_i8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); - _tile_dpbssd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[128_i32; 16]; 16]); + fn test_tile_dpbssd() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); + _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_dpbssd::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbsud() { - _init_amx(); - let ones = [-1_i8; 1024]; - let twos = [2_u8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbsud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[-128_i32; 16]; 16]); + fn test_tile_dpbsud() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbsud::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[-128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbusd() { - _init_amx(); - let ones = [1_u8; 1024]; - let twos = [-2_i8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); - _tile_dpbusd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[-128_i32; 16]; 16]); + fn test_tile_dpbusd() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_dpbusd::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[-128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbuud() { - _init_amx(); - let ones = [1_u8; 1024]; - let twos = [2_u8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbuud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[128_i32; 16]; 16]); + fn test_tile_dpbuud() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbuud::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-fp16")] - unsafe fn test_tile_dpfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_dpfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_dpfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_dpfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-complex")] - unsafe fn test_tile_cmmimfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_cmmimfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_cmmimfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_cmmimfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-complex")] - unsafe fn test_tile_cmmrlfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_cmmrlfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[0f32; 16]; 16]); + fn test_tile_cmmrlfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_cmmrlfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[0f32; 16]; 16]); + } } const BF8_ONE: u8 = 0x3c; @@ -850,223 +880,245 @@ mod tests { const HF8_TWO: u8 = 0x40; #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dpbf8ps() { - _init_amx(); - let ones = [BF8_ONE; 1024]; - let twos = [BF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dpbf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dpbhf8ps() { - _init_amx(); - let ones = [BF8_ONE; 1024]; - let twos = [HF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbhf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dpbhf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbhf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dphbf8ps() { - _init_amx(); - let ones = [HF8_ONE; 1024]; - let twos = [BF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dphbf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dphbf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dphbf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dphf8ps() { - _init_amx(); - let ones = [HF8_ONE; 1024]; - let twos = [HF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dphf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dphf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dphf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-movrs")] - unsafe fn test_tile_loaddrs() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_loaddrs() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-movrs")] - unsafe fn test_tile_stream_loaddrs() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_stream_loaddrs() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_movrow() { - _init_amx(); - let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); - - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_movrow::<0>(i); - assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + fn test_tile_movrow() { + unsafe { + _init_amx(); + let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_movrow::<0>(i); + assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + } } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowd2ps() { - _init_amx(); - let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); - - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowd2ps::<0>(i); - assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + fn test_tile_cvtrowd2ps() { + unsafe { + _init_amx(); + let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowd2ps::<0>(i); + assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + } } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowps2phh() { - _init_amx(); - let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowps2phh::<0>(i); - assert_eq!( - *row.as_f16x32().as_array(), - array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) - ); + fn test_tile_cvtrowps2phh() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2phh::<0>(i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) + ); + } } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowps2phl() { - _init_amx(); - let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowps2phl::<0>(i); - assert_eq!( - *row.as_f16x32().as_array(), - array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) - ); + fn test_tile_cvtrowps2phl() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2phl::<0>(i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) + ); + } } } #[simd_test(enable = "amx-tf32")] - unsafe fn test_tile_mmultf32ps() { - _init_amx(); - let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _]; - let mut res = [[0.0; 16]; 16]; - - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(a.as_ptr().cast(), 64); - _tile_loadd::<2>(b.as_ptr().cast(), 64); - _tile_mmultf32ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - - let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32)); - assert_eq!(res, expected); + fn test_tile_mmultf32ps() { + unsafe { + _init_amx(); + let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _]; + let mut res = [[0.0; 16]; 16]; + + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(a.as_ptr().cast(), 64); + _tile_loadd::<2>(b.as_ptr().cast(), 64); + _tile_mmultf32ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + + let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32)); + assert_eq!(res, expected); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs index 368fb0c238e4c..0fd9b09363d4b 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs @@ -7446,81 +7446,81 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_pd() { + fn test_mm512_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_pd::<8>(index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_pd() { + fn test_mm512_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); let src = _mm512_set1_pd(2.); let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_pd() { + fn test_mm512_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_pd::<8>(index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_pd() { + fn test_mm512_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); let src = _mm512_set1_pd(2.); let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_ps() { + fn test_mm512_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_ps::<4>(index, arr.as_ptr()) }; assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_ps() { + fn test_mm512_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); let src = _mm256_set1_ps(2.); let mask = 0b10101010; #[rustfmt::skip] let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()) }; assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_epi64() { + fn test_mm512_i32gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_epi64::<8>(index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_epi64() { + fn test_mm512_mask_i32gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7529,24 +7529,24 @@ mod tests { let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_epi64() { + fn test_mm512_i64gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_epi64::<8>(index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_epi64() { + fn test_mm512_mask_i64gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7555,24 +7555,24 @@ mod tests { let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_epi32() { + fn test_mm512_i64gather_epi32() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32); + let r = unsafe { _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32) }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_epi32() { + fn test_mm512_mask_i64gather_epi32() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7581,17 +7581,21 @@ mod tests { let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32); + let r = unsafe { + _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32) + }; assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_pd() { + fn test_mm512_i32scatter_pd() { let mut arr = [0f64; 128]; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f64; @@ -7600,13 +7604,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_pd() { + fn test_mm512_mask_i32scatter_pd() { let mut arr = [0f64; 128]; let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f64; @@ -7615,12 +7621,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_pd() { + fn test_mm512_i64scatter_pd() { let mut arr = [0f64; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f64; @@ -7629,13 +7637,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_pd() { + fn test_mm512_mask_i64scatter_pd() { let mut arr = [0f64; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f64; @@ -7644,12 +7654,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_ps() { + fn test_mm512_i64scatter_ps() { let mut arr = [0f32; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 4 is word-addressing - _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f32; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f32; @@ -7658,13 +7670,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_ps() { + fn test_mm512_mask_i64scatter_ps() { let mut arr = [0f32; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 4 is word-addressing - _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f32; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f32; @@ -7673,12 +7687,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_epi64() { + fn test_mm512_i32scatter_epi64() { let mut arr = [0i64; 128]; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i64; @@ -7687,13 +7703,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_epi64() { + fn test_mm512_mask_i32scatter_epi64() { let mut arr = [0i64; 128]; let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i64; @@ -7702,12 +7720,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_epi64() { + fn test_mm512_i64scatter_epi64() { let mut arr = [0i64; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i64; @@ -7716,13 +7736,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_epi64() { + fn test_mm512_mask_i64scatter_epi64() { let mut arr = [0i64; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i64; @@ -7731,12 +7753,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_epi32() { + fn test_mm512_i64scatter_epi32() { let mut arr = [0i32; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 4 is word-addressing - _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i32; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i32; @@ -7745,13 +7769,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_epi32() { + fn test_mm512_mask_i64scatter_epi32() { let mut arr = [0i32; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 4 is word-addressing - _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i32; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i32; @@ -7760,559 +7786,640 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32logather_epi64() { + fn test_mm512_i32logather_epi64() { let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()); + let r = unsafe { _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); assert_eq_m512i(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32logather_epi64() { + fn test_mm512_mask_i32logather_epi64() { let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16); let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = unsafe { + _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) + }; let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16); assert_eq_m512i(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32logather_pd() { + fn test_mm512_i32logather_pd() { let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()); + let r = unsafe { _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); assert_eq_m512d(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32logather_pd() { + fn test_mm512_mask_i32logather_pd() { let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.); let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.); assert_eq_m512d(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32loscatter_epi64() { + fn test_mm512_i32loscatter_epi64() { let mut base_addr: [i64; 8] = [0; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); - _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4, 5, 6, 7, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32loscatter_epi64() { + fn test_mm512_mask_i32loscatter_epi64() { let mut base_addr: [i64; 8] = [0; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); - _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0, 2, 0, 4, 0, 6, 0, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32loscatter_pd() { + fn test_mm512_i32loscatter_pd() { let mut base_addr: [f64; 8] = [0.; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); - _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4., 5., 6., 7., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32loscatter_pd() { + fn test_mm512_mask_i32loscatter_pd() { let mut base_addr: [f64; 8] = [0.; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); - _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0., 2., 0., 4., 0., 6., 0., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_epi32() { + fn test_mm_mmask_i32gather_epi32() { let base_addr: [i32; 4] = [1, 2, 3, 4]; let src = _mm_setr_epi32(5, 6, 7, 8); let vindex = _mm_setr_epi32(1, 2, 3, 0); - let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 6, 4, 8); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_epi64() { + fn test_mm_mmask_i32gather_epi64() { let base_addr: [i64; 2] = [1, 2]; let src = _mm_setr_epi64x(5, 6); let vindex = _mm_setr_epi32(1, 0, -1, -1); - let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi64x(2, 6); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_pd() { + fn test_mm_mmask_i32gather_pd() { let base_addr: [f64; 2] = [1., 2.]; let src = _mm_setr_pd(5., 6.); let vindex = _mm_setr_epi32(1, 0, -1, -1); - let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_pd(2., 6.); assert_eq_m128d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_ps() { + fn test_mm_mmask_i32gather_ps() { let base_addr: [f32; 4] = [1., 2., 3., 4.]; let src = _mm_setr_ps(5., 6., 7., 8.); let vindex = _mm_setr_epi32(1, 2, 3, 0); - let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 6., 4., 8.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_epi32() { + fn test_mm_mmask_i64gather_epi32() { let base_addr: [i32; 2] = [1, 2]; let src = _mm_setr_epi32(5, 6, 7, 8); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 6, 0, 0); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_epi64() { + fn test_mm_mmask_i64gather_epi64() { let base_addr: [i64; 2] = [1, 2]; let src = _mm_setr_epi64x(5, 6); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi64x(2, 6); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_pd() { + fn test_mm_mmask_i64gather_pd() { let base_addr: [f64; 2] = [1., 2.]; let src = _mm_setr_pd(5., 6.); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_pd(2., 6.); assert_eq_m128d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_ps() { + fn test_mm_mmask_i64gather_ps() { let base_addr: [f32; 2] = [1., 2.]; let src = _mm_setr_ps(5., 6., 7., 8.); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 6., 0., 0.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_epi32() { + fn test_mm256_mmask_i32gather_epi32() { let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16); let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); - let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = unsafe { + _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) + }; let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_epi64() { + fn test_mm256_mmask_i32gather_epi64() { let base_addr: [i64; 4] = [1, 2, 3, 4]; let src = _mm256_setr_epi64x(9, 10, 11, 12); let vindex = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_epi64x(2, 10, 4, 12); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_pd() { + fn test_mm256_mmask_i32gather_pd() { let base_addr: [f64; 4] = [1., 2., 3., 4.]; let src = _mm256_setr_pd(9., 10., 11., 12.); let vindex = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_pd(2., 10., 4., 12.); assert_eq_m256d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_ps() { + fn test_mm256_mmask_i32gather_ps() { let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.); let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); - let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.); assert_eq_m256(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_epi32() { + fn test_mm256_mmask_i64gather_epi32() { let base_addr: [i32; 4] = [1, 2, 3, 4]; let src = _mm_setr_epi32(9, 10, 11, 12); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 10, 4, 12); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_epi64() { + fn test_mm256_mmask_i64gather_epi64() { let base_addr: [i64; 4] = [1, 2, 3, 4]; let src = _mm256_setr_epi64x(9, 10, 11, 12); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_epi64x(2, 10, 4, 12); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_pd() { + fn test_mm256_mmask_i64gather_pd() { let base_addr: [f64; 4] = [1., 2., 3., 4.]; let src = _mm256_setr_pd(9., 10., 11., 12.); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_pd(2., 10., 4., 12.); assert_eq_m256d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_ps() { + fn test_mm256_mmask_i64gather_ps() { let base_addr: [f32; 4] = [1., 2., 3., 4.]; let src = _mm_setr_ps(9., 10., 11., 12.); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 10., 4., 12.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_epi32() { + fn test_mm_i32scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_epi32() { + fn test_mm_mask_i32scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_epi64() { + fn test_mm_i32scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_epi64x(2, 1); - _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_epi64() { + fn test_mm_mask_i32scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_epi64x(2, 1); - _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_pd() { + fn test_mm_i32scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_pd(2., 1.); - _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_pd() { + fn test_mm_mask_i32scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_pd(2., 1.); - _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_ps() { + fn test_mm_i32scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_ps() { + fn test_mm_mask_i32scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_epi32() { + fn test_mm_i64scatter_epi32() { let mut base_addr: [i32; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi32(2, 1, -1, -1); - _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_epi32() { + fn test_mm_mask_i64scatter_epi32() { let mut base_addr: [i32; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi32(2, 1, -1, -1); - _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_epi64() { + fn test_mm_i64scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi64x(2, 1); - _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_epi64() { + fn test_mm_mask_i64scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi64x(2, 1); - _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_pd() { + fn test_mm_i64scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_pd(2., 1.); - _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_pd() { + fn test_mm_mask_i64scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_pd(2., 1.); - _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_ps() { + fn test_mm_i64scatter_ps() { let mut base_addr: [f32; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_ps(2., 1., -1., -1.); - _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_ps() { + fn test_mm_mask_i64scatter_ps() { let mut base_addr: [f32; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_ps(2., 1., -1., -1.); - _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_epi32() { + fn test_mm256_i32scatter_epi32() { let mut base_addr: [i32; 8] = [0; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1); - _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4, 5, 6, 7, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_epi32() { + fn test_mm256_mask_i32scatter_epi32() { let mut base_addr: [i32; 8] = [0; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1); - _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0, 2, 0, 4, 0, 6, 0, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_epi64() { + fn test_mm256_i32scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_epi64() { + fn test_mm256_mask_i32scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_pd() { + fn test_mm256_i32scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_pd() { + fn test_mm256_mask_i32scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_ps() { + fn test_mm256_i32scatter_ps() { let mut base_addr: [f32; 8] = [0.; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.); - _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4., 5., 6., 7., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_ps() { + fn test_mm256_mask_i32scatter_ps() { let mut base_addr: [f32; 8] = [0.; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.); - _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0., 2., 0., 4., 0., 6., 0., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_epi32() { + fn test_mm256_i64scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_epi32() { + fn test_mm256_mask_i64scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_epi64() { + fn test_mm256_i64scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_epi64() { + fn test_mm256_mask_i64scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_pd() { + fn test_mm256_i64scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_pd() { + fn test_mm256_mask_i64scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_ps() { + fn test_mm256_i64scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_ps() { + fn test_mm256_mask_i64scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } @@ -12168,100 +12275,116 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_epi64() { + const fn test_mm512_loadu_epi64() { let a = &[4, 3, 2, 5, -8, -9, -64, -50]; let p = a.as_ptr(); - let r = _mm512_loadu_epi64(black_box(p)); + let r = unsafe { _mm512_loadu_epi64(black_box(p)) }; let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_loadu_epi64() { + const fn test_mm256_loadu_epi64() { let a = &[4, 3, 2, 5]; let p = a.as_ptr(); - let r = _mm256_loadu_epi64(black_box(p)); + let r = unsafe { _mm256_loadu_epi64(black_box(p)) }; let e = _mm256_setr_epi64x(4, 3, 2, 5); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_loadu_epi64() { + const fn test_mm_loadu_epi64() { let a = &[4, 3]; let p = a.as_ptr(); - let r = _mm_loadu_epi64(black_box(p)); + let r = unsafe { _mm_loadu_epi64(black_box(p)) }; let e = _mm_setr_epi64x(4, 3); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() { + fn test_mm512_mask_cvtepi64_storeu_epi16() { let a = _mm512_set1_epi64(9); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() { + fn test_mm256_mask_cvtepi64_storeu_epi16() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi16() { + fn test_mm_mask_cvtepi64_storeu_epi16() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() { + fn test_mm512_mask_cvtsepi64_storeu_epi16() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() { + fn test_mm256_mask_cvtsepi64_storeu_epi16() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() { + fn test_mm_mask_cvtsepi64_storeu_epi16() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() { + fn test_mm512_mask_cvtusepi64_storeu_epi16() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() { + fn test_mm256_mask_cvtusepi64_storeu_epi16() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16( 0, 0, @@ -12276,46 +12399,56 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() { + fn test_mm_mask_cvtusepi64_storeu_epi16() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() { + fn test_mm512_mask_cvtepi64_storeu_epi8() { let a = _mm512_set1_epi64(9); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() { + fn test_mm256_mask_cvtepi64_storeu_epi8() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi8() { + fn test_mm_mask_cvtepi64_storeu_epi8() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() { + fn test_mm512_mask_cvtsepi64_storeu_epi8() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12327,10 +12460,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() { + fn test_mm256_mask_cvtsepi64_storeu_epi8() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12342,19 +12477,23 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() { + fn test_mm_mask_cvtsepi64_storeu_epi8() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() { + fn test_mm512_mask_cvtusepi64_storeu_epi8() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12366,10 +12505,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() { + fn test_mm256_mask_cvtusepi64_storeu_epi8() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12381,10 +12522,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() { + fn test_mm_mask_cvtusepi64_storeu_epi8() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12396,112 +12539,136 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() { + fn test_mm512_mask_cvtepi64_storeu_epi32() { let a = _mm512_set1_epi64(9); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(9); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() { + fn test_mm256_mask_cvtepi64_storeu_epi32() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm_set_epi32(9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi32() { + fn test_mm_mask_cvtepi64_storeu_epi32() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm_set_epi32(0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() { + fn test_mm512_mask_cvtsepi64_storeu_epi32() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(i32::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() { + fn test_mm256_mask_cvtsepi64_storeu_epi32() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + } let e = _mm_set1_epi32(i32::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() { + fn test_mm_mask_cvtsepi64_storeu_epi32() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + } let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() { + fn test_mm512_mask_cvtusepi64_storeu_epi32() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(u32::MAX as i32); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() { + fn test_mm256_mask_cvtusepi64_storeu_epi32() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + } let e = _mm_set1_epi32(u32::MAX as i32); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() { + fn test_mm_mask_cvtusepi64_storeu_epi32() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + } let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_epi64() { + const fn test_mm512_storeu_epi64() { let a = _mm512_set1_epi64(9); let mut r = _mm512_set1_epi64(0); - _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_storeu_epi64() { + const fn test_mm256_storeu_epi64() { let a = _mm256_set1_epi64x(9); let mut r = _mm256_set1_epi64x(0); - _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_storeu_epi64() { + const fn test_mm_storeu_epi64() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi64x(0); - _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_epi64() { + const fn test_mm512_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -12510,63 +12677,69 @@ mod tests { data: [4, 3, 2, 5, -8, -9, -64, -50], }; let p = (a.data).as_ptr(); - let r = _mm512_load_epi64(black_box(p)); + let r = unsafe { _mm512_load_epi64(black_box(p)) }; let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_load_epi64() { + const fn test_mm256_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 4], } let a = Align { data: [4, 3, 2, 5] }; let p = (a.data).as_ptr(); - let r = _mm256_load_epi64(black_box(p)); + let r = unsafe { _mm256_load_epi64(black_box(p)) }; let e = _mm256_set_epi64x(5, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_load_epi64() { + const fn test_mm_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 2], } let a = Align { data: [4, 3] }; let p = (a.data).as_ptr(); - let r = _mm_load_epi64(black_box(p)); + let r = unsafe { _mm_load_epi64(black_box(p)) }; let e = _mm_set_epi64x(3, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_epi64() { + const fn test_mm512_store_epi64() { let a = _mm512_set1_epi64(9); let mut r = _mm512_set1_epi64(0); - _mm512_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm512_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_store_epi64() { + const fn test_mm256_store_epi64() { let a = _mm256_set1_epi64x(9); let mut r = _mm256_set1_epi64x(0); - _mm256_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm256_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_store_epi64() { + const fn test_mm_store_epi64() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi64x(0); - _mm_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_pd() { + const fn test_mm512_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -12575,16 +12748,18 @@ mod tests { data: [4., 3., 2., 5., -8., -9., -64., -50.], }; let p = (a.data).as_ptr(); - let r = _mm512_load_pd(black_box(p)); + let r = unsafe { _mm512_load_pd(black_box(p)) }; let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_pd() { + const fn test_mm512_store_pd() { let a = _mm512_set1_pd(9.); let mut r = _mm512_undefined_pd(); - _mm512_store_pd(&mut r as *mut _ as *mut f64, a); + unsafe { + _mm512_store_pd(&mut r as *mut _ as *mut f64, a); + } assert_eq_m512d(r, a); } diff --git a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs index a24b44fb1f7e3..28bf1951167a5 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs @@ -77,12 +77,14 @@ mod tests { #[simd_test(enable = "fxsr")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_fxsave64() { + fn test_fxsave64() { let mut a = FxsaveArea::new(); let mut b = FxsaveArea::new(); - fxsr::_fxsave64(a.ptr()); - fxsr::_fxrstor64(a.ptr()); - fxsr::_fxsave64(b.ptr()); + unsafe { + fxsr::_fxsave64(a.ptr()); + fxsr::_fxrstor64(a.ptr()); + fxsr::_fxsave64(b.ptr()); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs index b156af078a320..08dabf053d428 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs @@ -204,10 +204,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si64() { + fn test_mm_stream_si64() { let a: i64 = 7; let mut mem = boxed::Box::::new(-1); - _mm_stream_si64(ptr::addr_of_mut!(*mem), a); + unsafe { + _mm_stream_si64(ptr::addr_of_mut!(*mem), a); + } _mm_sfence(); assert_eq!(a, *mem); } diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs index fa1454a822e31..30a7123315e5f 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs @@ -132,37 +132,43 @@ mod tests { #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsave64() { + fn test_xsave64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsave64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsave64(b.ptr(), m); + unsafe { + _xsave64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsave64(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsaveopt")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsaveopt64() { + fn test_xsaveopt64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsaveopt64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsaveopt64(b.ptr(), m); + unsafe { + _xsaveopt64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsaveopt64(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsavec")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsavec64() { + fn test_xsavec64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsavec64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsavec64(b.ptr(), m); + unsafe { + _xsavec64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsavec64(b.ptr(), m); + } } } From c7c5adbe6452c1c904fbe6b6bb3fdd0ed7671a55 Mon Sep 17 00:00:00 2001 From: Trevor Gross Date: Sun, 11 Jan 2026 07:00:54 -0600 Subject: [PATCH 02/20] compiler-builtins: Remove the no-f16-f128 feature This option was used to gate `f16` and `f128` when support across backends and targets was inconsistent. We now have the rustc builtin cfg `target_has_reliable{f16,f128}` which has taken over this usecase. Remove no-f16-f128 since it is now unused and redundant. --- library/alloc/Cargo.toml | 1 - library/compiler-builtins/builtins-shim/Cargo.toml | 4 ---- library/compiler-builtins/builtins-test/Cargo.toml | 1 - library/compiler-builtins/ci/run.sh | 4 ---- library/compiler-builtins/compiler-builtins/Cargo.toml | 4 ---- library/compiler-builtins/compiler-builtins/configure.rs | 7 ++----- library/compiler-builtins/libm/configure.rs | 7 ++----- library/std/Cargo.toml | 1 - library/sysroot/Cargo.toml | 1 - 9 files changed, 4 insertions(+), 26 deletions(-) diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml index fb1f8c86dbfd5..541257b6cda6e 100644 --- a/library/alloc/Cargo.toml +++ b/library/alloc/Cargo.toml @@ -21,7 +21,6 @@ compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features [features] compiler-builtins-mem = ['compiler_builtins/mem'] compiler-builtins-c = ["compiler_builtins/c"] -compiler-builtins-no-f16-f128 = ["compiler_builtins/no-f16-f128"] # Choose algorithms that are optimized for binary size instead of runtime performance optimize_for_size = ["core/optimize_for_size"] diff --git a/library/compiler-builtins/builtins-shim/Cargo.toml b/library/compiler-builtins/builtins-shim/Cargo.toml index ac77224f5ce1e..746d5b21dc3f1 100644 --- a/library/compiler-builtins/builtins-shim/Cargo.toml +++ b/library/compiler-builtins/builtins-shim/Cargo.toml @@ -47,10 +47,6 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Workaround for codegen backends which haven't yet implemented `f16` and -# `f128` support. Disabled any intrinsics which use those types. -no-f16-f128 = [] - # Flag this library as the unstable compiler-builtins lib compiler-builtins = [] diff --git a/library/compiler-builtins/builtins-test/Cargo.toml b/library/compiler-builtins/builtins-test/Cargo.toml index 9346ea65420b2..550f736a76dbb 100644 --- a/library/compiler-builtins/builtins-test/Cargo.toml +++ b/library/compiler-builtins/builtins-test/Cargo.toml @@ -33,7 +33,6 @@ utest-macros = { git = "https://github.com/japaric/utest" } default = ["mangled-names"] c = ["compiler_builtins/c"] no-asm = ["compiler_builtins/no-asm"] -no-f16-f128 = ["compiler_builtins/no-f16-f128"] mem = ["compiler_builtins/mem"] mangled-names = ["compiler_builtins/mangled-names"] # Skip tests that rely on f128 symbols being available on the system diff --git a/library/compiler-builtins/ci/run.sh b/library/compiler-builtins/ci/run.sh index bc94d42fe837a..0c07b32c74b93 100755 --- a/library/compiler-builtins/ci/run.sh +++ b/library/compiler-builtins/ci/run.sh @@ -36,8 +36,6 @@ else "${test_builtins[@]}" --features c --release "${test_builtins[@]}" --features no-asm "${test_builtins[@]}" --features no-asm --release - "${test_builtins[@]}" --features no-f16-f128 - "${test_builtins[@]}" --features no-f16-f128 --release "${test_builtins[@]}" --benches "${test_builtins[@]}" --benches --release @@ -63,8 +61,6 @@ symcheck+=(-- build-and-check) "${symcheck[@]}" "$target" -- -p compiler_builtins --features c --release "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128 -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128 --release run_intrinsics_test() { build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml) diff --git a/library/compiler-builtins/compiler-builtins/Cargo.toml b/library/compiler-builtins/compiler-builtins/Cargo.toml index 0845861dcfe3c..496dde2d4cf25 100644 --- a/library/compiler-builtins/compiler-builtins/Cargo.toml +++ b/library/compiler-builtins/compiler-builtins/Cargo.toml @@ -45,10 +45,6 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Workaround for codegen backends which haven't yet implemented `f16` and -# `f128` support. Disabled any intrinsics which use those types. -no-f16-f128 = [] - # Flag this library as the unstable compiler-builtins lib compiler-builtins = [] diff --git a/library/compiler-builtins/compiler-builtins/configure.rs b/library/compiler-builtins/compiler-builtins/configure.rs index 79e238abc0f62..f16da6b58f812 100644 --- a/library/compiler-builtins/compiler-builtins/configure.rs +++ b/library/compiler-builtins/compiler-builtins/configure.rs @@ -95,16 +95,13 @@ pub fn configure_aliases(target: &Target) { * * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 */ - // If the feature is set, disable both of these types. - let no_f16_f128 = target.cargo_features.iter().any(|s| s == "no-f16-f128"); - println!("cargo::rustc-check-cfg=cfg(f16_enabled)"); - if target.reliable_f16 && !no_f16_f128 { + if target.reliable_f16 { println!("cargo::rustc-cfg=f16_enabled"); } println!("cargo::rustc-check-cfg=cfg(f128_enabled)"); - if target.reliable_f128 && !no_f16_f128 { + if target.reliable_f128 { println!("cargo::rustc-cfg=f128_enabled"); } } diff --git a/library/compiler-builtins/libm/configure.rs b/library/compiler-builtins/libm/configure.rs index 857a302297169..ee65a3a8d6243 100644 --- a/library/compiler-builtins/libm/configure.rs +++ b/library/compiler-builtins/libm/configure.rs @@ -143,16 +143,13 @@ fn emit_f16_f128_cfg(cfg: &Config) { /* See the compiler-builtins configure file for info about the meaning of these options */ - // If the feature is set, disable both of these types. - let no_f16_f128 = cfg.cargo_features.iter().any(|s| s == "no-f16-f128"); - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - if cfg.reliable_f16 && !no_f16_f128 { + if cfg.reliable_f16 { println!("cargo:rustc-cfg=f16_enabled"); } println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - if cfg.reliable_f128 && !no_f16_f128 { + if cfg.reliable_f128 { println!("cargo:rustc-cfg=f128_enabled"); } } diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml index 5c9ae52d9e6c0..b6683a2ae9ece 100644 --- a/library/std/Cargo.toml +++ b/library/std/Cargo.toml @@ -115,7 +115,6 @@ backtrace-trace-only = [] panic-unwind = ["dep:panic_unwind"] compiler-builtins-c = ["alloc/compiler-builtins-c"] compiler-builtins-mem = ["alloc/compiler-builtins-mem"] -compiler-builtins-no-f16-f128 = ["alloc/compiler-builtins-no-f16-f128"] llvm-libunwind = ["unwind/llvm-libunwind"] system-llvm-libunwind = ["unwind/system-llvm-libunwind"] diff --git a/library/sysroot/Cargo.toml b/library/sysroot/Cargo.toml index a188680829166..b2069ef6a613b 100644 --- a/library/sysroot/Cargo.toml +++ b/library/sysroot/Cargo.toml @@ -25,7 +25,6 @@ backtrace = ["std/backtrace"] backtrace-trace-only = ["std/backtrace-trace-only"] compiler-builtins-c = ["std/compiler-builtins-c"] compiler-builtins-mem = ["std/compiler-builtins-mem"] -compiler-builtins-no-f16-f128 = ["std/compiler-builtins-no-f16-f128"] debug_refcell = ["std/debug_refcell"] llvm-libunwind = ["std/llvm-libunwind"] system-llvm-libunwind = ["std/system-llvm-libunwind"] From f09b0bc2cb7b7f43ecd6e0adee5e7b3dbc2c1290 Mon Sep 17 00:00:00 2001 From: reucru01 Date: Mon, 22 Dec 2025 10:31:05 +0000 Subject: [PATCH 03/20] Creates README for stdarch-gen-arm --- .../stdarch/crates/stdarch-gen-arm/README.md | 300 ++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 library/stdarch/crates/stdarch-gen-arm/README.md diff --git a/library/stdarch/crates/stdarch-gen-arm/README.md b/library/stdarch/crates/stdarch-gen-arm/README.md new file mode 100644 index 0000000000000..4da14bcbb6c9b --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/README.md @@ -0,0 +1,300 @@ +# stdarch-gen-arm generator guide +## Running the generator +- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec` +``` +$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec + Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s + Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec` +``` +## Input/Output +### Input files (intrinsic YAML definitions) + - `crates/stdarch-gen-arm/spec//*.spec.yml` +### Output files + - Generated intrinsics: + - `crates/core_arch/src///generated.rs` + - Generated load/store tests: + - `crates/core_arch/src///ld_st_tests_.rs` + - Only generated when `test: { load: }` or `test: { store: }` is set for SVE/SVE2 intrinsics. +## `.spec.yml` file anatomy +``` +--- +Configs +--- +Variable definitions +--- + +Intrinsic definitions + +--- +``` +- If you're new to YAML syntax, consider [reviewing](https://quickref.me/yaml.html) some of the less obvious syntax and features. +- For example, mapping an attribute to a sequence can be done in two different ways: +```yaml +attribute: [item_a, item_b, item_c] +``` +or +```yaml +attribute: + - item_a + - item_b + - item_c +``` +## Configs +- Mappings defining top-level settings applied to all intrinsics: +- `arch_cfgs` + - Sequence of mappings specifying `arch_name`, `target_feature` (sequence), and `llvm_prefix`. +- `uses_neon_types`(_Optional_) + - A boolean specifying whether to emit NEON type imports in generated code. +- `auto_big_endian`(_Optional_) + - A boolean specifying whether to auto-generate big-endian shuffles when possible. +- `auto_llvm_sign_conversion`(_Optional_) + - A boolean specifying whether to auto-convert LLVM wrapper args to signed types. +## Variable definitions +- Defines YAML anchors/variables to avoid repetition. +- Commonly used for stability attributes, cfgs and target features. +## Intrinsic definitions +### Example +```yaml + - name: "vtst{neon_type[0].no}" + doc: "Signed compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: safe + types: + - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + - [poly64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [poly64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[2]}", "{type[3]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] +``` + +### Explanation of fields +- `name` + - The name of the intrinsic + - Often built from a base name followed by a type suffix +- `doc` (_Optional_) + - A string explaining the purpose of the intrinsic +- `static_defs` (_Optional_) + - A sequence of const generics of the format `"const : "` +- `arguments` + - A sequence of strings in the format `": "` +- `return_type` (_Optional_) + - A string specifying the return type. If omitted, the intrinsic returns `()`. +- `attr` (_Optional_) + - A sequence of items defining the attributes to be applied to the intrinsic. Often stability attributes, target features, or `assert_instr` tests. At least one of `attr` or `assert_instr` must be set. +- `target_features` (_Optional_) + - A sequence of target features to enable for this intrinsic (merged with any global `arch_cfgs` settings). +- `assert_instr` (_Optional_) + - A sequence of strings expected to be found in the assembly. Required if `attr` is not set. +- `safety` (_Optional_) + - Use `safe`, or map `unsafe:` to a sequence of unsafety comments: + - `custom: ""` + - `uninitialized` + - `pointer_offset`, `pointer_offset_vnum`, or `dereference` (optionally qualified with `predicated`, `predicated_non_faulting`, or `predicated_first_faulting`) + - `unpredictable_on_fault` + - `non_temporal` + - `neon` + - `no_provenance: ""` +- `substitutions` (_Optional_) + - Mappings of custom wildcard names to either `MatchSize` or `MatchKind` expressions +- `types` + - A sequence or sequence of sequences specifying the types to use when producing each intrinsic variant. These sequences can then be indexed by wildcards. +- `constraints` (_Optional_) + - A sequence of mappings. Each specifies a variable and a constraint. The available mappings are: + - Assert a variable's value exists in a sequence of i32's + - Usage: `{ variable: , any_values: [,...] }` + - Assert a variable's value exists in a range (inclusive) + - Usage: `{ variable: , range: [, ] }` + - Assert a variable's value exists in a range via a match (inclusive) + - Usage: `{ variable: , range: }` + - Assert a variable's value does not exceed the number of elements in a SVE type ``. + - Usage: `{ variable: , sve_max_elems_type: }` + - Assert a variable's value does not exceed the number of elements in a vector type ``. + - Usage: `{ variable: , vec_max_elems_type: }` +- `predication_methods` (_Optional_) + - Configuration for predicate-form variants. Only used when the intrinsic name includes an `_m*_` wildcard (e.g., `{_mx}`, `{_mxz}`). + - `zeroing_method`: Required when requesting `_z`; either `{ drop: }` to remove an argument and replace it with a zero initialiser, or `{ select: }` to select zeros into a predicate. + - `dont_care_method`: How `_x` should be implemented (`inferred`, `as_zeroing`, or `as_merging`). +- `compose` + - A sequence of expressions that make up the body of the intrinsic +- `big_endian_inverse` (_Optional_) + - A boolean, default false. If true, generates two implementations of each intrinsic variant, one for each endianness, and attempts to automatically generate the required bit swizzles +- `visibility` (_Optional_) + - Function visibility. One of `public` (default) or `private`. +- `n_variant_op` (_Optional_) + - Enables generation of an `_n` variant when the intrinsic name includes the `{_n}` wildcard. Set to the operand name that should be splattered for the `_n` form. +- `test` (_Optional_) + - When set, load/store tests are automatically generated. + - A mapping of either `load` or `store` to a number that indexes `types` to specify the type that the test should be addressing in memory. +### Expressions +#### Common +- `Let` + - Defines a variable + - Usage: `Let: [, , ]` +- `Const` + - Defines a const + - Usage: `Const: [, , ]` +- `Assign` + - Performs variable assignment + - Usage: `Assign: [, ]` +- `FnCall` + - Performs a function call + - Usage: `FnCall: [, [, ... ], [, ...](optional), ]` +- `MacroCall` + - Performs a macro call + - Usage: `MacroCall: [, ]` +- `MethodCall` + - Performs a method call + - Usage: `MethodCall: [, , [, ... ]]` +- `LLVMLink` + - Creates an LLVM link and stores the function's name in the wildcard `{llvm_link}` for later use in subsequent expressions. + - If left unset, the arguments and return type inherit from the intrinsic's signature by default. The links will also be set automatically if unset. + - Usage: +```yaml +LLVMLink: + name: + arguments: [, ... ](optional) + return_type: (optional) + links: (optional) + - link: + arch: + - ... +``` +- `Identifier` + - Emits a symbol. Prepend with a `$` to treat it as a scope variable, which engages variable tracking and enables inference. For example, `my_function_name` for a generic symbol or `$my_variable` for a variable. + - Usage `Identifier: [, ]` +- `CastAs` + - Casts an expression to an unchecked type + - Usage: `CastAs: [, ]` +- `MatchSize` + - Allows for conditional generation depending on the size of a specified type + - Usage: +```yaml +MatchSize: + - + - default: + byte(optional): + halfword(optional): + doubleword(optional): +``` +- `MatchKind` + - Allows for conditional generation depending on the kind of a specified type +```yaml +MatchKind: + - + - default: + float(optional): + unsigned(optional): +``` +#### Rarely Used +- `IntConstant` + - Constant signed integer expression + - Usage: `IntConstant: ` +- `FloatConstant` + - Constant floating-point expression + - Usage: `FloatConstant: ` +- `BoolConstant` + - Constant boolean expression + - Usage: `BoolConstant: ` +- `Array` + - An array of expressions + - Usage: `Array: [, ...]` +- `SvUndef` + - Returns the LLVM `undef` symbol + - Usage: `SvUndef` +- `Multiply` + - Simply `*` + - Usage: `Multiply: [, ]` +- `Xor` + - Simply `^` + - Usage: `Xor: [, ]` +- `ConvertConst` + - Converts the specified constant to the specified type's kind + - Usage: `ConvertConst: [, ]` +- `Type` + - Yields the given type in the Rust representation + - Usage: `Type: []` + +### Wildstrings +- Wildstrings let you take advantage of wildcards. +- For example, they are often used in intrinsic names `name: "vtst{neon_type[0].no}"` +- As shown above, wildcards are identified by the surrounding curly brackets. +- Double curly brackets can be used to escape wildcard functionality if you need literal curly brackets in the generated intrinsic. +### Wildcards +Wildcards are heavily used in the spec. They let you write generalised definitions for a group of intrinsics that generate multiple variants. The wildcard itself is replaced with the relevant string in each variant. +Ignoring endianness, for each row in the `types` field of an intrinsic in the spec, a variant of the intrinsic will be generated. That row's contents can be indexed by the wildcards. Below is the behaviour of each wildcard. +- `type[]` + - Replaced in each variant with the value in the indexed position in the relevant row of the `types` field. + - For unnested sequences of `types` (i.e., `types` is a sequence where each element is a single item, not another sequence), the square brackets can be omitted. Simply: `type` +- `neon_type[]` + - Extends the behaviour of `type` with some NEON-specific features and inference. + - Tuples: This wildcard can also be written as `neon_type_x` where `n` is in the set `{2,3,4}`. This generates the `n`-tuple variant of the (inferred) NEON type. + - Suffixes: These modify the behaviour of the wildcard from simple substitution. + - `no` - normal behaviour. Tries to do as much work as it can for you, inferring when to emit: + - Regular type-size suffixes: `_s8`, `_u16`, `_f32`, ... + - `q` variants for double-width (128b) vector types: `q_s8`, `q_u16`, `q_f32`, ... + - `_x` variants for tuple vector types: `_s8_x2`, `_u32_x3`, `_f64_x4`, ... + - As well as any combination of the above: `q_s16_x16` ... + - Most of the other suffixes modify the normal behaviour by disabling features or adding new ones. (See table below) +- `sve_type[]` + - Similar to `neon_type`, but without the suffixes. +- `size[]` + - The size (in bits) of the indexed type. +- `size_minus_one[]` + - Emits the size (in bits) of the indexed type minus one. +- `size_literal[]` + - The literal representation of the indexed type. + - `b`: byte, `h`: halfword, `w`: word, or `d`: double. +- `type_kind[]` + - The literal representation of the indexed type's kind. + - `f`: float, `s`: signed, `u`: unsigned, `p`: polynomial, `b`: boolean. +- `size_in_bytes_log2[]` + - Log2 of the size of the indexed type in *bytes*. +- `predicate[]` + - SVE predicate vector type inferred from the indexed type. +- `max_predicate` + - The same as predicate, but uses the largest type in the relevant `types` sequence/row. +- `_n` + - Emits the current N-variant suffix when `n_variant_op` is configured. +- ` as ` + - If `` evaluates to a vector, it produces a vector of the same shape, but with `` as the base type. +- `llvm_link` + - If the `LLVMLink` mapping has been set for an intrinsic, this will give the name of the link. +- `_m*` + - Predicate form masks. Use wildcards such as `{_mx}` or `{_mxz}` to expand merging/don't-care/zeroing variants according to the mask. +- `` + - You may simply call upon wildcards defined under `substitutions`. +### neon_type suffixes + +| suffix | implication | +| ----------------- | --------------------------------------------- | +| `.no` | Normal | +| `.noq` | Never include `q`s | +| `.nox` | Never include `_x`s | +| `.N` | Include `_n_`, e.g., `_n_s8` | +| `.noq_N` | Include `_n_`, but never `q`s | +| `.dup` | Include `_dup_`, e.g., `_dup_s8` | +| `.dup_nox` | Include `_dup_` but never `_x`s | +| `.lane` | Include `_lane_`, e.g., `_lane_s8` | +| `.lane_nox` | Include `_lane_`, but never `_x`s | +| `.rot90` | Include `_rot90_`, e.g., `_rot90_s8` | +| `.rot180` | Include `_rot180_`, e.g., `_rot180_s8` | +| `.rot270` | Include `_rot270_`, e.g., `_rot270_s8` | +| `.rot90_lane` | Include `_rot90_lane_` | +| `.rot180_lane` | Include `_rot180_lane_` | +| `.rot270_lane` | Include `_rot270_lane_` | +| `.rot90_laneq` | Include `_rot90_laneq_` | +| `.rot180_laneq` | Include `_rot180_laneq_` | +| `.rot270_laneq` | Include `_rot270_laneq_` | +| `.base` | Produce only the size, e.g., `8`, `16` | +| `.u` | Produce the type's unsigned equivalent | +| `.laneq_nox` | Include `_laneq_`, but never `_x`s | +| `.tuple` | Produce only the size of the tuple, e.g., `3` | +| `.base_byte_size` | Produce only the size in bytes. | + From f4731a17f696cdde1650d9e660236c3077f06a3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Le=C3=B3n=20Orell=20Valerian=20Liehr?= Date: Mon, 26 Jan 2026 00:06:59 +0100 Subject: [PATCH 04/20] Bump `std`'s `backtrace`'s `rustc-demangle` --- library/Cargo.lock | 4 ++-- library/std/Cargo.toml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/library/Cargo.lock b/library/Cargo.lock index f6c14bc58a044..92dbedb6457a6 100644 --- a/library/Cargo.lock +++ b/library/Cargo.lock @@ -274,9 +274,9 @@ dependencies = [ [[package]] name = "rustc-demangle" -version = "0.1.26" +version = "0.1.27" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace" +checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d" dependencies = [ "rustc-std-workspace-core", ] diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml index 5c9ae52d9e6c0..80dd0801333b2 100644 --- a/library/std/Cargo.toml +++ b/library/std/Cargo.toml @@ -26,7 +26,7 @@ hashbrown = { version = "0.16.1", default-features = false, features = [ std_detect = { path = "../std_detect", public = true } # Dependencies of the `backtrace` crate -rustc-demangle = { version = "0.1.24", features = ['rustc-dep-of-std'] } +rustc-demangle = { version = "0.1.27", features = ['rustc-dep-of-std'] } [target.'cfg(not(all(windows, target_env = "msvc", not(target_vendor = "uwp"))))'.dependencies] miniz_oxide = { version = "0.8.0", optional = true, default-features = false } From a8e91473c5bc1261487079db19e7fbfa19ac33f5 Mon Sep 17 00:00:00 2001 From: Vadim Petrochenkov Date: Sun, 28 Dec 2025 23:11:15 +0300 Subject: [PATCH 05/20] tests: Reproduce the issue with missing MIR for ambiguous reexports --- tests/ui/imports/ambiguous-reachable.rs | 10 ++++++ tests/ui/imports/ambiguous-reachable.stderr | 31 +++++++++++++++++++ .../auxiliary/ambiguous-reachable-extern.rs | 14 +++++++++ 3 files changed, 55 insertions(+) create mode 100644 tests/ui/imports/ambiguous-reachable.rs create mode 100644 tests/ui/imports/ambiguous-reachable.stderr create mode 100644 tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs diff --git a/tests/ui/imports/ambiguous-reachable.rs b/tests/ui/imports/ambiguous-reachable.rs new file mode 100644 index 0000000000000..1ca31c402ae61 --- /dev/null +++ b/tests/ui/imports/ambiguous-reachable.rs @@ -0,0 +1,10 @@ +//@ build-fail +//@ aux-crate: ambiguous_reachable_extern=ambiguous-reachable-extern.rs + +#![allow(ambiguous_glob_imports)] + +fn main() { + ambiguous_reachable_extern::generic::(); +} + +//~? ERROR missing optimized MIR diff --git a/tests/ui/imports/ambiguous-reachable.stderr b/tests/ui/imports/ambiguous-reachable.stderr new file mode 100644 index 0000000000000..5ba00970a23a0 --- /dev/null +++ b/tests/ui/imports/ambiguous-reachable.stderr @@ -0,0 +1,31 @@ +error: missing optimized MIR for `ambiguous_reachable_extern::m1::generic::` in the crate `ambiguous_reachable_extern` + | +note: missing optimized MIR for this item (was the crate `ambiguous_reachable_extern` compiled with `--emit=metadata`?) + --> $DIR/auxiliary/ambiguous-reachable-extern.rs:2:5 + | +LL | pub fn generic() { + | ^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + +Future incompatibility report: Future breakage diagnostic: +warning: `generic` is ambiguous + --> $DIR/ambiguous-reachable.rs:7:33 + | +LL | ambiguous_reachable_extern::generic::(); + | ^^^^^^^ ambiguous name + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #114095 + = note: ambiguous because of multiple glob imports of a name in the same module +note: `generic` could refer to the function defined here + --> $DIR/auxiliary/ambiguous-reachable-extern.rs:13:9 + | +LL | pub use m1::*; + | ^^ +note: `generic` could also refer to the function defined here + --> $DIR/auxiliary/ambiguous-reachable-extern.rs:14:9 + | +LL | pub use m2::*; + | ^^ + diff --git a/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs new file mode 100644 index 0000000000000..af81812560e38 --- /dev/null +++ b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs @@ -0,0 +1,14 @@ +mod m1 { + pub fn generic() { + let x = 10; + let y = 11; + println!("hello {x} world {:?}", y); + } +} + +mod m2 { + pub fn generic() {} +} + +pub use m1::*; +pub use m2::*; From 4bdccabda5ab612f07eadfde96915bf0edd61e95 Mon Sep 17 00:00:00 2001 From: Amanda Stjerna Date: Mon, 26 Jan 2026 17:02:31 +0100 Subject: [PATCH 06/20] Borrowck: Simplify SCC annotation computation, placeholder rewriting This simplifies the `PlaceholderReachability` `enum` by replacing the case when no placeholders were reached with a standard `Option::None`. It also rewrites the API for `scc::Annotations` to be update-mut rather than a more Functional programming style. This showed some slight performance impact in early tests of the PR and definitely makes the implementation simpler. --- .../rustc_borrowck/src/handle_placeholders.rs | 115 +++++++----------- .../src/graph/scc/mod.rs | 28 ++--- .../src/graph/scc/tests.rs | 17 ++- 3 files changed, 58 insertions(+), 102 deletions(-) diff --git a/compiler/rustc_borrowck/src/handle_placeholders.rs b/compiler/rustc_borrowck/src/handle_placeholders.rs index 60be521c29af0..2a7dc8ba10162 100644 --- a/compiler/rustc_borrowck/src/handle_placeholders.rs +++ b/compiler/rustc_borrowck/src/handle_placeholders.rs @@ -62,57 +62,23 @@ impl scc::Annotations for SccAnnotations<'_, '_, RegionTracker> { } #[derive(Copy, Debug, Clone, PartialEq, Eq)] -enum PlaceholderReachability { - /// This SCC reaches no placeholders. - NoPlaceholders, - /// This SCC reaches at least one placeholder. - Placeholders { - /// The largest-universed placeholder we can reach - max_universe: (UniverseIndex, RegionVid), - - /// The placeholder with the smallest ID - min_placeholder: RegionVid, - - /// The placeholder with the largest ID - max_placeholder: RegionVid, - }, +struct PlaceholderReachability { + /// The largest-universed placeholder we can reach + max_universe: (UniverseIndex, RegionVid), + + /// The placeholder with the smallest ID + min_placeholder: RegionVid, + + /// The placeholder with the largest ID + max_placeholder: RegionVid, } impl PlaceholderReachability { /// Merge the reachable placeholders of two graph components. - fn merge(self, other: PlaceholderReachability) -> PlaceholderReachability { - use PlaceholderReachability::*; - match (self, other) { - (NoPlaceholders, NoPlaceholders) => NoPlaceholders, - (NoPlaceholders, p @ Placeholders { .. }) - | (p @ Placeholders { .. }, NoPlaceholders) => p, - ( - Placeholders { - min_placeholder: min_pl, - max_placeholder: max_pl, - max_universe: max_u, - }, - Placeholders { min_placeholder, max_placeholder, max_universe }, - ) => Placeholders { - min_placeholder: min_pl.min(min_placeholder), - max_placeholder: max_pl.max(max_placeholder), - max_universe: max_u.max(max_universe), - }, - } - } - - fn max_universe(&self) -> Option<(UniverseIndex, RegionVid)> { - match self { - Self::NoPlaceholders => None, - Self::Placeholders { max_universe, .. } => Some(*max_universe), - } - } - - /// If we have reached placeholders, determine if they can - /// be named from this universe. - fn can_be_named_by(&self, from: UniverseIndex) -> bool { - self.max_universe() - .is_none_or(|(max_placeholder_universe, _)| from.can_name(max_placeholder_universe)) + fn merge(&mut self, other: &Self) { + self.max_universe = self.max_universe.max(other.max_universe); + self.min_placeholder = self.min_placeholder.min(other.min_placeholder); + self.max_placeholder = self.max_placeholder.max(other.max_placeholder); } } @@ -120,7 +86,7 @@ impl PlaceholderReachability { /// the values of its elements. This annotates a single SCC. #[derive(Copy, Debug, Clone)] pub(crate) struct RegionTracker { - reachable_placeholders: PlaceholderReachability, + reachable_placeholders: Option, /// The largest universe nameable from this SCC. /// It is the smallest nameable universes of all @@ -135,13 +101,13 @@ impl RegionTracker { pub(crate) fn new(rvid: RegionVid, definition: &RegionDefinition<'_>) -> Self { let reachable_placeholders = if matches!(definition.origin, NllRegionVariableOrigin::Placeholder(_)) { - PlaceholderReachability::Placeholders { + Some(PlaceholderReachability { max_universe: (definition.universe, rvid), min_placeholder: rvid, max_placeholder: rvid, - } + }) } else { - PlaceholderReachability::NoPlaceholders + None }; Self { @@ -159,43 +125,46 @@ impl RegionTracker { } pub(crate) fn max_placeholder_universe_reached(self) -> UniverseIndex { - if let Some((universe, _)) = self.reachable_placeholders.max_universe() { - universe - } else { - UniverseIndex::ROOT - } + self.reachable_placeholders.map(|pls| pls.max_universe.0).unwrap_or(UniverseIndex::ROOT) + } + + /// Can all reachable placeholders be named from `from`? + /// True vacuously in case no placeholders were reached. + fn placeholders_can_be_named_by(&self, from: UniverseIndex) -> bool { + self.reachable_placeholders.is_none_or(|pls| from.can_name(pls.max_universe.0)) } /// Determine if we can name all the placeholders in `other`. pub(crate) fn can_name_all_placeholders(&self, other: Self) -> bool { - other.reachable_placeholders.can_be_named_by(self.max_nameable_universe.0) + // HACK: We first check whether we can name the highest existential universe + // of `other`. This only exists to avoid errors in case that scc already + // depends on a placeholder it cannot name itself. + self.max_nameable_universe().can_name(other.max_nameable_universe()) + || other.placeholders_can_be_named_by(self.max_nameable_universe.0) } /// If this SCC reaches a placeholder it can't name, return it. fn unnameable_placeholder(&self) -> Option<(UniverseIndex, RegionVid)> { - self.reachable_placeholders.max_universe().filter(|&(placeholder_universe, _)| { - !self.max_nameable_universe().can_name(placeholder_universe) - }) + self.reachable_placeholders + .filter(|pls| !self.max_nameable_universe().can_name(pls.max_universe.0)) + .map(|pls| pls.max_universe) } } impl scc::Annotation for RegionTracker { - fn merge_scc(self, other: Self) -> Self { + fn update_scc(&mut self, other: &Self) { trace!("{:?} << {:?}", self.representative, other.representative); - - Self { - representative: self.representative.min(other.representative), - max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe), - reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders), - } + self.representative = self.representative.min(other.representative); + self.update_reachable(other); } - fn merge_reached(self, other: Self) -> Self { - Self { - max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe), - reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders), - representative: self.representative, - } + fn update_reachable(&mut self, other: &Self) { + self.max_nameable_universe = self.max_nameable_universe.min(other.max_nameable_universe); + match (self.reachable_placeholders.as_mut(), other.reachable_placeholders.as_ref()) { + (None, None) | (Some(_), None) => (), + (None, Some(theirs)) => self.reachable_placeholders = Some(*theirs), + (Some(ours), Some(theirs)) => ours.merge(theirs), + }; } } diff --git a/compiler/rustc_data_structures/src/graph/scc/mod.rs b/compiler/rustc_data_structures/src/graph/scc/mod.rs index 91cbe3c533bbc..954e4116fb55f 100644 --- a/compiler/rustc_data_structures/src/graph/scc/mod.rs +++ b/compiler/rustc_data_structures/src/graph/scc/mod.rs @@ -27,26 +27,18 @@ mod tests; /// the max/min element of the SCC, or all of the above. /// /// Concretely, the both merge operations must commute, e.g. where `merge` -/// is `merge_scc` and `merge_reached`: `a.merge(b) == b.merge(a)` +/// is `update_scc` and `update_reached`: `a.merge(b) == b.merge(a)` /// /// In general, what you want is probably always min/max according /// to some ordering, potentially with side constraints (min x such /// that P holds). pub trait Annotation: Debug + Copy { /// Merge two existing annotations into one during - /// path compression.o - fn merge_scc(self, other: Self) -> Self; + /// path compression. + fn update_scc(&mut self, other: &Self); /// Merge a successor into this annotation. - fn merge_reached(self, other: Self) -> Self; - - fn update_scc(&mut self, other: Self) { - *self = self.merge_scc(other) - } - - fn update_reachable(&mut self, other: Self) { - *self = self.merge_reached(other) - } + fn update_reachable(&mut self, other: &Self); } /// An accumulator for annotations. @@ -70,12 +62,8 @@ impl Annotations for NoAnnotations { /// The empty annotation, which does nothing. impl Annotation for () { - fn merge_reached(self, _other: Self) -> Self { - () - } - fn merge_scc(self, _other: Self) -> Self { - () - } + fn update_reachable(&mut self, _other: &Self) {} + fn update_scc(&mut self, _other: &Self) {} } /// Strongly connected components (SCC) of a graph. The type `N` is @@ -614,7 +602,7 @@ where *min_depth = successor_min_depth; *min_cycle_root = successor_node; } - current_component_annotation.update_scc(successor_annotation); + current_component_annotation.update_scc(&successor_annotation); } // The starting node `node` is succeeded by a fully identified SCC // which is now added to the set under `scc_index`. @@ -629,7 +617,7 @@ where // the `successors_stack` for later. trace!(?node, ?successor_scc_index); successors_stack.push(successor_scc_index); - current_component_annotation.update_reachable(successor_annotation); + current_component_annotation.update_reachable(&successor_annotation); } // `node` has no more (direct) successors; search recursively. None => { diff --git a/compiler/rustc_data_structures/src/graph/scc/tests.rs b/compiler/rustc_data_structures/src/graph/scc/tests.rs index 8f04baf51f355..4626861c3e00b 100644 --- a/compiler/rustc_data_structures/src/graph/scc/tests.rs +++ b/compiler/rustc_data_structures/src/graph/scc/tests.rs @@ -32,12 +32,12 @@ impl Maxes { } impl Annotation for MaxReached { - fn merge_scc(self, other: Self) -> Self { - Self(std::cmp::max(other.0, self.0)) + fn update_scc(&mut self, other: &Self) { + self.0 = self.0.max(other.0); } - fn merge_reached(self, other: Self) -> Self { - Self(std::cmp::max(other.0, self.0)) + fn update_reachable(&mut self, other: &Self) { + self.0 = self.0.max(other.0); } } @@ -75,13 +75,12 @@ impl Annotations for MinMaxes { } impl Annotation for MinMaxIn { - fn merge_scc(self, other: Self) -> Self { - Self { min: std::cmp::min(self.min, other.min), max: std::cmp::max(self.max, other.max) } + fn update_scc(&mut self, other: &Self) { + self.min = self.min.min(other.min); + self.max = self.max.max(other.max); } - fn merge_reached(self, _other: Self) -> Self { - self - } + fn update_reachable(&mut self, _other: &Self) {} } #[test] From 44e89f8262c21222ab0fb97cee026d87501b007a Mon Sep 17 00:00:00 2001 From: Vadim Petrochenkov Date: Thu, 8 Jan 2026 23:48:46 +0300 Subject: [PATCH 07/20] resolve: Mark items under ambigous imports as exported --- .../src/effective_visibilities.rs | 31 +++---------------- tests/rustdoc-html/glob-shadowing.rs | 12 ++++--- tests/rustdoc-json/reexport/glob_collision.rs | 4 ++- tests/ui/imports/ambiguous-reachable.rs | 4 +-- tests/ui/imports/ambiguous-reachable.stderr | 12 ++----- 5 files changed, 18 insertions(+), 45 deletions(-) diff --git a/compiler/rustc_resolve/src/effective_visibilities.rs b/compiler/rustc_resolve/src/effective_visibilities.rs index 295635a605477..55518276a4f0f 100644 --- a/compiler/rustc_resolve/src/effective_visibilities.rs +++ b/compiler/rustc_resolve/src/effective_visibilities.rs @@ -96,13 +96,10 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> { // is the maximum value among visibilities of declarations corresponding to that def id. for (decl, eff_vis) in visitor.import_effective_visibilities.iter() { let DeclKind::Import { import, .. } = decl.kind else { unreachable!() }; - if !decl.is_ambiguity_recursive() { - if let Some(node_id) = import.id() { - r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx) - } - } else if decl.ambiguity.get().is_some() - && eff_vis.is_public_at_level(Level::Reexported) - { + if let Some(node_id) = import.id() { + r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx) + } + if decl.ambiguity.get().is_some() && eff_vis.is_public_at_level(Level::Reexported) { exported_ambiguities.insert(*decl); } } @@ -123,31 +120,13 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> { // Set the given effective visibility level to `Level::Direct` and // sets the rest of the `use` chain to `Level::Reexported` until // we hit the actual exported item. - // - // If the binding is ambiguous, put the root ambiguity binding and all reexports - // leading to it into the table. They are used by the `ambiguous_glob_reexports` - // lint. For all bindings added to the table this way `is_ambiguity` returns true. - let is_ambiguity = - |decl: Decl<'ra>, warn: bool| decl.ambiguity.get().is_some() && !warn; let mut parent_id = ParentId::Def(module_id); - let mut warn_ambiguity = decl.warn_ambiguity.get(); while let DeclKind::Import { source_decl, .. } = decl.kind { self.update_import(decl, parent_id); - - if is_ambiguity(decl, warn_ambiguity) { - // Stop at the root ambiguity, further bindings in the chain should not - // be reexported because the root ambiguity blocks any access to them. - // (Those further bindings are most likely not ambiguities themselves.) - break; - } - parent_id = ParentId::Import(decl); decl = source_decl; - warn_ambiguity |= source_decl.warn_ambiguity.get(); } - if !is_ambiguity(decl, warn_ambiguity) - && let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local()) - { + if let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local()) { self.update_def(def_id, decl.vis().expect_local(), parent_id); } } diff --git a/tests/rustdoc-html/glob-shadowing.rs b/tests/rustdoc-html/glob-shadowing.rs index d9e9ead3f9a90..c1eeb7e663e7b 100644 --- a/tests/rustdoc-html/glob-shadowing.rs +++ b/tests/rustdoc-html/glob-shadowing.rs @@ -1,9 +1,9 @@ //@ has 'glob_shadowing/index.html' -//@ count - '//dt' 6 -//@ !has - '//dd' 'sub1::describe' +//@ count - '//dt' 7 +//@ !has - '//dd' 'sub1::describe1' //@ has - '//dd' 'sub2::describe' -//@ !has - '//dd' 'sub1::describe2' +//@ has - '//dd' 'sub1::describe2' //@ !has - '//dd' 'sub1::prelude' //@ has - '//dd' 'mod::prelude' @@ -18,7 +18,7 @@ mod sub1 { // this should be shadowed by sub2::describe - /// sub1::describe + /// sub1::describe1 pub fn describe() -> &'static str { "sub1::describe" } @@ -33,7 +33,9 @@ mod sub1 { pub struct Foo; // this should be shadowed, - // because both sub1::describe2 and sub3::describe2 are from glob reexport + // because both sub1::describe2 and sub3::describe2 are from glob reexport, + // but it is still usable from other crates under the `ambiguous_glob_imports` lint, + // so it is reachable and documented /// sub1::describe2 pub fn describe2() -> &'static str { "sub1::describe2" diff --git a/tests/rustdoc-json/reexport/glob_collision.rs b/tests/rustdoc-json/reexport/glob_collision.rs index 48de1b5e77213..dd6eab6517b09 100644 --- a/tests/rustdoc-json/reexport/glob_collision.rs +++ b/tests/rustdoc-json/reexport/glob_collision.rs @@ -1,7 +1,9 @@ // Regression test for https://github.com/rust-lang/rust/issues/100973 +// Update: the rules has changed after #147984, one of the colliding items is now available +// from other crates under a deprecation lint. //@ set m1 = "$.index[?(@.name == 'm1' && @.inner.module)].id" -//@ is "$.index[?(@.name == 'm1')].inner.module.items" [] +//@ is "$.index[?(@.name == 'm1')].inner.module.items" [0] //@ is "$.index[?(@.name == 'm1')].inner.module.is_stripped" true mod m1 { pub fn f() {} diff --git a/tests/ui/imports/ambiguous-reachable.rs b/tests/ui/imports/ambiguous-reachable.rs index 1ca31c402ae61..fc92315622aa1 100644 --- a/tests/ui/imports/ambiguous-reachable.rs +++ b/tests/ui/imports/ambiguous-reachable.rs @@ -1,4 +1,4 @@ -//@ build-fail +//@ build-pass //@ aux-crate: ambiguous_reachable_extern=ambiguous-reachable-extern.rs #![allow(ambiguous_glob_imports)] @@ -6,5 +6,3 @@ fn main() { ambiguous_reachable_extern::generic::(); } - -//~? ERROR missing optimized MIR diff --git a/tests/ui/imports/ambiguous-reachable.stderr b/tests/ui/imports/ambiguous-reachable.stderr index 5ba00970a23a0..78a0d76d68b5b 100644 --- a/tests/ui/imports/ambiguous-reachable.stderr +++ b/tests/ui/imports/ambiguous-reachable.stderr @@ -1,13 +1,3 @@ -error: missing optimized MIR for `ambiguous_reachable_extern::m1::generic::` in the crate `ambiguous_reachable_extern` - | -note: missing optimized MIR for this item (was the crate `ambiguous_reachable_extern` compiled with `--emit=metadata`?) - --> $DIR/auxiliary/ambiguous-reachable-extern.rs:2:5 - | -LL | pub fn generic() { - | ^^^^^^^^^^^^^^^^^^^ - -error: aborting due to 1 previous error - Future incompatibility report: Future breakage diagnostic: warning: `generic` is ambiguous --> $DIR/ambiguous-reachable.rs:7:33 @@ -23,6 +13,8 @@ note: `generic` could refer to the function defined here | LL | pub use m1::*; | ^^ + = help: consider updating this dependency to resolve this error + = help: if updating the dependency does not resolve the problem report the problem to the author of the relevant crate note: `generic` could also refer to the function defined here --> $DIR/auxiliary/ambiguous-reachable-extern.rs:14:9 | From 354365a0e0055c6f908a2d1965a8b86ebf4f11d1 Mon Sep 17 00:00:00 2001 From: Reuben Cruise Date: Wed, 14 Jan 2026 16:46:45 +0000 Subject: [PATCH 08/20] Adds some arm intrinsics to bring more up-to-date with acle - Adds vluti2 intrinsics - Adds famin/famax intrinsics - Adds vstl1(q) intrinsics - Adds vldap1(q) intrinsics - Excludes vldap1_lane_f64 as in testing it fails assert_intr. There seems to be some bad IR gen from rust. - Adds vscale(q) intrinsics - Adds new intrinsics to arm_intrinsics.json - Had to be done manually as intrinsics are not yet on developer.arm.com --- .../core_arch/src/aarch64/neon/generated.rs | 669 +++++++- .../crates/intrinsic-test/missing_aarch64.txt | 52 +- .../intrinsic-test/missing_aarch64_be.txt | 51 +- .../spec/neon/aarch64.spec.yml | 235 ++- .../intrinsics_data/arm_intrinsics.json | 1385 ++++++++++++++++- 5 files changed, 2258 insertions(+), 134 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index b042bd0c3c724..b763d64ca3bc6 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -733,10 +733,42 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { unsafe { simd_reduce_add_ordered(a, 0) } } #[doc = "Multi-vector floating-point absolute maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] +#[inline] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(test, assert_instr(famax))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famax.v4f16" + )] + fn _vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vamax_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] +#[inline] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(test, assert_instr(famax))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famax.v8f16" + )] + fn _vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vamaxq_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -752,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -768,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -781,10 +813,42 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vamaxq_f64(a, b) } } #[doc = "Multi-vector floating-point absolute minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] +#[inline] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(test, assert_instr(famin))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famin.v4f16" + )] + fn _vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vamin_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] +#[inline] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(test, assert_instr(famin))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famin.v8f16" + )] + fn _vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vaminq_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -800,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -816,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -12847,6 +12911,237 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; ret_val } +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); + simd_insert!( + src, + LANE as u32, + atomic_src.load(crate::sync::atomic::Ordering::Acquire) + ) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); + simd_insert!( + src, + LANE as u32, + atomic_src.load(crate::sync::atomic::Ordering::Acquire) + ) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2q_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2q_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"] #[doc = "## Safety"] @@ -12928,108 +13223,214 @@ pub unsafe fn vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t) -> i _vluti2q_lane_s16(a, b, LANE) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2_laneq_f16(a: float16x4_t, b: uint8x16_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2q_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_f16(a: float16x8_t, b: uint8x16_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2q_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2_laneq_u16(a: uint16x4_t, b: uint8x16_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2q_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_u16(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2_laneq_p8(a: poly8x8_t, b: uint8x16_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2q_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_laneq_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> int8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v8i8" + )] + fn _vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t, n: i32) -> int8x16_t; + } + _vluti2_laneq_s8(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v16i8" + )] + fn _vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t; + } + _vluti2q_laneq_s8(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> int16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v4i16" + )] + fn _vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t, n: i32) -> int16x8_t; + } + _vluti2_laneq_s16(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t) -> int16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v8i16" + )] + fn _vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t, n: i32) -> int16x8_t; + } + _vluti2q_laneq_s16(a, b, INDEX) } #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"] @@ -24113,6 +24514,86 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4 let x: uint32x2_t = vrsubhn_u64(b, c); unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } } +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"] +#[inline] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v4f16" + )] + fn _vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t; + } + unsafe { _vscale_f16(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"] +#[inline] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v8f16" + )] + fn _vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t; + } + unsafe { _vscaleq_f16(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"] +#[inline] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v2f32" + )] + fn _vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t; + } + unsafe { _vscale_f32(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"] +#[inline] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v4f32" + )] + fn _vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t; + } + unsafe { _vscaleq_f32(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"] +#[inline] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v2f64" + )] + fn _vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t; + } + unsafe { _vscaleq_f64(vn, vm) } +} #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] #[inline(always)] @@ -26696,6 +27177,102 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { vst4q_s64(transmute(a), transmute(b)) } +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { + static_assert!(LANE == 0); + let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; + unsafe { + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) + } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] +#[inline] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { + static_assert_uimm_bits!(LANE, 1); + let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; + unsafe { + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) + } +} #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] #[inline(always)] diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt index 814756cefa406..3c1ac59e910e9 100644 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt @@ -1,3 +1,43 @@ +# Not supported by qemu (will throw illegal instruction) +vamax_f16 +vamaxq_f16 +vamin_f16 +vaminq_f16 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 + # Not implemented in stdarch yet vbfdot_f32 vbfdot_lane_f32 @@ -30,18 +70,6 @@ vrnd32x_f64 vrnd32z_f64 vrnd64x_f64 vrnd64z_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2q_lane_u8 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt index 1fa8fb7f1693e..f3c4ffa3d0640 100644 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt @@ -38,6 +38,45 @@ vusdotq_lane_s32 vusdotq_laneq_s32 # Below are in common to missing_aarch64.txt +# Not supported by qemu (will throw illegal instruction) +vamax_f16 +vamaxq_f16 +vamin_f16 +vaminq_f16 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 # Not implemented in stdarch yet vbfdot_f32 @@ -71,18 +110,6 @@ vrnd32x_f64 vrnd32z_f64 vrnd64x_f64 vrnd64z_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2q_lane_u8 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a951343e01835..10085422e8e85 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -66,6 +66,14 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut aarch64-stable-jscvt: &aarch64-stable-jscvt FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']] +# #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3 + FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']] + +# #[unstable(feature = "stdarch_neon_fp8", issue = "none")] +neon-unstable-fp8: &neon-unstable-fp8 + FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] + # #[cfg(target_endian = "little")] little-endian: &little-endian FnCall: [cfg, ['target_endian = "little"']] @@ -4398,6 +4406,116 @@ intrinsics: - - FnCall: [transmute, [a]] - FnCall: [transmute, [b]] + - name: "vldap1{neon_type[1].lane_nox}" + doc: "Load-acquire RCpc one single-element structure to one lane of one register" + arguments: ["ptr: {type[0]}", "src: {type[1]}"] + static_defs: ["const LANE: i32"] + return_type: "{type[1]}" + safety: + unsafe: [neon] + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0'] + - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - Let: + - "atomic_src" + - FnCall: ["crate::sync::atomic::AtomicI64::from_ptr", ['ptr as *mut i64']] + - Identifier: [';', Symbol] + - FnCall: + - simd_insert! + - - src + - "LANE as u32" + - MethodCall: + - "atomic_src" + - load + - ["crate::sync::atomic::Ordering::Acquire"] + + - name: "vldap1{neon_type[1].lane_nox}" + doc: "Load-acquire RCpc one single-element structure to one lane of one register" + arguments: ["ptr: {type[0]}","src: {type[1]}"] + static_defs: ["const LANE: i32"] + return_type: "{type[1]}" + safety: + unsafe: [neon] + attr: + - FnCall: [rustc_legacy_const_generics, ["2"]] + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] + #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust + - ['*const p64', poly64x1_t,'static_assert!', 'LANE == 0',''] + - ['*const u64', uint64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*const f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*const p64', poly64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vldap1{type[4]}_lane_s64::' + - - "ptr as *mut i64" + - FnCall: [transmute,[src]] + + - name: "vstl1{neon_type[1].lane_nox}" + doc: "Store-Release a single-element structure from one lane of one register." + arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: safe + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0'] + - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - Let: + - "atomic_dst" + - "ptr as *mut crate::sync::atomic::AtomicI64" + - Identifier: [';', Symbol] + - Let: + - "lane" + - i64 + - FnCall: [simd_extract!, [val, 'LANE as u32']] + - MethodCall: + - "(*atomic_dst)" + - store + - [FnCall: [transmute, [lane]],"crate::sync::atomic::Ordering::Release"] + + - name: "vstl1{neon_type[1].lane_nox}" + doc: "Store-Release a single-element structure from one lane of one register." + arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: safe + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0',''] + - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0',''] + - ['*mut p64', poly64x1_t, 'static_assert!', 'LANE == 0',''] + - ['*mut u64', uint64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*mut f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*mut p64', poly64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - FnCall: + - "vstl1{type[4]}_lane_s64::" + - - "ptr as *mut i64" + - FnCall: [transmute, [val]] + - name: "vst1{neon_type[1].lane_nox}" doc: "Store multiple single-element structures from one, two, three, or four registers" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] @@ -13966,10 +14084,12 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: + - float16x4_t + - float16x8_t - float32x2_t - float32x4_t - float64x2_t @@ -13986,10 +14106,12 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: + - float16x4_t + - float16x8_t - float32x2_t - float32x4_t - float64x2_t @@ -14030,36 +14152,101 @@ intrinsics: arch: aarch64,arm64ec - FnCall: ['_vluti2{neon_type[0].lane_nox}', [a, b, LANE]] + - name: "vluti2{neon_type[0].laneq_nox}" + doc: "Lookup table read with 2-bit indices" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [target_feature, ['enable = {type[4]}']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] + - *neon-unstable-feat-lut + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ["const INDEX: i32"] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"'] + - [int8x16_t, uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"'] + - [int16x4_t, uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"'] + - [int16x8_t, uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"'] + compose: + - FnCall: ['static_assert!', ['{type[3]}']] + - LLVMLink: + name: "vluti2{neon_type[0].laneq_nox}" + arguments: + - 'a: {neon_type[0]}' + - 'b: {neon_type[1]}' + - 'n: i32' + links: + - link: "llvm.aarch64.neon.vluti2.laneq.{neon_type[2]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ['_vluti2{neon_type[0].laneq_nox}', [a, b, INDEX]] + - name: "vluti2{neon_type[0].lane_nox}" doc: "Lookup table read with 2-bit indices" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - FnCall: [target_feature, ['enable = "neon,lut"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] - *neon-unstable-feat-lut - FnCall: [rustc_legacy_const_generics, ['2']] - static_defs: ["const LANE: i32"] + static_defs: ["const INDEX: i32"] safety: unsafe: [neon] types: - - [uint8x8_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t'] - - [uint8x16_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t'] - - [poly8x8_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t'] - - [poly8x16_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t'] - - [uint16x4_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t'] - - [uint16x8_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t'] - - [poly16x4_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t'] - - [poly16x8_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t'] + - [uint8x8_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t'] + - [uint8x16_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t'] + - [poly8x8_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t'] + - [poly8x16_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t'] + - [uint16x4_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [uint16x8_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] + - [poly16x4_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [poly16x8_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] + - [float16x4_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [float16x8_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] compose: - FnCall: ['static_assert!', ['{type[3]}']] - FnCall: - transmute - - FnCall: - - 'vluti2{neon_type[4].lane_nox}::' + - 'vluti2{neon_type[4].lane_nox}::' - - FnCall: [transmute, [a]] - b + - name: "vluti2{neon_type[0].laneq_nox}" + doc: "Lookup table read with 2-bit indices" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [target_feature, ['enable = "neon,lut"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] + - *neon-unstable-feat-lut + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ["const INDEX: i32"] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t'] + - [uint8x16_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t'] + - [poly8x8_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t'] + - [poly8x16_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t'] + - [uint16x4_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [uint16x8_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + - [poly16x4_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [poly16x8_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + - [float16x4_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [float16x8_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + compose: + - FnCall: ['static_assert!', ['{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vluti2{neon_type[4].laneq_nox}::' + - - FnCall: [transmute, [a]] + - b + + - name: "vluti4{neon_type[0].lane_nox}" doc: "Lookup table read with 4-bit indices" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] @@ -14268,6 +14455,28 @@ intrinsics: - - FnCall: [transmute, [a]] - b + - name: "vscale{neon_type[0].no}" + doc: "Multi-vector floating-point adjust exponent" + arguments: ["vn: {type[0]}", "vm: {type[1]}"] + return_type: "{type[0]}" + attr: + - *neon-unstable-fp8 + - FnCall: [target_feature, ['enable = "neon,fp8"']] + assert_instr: [fscale] + safety: safe + types: + - [float16x4_t, int16x4_t] + - [float16x8_t, int16x8_t] + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vscale{neon_type[0].no}" + links: + - link: "llvm.aarch64.neon.fp8.fscale.{neon_type[0]}" + arch: aarch64,arm64ec + - name: "__jcvt" doc: "Floating-point JavaScript convert to signed fixed-point, rounding toward zero" arguments: ["a: {type}"] diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index 19c655cd6d24e..bce85d19a10f1 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -223,6 +223,141 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f16", + "arguments": [ + "float16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f16", + "arguments": [ + "float16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f32", + "arguments": [ + "float32x2_t a", + "int32x2_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f32", + "arguments": [ + "float32x4_t a", + "int32x4_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f64", + "arguments": [ + "float64x2_t a", + "int64x2_t b" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vaba_s16", @@ -34733,6 +34868,230 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x1_t src", + "const int lane" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x2_t src", + "const int lane" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x2_t src", + "const int lane" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f16", @@ -109193,6 +109552,262 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_f64", + "arguments": [ + "float64_t * ptr", + "float64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_f64", + "arguments": [ + "float64_t * ptr", + "float64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_p64", + "arguments": [ + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_p64", + "arguments": [ + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsub_f16", @@ -118682,6 +119297,60 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vamin_f32", @@ -118763,6 +119432,60 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vamax_f32", @@ -118844,6 +119567,531 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_f16", + "arguments": [ + "float16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s16", + "arguments": [ + "int16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u16", + "arguments": [ + "uint16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p16", + "arguments": [ + "poly16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_f16", + "arguments": [ + "float16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_s16", + "arguments": [ + "int16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_u16", + "arguments": [ + "uint16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_p16", + "arguments": [ + "poly16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_f16", + "arguments": [ + "float16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_s16", + "arguments": [ + "int16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_u16", + "arguments": [ + "uint16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_p16", + "arguments": [ + "poly16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_f16", + "arguments": [ + "float16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_s16", + "arguments": [ + "int16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_u16", + "arguments": [ + "uint16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vluti2_lane_u8", @@ -118862,7 +120110,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118897,7 +120145,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118932,7 +120180,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118967,7 +120215,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119002,7 +120250,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119037,7 +120285,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119056,28 +120304,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u16", + "name": "vluti2_laneq_u8", "arguments": [ - "uint16x4_t a", - "uint8x8_t b", - "const int lane" + "uint8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119091,28 +120339,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u16", + "name": "vluti2q_laneq_u8", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "const int lane" + "uint8x16_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119126,28 +120374,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s16", + "name": "vluti2_laneq_s8", "arguments": [ - "int16x4_t a", - "uint8x8_t b", - "const int lane" + "int8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119161,28 +120409,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s16", + "name": "vluti2q_laneq_s8", "arguments": [ - "int16x8_t a", - "uint8x8_t b", - "const int lane" + "int8x16_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119196,28 +120444,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p16", + "name": "vluti2_laneq_p8", "arguments": [ - "poly16x4_t a", - "uint8x8_t b", - "const int lane" + "poly8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "poly16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119231,11 +120479,46 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p16", + "name": "vluti2q_laneq_p8", + "arguments": [ + "poly8x16_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_p16", "arguments": [ "poly16x8_t a", - "uint8x8_t b", - "const int lane" + "uint8x16_t b", + "const int index" ], "return_type": { "value": "poly16x8_t" @@ -119247,9 +120530,9 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "r": { "register": "Vd.8H" From 57a42dbf5494d4375c9b8e1d52b39746656b7cd4 Mon Sep 17 00:00:00 2001 From: reucru01 Date: Wed, 17 Dec 2025 09:41:31 +0000 Subject: [PATCH 09/20] Makes some A64 intrinsics available on A32 Moves the relevant defintions from the aarch64 yaml to the arm_shared. --- .../core_arch/src/aarch64/neon/generated.rs | 204 +++-------- .../src/arm_shared/neon/generated.rs | 332 ++++++++++++++++++ .../spec/neon/aarch64.spec.yml | 111 ------ .../spec/neon/arm_shared.spec.yml | 126 +++++++ 4 files changed, 498 insertions(+), 275 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index b763d64ca3bc6..c4fd6a8cd9f9f 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(test, assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -750,7 +750,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(test, assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] @@ -814,7 +814,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(test, assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -830,7 +830,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,faminmax")] #[cfg_attr(test, assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] @@ -9555,68 +9555,6 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub fn vdivh_f16(a: f16, b: f16) -> f16 { a / b } -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, vreinterpret_s8_s32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, vreinterpretq_s8_s32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = vreinterpretq_u32_u8(c); - unsafe { - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, vreinterpret_u8_u32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = vreinterpretq_u32_u8(c); - unsafe { - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, vreinterpretq_u8_u32(c)) - } -} #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] #[inline(always)] @@ -12915,7 +12853,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12933,7 +12871,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -12951,7 +12889,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] @@ -12964,7 +12902,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] @@ -12977,7 +12915,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] @@ -12990,7 +12928,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] @@ -13003,7 +12941,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(ldap1, LANE = 0))] @@ -13016,7 +12954,7 @@ pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13029,7 +12967,7 @@ pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13042,7 +12980,7 @@ pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13055,7 +12993,7 @@ pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> ui #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13068,7 +13006,7 @@ pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13081,7 +13019,7 @@ pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13094,7 +13032,7 @@ pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13107,7 +13045,7 @@ pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> po #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13120,7 +13058,7 @@ pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13133,7 +13071,7 @@ pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13330,7 +13268,7 @@ pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13343,7 +13281,7 @@ pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) - #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13356,7 +13294,7 @@ pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13376,7 +13314,7 @@ pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> i #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13396,7 +13334,7 @@ pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -13416,7 +13354,7 @@ pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] #[doc = "## Safety"] #[doc = " * Neon instrinsic unsafe"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] @@ -24516,7 +24454,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4 } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"] -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(test, assert_instr(fscale))] @@ -24532,7 +24470,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"] -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(test, assert_instr(fscale))] @@ -24548,7 +24486,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"] -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(test, assert_instr(fscale))] @@ -24564,7 +24502,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"] -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(test, assert_instr(fscale))] @@ -24580,7 +24518,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { } #[doc = "Multi-vector floating-point adjust exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"] -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] #[cfg_attr(test, assert_instr(fscale))] @@ -27179,7 +27117,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27190,7 +27128,7 @@ pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27201,7 +27139,7 @@ pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27212,7 +27150,7 @@ pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27223,7 +27161,7 @@ pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27234,7 +27172,7 @@ pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27245,7 +27183,7 @@ pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27260,7 +27198,7 @@ pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] -#[inline] +#[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(test, assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] @@ -27481,37 +27419,6 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { simd_sub(a, simd_cast(c)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) - } -} #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] #[inline(always)] @@ -28851,37 +28758,6 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { } unsafe { _vuqadds_s32(a, b) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, vreinterpret_s8_s32(c)) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) - } -} #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] #[inline(always)] diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 324ff73f62a14..ac3b649fbf2dc 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -9816,6 +9816,200 @@ pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: int8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: uint8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: uint8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: uint8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] #[inline(always)] @@ -73395,6 +73589,47 @@ pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] +#[inline(always)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) + } +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] +#[inline(always)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) + } +} #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] #[inline(always)] @@ -75397,6 +75632,103 @@ pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: uint8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] #[inline(always)] diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index 10085422e8e85..ec5bc8c954d7c 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -5199,56 +5199,6 @@ intrinsics: arch: aarch64,arm64ec - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] - - name: "vusdot{neon_type[0].laneq_nox}" - doc: "Dot product index form with unsigned and signed integers" - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - attr: - - *neon-i8mm - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] - static_defs: ["const LANE: i32"] - safety: safe - types: - - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: [c, int32x4_t, {FnCall: ['vreinterpretq_s32_s8', [c]]}] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] - - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] - - - name: "vsudot{neon_type[0].laneq_nox}" - doc: "Dot product index form with signed and unsigned integers" - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - attr: - - *neon-i8mm - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] - static_defs: ["const LANE: i32"] - safety: safe - types: - - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] - - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - uint32x4_t - - FnCall: [transmute, [c]] - - Let: - - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] - - FnCall: - - "vusdot{neon_type[0].no}" - - - a - - FnCall: [transmute, [c]] - - b - - name: "vmul{neon_type.no}" doc: Multiply arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -6670,7 +6620,6 @@ intrinsics: - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - - name: "vcmla{neon_type[0].rot270_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] @@ -6692,66 +6641,6 @@ intrinsics: - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - - name: "vdot{neon_type[0].laneq_nox}" - doc: Dot product arithmetic (indexed) - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - static_defs: ["const LANE: i32"] - attr: - - FnCall: [target_feature, ['enable = "neon,dotprod"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: safe - types: - - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] - - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: - - c - - "{neon_type[3]}" - - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] - - FnCall: - - "vdot{neon_type[0].no}" - - - a - - b - - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] - - - name: "vdot{neon_type[0].laneq_nox}" - doc: Dot product arithmetic (indexed) - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - static_defs: ["const LANE: i32"] - attr: - - FnCall: [target_feature, ['enable = "neon,dotprod"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: safe - types: - - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: - - c - - "{neon_type[3]}" - - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] - - FnCall: - - "vdot{neon_type[0].no}" - - - a - - b - - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] - - name: "vmax{neon_type.no}" doc: Maximum (vector) arguments: ["a: {neon_type}", "b: {neon_type}"] diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index c7a333d7f75ec..2bd1bf2a53fa6 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -7096,6 +7096,132 @@ intrinsics: - FnCall: [simd_cast, [b]] - FnCall: [simd_sub, [c, d]] + - name: "vusdot{neon_type[0].laneq_nox}" + doc: "Dot product index form with unsigned and signed integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - *neon-i8mm + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot, 'LANE = 3']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: safe + types: + - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] + - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}] + - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]] + #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] + + - name: "vsudot{neon_type[0].laneq_nox}" + doc: "Dot product index form with signed and unsigned integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v8 + - *neon-i8mm + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: safe + types: + - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] + - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 2]] + - Let: + - c + - uint32x4_t + - FnCall: [transmute, [c]] + - Let: + - c + - "{type[4]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: + - "vusdot{neon_type[0].no}" + - - a + - FnCall: [transmute, [c]] + - b + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: safe + types: + - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] + - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: safe + types: + - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] + - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - name: "vdot{neon_type[0].no}" doc: Dot product arithmetic (vector) arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] From 9ce0ebf994e601ebed0c74e39ea6457a44d111ef Mon Sep 17 00:00:00 2001 From: reucru01 Date: Wed, 14 Jan 2026 13:29:20 +0000 Subject: [PATCH 10/20] Disables `assert_instr` tests on windows msvc The opcodes for these intructions are not recognised by the dissasembler on the windows msvc toolchain. As such they are not translated to the relevant mneumonic and the `assert_instr` test fails. Please see [failing test](https://github.com/rust-lang/stdarch/actions/runs/20992978794/job/60342796821?pr=1994#logs). --- .../core_arch/src/aarch64/neon/generated.rs | 60 +++++++++---------- .../spec/neon/aarch64.spec.yml | 14 ++--- 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index c4fd6a8cd9f9f..68676ebd2c867 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -736,7 +736,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famax))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { @@ -752,7 +752,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famax))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { @@ -768,7 +768,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famax))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -784,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famax))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -800,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famax))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -816,7 +816,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famin))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { @@ -832,7 +832,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famin))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { @@ -848,7 +848,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famin))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -864,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famin))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -880,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(famin))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -12855,7 +12855,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { @@ -12873,7 +12873,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[doc = " * Neon instrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { @@ -12892,7 +12892,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); @@ -12905,7 +12905,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { static_assert!(LANE == 0); @@ -12918,7 +12918,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); @@ -12931,7 +12931,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { static_assert!(LANE == 0); @@ -12944,7 +12944,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(ldap1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); @@ -24457,7 +24457,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4 #[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] -#[cfg_attr(test, assert_instr(fscale))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( @@ -24473,7 +24473,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { #[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] -#[cfg_attr(test, assert_instr(fscale))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( @@ -24489,7 +24489,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { #[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] -#[cfg_attr(test, assert_instr(fscale))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( @@ -24505,7 +24505,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { #[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] -#[cfg_attr(test, assert_instr(fscale))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( @@ -24521,7 +24521,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { #[inline(always)] #[unstable(feature = "stdarch_neon_fp8", issue = "none")] #[target_feature(enable = "neon,fp8")] -#[cfg_attr(test, assert_instr(fscale))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( @@ -27119,7 +27119,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { @@ -27130,7 +27130,7 @@ pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { @@ -27141,7 +27141,7 @@ pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { @@ -27152,7 +27152,7 @@ pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { @@ -27163,7 +27163,7 @@ pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { @@ -27174,7 +27174,7 @@ pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { @@ -27185,7 +27185,7 @@ pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { @@ -27200,7 +27200,7 @@ pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] -#[cfg_attr(test, assert_instr(stl1, LANE = 0))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index ec5bc8c954d7c..a9bc377924dd0 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -4415,7 +4415,7 @@ intrinsics: unsafe: [neon] attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 types: @@ -4446,7 +4446,7 @@ intrinsics: attr: - FnCall: [rustc_legacy_const_generics, ["2"]] - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - *neon-unstable-feat-lrcpc3 types: - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] @@ -4471,7 +4471,7 @@ intrinsics: safety: safe attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 types: @@ -4499,7 +4499,7 @@ intrinsics: safety: safe attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 types: @@ -13973,7 +13973,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famax]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: @@ -13995,7 +13995,7 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famin]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: @@ -14351,7 +14351,7 @@ intrinsics: attr: - *neon-unstable-fp8 - FnCall: [target_feature, ['enable = "neon,fp8"']] - assert_instr: [fscale] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [fscale]]}]] safety: safe types: - [float16x4_t, int16x4_t] From 9fddd28d38eda100b07b0b11fa578da64c09da6b Mon Sep 17 00:00:00 2001 From: reucru01 Date: Wed, 14 Jan 2026 13:59:59 +0000 Subject: [PATCH 11/20] Ammends typo in generator & generated --- .../core_arch/src/aarch64/neon/generated.rs | 484 ++--- .../src/arm_shared/neon/generated.rs | 1772 ++++++++--------- .../crates/stdarch-gen-arm/src/intrinsic.rs | 2 +- 3 files changed, 1129 insertions(+), 1129 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 68676ebd2c867..9507b71106dd1 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -11174,7 +11174,7 @@ pub fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] @@ -11186,7 +11186,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] @@ -11198,7 +11198,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11209,7 +11209,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11220,7 +11220,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11231,7 +11231,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11242,7 +11242,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11253,7 +11253,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11264,7 +11264,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11275,7 +11275,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11286,7 +11286,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11297,7 +11297,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11308,7 +11308,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11319,7 +11319,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11330,7 +11330,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11341,7 +11341,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11352,7 +11352,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11363,7 +11363,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11374,7 +11374,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11385,7 +11385,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11396,7 +11396,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11407,7 +11407,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11418,7 +11418,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11429,7 +11429,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11440,7 +11440,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11451,7 +11451,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11462,7 +11462,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] @@ -11473,7 +11473,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] @@ -11484,7 +11484,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11502,7 +11502,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11520,7 +11520,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11538,7 +11538,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11556,7 +11556,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11574,7 +11574,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11592,7 +11592,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11610,7 +11610,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11628,7 +11628,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11646,7 +11646,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11664,7 +11664,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11684,7 +11684,7 @@ pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11704,7 +11704,7 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11717,7 +11717,7 @@ pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11730,7 +11730,7 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -11742,7 +11742,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -11757,7 +11757,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -11769,7 +11769,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -11784,7 +11784,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11802,7 +11802,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11820,7 +11820,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11841,7 +11841,7 @@ pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11861,7 +11861,7 @@ pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> in #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11881,7 +11881,7 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11894,7 +11894,7 @@ pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11907,7 +11907,7 @@ pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> u #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11920,7 +11920,7 @@ pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11933,7 +11933,7 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -11945,7 +11945,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -11960,7 +11960,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -11972,7 +11972,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -11987,7 +11987,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12005,7 +12005,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12023,7 +12023,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12041,7 +12041,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12059,7 +12059,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12085,7 +12085,7 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12098,7 +12098,7 @@ pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12124,7 +12124,7 @@ pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> i #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12137,7 +12137,7 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12149,7 +12149,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12165,7 +12165,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12177,7 +12177,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12193,7 +12193,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12211,7 +12211,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12229,7 +12229,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12255,7 +12255,7 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12268,7 +12268,7 @@ pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12294,7 +12294,7 @@ pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> in #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12320,7 +12320,7 @@ pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12333,7 +12333,7 @@ pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> u #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12346,7 +12346,7 @@ pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12359,7 +12359,7 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12371,7 +12371,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12387,7 +12387,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12399,7 +12399,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12415,7 +12415,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12433,7 +12433,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12451,7 +12451,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12469,7 +12469,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12487,7 +12487,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12514,7 +12514,7 @@ pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12541,7 +12541,7 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12554,7 +12554,7 @@ pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12567,7 +12567,7 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12579,7 +12579,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12596,7 +12596,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12608,7 +12608,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12625,7 +12625,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12643,7 +12643,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12661,7 +12661,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12688,7 +12688,7 @@ pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12715,7 +12715,7 @@ pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> in #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12742,7 +12742,7 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12755,7 +12755,7 @@ pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12768,7 +12768,7 @@ pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> u #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12781,7 +12781,7 @@ pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12794,7 +12794,7 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12806,7 +12806,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12823,7 +12823,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12835,7 +12835,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12852,7 +12852,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12870,7 +12870,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] @@ -12888,7 +12888,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] @@ -12901,7 +12901,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] @@ -12914,7 +12914,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] @@ -12927,7 +12927,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] @@ -12940,7 +12940,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,rcpc3")] @@ -12953,7 +12953,7 @@ pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -12966,7 +12966,7 @@ pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -12979,7 +12979,7 @@ pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) - #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -12992,7 +12992,7 @@ pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> ui #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13005,7 +13005,7 @@ pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13018,7 +13018,7 @@ pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13031,7 +13031,7 @@ pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13044,7 +13044,7 @@ pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> po #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13057,7 +13057,7 @@ pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13070,7 +13070,7 @@ pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13083,7 +13083,7 @@ pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -13103,7 +13103,7 @@ pub unsafe fn vluti2_lane_s8(a: int8x8_t, b: uint8x8_t) -> int8 #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -13123,7 +13123,7 @@ pub unsafe fn vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -13143,7 +13143,7 @@ pub unsafe fn vluti2_lane_s16(a: int16x4_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -13163,7 +13163,7 @@ pub unsafe fn vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t) -> i #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13176,7 +13176,7 @@ pub unsafe fn vluti2_laneq_f16(a: float16x4_t, b: uint8x16_t) #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13189,7 +13189,7 @@ pub unsafe fn vluti2q_laneq_f16(a: float16x8_t, b: uint8x16_t) #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13202,7 +13202,7 @@ pub unsafe fn vluti2_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13215,7 +13215,7 @@ pub unsafe fn vluti2q_laneq_u8(a: uint8x16_t, b: uint8x16_t) - #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13228,7 +13228,7 @@ pub unsafe fn vluti2_laneq_u16(a: uint16x4_t, b: uint8x16_t) - #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13241,7 +13241,7 @@ pub unsafe fn vluti2q_laneq_u16(a: uint16x8_t, b: uint8x16_t) #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13254,7 +13254,7 @@ pub unsafe fn vluti2_laneq_p8(a: poly8x8_t, b: uint8x16_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13267,7 +13267,7 @@ pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) - #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13280,7 +13280,7 @@ pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) - #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13293,7 +13293,7 @@ pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13313,7 +13313,7 @@ pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> i #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13333,7 +13333,7 @@ pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13353,7 +13353,7 @@ pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, INDEX = 1))] @@ -13373,7 +13373,7 @@ pub unsafe fn vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t) - #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13386,7 +13386,7 @@ pub unsafe fn vluti4q_lane_f16_x2(a: float16x8x2_t, b: uint8x8_ #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13399,7 +13399,7 @@ pub unsafe fn vluti4q_lane_u16_x2(a: uint16x8x2_t, b: uint8x8_t #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13412,7 +13412,7 @@ pub unsafe fn vluti4q_lane_p16_x2(a: poly16x8x2_t, b: uint8x8_t #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13432,7 +13432,7 @@ pub unsafe fn vluti4q_lane_s16_x2(a: int16x8x2_t, b: uint8x8_t) #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13452,7 +13452,7 @@ pub unsafe fn vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13465,7 +13465,7 @@ pub unsafe fn vluti4q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> u #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13478,7 +13478,7 @@ pub unsafe fn vluti4q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> p #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13494,7 +13494,7 @@ pub unsafe fn vluti4q_laneq_f16_x2( #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13507,7 +13507,7 @@ pub unsafe fn vluti4q_laneq_u16_x2(a: uint16x8x2_t, b: uint8x16 #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13520,7 +13520,7 @@ pub unsafe fn vluti4q_laneq_p16_x2(a: poly16x8x2_t, b: uint8x16 #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13540,7 +13540,7 @@ pub unsafe fn vluti4q_laneq_s16_x2(a: int16x8x2_t, b: uint8x16_ #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13560,7 +13560,7 @@ pub unsafe fn vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13573,7 +13573,7 @@ pub unsafe fn vluti4q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -25837,7 +25837,7 @@ pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] @@ -25850,7 +25850,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] @@ -25863,7 +25863,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25875,7 +25875,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25887,7 +25887,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25899,7 +25899,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25911,7 +25911,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25923,7 +25923,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25935,7 +25935,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25947,7 +25947,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25959,7 +25959,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25971,7 +25971,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25983,7 +25983,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25995,7 +25995,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26007,7 +26007,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26019,7 +26019,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26031,7 +26031,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26043,7 +26043,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26055,7 +26055,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26067,7 +26067,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26079,7 +26079,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26091,7 +26091,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26103,7 +26103,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26115,7 +26115,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26127,7 +26127,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26139,7 +26139,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -26151,7 +26151,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] @@ -26163,7 +26163,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] @@ -26175,7 +26175,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26193,7 +26193,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26211,7 +26211,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26229,7 +26229,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26247,7 +26247,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26271,7 +26271,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -26295,7 +26295,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -26308,7 +26308,7 @@ pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -26321,7 +26321,7 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26339,7 +26339,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26359,7 +26359,7 @@ pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26379,7 +26379,7 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26392,7 +26392,7 @@ pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26405,7 +26405,7 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26423,7 +26423,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26441,7 +26441,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26461,7 +26461,7 @@ pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26481,7 +26481,7 @@ pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26501,7 +26501,7 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26514,7 +26514,7 @@ pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26527,7 +26527,7 @@ pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26540,7 +26540,7 @@ pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26553,7 +26553,7 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2))] @@ -26564,7 +26564,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26575,7 +26575,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26593,7 +26593,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26613,7 +26613,7 @@ pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26633,7 +26633,7 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26646,7 +26646,7 @@ pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26659,7 +26659,7 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26677,7 +26677,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26695,7 +26695,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26715,7 +26715,7 @@ pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26735,7 +26735,7 @@ pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26755,7 +26755,7 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26768,7 +26768,7 @@ pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26781,7 +26781,7 @@ pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26794,7 +26794,7 @@ pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26807,7 +26807,7 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26818,7 +26818,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26829,7 +26829,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26847,7 +26847,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26874,7 +26874,7 @@ pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26901,7 +26901,7 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26914,7 +26914,7 @@ pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26927,7 +26927,7 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26945,7 +26945,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26963,7 +26963,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26990,7 +26990,7 @@ pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27017,7 +27017,7 @@ pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -27044,7 +27044,7 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -27057,7 +27057,7 @@ pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27070,7 +27070,7 @@ pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27083,7 +27083,7 @@ pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27096,7 +27096,7 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -27107,7 +27107,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index ac3b649fbf2dc..5a415acc0c703 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -12370,7 +12370,7 @@ pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -12395,7 +12395,7 @@ pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15133,7 +15133,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[doc = "Load one single-element structure and replicate to all lanes of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15152,7 +15152,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load one single-element structure and replicate to all lanes of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15171,7 +15171,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15194,7 +15194,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15217,7 +15217,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15240,7 +15240,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15263,7 +15263,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15286,7 +15286,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15309,7 +15309,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15332,7 +15332,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15355,7 +15355,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15378,7 +15378,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15401,7 +15401,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15424,7 +15424,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15447,7 +15447,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15470,7 +15470,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15493,7 +15493,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15516,7 +15516,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15539,7 +15539,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15562,7 +15562,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15585,7 +15585,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15608,7 +15608,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15631,7 +15631,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15663,7 +15663,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15695,7 +15695,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15727,7 +15727,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[cfg(target_arch = "arm")] @@ -15745,7 +15745,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[cfg(target_arch = "arm")] @@ -15764,7 +15764,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[cfg(target_arch = "arm")] @@ -15782,7 +15782,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[cfg(target_arch = "arm")] @@ -15801,7 +15801,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15827,7 +15827,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15853,7 +15853,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15879,7 +15879,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15905,7 +15905,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15931,7 +15931,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15957,7 +15957,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15970,7 +15970,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15983,7 +15983,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15996,7 +15996,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16009,7 +16009,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16022,7 +16022,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16035,7 +16035,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16048,7 +16048,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16061,7 +16061,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16074,7 +16074,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16087,7 +16087,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16100,7 +16100,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16113,7 +16113,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16126,7 +16126,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -16139,7 +16139,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,aes")] @@ -16152,7 +16152,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16183,7 +16183,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16214,7 +16214,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16245,7 +16245,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16276,7 +16276,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16307,7 +16307,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16338,7 +16338,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16358,7 +16358,7 @@ pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16378,7 +16378,7 @@ pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16403,7 +16403,7 @@ pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16428,7 +16428,7 @@ pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16453,7 +16453,7 @@ pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> p #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16478,7 +16478,7 @@ pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16503,7 +16503,7 @@ pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16528,7 +16528,7 @@ pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16553,7 +16553,7 @@ pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> in #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16578,7 +16578,7 @@ pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16603,7 +16603,7 @@ pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16628,7 +16628,7 @@ pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16653,7 +16653,7 @@ pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> u #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16678,7 +16678,7 @@ pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16703,7 +16703,7 @@ pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16728,7 +16728,7 @@ pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16753,7 +16753,7 @@ pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16778,7 +16778,7 @@ pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16803,7 +16803,7 @@ pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16828,7 +16828,7 @@ pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16853,7 +16853,7 @@ pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16878,7 +16878,7 @@ pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16903,7 +16903,7 @@ pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16928,7 +16928,7 @@ pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16953,7 +16953,7 @@ pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16978,7 +16978,7 @@ pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,aes")] @@ -16996,7 +16996,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -17019,7 +17019,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -17042,7 +17042,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -17065,7 +17065,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -17089,7 +17089,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -17116,7 +17116,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -17140,7 +17140,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -17168,7 +17168,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -17192,7 +17192,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -17221,7 +17221,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17234,7 +17234,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17247,7 +17247,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17260,7 +17260,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17273,7 +17273,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17286,7 +17286,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17299,7 +17299,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17312,7 +17312,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17325,7 +17325,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17356,7 +17356,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17387,7 +17387,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17418,7 +17418,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17449,7 +17449,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17480,7 +17480,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17511,7 +17511,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17542,7 +17542,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17573,7 +17573,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17604,7 +17604,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17635,7 +17635,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17666,7 +17666,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17697,7 +17697,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17728,7 +17728,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17759,7 +17759,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17790,7 +17790,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17821,7 +17821,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17852,7 +17852,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17883,7 +17883,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17914,7 +17914,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17945,7 +17945,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17976,7 +17976,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18007,7 +18007,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18038,7 +18038,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18069,7 +18069,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18093,7 +18093,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18120,7 +18120,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18144,7 +18144,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18172,7 +18172,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18196,7 +18196,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18225,7 +18225,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18249,7 +18249,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18288,7 +18288,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18312,7 +18312,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18358,7 +18358,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18382,7 +18382,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18435,7 +18435,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18459,7 +18459,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18486,7 +18486,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18510,7 +18510,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18538,7 +18538,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18562,7 +18562,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18591,7 +18591,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18615,7 +18615,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18642,7 +18642,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18666,7 +18666,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18694,7 +18694,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18718,7 +18718,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18747,7 +18747,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18771,7 +18771,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18798,7 +18798,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18822,7 +18822,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18850,7 +18850,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18874,7 +18874,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18903,7 +18903,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18927,7 +18927,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18954,7 +18954,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18978,7 +18978,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19006,7 +19006,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19030,7 +19030,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19059,7 +19059,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19082,7 +19082,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19105,7 +19105,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19128,7 +19128,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19152,7 +19152,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19179,7 +19179,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19203,7 +19203,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19231,7 +19231,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19255,7 +19255,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19284,7 +19284,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19308,7 +19308,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19335,7 +19335,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19359,7 +19359,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19387,7 +19387,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19411,7 +19411,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19440,7 +19440,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19464,7 +19464,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19503,7 +19503,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19527,7 +19527,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19573,7 +19573,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19597,7 +19597,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19650,7 +19650,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19674,7 +19674,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19701,7 +19701,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19725,7 +19725,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19753,7 +19753,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19777,7 +19777,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19806,7 +19806,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19830,7 +19830,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19857,7 +19857,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19881,7 +19881,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19909,7 +19909,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19933,7 +19933,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20120,7 +20120,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20144,7 +20144,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20163,7 +20163,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20182,7 +20182,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20206,7 +20206,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20230,7 +20230,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20246,7 +20246,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20262,7 +20262,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20278,7 +20278,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20294,7 +20294,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20310,7 +20310,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20326,7 +20326,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20342,7 +20342,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20358,7 +20358,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20377,7 +20377,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20396,7 +20396,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20415,7 +20415,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20434,7 +20434,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20453,7 +20453,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20472,7 +20472,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20491,7 +20491,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20510,7 +20510,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -20533,7 +20533,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20549,7 +20549,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20568,7 +20568,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20591,7 +20591,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20615,7 +20615,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20642,7 +20642,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20666,7 +20666,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20705,7 +20705,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20729,7 +20729,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20756,7 +20756,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20780,7 +20780,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20807,7 +20807,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20831,7 +20831,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20858,7 +20858,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20882,7 +20882,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20909,7 +20909,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20933,7 +20933,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20960,7 +20960,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20984,7 +20984,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -21023,7 +21023,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -21047,7 +21047,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -21074,7 +21074,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -21098,7 +21098,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -21125,7 +21125,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21144,7 +21144,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21163,7 +21163,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21187,7 +21187,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21211,7 +21211,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21227,7 +21227,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21243,7 +21243,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21259,7 +21259,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21275,7 +21275,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21291,7 +21291,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21307,7 +21307,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21323,7 +21323,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21339,7 +21339,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21358,7 +21358,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21377,7 +21377,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21396,7 +21396,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21415,7 +21415,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21434,7 +21434,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21453,7 +21453,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21472,7 +21472,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21491,7 +21491,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21517,7 +21517,7 @@ pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21543,7 +21543,7 @@ pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21570,7 +21570,7 @@ pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21601,7 +21601,7 @@ pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21622,7 +21622,7 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21644,7 +21644,7 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21665,7 +21665,7 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21686,7 +21686,7 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21707,7 +21707,7 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21728,7 +21728,7 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21749,7 +21749,7 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21773,7 +21773,7 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21797,7 +21797,7 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21821,7 +21821,7 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21845,7 +21845,7 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21864,7 +21864,7 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21888,7 +21888,7 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21912,7 +21912,7 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21937,7 +21937,7 @@ pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uin #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21962,7 +21962,7 @@ pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21987,7 +21987,7 @@ pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22012,7 +22012,7 @@ pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22037,7 +22037,7 @@ pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22062,7 +22062,7 @@ pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> pol #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22087,7 +22087,7 @@ pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22112,7 +22112,7 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -22135,7 +22135,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22151,7 +22151,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22170,7 +22170,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22193,7 +22193,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22217,7 +22217,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22244,7 +22244,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22268,7 +22268,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22307,7 +22307,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22331,7 +22331,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22358,7 +22358,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22382,7 +22382,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22409,7 +22409,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22433,7 +22433,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22460,7 +22460,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22484,7 +22484,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22511,7 +22511,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22535,7 +22535,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22562,7 +22562,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22586,7 +22586,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22625,7 +22625,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22649,7 +22649,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22676,7 +22676,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22700,7 +22700,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22727,7 +22727,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22746,7 +22746,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22765,7 +22765,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22789,7 +22789,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22813,7 +22813,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22832,7 +22832,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22851,7 +22851,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22870,7 +22870,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22889,7 +22889,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22908,7 +22908,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22927,7 +22927,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22946,7 +22946,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22965,7 +22965,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22984,7 +22984,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23000,7 +23000,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23016,7 +23016,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23032,7 +23032,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23048,7 +23048,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23064,7 +23064,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23080,7 +23080,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23096,7 +23096,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23112,7 +23112,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -23135,7 +23135,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23151,7 +23151,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23174,7 +23174,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23198,7 +23198,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23226,7 +23226,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23250,7 +23250,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23296,7 +23296,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23320,7 +23320,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23348,7 +23348,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23372,7 +23372,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23400,7 +23400,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23424,7 +23424,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23452,7 +23452,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23476,7 +23476,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23504,7 +23504,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23528,7 +23528,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23556,7 +23556,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23580,7 +23580,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23626,7 +23626,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23650,7 +23650,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23678,7 +23678,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23702,7 +23702,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23730,7 +23730,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23749,7 +23749,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23768,7 +23768,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -23792,7 +23792,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -23816,7 +23816,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23835,7 +23835,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23854,7 +23854,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23873,7 +23873,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23892,7 +23892,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23911,7 +23911,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23930,7 +23930,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23949,7 +23949,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23968,7 +23968,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23984,7 +23984,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24000,7 +24000,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24016,7 +24016,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24032,7 +24032,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24048,7 +24048,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24064,7 +24064,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24080,7 +24080,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24096,7 +24096,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -24123,7 +24123,7 @@ pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -24150,7 +24150,7 @@ pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24182,7 +24182,7 @@ pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24214,7 +24214,7 @@ pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24241,7 +24241,7 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24268,7 +24268,7 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24293,7 +24293,7 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24320,7 +24320,7 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24347,7 +24347,7 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24374,7 +24374,7 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24401,7 +24401,7 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24428,7 +24428,7 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24453,7 +24453,7 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24478,7 +24478,7 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24503,7 +24503,7 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24528,7 +24528,7 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24553,7 +24553,7 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24578,7 +24578,7 @@ pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uin #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24603,7 +24603,7 @@ pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24628,7 +24628,7 @@ pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24653,7 +24653,7 @@ pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24678,7 +24678,7 @@ pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24703,7 +24703,7 @@ pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> pol #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24728,7 +24728,7 @@ pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24753,7 +24753,7 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -24776,7 +24776,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24795,7 +24795,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24811,7 +24811,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24834,7 +24834,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24858,7 +24858,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24886,7 +24886,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24910,7 +24910,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24956,7 +24956,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24980,7 +24980,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25008,7 +25008,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25032,7 +25032,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25060,7 +25060,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25084,7 +25084,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25112,7 +25112,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25136,7 +25136,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25164,7 +25164,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25188,7 +25188,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25216,7 +25216,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25240,7 +25240,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25286,7 +25286,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25310,7 +25310,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25338,7 +25338,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25362,7 +25362,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25390,7 +25390,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25415,7 +25415,7 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -25433,7 +25433,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -25451,7 +25451,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -25474,7 +25474,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -25497,7 +25497,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25513,7 +25513,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25529,7 +25529,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25545,7 +25545,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25561,7 +25561,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25577,7 +25577,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25593,7 +25593,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25609,7 +25609,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25625,7 +25625,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25644,7 +25644,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25663,7 +25663,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25682,7 +25682,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25701,7 +25701,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25720,7 +25720,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25739,7 +25739,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25758,7 +25758,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25777,7 +25777,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25796,7 +25796,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -25819,7 +25819,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25835,7 +25835,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25858,7 +25858,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25882,7 +25882,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25911,7 +25911,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25935,7 +25935,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25988,7 +25988,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26012,7 +26012,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26041,7 +26041,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26065,7 +26065,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26094,7 +26094,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26118,7 +26118,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26147,7 +26147,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26171,7 +26171,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26200,7 +26200,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26224,7 +26224,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26253,7 +26253,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26277,7 +26277,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26330,7 +26330,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26354,7 +26354,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26383,7 +26383,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26407,7 +26407,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26436,7 +26436,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -26454,7 +26454,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -26472,7 +26472,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26495,7 +26495,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26518,7 +26518,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26537,7 +26537,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26556,7 +26556,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26575,7 +26575,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26594,7 +26594,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26613,7 +26613,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26632,7 +26632,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26651,7 +26651,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26670,7 +26670,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26686,7 +26686,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26702,7 +26702,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26718,7 +26718,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26734,7 +26734,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26750,7 +26750,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26766,7 +26766,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26782,7 +26782,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26798,7 +26798,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26826,7 +26826,7 @@ pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26854,7 +26854,7 @@ pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) - #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26886,7 +26886,7 @@ pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26918,7 +26918,7 @@ pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26946,7 +26946,7 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26974,7 +26974,7 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27002,7 +27002,7 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27030,7 +27030,7 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27058,7 +27058,7 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27086,7 +27086,7 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27114,7 +27114,7 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27140,7 +27140,7 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27166,7 +27166,7 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27192,7 +27192,7 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27218,7 +27218,7 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27244,7 +27244,7 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27270,7 +27270,7 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27296,7 +27296,7 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27321,7 +27321,7 @@ pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uin #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27346,7 +27346,7 @@ pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27371,7 +27371,7 @@ pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27396,7 +27396,7 @@ pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27421,7 +27421,7 @@ pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27446,7 +27446,7 @@ pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> pol #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27471,7 +27471,7 @@ pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27496,7 +27496,7 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -27519,7 +27519,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27538,7 +27538,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27554,7 +27554,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27577,7 +27577,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27601,7 +27601,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27630,7 +27630,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27654,7 +27654,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27707,7 +27707,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27731,7 +27731,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27760,7 +27760,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27784,7 +27784,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27813,7 +27813,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27837,7 +27837,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27866,7 +27866,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27890,7 +27890,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27919,7 +27919,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27943,7 +27943,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27972,7 +27972,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27996,7 +27996,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -28049,7 +28049,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -28073,7 +28073,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -28102,7 +28102,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -28126,7 +28126,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -28155,7 +28155,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65084,7 +65084,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65102,7 +65102,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65120,7 +65120,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65138,7 +65138,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65156,7 +65156,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65176,7 +65176,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65196,7 +65196,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65214,7 +65214,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65232,7 +65232,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65252,7 +65252,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65272,7 +65272,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65297,7 +65297,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65322,7 +65322,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65348,7 +65348,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65374,7 +65374,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65388,7 +65388,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65402,7 +65402,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65416,7 +65416,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65430,7 +65430,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65444,7 +65444,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65458,7 +65458,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65472,7 +65472,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65486,7 +65486,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65500,7 +65500,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65514,7 +65514,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65528,7 +65528,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65542,7 +65542,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65556,7 +65556,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65570,7 +65570,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65584,7 +65584,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65598,7 +65598,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65612,7 +65612,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65626,7 +65626,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65640,7 +65640,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65654,7 +65654,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65668,7 +65668,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65682,7 +65682,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65696,7 +65696,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65710,7 +65710,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65726,7 +65726,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65742,7 +65742,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65761,7 +65761,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65780,7 +65780,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65799,7 +65799,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65818,7 +65818,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65840,7 +65840,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65862,7 +65862,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65887,7 +65887,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65912,7 +65912,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65932,7 +65932,7 @@ pub unsafe fn vst1_lane_f16(a: *mut f16, b: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65952,7 +65952,7 @@ pub unsafe fn vst1q_lane_f16(a: *mut f16, b: float16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65977,7 +65977,7 @@ pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66002,7 +66002,7 @@ pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66027,7 +66027,7 @@ pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66052,7 +66052,7 @@ pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66077,7 +66077,7 @@ pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66102,7 +66102,7 @@ pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66127,7 +66127,7 @@ pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66152,7 +66152,7 @@ pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66177,7 +66177,7 @@ pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66202,7 +66202,7 @@ pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66227,7 +66227,7 @@ pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66252,7 +66252,7 @@ pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66277,7 +66277,7 @@ pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66302,7 +66302,7 @@ pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66327,7 +66327,7 @@ pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66352,7 +66352,7 @@ pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66377,7 +66377,7 @@ pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66402,7 +66402,7 @@ pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66427,7 +66427,7 @@ pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66452,7 +66452,7 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -66477,7 +66477,7 @@ pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66502,7 +66502,7 @@ pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66527,7 +66527,7 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66550,7 +66550,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66573,7 +66573,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66596,7 +66596,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66619,7 +66619,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66642,7 +66642,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66665,7 +66665,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66684,7 +66684,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66703,7 +66703,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66722,7 +66722,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66741,7 +66741,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66760,7 +66760,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66779,7 +66779,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66798,7 +66798,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66817,7 +66817,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66833,7 +66833,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66849,7 +66849,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66865,7 +66865,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66881,7 +66881,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66897,7 +66897,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66913,7 +66913,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66929,7 +66929,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66945,7 +66945,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66964,7 +66964,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66983,7 +66983,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67002,7 +67002,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67021,7 +67021,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67040,7 +67040,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67059,7 +67059,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67078,7 +67078,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67097,7 +67097,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67113,7 +67113,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67129,7 +67129,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67145,7 +67145,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67161,7 +67161,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67177,7 +67177,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67193,7 +67193,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67209,7 +67209,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67225,7 +67225,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67244,7 +67244,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67263,7 +67263,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67282,7 +67282,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67301,7 +67301,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67320,7 +67320,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67339,7 +67339,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67358,7 +67358,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67377,7 +67377,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67393,7 +67393,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67409,7 +67409,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67425,7 +67425,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67441,7 +67441,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67457,7 +67457,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67473,7 +67473,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67489,7 +67489,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67505,7 +67505,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67528,7 +67528,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67551,7 +67551,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67574,7 +67574,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67597,7 +67597,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67620,7 +67620,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67643,7 +67643,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67666,7 +67666,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67689,7 +67689,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67712,7 +67712,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67735,7 +67735,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67758,7 +67758,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67781,7 +67781,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67804,7 +67804,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67827,7 +67827,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67850,7 +67850,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67873,7 +67873,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67896,7 +67896,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67919,7 +67919,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67942,7 +67942,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67965,7 +67965,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67988,7 +67988,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68011,7 +68011,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68034,7 +68034,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68057,7 +68057,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68080,7 +68080,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68103,7 +68103,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68126,7 +68126,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68149,7 +68149,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68172,7 +68172,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68195,7 +68195,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68218,7 +68218,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68241,7 +68241,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68264,7 +68264,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68287,7 +68287,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68310,7 +68310,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68473,7 +68473,7 @@ unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68491,7 +68491,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68509,7 +68509,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -68534,7 +68534,7 @@ pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68555,7 +68555,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68576,7 +68576,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68595,7 +68595,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68614,7 +68614,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68633,7 +68633,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68652,7 +68652,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68671,7 +68671,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68690,7 +68690,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68709,7 +68709,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68728,7 +68728,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68747,7 +68747,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68766,7 +68766,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68782,7 +68782,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68798,7 +68798,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68814,7 +68814,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68830,7 +68830,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68846,7 +68846,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68862,7 +68862,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68878,7 +68878,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68894,7 +68894,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68917,7 +68917,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68940,7 +68940,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68961,7 +68961,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68982,7 +68982,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69003,7 +69003,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69024,7 +69024,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69045,7 +69045,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69066,7 +69066,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69087,7 +69087,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69108,7 +69108,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69129,7 +69129,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69147,7 +69147,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69165,7 +69165,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69183,7 +69183,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69201,7 +69201,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69219,7 +69219,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69237,7 +69237,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69255,7 +69255,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69280,7 +69280,7 @@ pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69305,7 +69305,7 @@ pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69330,7 +69330,7 @@ pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69355,7 +69355,7 @@ pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69380,7 +69380,7 @@ pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69405,7 +69405,7 @@ pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69430,7 +69430,7 @@ pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69455,7 +69455,7 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -69478,7 +69478,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69494,7 +69494,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69513,7 +69513,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69536,7 +69536,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69559,7 +69559,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69582,7 +69582,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69605,7 +69605,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69628,7 +69628,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69651,7 +69651,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69674,7 +69674,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69697,7 +69697,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69720,7 +69720,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69743,7 +69743,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69766,7 +69766,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69785,7 +69785,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69804,7 +69804,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69825,7 +69825,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69846,7 +69846,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69862,7 +69862,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69878,7 +69878,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69894,7 +69894,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69910,7 +69910,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69926,7 +69926,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69942,7 +69942,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69958,7 +69958,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69974,7 +69974,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69993,7 +69993,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70012,7 +70012,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70031,7 +70031,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70050,7 +70050,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70069,7 +70069,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70088,7 +70088,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70107,7 +70107,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70126,7 +70126,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -70154,7 +70154,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -70182,7 +70182,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70205,7 +70205,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70228,7 +70228,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70253,7 +70253,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70278,7 +70278,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70296,7 +70296,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70321,7 +70321,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70346,7 +70346,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70371,7 +70371,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70396,7 +70396,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70417,7 +70417,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70438,7 +70438,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70459,7 +70459,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70480,7 +70480,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70501,7 +70501,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70522,7 +70522,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70543,7 +70543,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70568,7 +70568,7 @@ pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70593,7 +70593,7 @@ pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70618,7 +70618,7 @@ pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70643,7 +70643,7 @@ pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70668,7 +70668,7 @@ pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70693,7 +70693,7 @@ pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70718,7 +70718,7 @@ pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70743,7 +70743,7 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -70766,7 +70766,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70785,7 +70785,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70801,7 +70801,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70824,7 +70824,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70847,7 +70847,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70870,7 +70870,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70893,7 +70893,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70916,7 +70916,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70939,7 +70939,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70962,7 +70962,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70985,7 +70985,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71008,7 +71008,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71031,7 +71031,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71054,7 +71054,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71080,7 +71080,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71106,7 +71106,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71127,7 +71127,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71148,7 +71148,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71171,7 +71171,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71194,7 +71194,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71210,7 +71210,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71233,7 +71233,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71256,7 +71256,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71279,7 +71279,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71302,7 +71302,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71325,7 +71325,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71344,7 +71344,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71363,7 +71363,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71382,7 +71382,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71401,7 +71401,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71420,7 +71420,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71439,7 +71439,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71458,7 +71458,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71477,7 +71477,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71506,7 +71506,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71535,7 +71535,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71565,7 +71565,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71595,7 +71595,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71621,7 +71621,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71647,7 +71647,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71673,7 +71673,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71699,7 +71699,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71725,7 +71725,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71751,7 +71751,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71777,7 +71777,7 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71805,7 +71805,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71833,7 +71833,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71854,7 +71854,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71882,7 +71882,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71910,7 +71910,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71938,7 +71938,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71966,7 +71966,7 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71991,7 +71991,7 @@ pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72016,7 +72016,7 @@ pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72041,7 +72041,7 @@ pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72066,7 +72066,7 @@ pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72091,7 +72091,7 @@ pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72116,7 +72116,7 @@ pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72141,7 +72141,7 @@ pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72166,7 +72166,7 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -72189,7 +72189,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -72212,7 +72212,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -72231,7 +72231,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72254,7 +72254,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72277,7 +72277,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72300,7 +72300,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72323,7 +72323,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72346,7 +72346,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72369,7 +72369,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72392,7 +72392,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72415,7 +72415,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72438,7 +72438,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72461,7 +72461,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72484,7 +72484,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs index 71301c5ba6cea..ce427d54b3552 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs @@ -840,7 +840,7 @@ impl fmt::Display for UnsafetyComment { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { Self::Custom(s) => s.fmt(f), - Self::Neon => write!(f, "Neon instrinsic unsafe"), + Self::Neon => write!(f, "Neon intrinsic unsafe"), Self::Uninitialized => write!( f, "This creates an uninitialized value, and may be unsound (like \ From 5dbaac135785bca7152c5809430b1fb1653db8b1 Mon Sep 17 00:00:00 2001 From: Leonard Chan Date: Tue, 27 Jan 2026 11:25:04 -0800 Subject: [PATCH 12/20] Remove Fuchsia from target OS list in unix.rs for sleep --- library/std/src/sys/thread/mod.rs | 2 -- library/std/src/sys/thread/unix.rs | 2 -- library/std/src/thread/functions.rs | 1 - 3 files changed, 5 deletions(-) diff --git a/library/std/src/sys/thread/mod.rs b/library/std/src/sys/thread/mod.rs index 5010774dafde2..9816981c7fc88 100644 --- a/library/std/src/sys/thread/mod.rs +++ b/library/std/src/sys/thread/mod.rs @@ -70,7 +70,6 @@ cfg_select! { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", target_vendor = "apple", @@ -131,7 +130,6 @@ cfg_select! { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", target_vendor = "apple", diff --git a/library/std/src/sys/thread/unix.rs b/library/std/src/sys/thread/unix.rs index e708c9a3f1bab..b758737d00c64 100644 --- a/library/std/src/sys/thread/unix.rs +++ b/library/std/src/sys/thread/unix.rs @@ -542,7 +542,6 @@ pub fn sleep(dur: Duration) { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", ) => { @@ -640,7 +639,6 @@ pub fn sleep(dur: Duration) { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", ))] diff --git a/library/std/src/thread/functions.rs b/library/std/src/thread/functions.rs index 73d7278785704..95d7aaf518408 100644 --- a/library/std/src/thread/functions.rs +++ b/library/std/src/thread/functions.rs @@ -316,7 +316,6 @@ pub fn sleep(dur: Duration) { /// | Illumos | [clock_nanosleep] (Monotonic Clock)] | /// | Dragonfly | [clock_nanosleep] (Monotonic Clock)] | /// | Hurd | [clock_nanosleep] (Monotonic Clock)] | -/// | Fuchsia | [clock_nanosleep] (Monotonic Clock)] | /// | Vxworks | [clock_nanosleep] (Monotonic Clock)] | /// | Apple | `mach_wait_until` | /// | Other | `sleep_until` uses [`sleep`] and does not issue a syscall itself | From 35ccf1847726e3f0b62c6fa55f3979dfe5c1d533 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 21 Jan 2026 11:46:49 +0100 Subject: [PATCH 13/20] Add regression test for #151411 --- .../deprecated-note-from-reexported.rs | 17 ++++++++++++ .../deprecated-note-from-reexported.stderr | 27 ++++++++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs index 3d1e48a4c6382..91447e5fa166b 100644 --- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs +++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs @@ -14,3 +14,20 @@ pub mod bar { //~| ERROR: unresolved link pub fn sql_function_proc() {} } + +// From here, this is a regression test for . +pub use fuzz_test_helpers::*; + +/// A type referenced in the deprecation note. +pub struct Env; + +impl Env { + pub fn try_invoke(&self) {} +} + +mod fuzz_test_helpers { + #[deprecated(note = "use [Env::try_invoke] instead")] + //~^ ERROR: unresolved link + //~| ERROR: unresolved link + pub fn fuzz_catch_panic() {} +} diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr index 25f10b24d9fb5..cb7a5f0c6e022 100644 --- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr +++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr @@ -16,6 +16,18 @@ note: the lint level is defined here LL | #![deny(rustdoc::broken_intra_doc_links)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +error: unresolved link to `Env::try_invoke` + --> $DIR/deprecated-note-from-reexported.rs:29:25 + | +LL | #[deprecated(note = "use [Env::try_invoke] instead")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: the link appears in this line: + + use [Env::try_invoke] instead + ^^^^^^^^^^^^^^^ + = note: no item named `Env` in scope + error: unresolved link to `define_sql_function` --> $DIR/deprecated-note-from-reexported.rs:12:25 | @@ -30,5 +42,18 @@ LL | #[deprecated(note = "Use [`define_sql_function`] instead")] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]` = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` -error: aborting due to 2 previous errors +error: unresolved link to `Env::try_invoke` + --> $DIR/deprecated-note-from-reexported.rs:29:25 + | +LL | #[deprecated(note = "use [Env::try_invoke] instead")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: the link appears in this line: + + use [Env::try_invoke] instead + ^^^^^^^^^^^^^^^ + = note: no item named `Env` in scope + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 4 previous errors From b0d96492d032f6107bbcad2a02895592034e5ab7 Mon Sep 17 00:00:00 2001 From: Jeremy Smart Date: Tue, 27 Jan 2026 19:30:37 -0500 Subject: [PATCH 14/20] fix undefined behavior in VecDeque::splice --- library/alloc/src/collections/vec_deque/splice.rs | 6 +++++- library/alloctests/tests/vec_deque.rs | 11 +++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/library/alloc/src/collections/vec_deque/splice.rs b/library/alloc/src/collections/vec_deque/splice.rs index cd98af7341ded..d7b9a96291c39 100644 --- a/library/alloc/src/collections/vec_deque/splice.rs +++ b/library/alloc/src/collections/vec_deque/splice.rs @@ -143,7 +143,11 @@ impl Drain<'_, T, A> { let new_tail_start = tail_start + additional; unsafe { - deque.wrap_copy(tail_start, new_tail_start, self.tail_len); + deque.wrap_copy( + deque.to_physical_idx(tail_start), + deque.to_physical_idx(new_tail_start), + self.tail_len, + ); } self.drain_len += additional; } diff --git a/library/alloctests/tests/vec_deque.rs b/library/alloctests/tests/vec_deque.rs index e06d18250a51a..92853fe00fd63 100644 --- a/library/alloctests/tests/vec_deque.rs +++ b/library/alloctests/tests/vec_deque.rs @@ -2336,3 +2336,14 @@ fn test_splice_forget() { std::mem::forget(v.splice(2..4, a)); assert_eq!(v, &[1, 2]); } + +#[test] +fn test_splice_wrapping() { + let mut vec = VecDeque::with_capacity(10); + vec.push_front(7u8); + vec.push_back(9); + + vec.splice(1..1, [8]); + + assert_eq!(Vec::from(vec), [7, 8, 9]); +} From 5ddb7f6dd2279d920b8277485afef4a1dee3270d Mon Sep 17 00:00:00 2001 From: dianne Date: Tue, 27 Jan 2026 17:12:11 -0800 Subject: [PATCH 15/20] clean up checks for integer div/rem promotion --- .../rustc_mir_transform/src/promote_consts.rs | 62 +++++++------------ 1 file changed, 24 insertions(+), 38 deletions(-) diff --git a/compiler/rustc_mir_transform/src/promote_consts.rs b/compiler/rustc_mir_transform/src/promote_consts.rs index 6e7b93a5e719f..3d1537b95efa9 100644 --- a/compiler/rustc_mir_transform/src/promote_consts.rs +++ b/compiler/rustc_mir_transform/src/promote_consts.rs @@ -485,47 +485,33 @@ impl<'tcx> Validator<'_, 'tcx> { if lhs_ty.is_integral() { let sz = lhs_ty.primitive_size(self.tcx); // Integer division: the RHS must be a non-zero const. - let rhs_val = match rhs { - Operand::Constant(c) - if self.should_evaluate_for_promotion_checks(c.const_) => - { - c.const_.try_eval_scalar_int(self.tcx, self.typing_env) - } - _ => None, - }; - match rhs_val.map(|x| x.to_uint(sz)) { + let rhs_val = if let Operand::Constant(rhs_c) = rhs + && self.should_evaluate_for_promotion_checks(rhs_c.const_) + && let Some(rhs_val) = + rhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env) // for the zero test, int vs uint does not matter - Some(x) if x != 0 => {} // okay - _ => return Err(Unpromotable), // value not known or 0 -- not okay - } + && rhs_val.to_uint(sz) != 0 + { + rhs_val + } else { + // value not known or 0 -- not okay + return Err(Unpromotable); + }; // Furthermore, for signed division, we also have to exclude `int::MIN / // -1`. - if lhs_ty.is_signed() { - match rhs_val.map(|x| x.to_int(sz)) { - Some(-1) | None => { - // The RHS is -1 or unknown, so we have to be careful. - // But is the LHS int::MIN? - let lhs_val = match lhs { - Operand::Constant(c) - if self.should_evaluate_for_promotion_checks( - c.const_, - ) => - { - c.const_ - .try_eval_scalar_int(self.tcx, self.typing_env) - } - _ => None, - }; - let lhs_min = sz.signed_int_min(); - match lhs_val.map(|x| x.to_int(sz)) { - // okay - Some(x) if x != lhs_min => {} - - // value not known or int::MIN -- not okay - _ => return Err(Unpromotable), - } - } - _ => {} + if lhs_ty.is_signed() && rhs_val.to_int(sz) == -1 { + // The RHS is -1, so we have to be careful. But is the LHS int::MIN? + if let Operand::Constant(lhs_c) = lhs + && self.should_evaluate_for_promotion_checks(lhs_c.const_) + && let Some(lhs_val) = + lhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env) + && let lhs_min = sz.signed_int_min() + && lhs_val.to_int(sz) != lhs_min + { + // okay + } else { + // value not known or int::MIN -- not okay + return Err(Unpromotable); } } } From 10e053dbb5c7ac3679044f222112682c9fc0758a Mon Sep 17 00:00:00 2001 From: Hood Chatham Date: Mon, 26 Jan 2026 10:34:50 -0800 Subject: [PATCH 16/20] Implement `set_output_kind` for Emscripten linker This makes cdylibs compile to working Emscripten dynamic libraries without passing extra RUSTFLAGS. This was previously approved as PR 98358 but there were CI failures that I never got around to fixing. --- compiler/rustc_codegen_ssa/src/back/linker.rs | 15 ++++++++++++++- .../src/spec/targets/wasm32_unknown_emscripten.rs | 2 ++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_codegen_ssa/src/back/linker.rs b/compiler/rustc_codegen_ssa/src/back/linker.rs index 1b75db51140b8..db49f92e39acc 100644 --- a/compiler/rustc_codegen_ssa/src/back/linker.rs +++ b/compiler/rustc_codegen_ssa/src/back/linker.rs @@ -1208,10 +1208,23 @@ impl<'a> Linker for EmLinker<'a> { fn set_output_kind( &mut self, - _output_kind: LinkOutputKind, + output_kind: LinkOutputKind, _crate_type: CrateType, _out_filename: &Path, ) { + match output_kind { + LinkOutputKind::DynamicNoPicExe | LinkOutputKind::DynamicPicExe => { + self.cmd.arg("-sMAIN_MODULE=2"); + } + LinkOutputKind::DynamicDylib | LinkOutputKind::StaticDylib => { + self.cmd.arg("-sSIDE_MODULE=2"); + } + // -fno-pie is the default on Emscripten. + LinkOutputKind::StaticNoPicExe | LinkOutputKind::StaticPicExe => {} + LinkOutputKind::WasiReactorExe => { + unreachable!(); + } + } } fn link_dylib_by_name(&mut self, name: &str, _verbatim: bool, _as_needed: bool) { diff --git a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs index 47623c34dce32..fb735b54dd82c 100644 --- a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs +++ b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs @@ -19,6 +19,8 @@ pub(crate) fn target() -> Target { pre_link_args, post_link_args, relocation_model: RelocModel::Pic, + crt_static_respected: true, + crt_static_default: true, panic_strategy: PanicStrategy::Unwind, no_default_libraries: false, families: cvs!["unix", "wasm"], From 11ae531ac82fd502a6de59e7508a4546960cbee4 Mon Sep 17 00:00:00 2001 From: Arseni Novikau Date: Tue, 6 Jan 2026 01:22:43 +0300 Subject: [PATCH 17/20] diagnostics: don't suggest `#[derive]` if impl already exists --- .../rustc_hir_typeck/src/method/suggest.rs | 88 +++++++++++++------ ...rive-clone-already-present-issue-146515.rs | 20 +++++ ...-clone-already-present-issue-146515.stderr | 23 +++++ 3 files changed, 102 insertions(+), 29 deletions(-) create mode 100644 tests/ui/suggestions/derive-clone-already-present-issue-146515.rs create mode 100644 tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr diff --git a/compiler/rustc_hir_typeck/src/method/suggest.rs b/compiler/rustc_hir_typeck/src/method/suggest.rs index b2803f4347e37..5673d044ad2ce 100644 --- a/compiler/rustc_hir_typeck/src/method/suggest.rs +++ b/compiler/rustc_hir_typeck/src/method/suggest.rs @@ -3281,6 +3281,63 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { } } + /// Checks if we can suggest a derive macro for the unmet trait bound. + /// Returns Some(list_of_derives) if possible, or None if not. + fn consider_suggesting_derives_for_ty( + &self, + trait_pred: ty::TraitPredicate<'tcx>, + adt: ty::AdtDef<'tcx>, + ) -> Option> { + let diagnostic_name = self.tcx.get_diagnostic_name(trait_pred.def_id())?; + + let can_derive = match diagnostic_name { + sym::Default + | sym::Eq + | sym::PartialEq + | sym::Ord + | sym::PartialOrd + | sym::Clone + | sym::Copy + | sym::Hash + | sym::Debug => true, + _ => false, + }; + + if !can_derive { + return None; + } + + let trait_def_id = trait_pred.def_id(); + let self_ty = trait_pred.self_ty(); + + // We need to check if there is already a manual implementation of the trait + // for this specific ADT to avoid suggesting `#[derive(..)]` that would conflict. + if self.tcx.non_blanket_impls_for_ty(trait_def_id, self_ty).any(|impl_def_id| { + self.tcx + .type_of(impl_def_id) + .instantiate_identity() + .ty_adt_def() + .is_some_and(|def| def.did() == adt.did()) + }) { + return None; + } + + let mut derives = Vec::new(); + let self_name = self_ty.to_string(); + let self_span = self.tcx.def_span(adt.did()); + + for super_trait in supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref)) { + if let Some(parent_diagnostic_name) = self.tcx.get_diagnostic_name(super_trait.def_id()) + { + derives.push((self_name.clone(), self_span, parent_diagnostic_name)); + } + } + + derives.push((self_name, self_span, diagnostic_name)); + + Some(derives) + } + fn note_predicate_source_and_get_derives( &self, err: &mut Diag<'_>, @@ -3298,35 +3355,8 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { Some(adt) if adt.did().is_local() => adt, _ => continue, }; - if let Some(diagnostic_name) = self.tcx.get_diagnostic_name(trait_pred.def_id()) { - let can_derive = match diagnostic_name { - sym::Default - | sym::Eq - | sym::PartialEq - | sym::Ord - | sym::PartialOrd - | sym::Clone - | sym::Copy - | sym::Hash - | sym::Debug => true, - _ => false, - }; - if can_derive { - let self_name = trait_pred.self_ty().to_string(); - let self_span = self.tcx.def_span(adt.did()); - for super_trait in - supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref)) - { - if let Some(parent_diagnostic_name) = - self.tcx.get_diagnostic_name(super_trait.def_id()) - { - derives.push((self_name.clone(), self_span, parent_diagnostic_name)); - } - } - derives.push((self_name, self_span, diagnostic_name)); - } else { - traits.push(trait_pred.def_id()); - } + if let Some(new_derives) = self.consider_suggesting_derives_for_ty(trait_pred, adt) { + derives.extend(new_derives); } else { traits.push(trait_pred.def_id()); } diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs new file mode 100644 index 0000000000000..083d73711a517 --- /dev/null +++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs @@ -0,0 +1,20 @@ +// issue: https://github.com/rust-lang/rust/issues/146515 + +use std::rc::Rc; + +#[derive(Clone)] +struct ContainsRc { + value: Rc, +} + +fn clone_me(x: &ContainsRc) -> ContainsRc { + //~^ NOTE expected `ContainsRc` because of return type + x.clone() + //~^ ERROR mismatched types + //~| NOTE expected `ContainsRc`, found `&ContainsRc` + //~| NOTE expected struct `ContainsRc<_>` + //~| NOTE `ContainsRc` does not implement `Clone`, so `&ContainsRc` was cloned instead + //~| NOTE the trait `Clone` must be implemented +} + +fn main() {} diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr new file mode 100644 index 0000000000000..516ef38f668dc --- /dev/null +++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr @@ -0,0 +1,23 @@ +error[E0308]: mismatched types + --> $DIR/derive-clone-already-present-issue-146515.rs:12:5 + | +LL | fn clone_me(x: &ContainsRc) -> ContainsRc { + | ------------- expected `ContainsRc` because of return type +LL | +LL | x.clone() + | ^^^^^^^^^ expected `ContainsRc`, found `&ContainsRc` + | + = note: expected struct `ContainsRc<_>` + found reference `&ContainsRc<_>` +note: `ContainsRc` does not implement `Clone`, so `&ContainsRc` was cloned instead + --> $DIR/derive-clone-already-present-issue-146515.rs:12:5 + | +LL | x.clone() + | ^ + = help: `Clone` is not implemented because the trait bound `T: Clone` is not satisfied +note: the trait `Clone` must be implemented + --> $SRC_DIR/core/src/clone.rs:LL:COL + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0308`. From f4b4ab3b23d0f5aac4de9c71ffb678ce25e52159 Mon Sep 17 00:00:00 2001 From: usamoi Date: Sat, 10 Jan 2026 20:53:43 +0800 Subject: [PATCH 18/20] remove fp16 target feature from some vreinterpret intrinsics --- .../src/arm_shared/neon/generated.rs | 200 +++++++++--------- .../spec/neon/arm_shared.spec.yml | 2 - 2 files changed, 100 insertions(+), 102 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 0aeb740efcd0a..1a994c153ade3 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -42565,13 +42565,13 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42588,13 +42588,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42615,13 +42615,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42638,13 +42638,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42665,13 +42665,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42688,13 +42688,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42715,13 +42715,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42738,13 +42738,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42765,13 +42765,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42788,13 +42788,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42812,13 +42812,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42835,13 +42835,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42862,13 +42862,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42885,13 +42885,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42912,13 +42912,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42935,13 +42935,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42962,13 +42962,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42985,13 +42985,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43009,13 +43009,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43032,13 +43032,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43059,13 +43059,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43082,13 +43082,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43109,13 +43109,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43132,13 +43132,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43159,13 +43159,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43182,13 +43182,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43213,13 +43213,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43236,13 +43236,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43263,13 +43263,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43286,13 +43286,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43313,13 +43313,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43336,13 +43336,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43363,13 +43363,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43386,13 +43386,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43417,13 +43417,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43440,13 +43440,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43467,13 +43467,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43490,13 +43490,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43517,13 +43517,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43540,13 +43540,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43567,13 +43567,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43590,13 +43590,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43621,13 +43621,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43644,13 +43644,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43671,13 +43671,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43694,13 +43694,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43721,13 +43721,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43744,13 +43744,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43771,13 +43771,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43794,13 +43794,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43821,13 +43821,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43844,13 +43844,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43872,13 +43872,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43895,13 +43895,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43922,13 +43922,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43945,13 +43945,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43972,13 +43972,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43995,13 +43995,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44022,13 +44022,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44045,13 +44045,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44072,13 +44072,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44095,13 +44095,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44121,13 +44121,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44144,13 +44144,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44171,13 +44171,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44194,13 +44194,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44221,13 +44221,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44244,13 +44244,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44272,13 +44272,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44295,13 +44295,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44322,13 +44322,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44345,13 +44345,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44372,13 +44372,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44395,13 +44395,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44422,13 +44422,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44445,13 +44445,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44472,13 +44472,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44495,13 +44495,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44521,13 +44521,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44544,13 +44544,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44571,13 +44571,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44594,13 +44594,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44621,13 +44621,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44644,13 +44644,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44672,13 +44672,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44695,13 +44695,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44722,13 +44722,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44745,13 +44745,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44772,13 +44772,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44795,13 +44795,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44821,13 +44821,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44844,13 +44844,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44868,13 +44868,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44891,13 +44891,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44915,13 +44915,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44938,13 +44938,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44965,13 +44965,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44988,13 +44988,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -45014,13 +45014,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] #[inline] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -45037,13 +45037,13 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] #[inline] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index c7a333d7f75ec..d8e8cd0e7c119 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -8785,7 +8785,6 @@ intrinsics: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-fp16 - *neon-not-arm-stable-fp16 - *neon-cfg-arm-unstable - *target-not-arm64ec @@ -8849,7 +8848,6 @@ intrinsics: - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-fp16 - *neon-not-arm-stable-fp16 - *neon-cfg-arm-unstable - *target-not-arm64ec From 18a4a3ace0afcce1e4be81dbd9954c58bf60e5aa Mon Sep 17 00:00:00 2001 From: usamoi Date: Wed, 28 Jan 2026 19:15:25 +0800 Subject: [PATCH 19/20] fix overflowing_literals in avx512fp16 tests --- library/stdarch/crates/core_arch/src/x86/avx512fp16.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 57d47c0bb010a..2b80215c41af7 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -23993,16 +23993,16 @@ mod tests { #[simd_test(enable = "avx512fp16,avx512vl")] const fn test_mm256_reduce_mul_ph() { - let a = _mm256_set1_ph(2.0); + let a = _mm256_set1_ph(1.2); let r = _mm256_reduce_mul_ph(a); - assert_eq!(r, 65536.0); + assert_eq!(r, 18.5); } #[simd_test(enable = "avx512fp16")] const fn test_mm512_reduce_mul_ph() { - let a = _mm512_set1_ph(2.0); + let a = _mm512_set1_ph(1.2); let r = _mm512_reduce_mul_ph(a); - assert_eq!(r, 16777216.0); + assert_eq!(r, 342.3); } #[simd_test(enable = "avx512fp16,avx512vl")] From 9ca8ed38eb3d1e138cd8b6a8f586baa7fe52e980 Mon Sep 17 00:00:00 2001 From: Usman Akinyemi Date: Wed, 28 Jan 2026 02:54:32 +0530 Subject: [PATCH 20/20] rustc_parse: improve the error diagnostic for "missing let in let chain" Signed-off-by: Usman Akinyemi --- compiler/rustc_parse/src/parser/expr.rs | 55 ++++++++++++++----- tests/ui/expr/if/bad-if-let-suggestion.rs | 4 +- tests/ui/expr/if/bad-if-let-suggestion.stderr | 30 ++-------- tests/ui/missing/missing-let.rs | 6 ++ tests/ui/missing/missing-let.stderr | 18 ++++++ 5 files changed, 73 insertions(+), 40 deletions(-) create mode 100644 tests/ui/missing/missing-let.rs create mode 100644 tests/ui/missing/missing-let.stderr diff --git a/compiler/rustc_parse/src/parser/expr.rs b/compiler/rustc_parse/src/parser/expr.rs index c31a4798b471e..44c6acec88660 100644 --- a/compiler/rustc_parse/src/parser/expr.rs +++ b/compiler/rustc_parse/src/parser/expr.rs @@ -2760,9 +2760,13 @@ impl<'a> Parser<'a> { let (mut cond, _) = self.parse_expr_res(Restrictions::NO_STRUCT_LITERAL | Restrictions::ALLOW_LET, attrs)?; - CondChecker::new(self, let_chains_policy).visit_expr(&mut cond); - - Ok(cond) + let mut checker = CondChecker::new(self, let_chains_policy); + checker.visit_expr(&mut cond); + Ok(if let Some(guar) = checker.found_incorrect_let_chain { + self.mk_expr_err(cond.span, guar) + } else { + cond + }) } /// Parses a `let $pat = $expr` pseudo-expression. @@ -3484,13 +3488,19 @@ impl<'a> Parser<'a> { let if_span = self.prev_token.span; let mut cond = self.parse_match_guard_condition()?; - CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond); + let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed); + checker.visit_expr(&mut cond); if has_let_expr(&cond) { let span = if_span.to(cond.span); self.psess.gated_spans.gate(sym::if_let_guard, span); } - Ok(Some(cond)) + + Ok(Some(if let Some(guar) = checker.found_incorrect_let_chain { + self.mk_expr_err(cond.span, guar) + } else { + cond + })) } fn parse_match_arm_pat_and_guard(&mut self) -> PResult<'a, (Pat, Option>)> { @@ -3511,13 +3521,23 @@ impl<'a> Parser<'a> { let ast::PatKind::Paren(subpat) = pat.kind else { unreachable!() }; let ast::PatKind::Guard(_, mut cond) = subpat.kind else { unreachable!() }; self.psess.gated_spans.ungate_last(sym::guard_patterns, cond.span); - CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond); + let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed); + checker.visit_expr(&mut cond); + let right = self.prev_token.span; self.dcx().emit_err(errors::ParenthesesInMatchPat { span: vec![left, right], sugg: errors::ParenthesesInMatchPatSugg { left, right }, }); - Ok((self.mk_pat(span, ast::PatKind::Wild), Some(cond))) + + Ok(( + self.mk_pat(span, ast::PatKind::Wild), + (if let Some(guar) = checker.found_incorrect_let_chain { + Some(self.mk_expr_err(cond.span, guar)) + } else { + Some(cond) + }), + )) } else { Ok((pat, self.parse_match_arm_guard()?)) } @@ -4208,6 +4228,7 @@ struct CondChecker<'a> { forbid_let_reason: Option, missing_let: Option, comparison: Option, + found_incorrect_let_chain: Option, } impl<'a> CondChecker<'a> { @@ -4218,6 +4239,7 @@ impl<'a> CondChecker<'a> { missing_let: None, comparison: None, let_chains_policy, + found_incorrect_let_chain: None, depth: 0, } } @@ -4236,12 +4258,19 @@ impl MutVisitor for CondChecker<'_> { NotSupportedOr(or_span) => { self.parser.dcx().emit_err(errors::OrInLetChain { span: or_span }) } - _ => self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet { - span, - reason, - missing_let: self.missing_let, - comparison: self.comparison, - }), + _ => { + let guar = + self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet { + span, + reason, + missing_let: self.missing_let, + comparison: self.comparison, + }); + if let Some(_) = self.missing_let { + self.found_incorrect_let_chain = Some(guar); + } + guar + } }; *recovered = Recovered::Yes(error); } else if self.depth > 1 { diff --git a/tests/ui/expr/if/bad-if-let-suggestion.rs b/tests/ui/expr/if/bad-if-let-suggestion.rs index b0d0676e1ea75..c462e32c9ef55 100644 --- a/tests/ui/expr/if/bad-if-let-suggestion.rs +++ b/tests/ui/expr/if/bad-if-let-suggestion.rs @@ -1,8 +1,6 @@ fn a() { if let x = 1 && i = 2 {} - //~^ ERROR cannot find value `i` in this scope - //~| ERROR mismatched types - //~| ERROR expected expression, found `let` statement + //~^ ERROR expected expression, found `let` statement } fn b() { diff --git a/tests/ui/expr/if/bad-if-let-suggestion.stderr b/tests/ui/expr/if/bad-if-let-suggestion.stderr index 4244a3bb06eea..d0838fec67d66 100644 --- a/tests/ui/expr/if/bad-if-let-suggestion.stderr +++ b/tests/ui/expr/if/bad-if-let-suggestion.stderr @@ -15,13 +15,7 @@ LL | if let x = 1 && i == 2 {} | + error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:2:21 - | -LL | if let x = 1 && i = 2 {} - | ^ not found in this scope - -error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:9 + --> $DIR/bad-if-let-suggestion.rs:7:9 | LL | fn a() { | ------ similarly named function `a` defined here @@ -36,7 +30,7 @@ LL + if (a + j) = i {} | error[E0425]: cannot find value `j` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:13 + --> $DIR/bad-if-let-suggestion.rs:7:13 | LL | fn a() { | ------ similarly named function `a` defined here @@ -51,7 +45,7 @@ LL + if (i + a) = i {} | error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:18 + --> $DIR/bad-if-let-suggestion.rs:7:18 | LL | fn a() { | ------ similarly named function `a` defined here @@ -66,7 +60,7 @@ LL + if (i + j) = a {} | error[E0425]: cannot find value `x` in this scope - --> $DIR/bad-if-let-suggestion.rs:16:8 + --> $DIR/bad-if-let-suggestion.rs:14:8 | LL | fn a() { | ------ similarly named function `a` defined here @@ -80,18 +74,6 @@ LL - if x[0] = 1 {} LL + if a[0] = 1 {} | -error[E0308]: mismatched types - --> $DIR/bad-if-let-suggestion.rs:2:8 - | -LL | if let x = 1 && i = 2 {} - | ^^^^^^^^^^^^^^^^^^ expected `bool`, found `()` - | -help: you might have meant to compare for equality - | -LL | if let x = 1 && i == 2 {} - | + - -error: aborting due to 7 previous errors +error: aborting due to 5 previous errors -Some errors have detailed explanations: E0308, E0425. -For more information about an error, try `rustc --explain E0308`. +For more information about this error, try `rustc --explain E0425`. diff --git a/tests/ui/missing/missing-let.rs b/tests/ui/missing/missing-let.rs new file mode 100644 index 0000000000000..36db7bc95826b --- /dev/null +++ b/tests/ui/missing/missing-let.rs @@ -0,0 +1,6 @@ +fn main() { + let x = Some(42); + if let Some(_) = x + && Some(x) = x //~^ ERROR expected expression, found `let` statement + {} +} diff --git a/tests/ui/missing/missing-let.stderr b/tests/ui/missing/missing-let.stderr new file mode 100644 index 0000000000000..897ff6329d593 --- /dev/null +++ b/tests/ui/missing/missing-let.stderr @@ -0,0 +1,18 @@ +error: expected expression, found `let` statement + --> $DIR/missing-let.rs:3:8 + | +LL | if let Some(_) = x + | ^^^^^^^^^^^^^^^ + | + = note: only supported directly in conditions of `if` and `while` expressions +help: you might have meant to continue the let-chain + | +LL | && let Some(x) = x + | +++ +help: you might have meant to compare for equality + | +LL | && Some(x) == x + | + + +error: aborting due to 1 previous error +