From 557cfbc5039d019f61a71ad106af0ec93279736e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Kr=C3=B6ning?= Date: Wed, 7 Jan 2026 17:48:54 +0100 Subject: [PATCH] fix(instructions): allow unused_unsafe for cpuid --- src/instructions/random.rs | 1 + src/instructions/smap.rs | 1 + src/instructions/tlb.rs | 2 ++ 3 files changed, 4 insertions(+) diff --git a/src/instructions/random.rs b/src/instructions/random.rs index 604da10e..d6b2009b 100644 --- a/src/instructions/random.rs +++ b/src/instructions/random.rs @@ -10,6 +10,7 @@ impl RdRand { pub fn new() -> Option { // RDRAND support indicated by CPUID page 01h, ecx bit 30 // https://en.wikipedia.org/wiki/RdRand#Overview + #[allow(unused_unsafe)] let cpuid = unsafe { core::arch::x86_64::__cpuid(0x1) }; if cpuid.ecx & (1 << 30) != 0 { Some(RdRand(())) diff --git a/src/instructions/smap.rs b/src/instructions/smap.rs index eb8d8a91..b616453f 100644 --- a/src/instructions/smap.rs +++ b/src/instructions/smap.rs @@ -35,6 +35,7 @@ impl Smap { /// CR4. pub fn new() -> Option { // Check if the CPU supports `stac` and `clac`. + #[allow(unused_unsafe)] let cpuid = unsafe { core::arch::x86_64::__cpuid(7) }; if cpuid.ebx.get_bit(20) { Some(Self(())) diff --git a/src/instructions/tlb.rs b/src/instructions/tlb.rs index 4a523483..d96cc895 100644 --- a/src/instructions/tlb.rs +++ b/src/instructions/tlb.rs @@ -160,6 +160,7 @@ impl Invlpgb { assert_eq!(cs.rpl(), PrivilegeLevel::Ring0); // Check if the `INVLPGB` and `TLBSYNC` instruction are supported. + #[allow(unused_unsafe)] let cpuid = unsafe { core::arch::x86_64::__cpuid(0x8000_0008) }; if !cpuid.ebx.get_bit(3) { return None; @@ -169,6 +170,7 @@ impl Invlpgb { let invlpgb_count_max = cpuid.edx.get_bits(0..=15) as u16; // Figure out the number of supported ASIDs. + #[allow(unused_unsafe)] let cpuid = unsafe { core::arch::x86_64::__cpuid(0x8000_000a) }; let nasid = cpuid.ebx;