From 4bb415a0f3b20a6bd4cbb30d9fc8910efe742cc3 Mon Sep 17 00:00:00 2001
From: Zhouqi Jiang <luojia@hust.edu.cn>
Date: Sat, 12 Jul 2025 19:09:56 +0800
Subject: [PATCH] feat(uart_xilinx): add documentation for struct Registers of
 uart_lite

Signed-off-by: Zhouqi Jiang <luojia@hust.edu.cn>
---
 uart_xilinx/src/uart_lite/registers.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/uart_xilinx/src/uart_lite/registers.rs b/uart_xilinx/src/uart_lite/registers.rs
index dc9c7b9..45d3b89 100644
--- a/uart_xilinx/src/uart_lite/registers.rs
+++ b/uart_xilinx/src/uart_lite/registers.rs
@@ -1,10 +1,17 @@
 use volatile_register::{RO, WO};
 
-/// # UART Registers
+/// UART Lite register block.
+///
+/// It consists of a control register, a status register, and a pair of
+/// transmit/receive FIFOs.
 #[repr(C)]
 pub struct Registers {
+    /// Receive data first-in first-out (FIFO) queue register.
     pub rx: RO<u32>,
+    /// Transmit data first-in first-out (FIFO) queue register.
     pub tx: WO<u32>,
+    /// Status register.
     pub stat: RO<u32>,
+    /// Control register.
     pub ctrl: WO<u32>,
 }