diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml index a0b0bf7..85ac83c 100644 --- a/.github/workflows/rust.yml +++ b/.github/workflows/rust.yml @@ -13,6 +13,8 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v3 + - name: Select nightly toolchain + run: rustup override set nightly - name: Build run: cargo build - name: Run tests diff --git a/Cargo.lock b/Cargo.lock index 87d31ab..24def58 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -33,14 +33,19 @@ version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae" +[[package]] +name = "tock-registers" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4ee8fba06c1f4d0b396ef61a54530bb6b28f0dc61c38bc8bc5a5a48161e6282e" + [[package]] name = "uart8250" version = "0.5.0" dependencies = [ - "bitflags", "embedded-hal", "nb 1.0.0", - "volatile-register", + "tock-registers", ] [[package]] diff --git a/uart8250/Cargo.toml b/uart8250/Cargo.toml index ff79064..54bffeb 100644 --- a/uart8250/Cargo.toml +++ b/uart8250/Cargo.toml @@ -14,10 +14,9 @@ readme = "README.md" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -bitflags = "1" embedded-hal = { version = "0.2.7", optional = true } nb = { version = "1.0.0", optional = true } -volatile-register = "0.2" +tock-registers = "0.7.0" [features] default = [] diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index 85b5c39..a934aeb 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -1,39 +1,209 @@ use core::u8; +use tock_registers::{ + register_bitfields, register_structs, + registers::{Aliased, ReadOnly, ReadWrite}, +}; -use volatile_register::{RO, RW}; - -/// # UART Registers -/// -/// The chip has a total of 12 different registers that are mapped into 8 different Port I/O locations / Memory Mapped I/O addresses. -/// -/// The following is a table of each of the registers that can be found in a typical UART chip -/// -/// | Base Address | DLAB | I/O Access | Abbrv. | Register Name | -/// | ------------ | ---- | ---------- | ------ | --------------------------------- | -/// | +0 | 0 | Write | THR | Transmitter Holding Buffer | -/// | +0 | 0 | Read | RBR | Receiver Buffer | -/// | +0 | 1 | Read/Write | DLL | Divisor Latch Low Byte | -/// | +1 | 0 | Read/Write | IER | Interrupt Enable Register | -/// | +1 | 1 | Read/Write | DLH | Divisor Latch High Byte | -/// | +2 | x | Read | IIR | Interrupt Identification Register | -/// | +2 | x | Write | FCR | FIFO Control Register | -/// | +3 | x | Read/Write | LCR | Line Control Register | -/// | +4 | x | Read/Write | MCR | Modem Control Register | -/// | +5 | x | Read | LSR | Line Status Register | -/// | +6 | x | Read | MSR | Modem Status Register | -/// | +7 | x | Read/Write | SR | Scratch Register | -#[repr(C, packed)] -pub struct Registers { - pub thr_rbr_dll: RW, - pub ier_dlh: RW, - pub iir_fcr: RW, - pub lcr: RW, - pub mcr: RW, - pub lsr: RO, - pub msr: RO, - pub scratch: RW, +register_structs! { + /// # UART Registers + /// + /// The chip has a total of 12 different registers that are mapped into 8 different Port I/O locations / Memory Mapped I/O addresses. + /// + /// The following is a table of each of the registers that can be found in a typical UART chip + /// + /// | Base Address | DLAB | I/O Access | Abbrv. | Register Name | + /// | ------------ | ---- | ---------- | ------ | --------------------------------- | + /// | +0 | 0 | Write | THR | Transmitter Holding Buffer | + /// | +0 | 0 | Read | RBR | Receiver Buffer | + /// | +0 | 1 | Read/Write | DLL | Divisor Latch Low Byte | + /// | +1 | 0 | Read/Write | IER | Interrupt Enable Register | + /// | +1 | 1 | Read/Write | DLH | Divisor Latch High Byte | + /// | +2 | x | Read | IIR | Interrupt Identification Register | + /// | +2 | x | Write | FCR | FIFO Control Register | + /// | +3 | x | Read/Write | LCR | Line Control Register | + /// | +4 | x | Read/Write | MCR | Modem Control Register | + /// | +5 | x | Read | LSR | Line Status Register | + /// | +6 | x | Read | MSR | Modem Status Register | + /// | +7 | x | Read/Write | SR | Scratch Register | + pub Registers { + (0x00 => pub thr_rbr_dll: ReadWrite), + (0x01 => pub ier_dlh: ReadWrite), + (0x02 => pub iir_fcr: Aliased), + (0x03 => pub lcr: ReadWrite), + (0x04 => pub mcr: ReadWrite), + (0x05 => pub lsr: ReadOnly), + (0x06 => pub msr: ReadOnly), + (0x07 => pub scratch: ReadWrite), + (0x08 => @END), + } } +register_bitfields![ + u8, + + /// Interrupt Enable Register + pub IER [ + /// Enable Received Data Available Interrupt + RDAI OFFSET(0) NUMBITS(1) [], + /// Enable Transmitter Holding Register Empty Interrupt + THREI OFFSET(1) NUMBITS(1) [], + /// Enable Receiver Line Status Interrupt + RLSI OFFSET(2) NUMBITS(1) [], + /// Enable Modem Status Interrupt + MSI OFFSET(3) NUMBITS(1) [], + /// Enable Sleep Mode (16750) + SM OFFSET(4) NUMBITS(1) [], + /// Enable Low Power Mode (16750) + LPM OFFSET(5) NUMBITS(1) [], + ], + + /// Line Control Register + pub LCR [ + /// Divisor Latch Access Bit + DLAB OFFSET(7) NUMBITS(1) [], + /// Set Break Enable + SBE OFFSET(6) NUMBITS(1) [], + /// Parity + Parity OFFSET(3) NUMBITS(3) [ + /// No parity + No = 0, + /// Odd parity + Odd = 1, + /// Even parity + Even = 3, + /// Mark + Mark = 5, + /// Space + Space = 7, + ], + /// Number of stop bits + STOP_BITS OFFSET(2) NUMBITS(1) [ + /// One stop bit + One = 0, + /// 1.5 or 2 stop bits + Two = 1, + ], + /// Word length + WORD_LENGTH OFFSET(0) NUMBITS(2) [ + /// 5 bit word length + Bits5 = 0, + /// 6 bit word length + Bits6 = 1, + /// 7 bit word length + Bits7 = 2, + /// 8 bit word length + Bits8 = 3, + ], + ], + + /// Line Status Register + pub LSR [ + /// Data Ready + DR OFFSET(0) NUMBITS(1) [], + /// Overrun Error + OE OFFSET(1) NUMBITS(1) [], + /// Parity Error + PE OFFSET(2) NUMBITS(1) [], + /// Framing Error + FE OFFSET(3) NUMBITS(1) [], + /// Break Interrupt + BI OFFSET(4) NUMBITS(1) [], + /// Transmitter Holding Register Empty + THRE OFFSET(5) NUMBITS(1) [], + /// Data Holding Registers Empty + DHRE OFFSET(6) NUMBITS(1) [], + /// Error in Received FIFO + RFE OFFSET(7) NUMBITS(1) [], + ], + + /// Modem Status Register + pub MSR [ + /// Delta Clear To Send + DCTS OFFSET(0) NUMBITS(1) [], + /// Delta Data Set Ready + DDSR OFFSET(1) NUMBITS(1) [], + /// Trailing Edge Ring Indicator + TERI OFFSET(2) NUMBITS(1) [], + /// Delta Data Carrier Detect + DDCD OFFSET(3) NUMBITS(1) [], + /// Clear To Send + CTS OFFSET(4) NUMBITS(1) [], + /// Data Set Ready + DSR OFFSET(5) NUMBITS(1) [], + /// Ring Indicator + RI OFFSET(6) NUMBITS(1) [], + /// Carrier Detect + CD OFFSET(7) NUMBITS(1) [], + ], + + /// FIFO Control Register + pub FCR [ + /// Interrupt trigger level. + InterruptTriggerLevel OFFSET(6) NUMBITS(2) [ + /// Interrupt trigger level is 1 byte. + Bytes1 = 0, + /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. + Bytes4Or16 = 1, + /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. + Bytes8Or32 = 2, + /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. + Bytes14Or56 = 3, + ], + /// Enable 64 byte FIFO (16750) + Enable64Byte OFFSET(5) NUMBITS(1) [], + /// DMA mode select + DmaMode OFFSET(3) NUMBITS(1) [], + /// Clear transmit FIFO + ClearTx OFFSET(2) NUMBITS(1) [], + /// Clear receive FIFO + ClearRx OFFSET(1) NUMBITS(1) [], + /// Enable FIFOs. + Enable OFFSET(0) NUMBITS(1) [], + ], + + /// Interrupt Identification Register + pub IIR [ + FifoInfo OFFSET(6) NUMBITS(2) [ + /// No FIFO on chip. + None = 0, + /// Reserved value. + Reserved = 1, + /// FIFO enabled but not functioning. + EnabledNotFunctioning = 2, + /// FIFO enabled. + Enabled = 3, + ], + /// 64 byte FIFO enabled (16750 only). + Fifo64Byte OFFSET(5) NUMBITS(1) [], + InterruptType OFFSET(1) NUMBITS(3) [ + ModemStatus = 0, + TransmitterHoldingRegisterEmpty = 1, + ReceivedDataAvailable = 2, + ReceiverLineStatus = 3, + Reserved = 4, + Timeout = 6, + ], + /// Interrupt pending flag. + InterruptPending OFFSET(0) NUMBITS(1) [], + ], + + /// Modem Control Register (bitflags) + pub MCR [ + /// Autoflow control enabled (16750) + AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [], + /// Loopback mode + LOOPBACK_MODE OFFSET(4) NUMBITS(1) [], + /// Auxiliary output 2 + AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [], + /// Auxiliary output 1 + AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [], + /// Request to Send + RTS OFFSET(1) NUMBITS(1) [], + /// Data Terminal Ready + DTR OFFSET(0) NUMBITS(1) [], + ], +]; + impl Registers { /// Constructs a new instance of the UART registers starting at the given base address. pub unsafe fn from_base_address(base_address: usize) -> &'static mut Self { diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index d13b345..c1a3d99 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -1,98 +1,16 @@ -use bitflags::bitflags; #[cfg(feature = "embedded")] use core::convert::Infallible; use core::fmt::{self, Display, Formatter}; +use tock_registers::{ + fields::FieldValue, + interfaces::{ReadWriteable, Readable, Writeable}, +}; -use crate::registers::Registers; - -bitflags! { - /// Interrupt Enable Register (bitflags) - pub struct IER: u8 { - /// Enable Received Data Available Interrupt - const RDAI = 0b0000_0001; - /// Enable Transmitter Holding Register Empty Interrupt - const THREI = 0b0000_0010; - /// Enable Receiver Line Status Interrupt - const RLSI = 0b0000_0100; - /// Enable Modem Status Interrupt - const MSI = 0b0000_1000; - /// Enable Sleep Mode (16750) - const SM = 0b0001_0000; - /// Enable Low Power Mode (16750) - const LPM = 0b0010_0000; - } -} +use crate::registers::{Registers, FCR, IER, IIR, LCR, LSR, MSR}; -bitflags! { - /// Line Status Register (bitflags) - pub struct LSR: u8 { - /// Data Ready - const DR = 0b0000_0001; - /// Overrun Error - const OE = 0b0000_0010; - /// Parity Error - const PE = 0b0000_0100; - /// Framing Error - const FE = 0b0000_1000; - /// Break Interrupt - const BI = 0b0001_0000; - /// Transmitter Holding Register Empty - const THRE = 0b0010_0000; - /// Data Holding Regiters Empty - const DHRE = 0b0100_0000; - /// Error in Received FIFO - const RFE = 0b1000_0000; - } -} - -bitflags! { - /// Modem Status Register (bitflags) - pub struct MSR: u8 { - /// Delta Clear To Send - const DCTS = 0b0000_0001; - ///Delta Data Set Ready - const DDSR = 0b0000_0010; - ///Trailing Edge Ring Indicator - const TERI = 0b0000_0100; - ///Delta Data Carrier Detect - const DDCD = 0b0000_1000; - ///Clear To Send - const CTS = 0b0001_0000; - ///Data Set Ready - const DSR = 0b0010_0000; - ///Ring Indicator - const RI = 0b0100_0000; - ///Carrier Detect - const CD = 0b1000_0000; - } -} - -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum ChipFifoInfo { - NoFifo, - Reserved, - EnabledNoFunction, - Enabled, -} - -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum InterruptType { - ModemStatus, - TransmitterHoldingRegisterEmpty, - ReceivedDataAvailable, - ReceiverLineStatus, - Timeout, - Reserved, -} - -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum Parity { - No, - Odd, - Even, - Mark, - Space, -} +pub type ChipFifoInfo = IIR::FifoInfo::Value; +pub type InterruptType = IIR::InterruptType::Value; +pub type Parity = LCR::Parity::Value; /// An error encountered which trying to transmit data. #[derive(Copy, Clone, Debug, Eq, PartialEq)] @@ -138,11 +56,13 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.write_lcr(3); + self.reg + .lcr + .write(LCR::Parity::No + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); // Enable FIFO - self.write_fcr(1); + self.reg.iir_fcr.write(FCR::Enable::SET); // No modem control - self.write_mcr(0); + self.reg.mcr.write(FieldValue::::new(0, 0, 0)); // Enable received_data_available_interrupt self.enable_received_data_available_interrupt(); // Enable transmitter_holding_register_empty_interrupt @@ -165,7 +85,7 @@ impl<'a> MmioUart8250<'a> { /// Returns `None` when data is not ready (RBR\[0\] != 1) pub fn read_byte(&self) -> Option { if self.is_data_ready() { - Some(self.read_rbr()) + Some(self.reg.thr_rbr_dll.get()) } else { None } @@ -174,53 +94,13 @@ impl<'a> MmioUart8250<'a> { /// Writes a byte to the UART. pub fn write_byte(&self, byte: u8) -> Result<(), TransmitError> { if self.is_transmitter_holding_register_empty() { - self.write_thr(byte); + self.reg.thr_rbr_dll.set(byte); Ok(()) } else { Err(TransmitError::BufferFull) } } - /// write THR (offset + 0) - /// - /// Write Transmitter Holding Buffer to send data - /// - /// > ## Transmitter Holding Buffer/Receiver Buffer - /// > - /// > Offset: +0 . The Transmit and Receive buffers are related, and often even use the very same memory. This is also one of the areas where later versions of the 8250 chip have a significant impact, as the later models incorporate some internal buffering of the data within the chip before it gets transmitted as serial data. The base 8250 chip can only receive one byte at a time, while later chips like the 16550 chip will hold up to 16 bytes either to transmit or to receive (sometimes both... depending on the manufacturer) before you have to wait for the character to be sent. This can be useful in multi-tasking environments where you have a computer doing many things, and it may be a couple of milliseconds before you get back to dealing with serial data flow. - /// > - /// > These registers really are the "heart" of serial data communication, and how data is transferred from your software to another computer and how it gets data from other devices. Reading and Writing to these registers is simply a matter of accessing the Port I/O address for the respective UART. - /// > - /// > If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register. - #[inline] - fn write_thr(&self, value: u8) { - unsafe { self.reg.thr_rbr_dll.write(value) } - } - - /// read RBR (offset + 0) - /// - /// Read Receiver Buffer to get data - #[inline] - fn read_rbr(&self) -> u8 { - self.reg.thr_rbr_dll.read() - } - - /// write DLL (offset + 0) - /// - /// set divisor latch low byte in the register - #[inline] - fn write_dll(&self, value: u8) { - unsafe { self.reg.thr_rbr_dll.write(value) } - } - - /// write DLH (offset + 1) - /// - /// set divisor latch high byte in the register - #[inline] - fn write_dlh(&self, value: u8) { - unsafe { self.reg.ier_dlh.write(value) } - } - /// Sets DLAB to true, sets divisor latch according to clock and baud_rate, then sets DLAB to /// false. /// @@ -251,418 +131,240 @@ impl<'a> MmioUart8250<'a> { /// | 115200 | 1 | $00 | $01 | #[inline] pub fn set_divisor(&self, clock: usize, baud_rate: usize) { - self.enable_divisor_latch_accessible(); - let divisor = clock / (16 * baud_rate); - self.write_dll(divisor as u8); - self.write_dlh((divisor >> 8) as u8); - self.disable_divisor_latch_accessible(); - } - - /// Read IER (offset + 1) - /// - /// Read IER to get what interrupts are enabled - /// - /// > ## Interrupt Enable Register - /// > - /// > Offset: +1 . This register allows you to control when and how the UART is going to trigger an interrupt event with the hardware interrupt associated with the serial COM port. If used properly, this can enable an efficient use of system resources and allow you to react to information being sent across a serial data line in essentially real-time conditions. Some more on that will be covered later, but the point here is that you can use the UART to let you know exactly when you need to extract some data. This register has both read- and write-access. - /// > - /// > The following is a table showing each bit in this register and what events that it will enable to allow you check on the status of this chip: - /// > - /// > | Bit | Notes | - /// > | --- | --------------------------------------------------- | - /// > | 7 | Reserved | - /// > | 6 | Reserved | - /// > | 5 | Enables Low Power Mode (16750) | - /// > | 4 | Enables Sleep Mode (16750) | - /// > | 3 | Enable Modem Status Interrupt | - /// > | 2 | Enable Receiver Line Status Interrupt | - /// > | 1 | Enable Transmitter Holding Register Empty Interrupt | - /// > | 0 | Enable Received Data Available Interrupt | - #[inline] - fn read_ier(&self) -> u8 { - self.reg.ier_dlh.read() - } - - /// Write IER (offset + 1) - /// - /// Write Interrupt Enable Register to turn on/off interrupts - #[inline] - pub fn write_ier(&self, value: u8) { - unsafe { self.reg.ier_dlh.write(value) } - } + // Enable DLAB. + self.reg.lcr.modify(LCR::DLAB::SET); - /// Get IER bitflags - #[inline] - fn ier(&self) -> IER { - IER::from_bits_truncate(self.read_ier()) - } + let divisor = clock / (16 * baud_rate); + self.reg.thr_rbr_dll.set(divisor as u8); + self.reg.ier_dlh.set((divisor >> 8) as u8); - /// Set IER via bitflags - #[inline] - fn set_ier(&self, flag: IER) { - self.write_ier(flag.bits()) + // Disable DLAB. + self.reg.lcr.modify(LCR::DLAB::CLEAR); } /// get whether low power mode (16750) is enabled (IER\[5\]) pub fn is_low_power_mode_enabled(&self) -> bool { - self.ier().contains(IER::LPM) + self.reg.ier_dlh.is_set(IER::LPM) } /// enable low power mode (16750) (IER\[5\]) pub fn enable_low_power_mode(&self) { - self.set_ier(self.ier() | IER::LPM) + self.reg.ier_dlh.modify(IER::LPM::SET) } /// disable low power mode (16750) (IER\[5\]) pub fn disable_low_power_mode(&self) { - self.set_ier(self.ier() & !IER::LPM) + self.reg.ier_dlh.modify(IER::LPM::CLEAR) } /// get whether sleep mode (16750) is enabled (IER\[4\]) pub fn is_sleep_mode_enabled(&self) -> bool { - self.ier().contains(IER::SM) + self.reg.ier_dlh.is_set(IER::SM) } /// enable sleep mode (16750) (IER\[4\]) pub fn enable_sleep_mode(&self) { - self.set_ier(self.ier() | IER::SM) + self.reg.ier_dlh.modify(IER::SM::SET) } /// disable sleep mode (16750) (IER\[4\]) pub fn disable_sleep_mode(&self) { - self.set_ier(self.ier() & !IER::SM) + self.reg.ier_dlh.modify(IER::SM::CLEAR) } /// get whether modem status interrupt is enabled (IER\[3\]) pub fn is_modem_status_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::MSI) + self.reg.ier_dlh.is_set(IER::MSI) } /// enable modem status interrupt (IER\[3\]) pub fn enable_modem_status_interrupt(&self) { - self.set_ier(self.ier() | IER::MSI) + self.reg.ier_dlh.modify(IER::MSI::SET) } /// disable modem status interrupt (IER\[3\]) pub fn disable_modem_status_interrupt(&self) { - self.set_ier(self.ier() & !IER::MSI) + self.reg.ier_dlh.modify(IER::MSI::CLEAR) } /// get whether receiver line status interrupt is enabled (IER\[2\]) pub fn is_receiver_line_status_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::RLSI) + self.reg.ier_dlh.is_set(IER::RLSI) } /// enable receiver line status interrupt (IER\[2\]) pub fn enable_receiver_line_status_interrupt(&self) { - self.set_ier(self.ier() | IER::RLSI) + self.reg.ier_dlh.modify(IER::RLSI::SET) } /// disable receiver line status interrupt (IER\[2\]) pub fn disable_receiver_line_status_interrupt(&self) { - self.set_ier(self.ier() & !IER::RLSI) + self.reg.ier_dlh.modify(IER::RLSI::CLEAR) } /// get whether transmitter holding register empty interrupt is enabled (IER\[1\]) pub fn is_transmitter_holding_register_empty_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::THREI) + self.reg.ier_dlh.is_set(IER::THREI) } /// enable transmitter holding register empty interrupt (IER\[1\]) pub fn enable_transmitter_holding_register_empty_interrupt(&self) { - self.set_ier(self.ier() | IER::THREI) + self.reg.ier_dlh.modify(IER::THREI::SET) } /// disable transmitter holding register empty interrupt (IER\[1\]) pub fn disable_transmitter_holding_register_empty_interrupt(&self) { - self.set_ier(self.ier() & !IER::THREI) + self.reg.ier_dlh.modify(IER::THREI::CLEAR) } /// get whether received data available is enabled (IER\[0\]) pub fn is_received_data_available_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::RDAI) + self.reg.ier_dlh.is_set(IER::RDAI) } /// enable received data available (IER\[0\]) pub fn enable_received_data_available_interrupt(&self) { - self.set_ier(self.ier() | IER::RDAI) + self.reg.ier_dlh.modify(IER::RDAI::SET); } /// disable received data available (IER\[0\]) pub fn disable_received_data_available_interrupt(&self) { - self.set_ier(self.ier() & !IER::RDAI) + self.reg.ier_dlh.modify(IER::RDAI::CLEAR); } /// Read IIR\[7:6\] to get FIFO status pub fn read_fifo_status(&self) -> ChipFifoInfo { - match self.reg.iir_fcr.read() & 0b1100_0000 { - 0 => ChipFifoInfo::NoFifo, - 0b0100_0000 => ChipFifoInfo::Reserved, - 0b1000_0000 => ChipFifoInfo::EnabledNoFunction, - 0b1100_0000 => ChipFifoInfo::Enabled, - _ => panic!("Can't reached"), - } + self.reg.iir_fcr.read_as_enum(IIR::FifoInfo).unwrap() } /// get whether 64 Byte fifo (16750 only) is enabled (IIR\[5\]) pub fn is_64byte_fifo_enabled(&self) -> bool { - self.reg.iir_fcr.read() & 0b0010_0000 != 0 + self.reg.iir_fcr.is_set(IIR::Fifo64Byte) } /// Read IIR\[3:1\] to get interrupt type pub fn read_interrupt_type(&self) -> Option { - let iir = self.reg.iir_fcr.read() & 0b0000_1111; - if iir & 1 != 0 { + let iir = self.reg.iir_fcr.extract(); + if iir.is_set(IIR::InterruptPending) { None } else { - match iir { - 0b0000 => Some(InterruptType::ModemStatus), - 0b0010 => Some(InterruptType::TransmitterHoldingRegisterEmpty), - 0b0100 => Some(InterruptType::ReceivedDataAvailable), - 0b0110 => Some(InterruptType::ReceiverLineStatus), - 0b1100 => Some(InterruptType::Timeout), - 0b1000 | 0b1010 | 0b1110 => Some(InterruptType::Reserved), - _ => panic!("Can't reached"), - } + Some( + iir.read_as_enum(IIR::InterruptType) + .unwrap_or(IIR::InterruptType::Value::Reserved), + ) } } - /// Write FCR (offset + 2) to control FIFO buffers - /// - /// > ## FIFO Control Register - /// > - /// > Offset: +2 . This is a relatively "new" register that was not a part of the original 8250 UART implementation. The purpose of this register is to control how the First In/First Out (FIFO) buffers will behave on the chip and to help you fine-tune their performance in your application. This even gives you the ability to "turn on" or "turn off" the FIFO. - /// > - /// > Keep in mind that this is a "write only" register. Attempting to read in the contents will only give you the Interrupt Identification Register (IIR), which has a totally different context. - /// > - /// > | Bit | Notes | | | | - /// > | ----- | --------------------------- | ----- | --------------------------------- | ----------------------- | - /// > | 7 & 6 | Bit 7 | Bit 6 | Interrupt Trigger Level (16 byte) | Trigger Level (64 byte) | - /// > | | 0 | 0 | 1 Byte | 1 Byte | - /// > | | 0 | 1 | 4 Bytes | 16 Bytes | - /// > | | 1 | 0 | 8 Bytes | 32 Bytes | - /// > | | 1 | 1 | 14 Bytes | 56 Bytes | - /// > | 5 | Enable 64 Byte FIFO (16750) | | | | - /// > | 4 | Reserved | | | | - /// > | 3 | DMA Mode Select | | | | - /// > | 2 | Clear Transmit FIFO | | | | - /// > | 1 | Clear Receive FIFO | | | | - /// > | 0 | Enable FIFOs | | | | - #[inline] - fn write_fcr(&self, value: u8) { - unsafe { self.reg.iir_fcr.write(value) } - } - - /// Write LCR (offset + 3) - /// - /// Write Line Control Register to set DLAB and the serial data protocol - #[inline] - fn write_lcr(&self, value: u8) { - unsafe { self.reg.lcr.write(value) } - } - - /// enable DLAB - fn enable_divisor_latch_accessible(&self) { - unsafe { self.reg.lcr.modify(|v| v | 0b1000_0000) } - } - - /// disable DLAB - fn disable_divisor_latch_accessible(&self) { - unsafe { self.reg.lcr.modify(|v| v & !0b1000_0000) } - } - /// get parity of used data protocol pub fn get_parity(&self) -> Parity { - match self.reg.lcr.read() & 0b0011_1000 { - 0b0000_0000 => Parity::No, - 0b0000_1000 => Parity::Odd, - 0b0001_1000 => Parity::Even, - 0b0010_1000 => Parity::Mark, - 0b0011_1000 => Parity::Space, - _ => panic!("Invalid Parity! Please check your uart"), - } + self.reg + .lcr + .read_as_enum(LCR::Parity) + .expect("Invalid Parity! Please check your UART.") } /// set parity pub fn set_parity(&self, parity: Parity) { - match parity { - Parity::No => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111)) }, - Parity::Odd => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0000_1000) }, - Parity::Even => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0001_1000) }, - Parity::Mark => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0010_1000) }, - Parity::Space => unsafe { self.reg.lcr.modify(|v| v | 0b0011_1000) }, - } + self.reg.lcr.modify(LCR::Parity.val(parity as u8)); } /// get stop bit of used data protocol /// /// Simply return a u8 to indicate 1 or 1.5/2 bits pub fn get_stop_bit(&self) -> u8 { - ((self.reg.lcr.read() & 0b100) >> 2) + 1 + self.reg.lcr.read(LCR::STOP_BITS) + 1 } /// set stop bit, only 1 and 2 can be used as `stop_bit` pub fn set_stop_bit(&self, stop_bit: u8) { match stop_bit { - 1 => unsafe { self.reg.lcr.modify(|v| v & 0b1111_1011) }, - 2 => unsafe { self.reg.lcr.modify(|v| v | 0b0000_0100) }, + 1 => self.reg.lcr.modify(LCR::STOP_BITS::One), + 2 => self.reg.lcr.modify(LCR::STOP_BITS::Two), _ => panic!("Invalid stop bit"), } } /// get word length of used data protocol pub fn get_word_length(&self) -> u8 { - (self.reg.lcr.read() & 0b11) + 5 + self.reg.lcr.read(LCR::WORD_LENGTH) + 5 } /// set word length, only 5..=8 can be used as `length` pub fn set_word_length(&self, length: u8) { if (5..=8).contains(&length) { - unsafe { self.reg.lcr.modify(|v| v | (length - 5)) } + self.reg.lcr.modify(LCR::WORD_LENGTH.val(length - 5)) } else { panic!("Invalid word length") } } - /// Write MCR (offset + 4) - /// - /// Write Modem Control Register to control flow - #[inline] - fn write_mcr(&self, value: u8) { - unsafe { self.reg.mcr.write(value) } - } - - /// Read LSR (offset + 5) - /// - /// > ## Line Status Register - /// > - /// > Offset: +5 . This register is used primarily to give you information on possible error conditions that may exist within the UART, based on the data that has been received. Keep in mind that this is a "read only" register, and any data written to this register is likely to be ignored or worse, cause different behavior in the UART. There are several uses for this information, and some information will be given below on how it can be useful for diagnosing problems with your serial data connection: - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------------- | - /// > | 7 | Error in Received FIFO | - /// > | 6 | Empty Data Holding Registers | - /// > | 5 | Empty Transmitter Holding Register | - /// > | 4 | Break Interrupt | - /// > | 3 | Framing Error | - /// > | 2 | Parity Error | - /// > | 1 | Overrun Error | - /// > | 0 | Data Ready | - #[inline] - fn read_lsr(&self) -> u8 { - self.reg.lsr.read() - } - - /// Get LSR bitflags - #[inline] - fn lsr(&self) -> LSR { - LSR::from_bits_truncate(self.read_lsr()) - } - /// get whether there is an error in received FIFO pub fn is_received_fifo_error(&self) -> bool { - self.lsr().contains(LSR::RFE) + self.reg.lsr.is_set(LSR::RFE) } /// Gets whether data holding registers are empty, i.e. the UART has finished transmitting all /// the data it has been given. pub fn is_data_holding_registers_empty(&self) -> bool { - self.lsr().contains(LSR::DHRE) + self.reg.lsr.is_set(LSR::DHRE) } /// Gets whether transmitter holding register is empty, i.e. the UART is ready to be given more /// data to transmit. pub fn is_transmitter_holding_register_empty(&self) -> bool { - self.lsr().contains(LSR::THRE) + self.reg.lsr.is_set(LSR::THRE) } pub fn is_break_interrupt(&self) -> bool { - self.lsr().contains(LSR::BI) + self.reg.lsr.is_set(LSR::BI) } pub fn is_framing_error(&self) -> bool { - self.lsr().contains(LSR::FE) + self.reg.lsr.is_set(LSR::FE) } pub fn is_parity_error(&self) -> bool { - self.lsr().contains(LSR::PE) + self.reg.lsr.is_set(LSR::PE) } pub fn is_overrun_error(&self) -> bool { - self.lsr().contains(LSR::OE) + self.reg.lsr.is_set(LSR::OE) } pub fn is_data_ready(&self) -> bool { - self.lsr().contains(LSR::DR) - } - - /// Read MSR (offset + 6) - /// - /// > ## Modem Status Register - /// > - /// > Offset: +6 . This register is another read-only register that is here to inform your software about the current status of the modem. The modem accessed in this manner can either be an external modem, or an internal modem that uses a UART as an interface to the computer. - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------- | - /// > | 7 | Carrier Detect | - /// > | 6 | Ring Indicator | - /// > | 5 | Data Set Ready | - /// > | 4 | Clear To Send | - /// > | 3 | Delta Data Carrier Detect | - /// > | 2 | Trailing Edge Ring Indicator | - /// > | 1 | Delta Data Set Ready | - /// > | 0 | Delta Clear To Send | - #[inline] - fn read_msr(&self) -> u8 { - self.reg.msr.read() - } - - /// Get MSR bitflags - #[inline] - fn msr(&self) -> MSR { - MSR::from_bits_truncate(self.read_msr()) + self.reg.lsr.is_set(LSR::DR) } pub fn is_carrier_detect(&self) -> bool { - self.msr().contains(MSR::CD) + self.reg.msr.is_set(MSR::CD) } pub fn is_ring_indicator(&self) -> bool { - self.msr().contains(MSR::RI) + self.reg.msr.is_set(MSR::RI) } pub fn is_data_set_ready(&self) -> bool { - self.msr().contains(MSR::DSR) + self.reg.msr.is_set(MSR::DSR) } pub fn is_clear_to_send(&self) -> bool { - self.msr().contains(MSR::CTS) + self.reg.msr.is_set(MSR::CTS) } pub fn is_delta_data_carrier_detect(&self) -> bool { - self.msr().contains(MSR::DDCD) + self.reg.msr.is_set(MSR::DDCD) } pub fn is_trailing_edge_ring_indicator(&self) -> bool { - self.msr().contains(MSR::TERI) + self.reg.msr.is_set(MSR::TERI) } pub fn is_delta_data_set_ready(&self) -> bool { - self.msr().contains(MSR::DDSR) + self.reg.msr.is_set(MSR::DDSR) } pub fn is_delta_clear_to_send(&self) -> bool { - self.msr().contains(MSR::DCTS) - } - - #[inline] - pub fn read_sr(&self) -> u8 { - self.reg.scratch.read() - } - - #[inline] - pub fn write_sr(&self, value: u8) { - unsafe { self.reg.scratch.write(value) } + self.reg.msr.is_set(MSR::DCTS) } }