From 7167b4f4469872ba460316cdc300380407e7cbf8 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Thu, 31 Mar 2022 17:23:20 +0100 Subject: [PATCH 01/10] Move low-level register access methods to Registers struct. Make fields private where possible. --- uart8250/src/registers.rs | 316 +++++++++++++++++++++++++++++++++++++- uart8250/src/uart.rs | 228 ++------------------------- 2 files changed, 326 insertions(+), 218 deletions(-) diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index 85b5c39..b6112cd 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -24,14 +24,14 @@ use volatile_register::{RO, RW}; /// | +7 | x | Read/Write | SR | Scratch Register | #[repr(C, packed)] pub struct Registers { - pub thr_rbr_dll: RW, - pub ier_dlh: RW, - pub iir_fcr: RW, + thr_rbr_dll: RW, + ier_dlh: RW, + iir_fcr: RW, pub lcr: RW, - pub mcr: RW, - pub lsr: RO, - pub msr: RO, - pub scratch: RW, + mcr: RW, + lsr: RO, + msr: RO, + scratch: RW, } impl Registers { @@ -39,4 +39,306 @@ impl Registers { pub unsafe fn from_base_address(base_address: usize) -> &'static mut Self { &mut *(base_address as *mut crate::registers::Registers) } + + /// write THR (offset + 0) + /// + /// Write Transmitter Holding Buffer to send data + /// + /// > ## Transmitter Holding Buffer/Receiver Buffer + /// > + /// > Offset: +0 . The Transmit and Receive buffers are related, and often even use the very same memory. This is also one of the areas where later versions of the 8250 chip have a significant impact, as the later models incorporate some internal buffering of the data within the chip before it gets transmitted as serial data. The base 8250 chip can only receive one byte at a time, while later chips like the 16550 chip will hold up to 16 bytes either to transmit or to receive (sometimes both... depending on the manufacturer) before you have to wait for the character to be sent. This can be useful in multi-tasking environments where you have a computer doing many things, and it may be a couple of milliseconds before you get back to dealing with serial data flow. + /// > + /// > These registers really are the "heart" of serial data communication, and how data is transferred from your software to another computer and how it gets data from other devices. Reading and Writing to these registers is simply a matter of accessing the Port I/O address for the respective UART. + /// > + /// > If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register. + #[inline] + pub fn write_thr(&self, value: u8) { + unsafe { self.thr_rbr_dll.write(value) } + } + + /// read RBR (offset + 0) + /// + /// Read Receiver Buffer to get data + #[inline] + pub fn read_rbr(&self) -> u8 { + self.thr_rbr_dll.read() + } + + /// read DLL (offset + 0) + /// + /// get divisor latch low byte in the register + /// + /// > ## Divisor Latch Bytes + /// > + /// > Offset: +0 and +1 . The Divisor Latch Bytes are what control the baud rate of the modem. As you might guess from the name of this register, it is used as a divisor to determine what baud rate that the chip is going to be transmitting at. + /// + /// Used clock 1.8432 MHz as example, first divide 16 and get 115200. Then use the formula to get divisor latch value: + /// + /// *DivisorLatchValue = 115200 / BaudRate* + /// + /// This gives the following table: + /// + /// | Baud Rate | Divisor (in decimal) | Divisor Latch High Byte | Divisor Latch Low Byte | + /// | --------- | -------------------- | ----------------------- | ---------------------- | + /// | 50 | 2304 | $09 | $00 | + /// | 110 | 1047 | $04 | $17 | + /// | 220 | 524 | $02 | $0C | + /// | 300 | 384 | $01 | $80 | + /// | 600 | 192 | $00 | $C0 | + /// | 1200 | 96 | $00 | $60 | + /// | 2400 | 48 | $00 | $30 | + /// | 4800 | 24 | $00 | $18 | + /// | 9600 | 12 | $00 | $0C | + /// | 19200 | 6 | $00 | $06 | + /// | 38400 | 3 | $00 | $03 | + /// | 57600 | 2 | $00 | $02 | + /// | 115200 | 1 | $00 | $01 | + #[inline] + pub fn read_dll(&self) -> u8 { + self.thr_rbr_dll.read() + } + + /// write DLL (offset + 0) + /// + /// set divisor latch low byte in the register + #[inline] + pub fn write_dll(&self, value: u8) { + unsafe { self.thr_rbr_dll.write(value) } + } + + /// read DLH (offset + 1) + /// + /// get divisor latch high byte in the register + #[inline] + pub fn read_dlh(&self) -> u8 { + self.ier_dlh.read() + } + + /// write DLH (offset + 1) + /// + /// set divisor latch high byte in the register + #[inline] + pub fn write_dlh(&self, value: u8) { + unsafe { self.ier_dlh.write(value) } + } + + /// Read IER (offset + 1) + /// + /// Read IER to get what interrupts are enabled + /// + /// > ## Interrupt Enable Register + /// > + /// > Offset: +1 . This register allows you to control when and how the UART is going to trigger an interrupt event with the hardware interrupt associated with the serial COM port. If used properly, this can enable an efficient use of system resources and allow you to react to information being sent across a serial data line in essentially real-time conditions. Some more on that will be covered later, but the point here is that you can use the UART to let you know exactly when you need to extract some data. This register has both read- and write-access. + /// > + /// > The following is a table showing each bit in this register and what events that it will enable to allow you check on the status of this chip: + /// > + /// > | Bit | Notes | + /// > | --- | --------------------------------------------------- | + /// > | 7 | Reserved | + /// > | 6 | Reserved | + /// > | 5 | Enables Low Power Mode (16750) | + /// > | 4 | Enables Sleep Mode (16750) | + /// > | 3 | Enable Modem Status Interrupt | + /// > | 2 | Enable Receiver Line Status Interrupt | + /// > | 1 | Enable Transmitter Holding Register Empty Interrupt | + /// > | 0 | Enable Received Data Available Interrupt | + #[inline] + pub fn read_ier(&self) -> u8 { + self.ier_dlh.read() + } + + /// Write IER (offset + 1) + /// + /// Write Interrupt Enable Register to turn on/off interrupts + #[inline] + pub fn write_ier(&self, value: u8) { + unsafe { self.ier_dlh.write(value) } + } + + /// Read IIR (offset + 2) + /// + /// > ## Interrupt Identification Register + /// > + /// > Offset: +2 . This register is to be used to help identify what the unique characteristics of the UART chip that you are using has. This chip has two uses: + /// > + /// > - Identification of why the UART triggered an interrupt. + /// > - Identification of the UART chip itself. + /// > + /// > Of these, identification of why the interrupt service routine has been invoked is perhaps the most important. + /// > + /// > The following table explains some of the details of this register, and what each bit on it represents: + /// > + /// > | Bit | Notes | | | | | + /// > | ---------- | --------------------------------- | ----- | --------------------------------- | -------------------------------------------- | ----------------------------------------------------------------------------------------- | + /// > | 7 and 6 | Bit 7 | Bit 6 | | | | + /// > | | 0 | 0 | No FIFO on chip | | | + /// > | | 0 | 1 | Reserved condition | | | + /// > | | 1 | 0 | FIFO enabled, but not functioning | | | + /// > | | 1 | 1 | FIFO enabled | | | + /// > | 5 | 64 Byte FIFO Enabled (16750 only) | | | | | + /// > | 4 | Reserved | | | | | + /// > | 3, 2 and 1 | Bit 3 | Bit 2 | Bit 1 | | Reset Method | + /// > | | 0 | 0 | 0 | Modem Status Interrupt | Reading Modem Status Register(MSR) | + /// > | | 0 | 0 | 1 | Transmitter Holding Register Empty Interrupt | Reading Interrupt Identification Register(IIR) or Writing to Transmit Holding Buffer(THR) | + /// > | | 0 | 1 | 0 | Received Data Available Interrupt | Reading Receive Buffer Register(RBR) | + /// > | | 0 | 1 | 1 | Receiver Line Status Interrupt | Reading Line Status Register(LSR) | + /// > | | 1 | 0 | 0 | Reserved | N/A | + /// > | | 1 | 0 | 1 | Reserved | N/A | + /// > | | 1 | 1 | 0 | Time-out Interrupt Pending (16550 & later) | Reading Receive Buffer Register(RBR) | + /// > | | 1 | 1 | 1 | Reserved | N/A | + /// > | 0 | Interrupt Pending Flag | | | | | + #[inline] + pub fn read_iir(&self) -> u8 { + self.iir_fcr.read() + } + + /// Write FCR (offset + 2) to control FIFO buffers + /// + /// > ## FIFO Control Register + /// > + /// > Offset: +2 . This is a relatively "new" register that was not a part of the original 8250 UART implementation. The purpose of this register is to control how the First In/First Out (FIFO) buffers will behave on the chip and to help you fine-tune their performance in your application. This even gives you the ability to "turn on" or "turn off" the FIFO. + /// > + /// > Keep in mind that this is a "write only" register. Attempting to read in the contents will only give you the Interrupt Identification Register (IIR), which has a totally different context. + /// > + /// > | Bit | Notes | | | | + /// > | ----- | --------------------------- | ----- | --------------------------------- | ----------------------- | + /// > | 7 & 6 | Bit 7 | Bit 6 | Interrupt Trigger Level (16 byte) | Trigger Level (64 byte) | + /// > | | 0 | 0 | 1 Byte | 1 Byte | + /// > | | 0 | 1 | 4 Bytes | 16 Bytes | + /// > | | 1 | 0 | 8 Bytes | 32 Bytes | + /// > | | 1 | 1 | 14 Bytes | 56 Bytes | + /// > | 5 | Enable 64 Byte FIFO (16750) | | | | + /// > | 4 | Reserved | | | | + /// > | 3 | DMA Mode Select | | | | + /// > | 2 | Clear Transmit FIFO | | | | + /// > | 1 | Clear Receive FIFO | | | | + /// > | 0 | Enable FIFOs | | | | + #[inline] + pub fn write_fcr(&self, value: u8) { + unsafe { self.iir_fcr.write(value) } + } + + /// Read LCR (offset + 3) + /// + /// Read Line Control Register to get the data protocol and DLAB + /// + /// > ## Line Control Register + /// > + /// > Offset: +3 . This register has two major purposes: + /// > + /// > - Setting the Divisor Latch Access Bit (DLAB), allowing you to set the values of the Divisor Latch Bytes. + /// > - Setting the bit patterns that will be used for both receiving and transmitting the serial data. In other words, the serial data protocol you will be using (8-1-None, 5-2-Even, etc.). + /// > + /// > | Bit | Notes | | | | + /// > | -------- | ------------------------ | ---------------------------- | ----------- | ------------- | + /// > | 7 | Divisor Latch Access Bit | | | | + /// > | 6 | Set Break Enable | | | | + /// > | 3, 4 & 5 | Bit 5 | Bit 4 | Bit 3 | Parity Select | + /// > | | 0 | 0 | 0 | No Parity | + /// > | | 0 | 0 | 1 | Odd Parity | + /// > | | 0 | 1 | 1 | Even Parity | + /// > | | 1 | 0 | 1 | Mark | + /// > | | 1 | 1 | 1 | Space | + /// > | 2 | 0 | One Stop Bit | | | + /// > | | 1 | 1.5 Stop Bits or 2 Stop Bits | | | + /// > | 0 & 1 | Bit 1 | Bit 0 | Word Length | | + /// > | | 0 | 0 | 5 Bits | | + /// > | | 0 | 1 | 6 Bits | | + /// > | | 1 | 0 | 7 Bits | | + /// > | | 1 | 1 | 8 Bits | | + #[inline] + pub fn read_lcr(&self) -> u8 { + self.lcr.read() + } + + /// Write LCR (offset + 3) + /// + /// Write Line Control Register to set DLAB and the serial data protocol + #[inline] + pub fn write_lcr(&self, value: u8) { + unsafe { self.lcr.write(value) } + } + + /// Read MCR (offset + 4) + /// + /// Read Modem Control Register to get how flow is controlled + /// + /// > ## Modem Control Register + /// > + /// > Offset: +4 . This register allows you to do "hardware" flow control, under software control. Or in a more practical manner, it allows direct manipulation of four different wires on the UART that you can set to any series of independent logical states, and be able to offer control of the modem. It should also be noted that most UARTs need Auxiliary Output 2 set to a logical "1" to enable interrupts. + /// > + /// > | Bit | Notes | + /// > | --- | -------------------------------- | + /// > | 7 | Reserved | + /// > | 6 | Reserved | + /// > | 5 | Autoflow Control Enabled (16750) | + /// > | 4 | Loopback Mode | + /// > | 3 | Auxiliary Output 2 | + /// > | 2 | Auxiliary Output 1 | + /// > | 1 | Request To Send | + /// > | 0 | Data Terminal Ready | + #[inline] + pub fn read_mcr(&self) -> u8 { + self.mcr.read() + } + + /// Write MCR (offset + 4) + /// + /// Write Modem Control Register to control flow + #[inline] + pub fn write_mcr(&self, value: u8) { + unsafe { self.mcr.write(value) } + } + + /// Read LSR (offset + 5) + /// + /// > ## Line Status Register + /// > + /// > Offset: +5 . This register is used primarily to give you information on possible error conditions that may exist within the UART, based on the data that has been received. Keep in mind that this is a "read only" register, and any data written to this register is likely to be ignored or worse, cause different behavior in the UART. There are several uses for this information, and some information will be given below on how it can be useful for diagnosing problems with your serial data connection: + /// > + /// > | Bit | Notes | + /// > | --- | ---------------------------------- | + /// > | 7 | Error in Received FIFO | + /// > | 6 | Empty Data Holding Registers | + /// > | 5 | Empty Transmitter Holding Register | + /// > | 4 | Break Interrupt | + /// > | 3 | Framing Error | + /// > | 2 | Parity Error | + /// > | 1 | Overrun Error | + /// > | 0 | Data Ready | + #[inline] + pub fn read_lsr(&self) -> u8 { + self.lsr.read() + } + + /// Read MSR (offset + 6) + /// + /// > ## Modem Status Register + /// > + /// > Offset: +6 . This register is another read-only register that is here to inform your software about the current status of the modem. The modem accessed in this manner can either be an external modem, or an internal modem that uses a UART as an interface to the computer. + /// > + /// > | Bit | Notes | + /// > | --- | ---------------------------- | + /// > | 7 | Carrier Detect | + /// > | 6 | Ring Indicator | + /// > | 5 | Data Set Ready | + /// > | 4 | Clear To Send | + /// > | 3 | Delta Data Carrier Detect | + /// > | 2 | Trailing Edge Ring Indicator | + /// > | 1 | Delta Data Set Ready | + /// > | 0 | Delta Clear To Send | + #[inline] + pub fn read_msr(&self) -> u8 { + self.msr.read() + } + + #[inline] + pub fn read_sr(&self) -> u8 { + self.scratch.read() + } + + #[inline] + pub fn write_sr(&self, value: u8) { + unsafe { self.scratch.write(value) } + } } diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index d13b345..44cd3e2 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -138,11 +138,11 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.write_lcr(3); + self.reg.write_lcr(3); // Enable FIFO - self.write_fcr(1); + self.reg.write_fcr(1); // No modem control - self.write_mcr(0); + self.reg.write_mcr(0); // Enable received_data_available_interrupt self.enable_received_data_available_interrupt(); // Enable transmitter_holding_register_empty_interrupt @@ -165,7 +165,7 @@ impl<'a> MmioUart8250<'a> { /// Returns `None` when data is not ready (RBR\[0\] != 1) pub fn read_byte(&self) -> Option { if self.is_data_ready() { - Some(self.read_rbr()) + Some(self.reg.read_rbr()) } else { None } @@ -174,133 +174,33 @@ impl<'a> MmioUart8250<'a> { /// Writes a byte to the UART. pub fn write_byte(&self, byte: u8) -> Result<(), TransmitError> { if self.is_transmitter_holding_register_empty() { - self.write_thr(byte); + self.reg.write_thr(byte); Ok(()) } else { Err(TransmitError::BufferFull) } } - /// write THR (offset + 0) - /// - /// Write Transmitter Holding Buffer to send data - /// - /// > ## Transmitter Holding Buffer/Receiver Buffer - /// > - /// > Offset: +0 . The Transmit and Receive buffers are related, and often even use the very same memory. This is also one of the areas where later versions of the 8250 chip have a significant impact, as the later models incorporate some internal buffering of the data within the chip before it gets transmitted as serial data. The base 8250 chip can only receive one byte at a time, while later chips like the 16550 chip will hold up to 16 bytes either to transmit or to receive (sometimes both... depending on the manufacturer) before you have to wait for the character to be sent. This can be useful in multi-tasking environments where you have a computer doing many things, and it may be a couple of milliseconds before you get back to dealing with serial data flow. - /// > - /// > These registers really are the "heart" of serial data communication, and how data is transferred from your software to another computer and how it gets data from other devices. Reading and Writing to these registers is simply a matter of accessing the Port I/O address for the respective UART. - /// > - /// > If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register. - #[inline] - fn write_thr(&self, value: u8) { - unsafe { self.reg.thr_rbr_dll.write(value) } - } - - /// read RBR (offset + 0) - /// - /// Read Receiver Buffer to get data - #[inline] - fn read_rbr(&self) -> u8 { - self.reg.thr_rbr_dll.read() - } - - /// write DLL (offset + 0) - /// - /// set divisor latch low byte in the register - #[inline] - fn write_dll(&self, value: u8) { - unsafe { self.reg.thr_rbr_dll.write(value) } - } - - /// write DLH (offset + 1) - /// - /// set divisor latch high byte in the register - #[inline] - fn write_dlh(&self, value: u8) { - unsafe { self.reg.ier_dlh.write(value) } - } - - /// Sets DLAB to true, sets divisor latch according to clock and baud_rate, then sets DLAB to - /// false. - /// - /// > ## Divisor Latch Bytes - /// > - /// > Offset: +0 and +1 . The Divisor Latch Bytes are what control the baud rate of the modem. As you might guess from the name of this register, it is used as a divisor to determine what baud rate that the chip is going to be transmitting at. - /// - /// Used clock 1.8432 MHz as example, first divide 16 and get 115200. Then use the formula to get divisor latch value: - /// - /// *DivisorLatchValue = 115200 / BaudRate* - /// - /// This gives the following table: - /// - /// | Baud Rate | Divisor (in decimal) | Divisor Latch High Byte | Divisor Latch Low Byte | - /// | --------- | -------------------- | ----------------------- | ---------------------- | - /// | 50 | 2304 | $09 | $00 | - /// | 110 | 1047 | $04 | $17 | - /// | 220 | 524 | $02 | $0C | - /// | 300 | 384 | $01 | $80 | - /// | 600 | 192 | $00 | $C0 | - /// | 1200 | 96 | $00 | $60 | - /// | 2400 | 48 | $00 | $30 | - /// | 4800 | 24 | $00 | $18 | - /// | 9600 | 12 | $00 | $0C | - /// | 19200 | 6 | $00 | $06 | - /// | 38400 | 3 | $00 | $03 | - /// | 57600 | 2 | $00 | $02 | - /// | 115200 | 1 | $00 | $01 | + /// Set divisor latch according to clock and baud_rate, then set DLAB to false #[inline] pub fn set_divisor(&self, clock: usize, baud_rate: usize) { self.enable_divisor_latch_accessible(); let divisor = clock / (16 * baud_rate); - self.write_dll(divisor as u8); - self.write_dlh((divisor >> 8) as u8); + self.reg.write_dll(divisor as u8); + self.reg.write_dlh((divisor >> 8) as u8); self.disable_divisor_latch_accessible(); } - /// Read IER (offset + 1) - /// - /// Read IER to get what interrupts are enabled - /// - /// > ## Interrupt Enable Register - /// > - /// > Offset: +1 . This register allows you to control when and how the UART is going to trigger an interrupt event with the hardware interrupt associated with the serial COM port. If used properly, this can enable an efficient use of system resources and allow you to react to information being sent across a serial data line in essentially real-time conditions. Some more on that will be covered later, but the point here is that you can use the UART to let you know exactly when you need to extract some data. This register has both read- and write-access. - /// > - /// > The following is a table showing each bit in this register and what events that it will enable to allow you check on the status of this chip: - /// > - /// > | Bit | Notes | - /// > | --- | --------------------------------------------------- | - /// > | 7 | Reserved | - /// > | 6 | Reserved | - /// > | 5 | Enables Low Power Mode (16750) | - /// > | 4 | Enables Sleep Mode (16750) | - /// > | 3 | Enable Modem Status Interrupt | - /// > | 2 | Enable Receiver Line Status Interrupt | - /// > | 1 | Enable Transmitter Holding Register Empty Interrupt | - /// > | 0 | Enable Received Data Available Interrupt | - #[inline] - fn read_ier(&self) -> u8 { - self.reg.ier_dlh.read() - } - - /// Write IER (offset + 1) - /// - /// Write Interrupt Enable Register to turn on/off interrupts - #[inline] - pub fn write_ier(&self, value: u8) { - unsafe { self.reg.ier_dlh.write(value) } - } - /// Get IER bitflags #[inline] fn ier(&self) -> IER { - IER::from_bits_truncate(self.read_ier()) + IER::from_bits_truncate(self.reg.read_ier()) } /// Set IER via bitflags #[inline] fn set_ier(&self, flag: IER) { - self.write_ier(flag.bits()) + self.reg.write_ier(flag.bits()) } /// get whether low power mode (16750) is enabled (IER\[5\]) @@ -395,7 +295,7 @@ impl<'a> MmioUart8250<'a> { /// Read IIR\[7:6\] to get FIFO status pub fn read_fifo_status(&self) -> ChipFifoInfo { - match self.reg.iir_fcr.read() & 0b1100_0000 { + match self.reg.read_iir() & 0b1100_0000 { 0 => ChipFifoInfo::NoFifo, 0b0100_0000 => ChipFifoInfo::Reserved, 0b1000_0000 => ChipFifoInfo::EnabledNoFunction, @@ -406,12 +306,12 @@ impl<'a> MmioUart8250<'a> { /// get whether 64 Byte fifo (16750 only) is enabled (IIR\[5\]) pub fn is_64byte_fifo_enabled(&self) -> bool { - self.reg.iir_fcr.read() & 0b0010_0000 != 0 + self.reg.read_iir() & 0b0010_0000 != 0 } /// Read IIR\[3:1\] to get interrupt type pub fn read_interrupt_type(&self) -> Option { - let iir = self.reg.iir_fcr.read() & 0b0000_1111; + let iir = self.reg.read_iir() & 0b0000_1111; if iir & 1 != 0 { None } else { @@ -427,40 +327,6 @@ impl<'a> MmioUart8250<'a> { } } - /// Write FCR (offset + 2) to control FIFO buffers - /// - /// > ## FIFO Control Register - /// > - /// > Offset: +2 . This is a relatively "new" register that was not a part of the original 8250 UART implementation. The purpose of this register is to control how the First In/First Out (FIFO) buffers will behave on the chip and to help you fine-tune their performance in your application. This even gives you the ability to "turn on" or "turn off" the FIFO. - /// > - /// > Keep in mind that this is a "write only" register. Attempting to read in the contents will only give you the Interrupt Identification Register (IIR), which has a totally different context. - /// > - /// > | Bit | Notes | | | | - /// > | ----- | --------------------------- | ----- | --------------------------------- | ----------------------- | - /// > | 7 & 6 | Bit 7 | Bit 6 | Interrupt Trigger Level (16 byte) | Trigger Level (64 byte) | - /// > | | 0 | 0 | 1 Byte | 1 Byte | - /// > | | 0 | 1 | 4 Bytes | 16 Bytes | - /// > | | 1 | 0 | 8 Bytes | 32 Bytes | - /// > | | 1 | 1 | 14 Bytes | 56 Bytes | - /// > | 5 | Enable 64 Byte FIFO (16750) | | | | - /// > | 4 | Reserved | | | | - /// > | 3 | DMA Mode Select | | | | - /// > | 2 | Clear Transmit FIFO | | | | - /// > | 1 | Clear Receive FIFO | | | | - /// > | 0 | Enable FIFOs | | | | - #[inline] - fn write_fcr(&self, value: u8) { - unsafe { self.reg.iir_fcr.write(value) } - } - - /// Write LCR (offset + 3) - /// - /// Write Line Control Register to set DLAB and the serial data protocol - #[inline] - fn write_lcr(&self, value: u8) { - unsafe { self.reg.lcr.write(value) } - } - /// enable DLAB fn enable_divisor_latch_accessible(&self) { unsafe { self.reg.lcr.modify(|v| v | 0b1000_0000) } @@ -498,7 +364,7 @@ impl<'a> MmioUart8250<'a> { /// /// Simply return a u8 to indicate 1 or 1.5/2 bits pub fn get_stop_bit(&self) -> u8 { - ((self.reg.lcr.read() & 0b100) >> 2) + 1 + ((self.reg.read_lcr() & 0b100) >> 2) + 1 } /// set stop bit, only 1 and 2 can be used as `stop_bit` @@ -512,7 +378,7 @@ impl<'a> MmioUart8250<'a> { /// get word length of used data protocol pub fn get_word_length(&self) -> u8 { - (self.reg.lcr.read() & 0b11) + 5 + (self.reg.read_lcr() & 0b11) + 5 } /// set word length, only 5..=8 can be used as `length` @@ -524,39 +390,10 @@ impl<'a> MmioUart8250<'a> { } } - /// Write MCR (offset + 4) - /// - /// Write Modem Control Register to control flow - #[inline] - fn write_mcr(&self, value: u8) { - unsafe { self.reg.mcr.write(value) } - } - - /// Read LSR (offset + 5) - /// - /// > ## Line Status Register - /// > - /// > Offset: +5 . This register is used primarily to give you information on possible error conditions that may exist within the UART, based on the data that has been received. Keep in mind that this is a "read only" register, and any data written to this register is likely to be ignored or worse, cause different behavior in the UART. There are several uses for this information, and some information will be given below on how it can be useful for diagnosing problems with your serial data connection: - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------------- | - /// > | 7 | Error in Received FIFO | - /// > | 6 | Empty Data Holding Registers | - /// > | 5 | Empty Transmitter Holding Register | - /// > | 4 | Break Interrupt | - /// > | 3 | Framing Error | - /// > | 2 | Parity Error | - /// > | 1 | Overrun Error | - /// > | 0 | Data Ready | - #[inline] - fn read_lsr(&self) -> u8 { - self.reg.lsr.read() - } - /// Get LSR bitflags #[inline] fn lsr(&self) -> LSR { - LSR::from_bits_truncate(self.read_lsr()) + LSR::from_bits_truncate(self.reg.read_lsr()) } /// get whether there is an error in received FIFO @@ -596,31 +433,10 @@ impl<'a> MmioUart8250<'a> { self.lsr().contains(LSR::DR) } - /// Read MSR (offset + 6) - /// - /// > ## Modem Status Register - /// > - /// > Offset: +6 . This register is another read-only register that is here to inform your software about the current status of the modem. The modem accessed in this manner can either be an external modem, or an internal modem that uses a UART as an interface to the computer. - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------- | - /// > | 7 | Carrier Detect | - /// > | 6 | Ring Indicator | - /// > | 5 | Data Set Ready | - /// > | 4 | Clear To Send | - /// > | 3 | Delta Data Carrier Detect | - /// > | 2 | Trailing Edge Ring Indicator | - /// > | 1 | Delta Data Set Ready | - /// > | 0 | Delta Clear To Send | - #[inline] - fn read_msr(&self) -> u8 { - self.reg.msr.read() - } - /// Get MSR bitflags #[inline] fn msr(&self) -> MSR { - MSR::from_bits_truncate(self.read_msr()) + MSR::from_bits_truncate(self.reg.read_msr()) } pub fn is_carrier_detect(&self) -> bool { @@ -654,16 +470,6 @@ impl<'a> MmioUart8250<'a> { pub fn is_delta_clear_to_send(&self) -> bool { self.msr().contains(MSR::DCTS) } - - #[inline] - pub fn read_sr(&self) -> u8 { - self.reg.scratch.read() - } - - #[inline] - pub fn write_sr(&self, value: u8) { - unsafe { self.reg.scratch.write(value) } - } } /// ## fmt::Write From f1f415e15b3fc112d6b0a56dbfab6e6e7ddd885e Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Thu, 31 Mar 2022 17:47:21 +0100 Subject: [PATCH 02/10] Add bitflags for FCR, LCR and MCR. --- uart8250/src/uart.rs | 111 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 108 insertions(+), 3 deletions(-) diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index 44cd3e2..cd255b5 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -67,6 +67,81 @@ bitflags! { } } +bitflags! { + /// FIFO Control Register (bitflags) + pub struct FCR: u8 { + /// Interrupt trigger level is 1 byte. + const INTERRUPT_TRIGGER_LEVEL_1 = 0b0000_0000; + /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. + const INTERRUPT_TRIGGER_LEVEL_4_16 = 0b0100_0000; + /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. + const INTERRUPT_TRIGGER_LEVEL_8_32 = 0b1000_0000; + /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. + const INTERRUPT_TRIGGER_LEVEL_14_56 = 0b1100_0000; + /// Enable 64 byte FIFO (16750) + const ENABLE_64_BYTE = 0b0010_0000; + /// DMA mode select + const DMA_MODE = 0b0000_1000; + /// Clear transmit FIFO + const CLEAR_TX = 0b0000_0100; + /// Clear receive FIFO + const CLEAR_RX = 0b0000_0010; + /// Enable FIFOs. + const ENABLE = 0b0000_0001; + } +} + +bitflags! { + /// Line Control Register (bitflags) + pub struct LCR: u8 { + /// Divisor Latch Access Bit + const DLAB = 0b1000_0000; + /// Set Break Enable + const SBE = 0b0100_0000; + /// No parity + const NO_PARITY = 0b0000_0000; + /// Odd parity + const ODD_PARITY = 0b0000_1000; + /// Even parity + const EVEN_PARITY = 0b0001_1000; + /// Mark + const MARK = 0b0010_1000; + /// Space + const SPACE = 0b0011_1000; + /// One stop bit + const ONE_STOP_BIT = 0b0000_0000; + /// 1.5 or 2 stop bits + const TWO_STOP_BITS = 0b0000_0100; + /// 5 bit word length + const WORD_5_BITS = 0b0000_0000; + /// 6 bit word length + const WORD_6_BITS = 0b0000_0001; + /// 7 bit word length + const WORD_7_BITS = 0b0000_0010; + /// 8 bit word length + const WORD_8_BITS = 0b0000_0011; + + } +} + +bitflags! { + /// Modem Control Register (bitflags) + pub struct MCR: u8 { + /// Autoflow control enabled (16750) + const AUTOFLOW_CONTROL_ENABLED = 0b0010_0000; + /// Loopback mode + const LOOPBACK_MODE = 0b0001_0000; + /// Auxiliary output 2 + const AUX_OUTPUT_2 = 0b0000_1000; + /// Auxiliary output 1 + const AUX_OUTPUT_1 = 0b0000_0100; + /// Request to Send + const RTS = 0b0000_0010; + /// Data Terminal Ready + const DTR = 0b0000_0001; + } +} + #[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum ChipFifoInfo { NoFifo, @@ -138,11 +213,11 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.reg.write_lcr(3); + self.set_lcr(LCR::NO_PARITY | LCR::ONE_STOP_BIT | LCR::WORD_8_BITS); // Enable FIFO - self.reg.write_fcr(1); + self.set_fcr(FCR::ENABLE); // No modem control - self.reg.write_mcr(0); + self.set_mcr(MCR::empty()); // Enable received_data_available_interrupt self.enable_received_data_available_interrupt(); // Enable transmitter_holding_register_empty_interrupt @@ -390,6 +465,36 @@ impl<'a> MmioUart8250<'a> { } } + /// Sets FCR bitflags + #[inline] + pub fn set_fcr(&self, fcr: FCR) { + self.reg.write_fcr(fcr.bits()) + } + + /// Gets LCR bitflags + #[inline] + pub fn lcr(&self) -> LCR { + LCR::from_bits_truncate(self.reg.read_lcr()) + } + + /// Sets LCR bitflags + #[inline] + pub fn set_lcr(&self, lcr: LCR) { + self.reg.write_lcr(lcr.bits()) + } + + /// Gets MCR bitflags + #[inline] + pub fn mcr(&self) -> MCR { + MCR::from_bits_truncate(self.reg.read_mcr()) + } + + /// Sets MCR bitflags + #[inline] + pub fn set_mcr(&self, mcr: MCR) { + self.reg.write_mcr(mcr.bits()) + } + /// Get LSR bitflags #[inline] fn lsr(&self) -> LSR { From 563ea427c8b60236bf9ecd0438e3b562b5ae4686 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 16:49:31 +0100 Subject: [PATCH 03/10] Use nightly toolchain. --- .github/workflows/rust.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml index a0b0bf7..85ac83c 100644 --- a/.github/workflows/rust.yml +++ b/.github/workflows/rust.yml @@ -13,6 +13,8 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v3 + - name: Select nightly toolchain + run: rustup override set nightly - name: Build run: cargo build - name: Run tests From 9f83f8e52b5c0a7cda4504b5ddc28dff68f1ecaf Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Fri, 8 Apr 2022 12:46:57 +0100 Subject: [PATCH 04/10] First cut at moving to tock-registers. --- Cargo.lock | 8 +- uart8250/Cargo.toml | 2 +- uart8250/src/registers.rs | 156 +++++++++++++------------------------- uart8250/src/uart.rs | 152 +++++++++++++++++++++++-------------- 4 files changed, 153 insertions(+), 165 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 87d31ab..f976576 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -33,6 +33,12 @@ version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae" +[[package]] +name = "tock-registers" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4ee8fba06c1f4d0b396ef61a54530bb6b28f0dc61c38bc8bc5a5a48161e6282e" + [[package]] name = "uart8250" version = "0.5.0" @@ -40,7 +46,7 @@ dependencies = [ "bitflags", "embedded-hal", "nb 1.0.0", - "volatile-register", + "tock-registers", ] [[package]] diff --git a/uart8250/Cargo.toml b/uart8250/Cargo.toml index ff79064..ca8bd22 100644 --- a/uart8250/Cargo.toml +++ b/uart8250/Cargo.toml @@ -17,7 +17,7 @@ readme = "README.md" bitflags = "1" embedded-hal = { version = "0.2.7", optional = true } nb = { version = "1.0.0", optional = true } -volatile-register = "0.2" +tock-registers = "0.7.0" [features] default = [] diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index b6112cd..f8545de 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -1,37 +1,43 @@ +use crate::uart::{IER2, LCR}; use core::u8; +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_structs, + registers::{ReadOnly, ReadWrite}, +}; -use volatile_register::{RO, RW}; - -/// # UART Registers -/// -/// The chip has a total of 12 different registers that are mapped into 8 different Port I/O locations / Memory Mapped I/O addresses. -/// -/// The following is a table of each of the registers that can be found in a typical UART chip -/// -/// | Base Address | DLAB | I/O Access | Abbrv. | Register Name | -/// | ------------ | ---- | ---------- | ------ | --------------------------------- | -/// | +0 | 0 | Write | THR | Transmitter Holding Buffer | -/// | +0 | 0 | Read | RBR | Receiver Buffer | -/// | +0 | 1 | Read/Write | DLL | Divisor Latch Low Byte | -/// | +1 | 0 | Read/Write | IER | Interrupt Enable Register | -/// | +1 | 1 | Read/Write | DLH | Divisor Latch High Byte | -/// | +2 | x | Read | IIR | Interrupt Identification Register | -/// | +2 | x | Write | FCR | FIFO Control Register | -/// | +3 | x | Read/Write | LCR | Line Control Register | -/// | +4 | x | Read/Write | MCR | Modem Control Register | -/// | +5 | x | Read | LSR | Line Status Register | -/// | +6 | x | Read | MSR | Modem Status Register | -/// | +7 | x | Read/Write | SR | Scratch Register | -#[repr(C, packed)] -pub struct Registers { - thr_rbr_dll: RW, - ier_dlh: RW, - iir_fcr: RW, - pub lcr: RW, - mcr: RW, - lsr: RO, - msr: RO, - scratch: RW, +register_structs! { + /// # UART Registers + /// + /// The chip has a total of 12 different registers that are mapped into 8 different Port I/O locations / Memory Mapped I/O addresses. + /// + /// The following is a table of each of the registers that can be found in a typical UART chip + /// + /// | Base Address | DLAB | I/O Access | Abbrv. | Register Name | + /// | ------------ | ---- | ---------- | ------ | --------------------------------- | + /// | +0 | 0 | Write | THR | Transmitter Holding Buffer | + /// | +0 | 0 | Read | RBR | Receiver Buffer | + /// | +0 | 1 | Read/Write | DLL | Divisor Latch Low Byte | + /// | +1 | 0 | Read/Write | IER | Interrupt Enable Register | + /// | +1 | 1 | Read/Write | DLH | Divisor Latch High Byte | + /// | +2 | x | Read | IIR | Interrupt Identification Register | + /// | +2 | x | Write | FCR | FIFO Control Register | + /// | +3 | x | Read/Write | LCR | Line Control Register | + /// | +4 | x | Read/Write | MCR | Modem Control Register | + /// | +5 | x | Read | LSR | Line Status Register | + /// | +6 | x | Read | MSR | Modem Status Register | + /// | +7 | x | Read/Write | SR | Scratch Register | + pub Registers { + (0x00 => thr_rbr_dll: ReadWrite), + (0x01 => ier_dlh: ReadWrite), + (0x02 => iir_fcr: ReadWrite), + (0x03 => pub lcr: ReadWrite), + (0x04 => mcr: ReadWrite), + (0x05 => lsr: ReadOnly), + (0x06 => msr: ReadOnly), + (0x07 => scratch: ReadWrite), + (0x08 => @END), + } } impl Registers { @@ -53,7 +59,7 @@ impl Registers { /// > If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register. #[inline] pub fn write_thr(&self, value: u8) { - unsafe { self.thr_rbr_dll.write(value) } + self.thr_rbr_dll.set(value) } /// read RBR (offset + 0) @@ -61,41 +67,7 @@ impl Registers { /// Read Receiver Buffer to get data #[inline] pub fn read_rbr(&self) -> u8 { - self.thr_rbr_dll.read() - } - - /// read DLL (offset + 0) - /// - /// get divisor latch low byte in the register - /// - /// > ## Divisor Latch Bytes - /// > - /// > Offset: +0 and +1 . The Divisor Latch Bytes are what control the baud rate of the modem. As you might guess from the name of this register, it is used as a divisor to determine what baud rate that the chip is going to be transmitting at. - /// - /// Used clock 1.8432 MHz as example, first divide 16 and get 115200. Then use the formula to get divisor latch value: - /// - /// *DivisorLatchValue = 115200 / BaudRate* - /// - /// This gives the following table: - /// - /// | Baud Rate | Divisor (in decimal) | Divisor Latch High Byte | Divisor Latch Low Byte | - /// | --------- | -------------------- | ----------------------- | ---------------------- | - /// | 50 | 2304 | $09 | $00 | - /// | 110 | 1047 | $04 | $17 | - /// | 220 | 524 | $02 | $0C | - /// | 300 | 384 | $01 | $80 | - /// | 600 | 192 | $00 | $C0 | - /// | 1200 | 96 | $00 | $60 | - /// | 2400 | 48 | $00 | $30 | - /// | 4800 | 24 | $00 | $18 | - /// | 9600 | 12 | $00 | $0C | - /// | 19200 | 6 | $00 | $06 | - /// | 38400 | 3 | $00 | $03 | - /// | 57600 | 2 | $00 | $02 | - /// | 115200 | 1 | $00 | $01 | - #[inline] - pub fn read_dll(&self) -> u8 { - self.thr_rbr_dll.read() + self.thr_rbr_dll.get() } /// write DLL (offset + 0) @@ -103,15 +75,7 @@ impl Registers { /// set divisor latch low byte in the register #[inline] pub fn write_dll(&self, value: u8) { - unsafe { self.thr_rbr_dll.write(value) } - } - - /// read DLH (offset + 1) - /// - /// get divisor latch high byte in the register - #[inline] - pub fn read_dlh(&self) -> u8 { - self.ier_dlh.read() + self.thr_rbr_dll.set(value) } /// write DLH (offset + 1) @@ -119,7 +83,7 @@ impl Registers { /// set divisor latch high byte in the register #[inline] pub fn write_dlh(&self, value: u8) { - unsafe { self.ier_dlh.write(value) } + self.ier_dlh.set(value) } /// Read IER (offset + 1) @@ -144,7 +108,7 @@ impl Registers { /// > | 0 | Enable Received Data Available Interrupt | #[inline] pub fn read_ier(&self) -> u8 { - self.ier_dlh.read() + self.ier_dlh.get() } /// Write IER (offset + 1) @@ -152,7 +116,7 @@ impl Registers { /// Write Interrupt Enable Register to turn on/off interrupts #[inline] pub fn write_ier(&self, value: u8) { - unsafe { self.ier_dlh.write(value) } + self.ier_dlh.set(value) } /// Read IIR (offset + 2) @@ -189,7 +153,7 @@ impl Registers { /// > | 0 | Interrupt Pending Flag | | | | | #[inline] pub fn read_iir(&self) -> u8 { - self.iir_fcr.read() + self.iir_fcr.get() } /// Write FCR (offset + 2) to control FIFO buffers @@ -215,7 +179,7 @@ impl Registers { /// > | 0 | Enable FIFOs | | | | #[inline] pub fn write_fcr(&self, value: u8) { - unsafe { self.iir_fcr.write(value) } + self.iir_fcr.set(value) } /// Read LCR (offset + 3) @@ -248,15 +212,7 @@ impl Registers { /// > | | 1 | 1 | 8 Bits | | #[inline] pub fn read_lcr(&self) -> u8 { - self.lcr.read() - } - - /// Write LCR (offset + 3) - /// - /// Write Line Control Register to set DLAB and the serial data protocol - #[inline] - pub fn write_lcr(&self, value: u8) { - unsafe { self.lcr.write(value) } + self.lcr.get() } /// Read MCR (offset + 4) @@ -279,7 +235,7 @@ impl Registers { /// > | 0 | Data Terminal Ready | #[inline] pub fn read_mcr(&self) -> u8 { - self.mcr.read() + self.mcr.get() } /// Write MCR (offset + 4) @@ -287,7 +243,7 @@ impl Registers { /// Write Modem Control Register to control flow #[inline] pub fn write_mcr(&self, value: u8) { - unsafe { self.mcr.write(value) } + self.mcr.set(value) } /// Read LSR (offset + 5) @@ -308,7 +264,7 @@ impl Registers { /// > | 0 | Data Ready | #[inline] pub fn read_lsr(&self) -> u8 { - self.lsr.read() + self.lsr.get() } /// Read MSR (offset + 6) @@ -329,16 +285,6 @@ impl Registers { /// > | 0 | Delta Clear To Send | #[inline] pub fn read_msr(&self) -> u8 { - self.msr.read() - } - - #[inline] - pub fn read_sr(&self) -> u8 { - self.scratch.read() - } - - #[inline] - pub fn write_sr(&self, value: u8) { - unsafe { self.scratch.write(value) } + self.msr.get() } } diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index cd255b5..4f5c880 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -2,9 +2,73 @@ use bitflags::bitflags; #[cfg(feature = "embedded")] use core::convert::Infallible; use core::fmt::{self, Display, Formatter}; +use tock_registers::{ + fields::FieldValue, + interfaces::{ReadWriteable, Readable, Writeable}, + register_bitfields, LocalRegisterCopy, +}; use crate::registers::Registers; +register_bitfields![ + u8, + + /// Interrupt Enable Register + pub IER2 [ + /// Enable Received Data Available Interrupt + RDAI OFFSET(0) NUMBITS(1) [], + /// Enable Transmitter Holding Register Empty Interrupt + THREI OFFSET(1) NUMBITS(1) [], + /// Enable Receiver Line Status Interrupt + RLSI OFFSET(2) NUMBITS(1) [], + /// Enable Modem Status Interrupt + MSI OFFSET(3) NUMBITS(1) [], + /// Enable Sleep Mode (16750) + SM OFFSET(4) NUMBITS(1) [], + /// Enable Low Power Mode (16750) + LPM OFFSET(5) NUMBITS(1) [], + ], + + /// Line Control Register + pub LCR [ + /// Divisor Latch Access Bit + DLAB OFFSET(7) NUMBITS(1) [], // = 0b1000_0000; + /// Set Break Enable + SBE OFFSET(6) NUMBITS(1) [], // = 0b0100_0000; + /// Parity + Parity OFFSET(3) NUMBITS(3) [ + /// No parity + None = 0, + /// Odd parity + Odd = 1, + /// Even parity + Even = 3, + /// Mark + Mark = 5, + /// Space + Space = 7, + ], + /// Number of stop bits + STOP_BITS OFFSET(2) NUMBITS(1) [ + /// One stop bit + One = 0, + /// 1.5 or 2 stop bits + Two = 1, + ], + /// Word length + WORD_LENGTH OFFSET(0) NUMBITS(2) [ + /// 5 bit word length + Bits5 = 0, + /// 6 bit word length + Bits6 = 1, + /// 7 bit word length + Bits7 = 2, + /// 8 bit word length + Bits8 = 3, + ], + ], +]; + bitflags! { /// Interrupt Enable Register (bitflags) pub struct IER: u8 { @@ -91,39 +155,6 @@ bitflags! { } } -bitflags! { - /// Line Control Register (bitflags) - pub struct LCR: u8 { - /// Divisor Latch Access Bit - const DLAB = 0b1000_0000; - /// Set Break Enable - const SBE = 0b0100_0000; - /// No parity - const NO_PARITY = 0b0000_0000; - /// Odd parity - const ODD_PARITY = 0b0000_1000; - /// Even parity - const EVEN_PARITY = 0b0001_1000; - /// Mark - const MARK = 0b0010_1000; - /// Space - const SPACE = 0b0011_1000; - /// One stop bit - const ONE_STOP_BIT = 0b0000_0000; - /// 1.5 or 2 stop bits - const TWO_STOP_BITS = 0b0000_0100; - /// 5 bit word length - const WORD_5_BITS = 0b0000_0000; - /// 6 bit word length - const WORD_6_BITS = 0b0000_0001; - /// 7 bit word length - const WORD_7_BITS = 0b0000_0010; - /// 8 bit word length - const WORD_8_BITS = 0b0000_0011; - - } -} - bitflags! { /// Modem Control Register (bitflags) pub struct MCR: u8 { @@ -213,7 +244,7 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.set_lcr(LCR::NO_PARITY | LCR::ONE_STOP_BIT | LCR::WORD_8_BITS); + self.set_lcr(LCR::Parity::None + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); // Enable FIFO self.set_fcr(FCR::ENABLE); // No modem control @@ -404,35 +435,40 @@ impl<'a> MmioUart8250<'a> { /// enable DLAB fn enable_divisor_latch_accessible(&self) { - unsafe { self.reg.lcr.modify(|v| v | 0b1000_0000) } + self.reg.lcr.modify(LCR::DLAB::SET) } /// disable DLAB fn disable_divisor_latch_accessible(&self) { - unsafe { self.reg.lcr.modify(|v| v & !0b1000_0000) } + self.reg.lcr.modify(LCR::DLAB::CLEAR) } /// get parity of used data protocol pub fn get_parity(&self) -> Parity { - match self.reg.lcr.read() & 0b0011_1000 { - 0b0000_0000 => Parity::No, - 0b0000_1000 => Parity::Odd, - 0b0001_1000 => Parity::Even, - 0b0010_1000 => Parity::Mark, - 0b0011_1000 => Parity::Space, - _ => panic!("Invalid Parity! Please check your uart"), + match self + .reg + .lcr + .read_as_enum(LCR::Parity) + .expect("Invalid Parity! Please check your UART.") + { + LCR::Parity::Value::None => Parity::No, + LCR::Parity::Value::Odd => Parity::Odd, + LCR::Parity::Value::Even => Parity::Even, + LCR::Parity::Value::Mark => Parity::Mark, + LCR::Parity::Value::Space => Parity::Space, } } /// set parity pub fn set_parity(&self, parity: Parity) { - match parity { - Parity::No => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111)) }, - Parity::Odd => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0000_1000) }, - Parity::Even => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0001_1000) }, - Parity::Mark => unsafe { self.reg.lcr.modify(|v| (v & 0b1100_0111) | 0b0010_1000) }, - Parity::Space => unsafe { self.reg.lcr.modify(|v| v | 0b0011_1000) }, - } + let parity = match parity { + Parity::No => LCR::Parity::None, + Parity::Odd => LCR::Parity::Odd, + Parity::Even => LCR::Parity::Even, + Parity::Mark => LCR::Parity::Mark, + Parity::Space => LCR::Parity::Space, + }; + self.reg.lcr.modify(parity); } /// get stop bit of used data protocol @@ -445,21 +481,21 @@ impl<'a> MmioUart8250<'a> { /// set stop bit, only 1 and 2 can be used as `stop_bit` pub fn set_stop_bit(&self, stop_bit: u8) { match stop_bit { - 1 => unsafe { self.reg.lcr.modify(|v| v & 0b1111_1011) }, - 2 => unsafe { self.reg.lcr.modify(|v| v | 0b0000_0100) }, + 1 => self.reg.lcr.modify(LCR::STOP_BITS::One), + 2 => self.reg.lcr.modify(LCR::STOP_BITS::Two), _ => panic!("Invalid stop bit"), } } /// get word length of used data protocol pub fn get_word_length(&self) -> u8 { - (self.reg.read_lcr() & 0b11) + 5 + self.reg.lcr.read(LCR::WORD_LENGTH) + 5 } /// set word length, only 5..=8 can be used as `length` pub fn set_word_length(&self, length: u8) { if (5..=8).contains(&length) { - unsafe { self.reg.lcr.modify(|v| v | (length - 5)) } + self.reg.lcr.modify(LCR::WORD_LENGTH.val(length - 5)) } else { panic!("Invalid word length") } @@ -473,14 +509,14 @@ impl<'a> MmioUart8250<'a> { /// Gets LCR bitflags #[inline] - pub fn lcr(&self) -> LCR { - LCR::from_bits_truncate(self.reg.read_lcr()) + pub fn lcr(&self) -> LocalRegisterCopy { + self.reg.lcr.extract() } /// Sets LCR bitflags #[inline] - pub fn set_lcr(&self, lcr: LCR) { - self.reg.write_lcr(lcr.bits()) + pub fn set_lcr(&self, lcr: FieldValue) { + self.reg.lcr.write(lcr) } /// Gets MCR bitflags From 2b19a7e360c5a028f7e8c0528ed11eae4541a9ad Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Mon, 4 Apr 2022 22:42:18 +0100 Subject: [PATCH 05/10] Use register_bitfields rather than bitflags. --- Cargo.lock | 1 - uart8250/Cargo.toml | 1 - uart8250/src/registers.rs | 216 +------------------------ uart8250/src/uart.rs | 323 ++++++++++++++++++-------------------- 4 files changed, 158 insertions(+), 383 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index f976576..24def58 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -43,7 +43,6 @@ checksum = "4ee8fba06c1f4d0b396ef61a54530bb6b28f0dc61c38bc8bc5a5a48161e6282e" name = "uart8250" version = "0.5.0" dependencies = [ - "bitflags", "embedded-hal", "nb 1.0.0", "tock-registers", diff --git a/uart8250/Cargo.toml b/uart8250/Cargo.toml index ca8bd22..54bffeb 100644 --- a/uart8250/Cargo.toml +++ b/uart8250/Cargo.toml @@ -14,7 +14,6 @@ readme = "README.md" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -bitflags = "1" embedded-hal = { version = "0.2.7", optional = true } nb = { version = "1.0.0", optional = true } tock-registers = "0.7.0" diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index f8545de..cc1f8b8 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -1,9 +1,9 @@ -use crate::uart::{IER2, LCR}; +use crate::uart::{FCR, IER, IIR, LCR, LSR, MCR, MSR}; use core::u8; use tock_registers::{ interfaces::{Readable, Writeable}, register_structs, - registers::{ReadOnly, ReadWrite}, + registers::{Aliased, ReadOnly, ReadWrite}, }; register_structs! { @@ -29,12 +29,12 @@ register_structs! { /// | +7 | x | Read/Write | SR | Scratch Register | pub Registers { (0x00 => thr_rbr_dll: ReadWrite), - (0x01 => ier_dlh: ReadWrite), - (0x02 => iir_fcr: ReadWrite), + (0x01 => pub ier_dlh: ReadWrite), + (0x02 => pub iir_fcr: Aliased), (0x03 => pub lcr: ReadWrite), - (0x04 => mcr: ReadWrite), - (0x05 => lsr: ReadOnly), - (0x06 => msr: ReadOnly), + (0x04 => pub mcr: ReadWrite), + (0x05 => pub lsr: ReadOnly), + (0x06 => pub msr: ReadOnly), (0x07 => scratch: ReadWrite), (0x08 => @END), } @@ -85,206 +85,4 @@ impl Registers { pub fn write_dlh(&self, value: u8) { self.ier_dlh.set(value) } - - /// Read IER (offset + 1) - /// - /// Read IER to get what interrupts are enabled - /// - /// > ## Interrupt Enable Register - /// > - /// > Offset: +1 . This register allows you to control when and how the UART is going to trigger an interrupt event with the hardware interrupt associated with the serial COM port. If used properly, this can enable an efficient use of system resources and allow you to react to information being sent across a serial data line in essentially real-time conditions. Some more on that will be covered later, but the point here is that you can use the UART to let you know exactly when you need to extract some data. This register has both read- and write-access. - /// > - /// > The following is a table showing each bit in this register and what events that it will enable to allow you check on the status of this chip: - /// > - /// > | Bit | Notes | - /// > | --- | --------------------------------------------------- | - /// > | 7 | Reserved | - /// > | 6 | Reserved | - /// > | 5 | Enables Low Power Mode (16750) | - /// > | 4 | Enables Sleep Mode (16750) | - /// > | 3 | Enable Modem Status Interrupt | - /// > | 2 | Enable Receiver Line Status Interrupt | - /// > | 1 | Enable Transmitter Holding Register Empty Interrupt | - /// > | 0 | Enable Received Data Available Interrupt | - #[inline] - pub fn read_ier(&self) -> u8 { - self.ier_dlh.get() - } - - /// Write IER (offset + 1) - /// - /// Write Interrupt Enable Register to turn on/off interrupts - #[inline] - pub fn write_ier(&self, value: u8) { - self.ier_dlh.set(value) - } - - /// Read IIR (offset + 2) - /// - /// > ## Interrupt Identification Register - /// > - /// > Offset: +2 . This register is to be used to help identify what the unique characteristics of the UART chip that you are using has. This chip has two uses: - /// > - /// > - Identification of why the UART triggered an interrupt. - /// > - Identification of the UART chip itself. - /// > - /// > Of these, identification of why the interrupt service routine has been invoked is perhaps the most important. - /// > - /// > The following table explains some of the details of this register, and what each bit on it represents: - /// > - /// > | Bit | Notes | | | | | - /// > | ---------- | --------------------------------- | ----- | --------------------------------- | -------------------------------------------- | ----------------------------------------------------------------------------------------- | - /// > | 7 and 6 | Bit 7 | Bit 6 | | | | - /// > | | 0 | 0 | No FIFO on chip | | | - /// > | | 0 | 1 | Reserved condition | | | - /// > | | 1 | 0 | FIFO enabled, but not functioning | | | - /// > | | 1 | 1 | FIFO enabled | | | - /// > | 5 | 64 Byte FIFO Enabled (16750 only) | | | | | - /// > | 4 | Reserved | | | | | - /// > | 3, 2 and 1 | Bit 3 | Bit 2 | Bit 1 | | Reset Method | - /// > | | 0 | 0 | 0 | Modem Status Interrupt | Reading Modem Status Register(MSR) | - /// > | | 0 | 0 | 1 | Transmitter Holding Register Empty Interrupt | Reading Interrupt Identification Register(IIR) or Writing to Transmit Holding Buffer(THR) | - /// > | | 0 | 1 | 0 | Received Data Available Interrupt | Reading Receive Buffer Register(RBR) | - /// > | | 0 | 1 | 1 | Receiver Line Status Interrupt | Reading Line Status Register(LSR) | - /// > | | 1 | 0 | 0 | Reserved | N/A | - /// > | | 1 | 0 | 1 | Reserved | N/A | - /// > | | 1 | 1 | 0 | Time-out Interrupt Pending (16550 & later) | Reading Receive Buffer Register(RBR) | - /// > | | 1 | 1 | 1 | Reserved | N/A | - /// > | 0 | Interrupt Pending Flag | | | | | - #[inline] - pub fn read_iir(&self) -> u8 { - self.iir_fcr.get() - } - - /// Write FCR (offset + 2) to control FIFO buffers - /// - /// > ## FIFO Control Register - /// > - /// > Offset: +2 . This is a relatively "new" register that was not a part of the original 8250 UART implementation. The purpose of this register is to control how the First In/First Out (FIFO) buffers will behave on the chip and to help you fine-tune their performance in your application. This even gives you the ability to "turn on" or "turn off" the FIFO. - /// > - /// > Keep in mind that this is a "write only" register. Attempting to read in the contents will only give you the Interrupt Identification Register (IIR), which has a totally different context. - /// > - /// > | Bit | Notes | | | | - /// > | ----- | --------------------------- | ----- | --------------------------------- | ----------------------- | - /// > | 7 & 6 | Bit 7 | Bit 6 | Interrupt Trigger Level (16 byte) | Trigger Level (64 byte) | - /// > | | 0 | 0 | 1 Byte | 1 Byte | - /// > | | 0 | 1 | 4 Bytes | 16 Bytes | - /// > | | 1 | 0 | 8 Bytes | 32 Bytes | - /// > | | 1 | 1 | 14 Bytes | 56 Bytes | - /// > | 5 | Enable 64 Byte FIFO (16750) | | | | - /// > | 4 | Reserved | | | | - /// > | 3 | DMA Mode Select | | | | - /// > | 2 | Clear Transmit FIFO | | | | - /// > | 1 | Clear Receive FIFO | | | | - /// > | 0 | Enable FIFOs | | | | - #[inline] - pub fn write_fcr(&self, value: u8) { - self.iir_fcr.set(value) - } - - /// Read LCR (offset + 3) - /// - /// Read Line Control Register to get the data protocol and DLAB - /// - /// > ## Line Control Register - /// > - /// > Offset: +3 . This register has two major purposes: - /// > - /// > - Setting the Divisor Latch Access Bit (DLAB), allowing you to set the values of the Divisor Latch Bytes. - /// > - Setting the bit patterns that will be used for both receiving and transmitting the serial data. In other words, the serial data protocol you will be using (8-1-None, 5-2-Even, etc.). - /// > - /// > | Bit | Notes | | | | - /// > | -------- | ------------------------ | ---------------------------- | ----------- | ------------- | - /// > | 7 | Divisor Latch Access Bit | | | | - /// > | 6 | Set Break Enable | | | | - /// > | 3, 4 & 5 | Bit 5 | Bit 4 | Bit 3 | Parity Select | - /// > | | 0 | 0 | 0 | No Parity | - /// > | | 0 | 0 | 1 | Odd Parity | - /// > | | 0 | 1 | 1 | Even Parity | - /// > | | 1 | 0 | 1 | Mark | - /// > | | 1 | 1 | 1 | Space | - /// > | 2 | 0 | One Stop Bit | | | - /// > | | 1 | 1.5 Stop Bits or 2 Stop Bits | | | - /// > | 0 & 1 | Bit 1 | Bit 0 | Word Length | | - /// > | | 0 | 0 | 5 Bits | | - /// > | | 0 | 1 | 6 Bits | | - /// > | | 1 | 0 | 7 Bits | | - /// > | | 1 | 1 | 8 Bits | | - #[inline] - pub fn read_lcr(&self) -> u8 { - self.lcr.get() - } - - /// Read MCR (offset + 4) - /// - /// Read Modem Control Register to get how flow is controlled - /// - /// > ## Modem Control Register - /// > - /// > Offset: +4 . This register allows you to do "hardware" flow control, under software control. Or in a more practical manner, it allows direct manipulation of four different wires on the UART that you can set to any series of independent logical states, and be able to offer control of the modem. It should also be noted that most UARTs need Auxiliary Output 2 set to a logical "1" to enable interrupts. - /// > - /// > | Bit | Notes | - /// > | --- | -------------------------------- | - /// > | 7 | Reserved | - /// > | 6 | Reserved | - /// > | 5 | Autoflow Control Enabled (16750) | - /// > | 4 | Loopback Mode | - /// > | 3 | Auxiliary Output 2 | - /// > | 2 | Auxiliary Output 1 | - /// > | 1 | Request To Send | - /// > | 0 | Data Terminal Ready | - #[inline] - pub fn read_mcr(&self) -> u8 { - self.mcr.get() - } - - /// Write MCR (offset + 4) - /// - /// Write Modem Control Register to control flow - #[inline] - pub fn write_mcr(&self, value: u8) { - self.mcr.set(value) - } - - /// Read LSR (offset + 5) - /// - /// > ## Line Status Register - /// > - /// > Offset: +5 . This register is used primarily to give you information on possible error conditions that may exist within the UART, based on the data that has been received. Keep in mind that this is a "read only" register, and any data written to this register is likely to be ignored or worse, cause different behavior in the UART. There are several uses for this information, and some information will be given below on how it can be useful for diagnosing problems with your serial data connection: - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------------- | - /// > | 7 | Error in Received FIFO | - /// > | 6 | Empty Data Holding Registers | - /// > | 5 | Empty Transmitter Holding Register | - /// > | 4 | Break Interrupt | - /// > | 3 | Framing Error | - /// > | 2 | Parity Error | - /// > | 1 | Overrun Error | - /// > | 0 | Data Ready | - #[inline] - pub fn read_lsr(&self) -> u8 { - self.lsr.get() - } - - /// Read MSR (offset + 6) - /// - /// > ## Modem Status Register - /// > - /// > Offset: +6 . This register is another read-only register that is here to inform your software about the current status of the modem. The modem accessed in this manner can either be an external modem, or an internal modem that uses a UART as an interface to the computer. - /// > - /// > | Bit | Notes | - /// > | --- | ---------------------------- | - /// > | 7 | Carrier Detect | - /// > | 6 | Ring Indicator | - /// > | 5 | Data Set Ready | - /// > | 4 | Clear To Send | - /// > | 3 | Delta Data Carrier Detect | - /// > | 2 | Trailing Edge Ring Indicator | - /// > | 1 | Delta Data Set Ready | - /// > | 0 | Delta Clear To Send | - #[inline] - pub fn read_msr(&self) -> u8 { - self.msr.get() - } } diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index 4f5c880..ab31877 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -1,4 +1,3 @@ -use bitflags::bitflags; #[cfg(feature = "embedded")] use core::convert::Infallible; use core::fmt::{self, Display, Formatter}; @@ -14,7 +13,7 @@ register_bitfields![ u8, /// Interrupt Enable Register - pub IER2 [ + pub IER [ /// Enable Received Data Available Interrupt RDAI OFFSET(0) NUMBITS(1) [], /// Enable Transmitter Holding Register Empty Interrupt @@ -32,13 +31,13 @@ register_bitfields![ /// Line Control Register pub LCR [ /// Divisor Latch Access Bit - DLAB OFFSET(7) NUMBITS(1) [], // = 0b1000_0000; + DLAB OFFSET(7) NUMBITS(1) [], /// Set Break Enable - SBE OFFSET(6) NUMBITS(1) [], // = 0b0100_0000; + SBE OFFSET(6) NUMBITS(1) [], /// Parity Parity OFFSET(3) NUMBITS(3) [ /// No parity - None = 0, + No = 0, /// Odd parity Odd = 1, /// Even parity @@ -67,111 +66,111 @@ register_bitfields![ Bits8 = 3, ], ], -]; - -bitflags! { - /// Interrupt Enable Register (bitflags) - pub struct IER: u8 { - /// Enable Received Data Available Interrupt - const RDAI = 0b0000_0001; - /// Enable Transmitter Holding Register Empty Interrupt - const THREI = 0b0000_0010; - /// Enable Receiver Line Status Interrupt - const RLSI = 0b0000_0100; - /// Enable Modem Status Interrupt - const MSI = 0b0000_1000; - /// Enable Sleep Mode (16750) - const SM = 0b0001_0000; - /// Enable Low Power Mode (16750) - const LPM = 0b0010_0000; - } -} -bitflags! { - /// Line Status Register (bitflags) - pub struct LSR: u8 { + /// Line Status Register + pub LSR [ /// Data Ready - const DR = 0b0000_0001; + DR OFFSET(0) NUMBITS(1) [], /// Overrun Error - const OE = 0b0000_0010; + OE OFFSET(1) NUMBITS(1) [], /// Parity Error - const PE = 0b0000_0100; + PE OFFSET(2) NUMBITS(1) [], /// Framing Error - const FE = 0b0000_1000; + FE OFFSET(3) NUMBITS(1) [], /// Break Interrupt - const BI = 0b0001_0000; + BI OFFSET(4) NUMBITS(1) [], /// Transmitter Holding Register Empty - const THRE = 0b0010_0000; + THRE OFFSET(5) NUMBITS(1) [], /// Data Holding Regiters Empty - const DHRE = 0b0100_0000; + DHRE OFFSET(6) NUMBITS(1) [], /// Error in Received FIFO - const RFE = 0b1000_0000; - } -} + RFE OFFSET(7) NUMBITS(1) [], + ], -bitflags! { - /// Modem Status Register (bitflags) - pub struct MSR: u8 { + /// Modem Status Register + pub MSR [ /// Delta Clear To Send - const DCTS = 0b0000_0001; - ///Delta Data Set Ready - const DDSR = 0b0000_0010; - ///Trailing Edge Ring Indicator - const TERI = 0b0000_0100; - ///Delta Data Carrier Detect - const DDCD = 0b0000_1000; - ///Clear To Send - const CTS = 0b0001_0000; - ///Data Set Ready - const DSR = 0b0010_0000; - ///Ring Indicator - const RI = 0b0100_0000; - ///Carrier Detect - const CD = 0b1000_0000; - } -} + DCTS OFFSET(0) NUMBITS(1) [], + /// Delta Data Set Ready + DDSR OFFSET(1) NUMBITS(1) [], + /// Trailing Edge Ring Indicator + TERI OFFSET(2) NUMBITS(1) [], + /// Delta Data Carrier Detect + DDCD OFFSET(3) NUMBITS(1) [], + /// Clear To Send + CTS OFFSET(4) NUMBITS(1) [], + /// Data Set Ready + DSR OFFSET(5) NUMBITS(1) [], + /// Ring Indicator + RI OFFSET(6) NUMBITS(1) [], + /// Carrier Detect + CD OFFSET(7) NUMBITS(1) [], + ], -bitflags! { - /// FIFO Control Register (bitflags) - pub struct FCR: u8 { - /// Interrupt trigger level is 1 byte. - const INTERRUPT_TRIGGER_LEVEL_1 = 0b0000_0000; - /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. - const INTERRUPT_TRIGGER_LEVEL_4_16 = 0b0100_0000; - /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. - const INTERRUPT_TRIGGER_LEVEL_8_32 = 0b1000_0000; - /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. - const INTERRUPT_TRIGGER_LEVEL_14_56 = 0b1100_0000; + /// FIFO Control Register + pub FCR [ + /// Interrupt trigger level. + InterruptTriggerLevel OFFSET(6) NUMBITS(2) [ + /// Interrupt trigger level is 1 byte. + Bytes1 = 0, + /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. + Bytes4Or16 = 1, + /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. + Bytes8Or32 = 2, + /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. + Bytes14Or56 = 3, + ], /// Enable 64 byte FIFO (16750) - const ENABLE_64_BYTE = 0b0010_0000; + Enable64Byte OFFSET(5) NUMBITS(1) [], /// DMA mode select - const DMA_MODE = 0b0000_1000; + DmaMode OFFSET(3) NUMBITS(1) [], /// Clear transmit FIFO - const CLEAR_TX = 0b0000_0100; + ClearTx OFFSET(2) NUMBITS(1) [], /// Clear receive FIFO - const CLEAR_RX = 0b0000_0010; + ClearRx OFFSET(1) NUMBITS(1) [], /// Enable FIFOs. - const ENABLE = 0b0000_0001; - } -} + Enable OFFSET(0) NUMBITS(1) [], + ], + + /// Interrupt Identification Register + pub IIR [ + FifoInfo OFFSET(6) NUMBITS(2) [ + /// No FIFO on chip. + None = 0, + /// FIFO enabled but not functioning. + EnabledNotFunctioning = 2, + /// FIFO enabled. + Enabled = 3, + ], + /// 64 byte FIFO enabled (16750 only). + Fifo64Byte OFFSET(5) NUMBITS(1) [], + InterruptType OFFSET(1) NUMBITS(3) [ + ModemStatus = 0, + TransmitterHoldingRegisterEmpty = 1, + ReceivedDataAvailable = 2, + ReceiverLineStatus = 3, + Timeout = 6, + ], + /// Interrupt pending flag. + InterruptPending OFFSET(0) NUMBITS(1) [], + ], -bitflags! { /// Modem Control Register (bitflags) - pub struct MCR: u8 { + pub MCR [ /// Autoflow control enabled (16750) - const AUTOFLOW_CONTROL_ENABLED = 0b0010_0000; + AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [], /// Loopback mode - const LOOPBACK_MODE = 0b0001_0000; + LOOPBACK_MODE OFFSET(4) NUMBITS(1) [], /// Auxiliary output 2 - const AUX_OUTPUT_2 = 0b0000_1000; + AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [], /// Auxiliary output 1 - const AUX_OUTPUT_1 = 0b0000_0100; + AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [], /// Request to Send - const RTS = 0b0000_0010; + RTS OFFSET(1) NUMBITS(1) [], /// Data Terminal Ready - const DTR = 0b0000_0001; - } -} + DTR OFFSET(0) NUMBITS(1) [], + ], +]; #[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum ChipFifoInfo { @@ -244,11 +243,11 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.set_lcr(LCR::Parity::None + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); + self.set_lcr(LCR::Parity::No + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); // Enable FIFO - self.set_fcr(FCR::ENABLE); + self.set_fcr(FCR::Enable::SET); // No modem control - self.set_mcr(MCR::empty()); + self.set_mcr(FieldValue::::new(0, 0, 0)); // Enable received_data_available_interrupt self.enable_received_data_available_interrupt(); // Enable transmitter_holding_register_empty_interrupt @@ -297,138 +296,130 @@ impl<'a> MmioUart8250<'a> { self.disable_divisor_latch_accessible(); } - /// Get IER bitflags - #[inline] - fn ier(&self) -> IER { - IER::from_bits_truncate(self.reg.read_ier()) - } - - /// Set IER via bitflags - #[inline] - fn set_ier(&self, flag: IER) { - self.reg.write_ier(flag.bits()) - } - /// get whether low power mode (16750) is enabled (IER\[5\]) pub fn is_low_power_mode_enabled(&self) -> bool { - self.ier().contains(IER::LPM) + self.reg.ier_dlh.is_set(IER::LPM) } /// enable low power mode (16750) (IER\[5\]) pub fn enable_low_power_mode(&self) { - self.set_ier(self.ier() | IER::LPM) + self.reg.ier_dlh.modify(IER::LPM::SET) } /// disable low power mode (16750) (IER\[5\]) pub fn disable_low_power_mode(&self) { - self.set_ier(self.ier() & !IER::LPM) + self.reg.ier_dlh.modify(IER::LPM::CLEAR) } /// get whether sleep mode (16750) is enabled (IER\[4\]) pub fn is_sleep_mode_enabled(&self) -> bool { - self.ier().contains(IER::SM) + self.reg.ier_dlh.is_set(IER::SM) } /// enable sleep mode (16750) (IER\[4\]) pub fn enable_sleep_mode(&self) { - self.set_ier(self.ier() | IER::SM) + self.reg.ier_dlh.modify(IER::SM::SET) } /// disable sleep mode (16750) (IER\[4\]) pub fn disable_sleep_mode(&self) { - self.set_ier(self.ier() & !IER::SM) + self.reg.ier_dlh.modify(IER::SM::CLEAR) } /// get whether modem status interrupt is enabled (IER\[3\]) pub fn is_modem_status_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::MSI) + self.reg.ier_dlh.is_set(IER::MSI) } /// enable modem status interrupt (IER\[3\]) pub fn enable_modem_status_interrupt(&self) { - self.set_ier(self.ier() | IER::MSI) + self.reg.ier_dlh.modify(IER::MSI::SET) } /// disable modem status interrupt (IER\[3\]) pub fn disable_modem_status_interrupt(&self) { - self.set_ier(self.ier() & !IER::MSI) + self.reg.ier_dlh.modify(IER::MSI::CLEAR) } /// get whether receiver line status interrupt is enabled (IER\[2\]) pub fn is_receiver_line_status_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::RLSI) + self.reg.ier_dlh.is_set(IER::RLSI) } /// enable receiver line status interrupt (IER\[2\]) pub fn enable_receiver_line_status_interrupt(&self) { - self.set_ier(self.ier() | IER::RLSI) + self.reg.ier_dlh.modify(IER::RLSI::SET) } /// disable receiver line status interrupt (IER\[2\]) pub fn disable_receiver_line_status_interrupt(&self) { - self.set_ier(self.ier() & !IER::RLSI) + self.reg.ier_dlh.modify(IER::RLSI::CLEAR) } /// get whether transmitter holding register empty interrupt is enabled (IER\[1\]) pub fn is_transmitter_holding_register_empty_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::THREI) + self.reg.ier_dlh.is_set(IER::THREI) } /// enable transmitter holding register empty interrupt (IER\[1\]) pub fn enable_transmitter_holding_register_empty_interrupt(&self) { - self.set_ier(self.ier() | IER::THREI) + self.reg.ier_dlh.modify(IER::THREI::SET) } /// disable transmitter holding register empty interrupt (IER\[1\]) pub fn disable_transmitter_holding_register_empty_interrupt(&self) { - self.set_ier(self.ier() & !IER::THREI) + self.reg.ier_dlh.modify(IER::THREI::CLEAR) } /// get whether received data available is enabled (IER\[0\]) pub fn is_received_data_available_interrupt_enabled(&self) -> bool { - self.ier().contains(IER::RDAI) + self.reg.ier_dlh.is_set(IER::RDAI) } /// enable received data available (IER\[0\]) pub fn enable_received_data_available_interrupt(&self) { - self.set_ier(self.ier() | IER::RDAI) + self.reg.ier_dlh.modify(IER::RDAI::SET); } /// disable received data available (IER\[0\]) pub fn disable_received_data_available_interrupt(&self) { - self.set_ier(self.ier() & !IER::RDAI) + self.reg.ier_dlh.modify(IER::RDAI::CLEAR); } /// Read IIR\[7:6\] to get FIFO status pub fn read_fifo_status(&self) -> ChipFifoInfo { - match self.reg.read_iir() & 0b1100_0000 { - 0 => ChipFifoInfo::NoFifo, - 0b0100_0000 => ChipFifoInfo::Reserved, - 0b1000_0000 => ChipFifoInfo::EnabledNoFunction, - 0b1100_0000 => ChipFifoInfo::Enabled, - _ => panic!("Can't reached"), + match self.reg.iir_fcr.read_as_enum(IIR::FifoInfo) { + Some(IIR::FifoInfo::Value::None) => ChipFifoInfo::NoFifo, + Some(IIR::FifoInfo::Value::EnabledNotFunctioning) => ChipFifoInfo::EnabledNoFunction, + Some(IIR::FifoInfo::Value::Enabled) => ChipFifoInfo::Enabled, + None => ChipFifoInfo::Reserved, } } /// get whether 64 Byte fifo (16750 only) is enabled (IIR\[5\]) pub fn is_64byte_fifo_enabled(&self) -> bool { - self.reg.read_iir() & 0b0010_0000 != 0 + self.reg.iir_fcr.is_set(IIR::Fifo64Byte) } /// Read IIR\[3:1\] to get interrupt type pub fn read_interrupt_type(&self) -> Option { - let iir = self.reg.read_iir() & 0b0000_1111; - if iir & 1 != 0 { + let iir = self.reg.iir_fcr.extract(); + if iir.is_set(IIR::InterruptPending) { None } else { - match iir { - 0b0000 => Some(InterruptType::ModemStatus), - 0b0010 => Some(InterruptType::TransmitterHoldingRegisterEmpty), - 0b0100 => Some(InterruptType::ReceivedDataAvailable), - 0b0110 => Some(InterruptType::ReceiverLineStatus), - 0b1100 => Some(InterruptType::Timeout), - 0b1000 | 0b1010 | 0b1110 => Some(InterruptType::Reserved), - _ => panic!("Can't reached"), + match iir.read_as_enum(IIR::InterruptType) { + Some(IIR::InterruptType::Value::ModemStatus) => Some(InterruptType::ModemStatus), + Some(IIR::InterruptType::Value::TransmitterHoldingRegisterEmpty) => { + Some(InterruptType::TransmitterHoldingRegisterEmpty) + } + Some(IIR::InterruptType::Value::ReceivedDataAvailable) => { + Some(InterruptType::ReceivedDataAvailable) + } + Some(IIR::InterruptType::Value::ReceiverLineStatus) => { + Some(InterruptType::ReceiverLineStatus) + } + Some(IIR::InterruptType::Value::Timeout) => Some(InterruptType::Timeout), + None => Some(InterruptType::Reserved), } } } @@ -451,7 +442,7 @@ impl<'a> MmioUart8250<'a> { .read_as_enum(LCR::Parity) .expect("Invalid Parity! Please check your UART.") { - LCR::Parity::Value::None => Parity::No, + LCR::Parity::Value::No => Parity::No, LCR::Parity::Value::Odd => Parity::Odd, LCR::Parity::Value::Even => Parity::Even, LCR::Parity::Value::Mark => Parity::Mark, @@ -462,7 +453,7 @@ impl<'a> MmioUart8250<'a> { /// set parity pub fn set_parity(&self, parity: Parity) { let parity = match parity { - Parity::No => LCR::Parity::None, + Parity::No => LCR::Parity::No, Parity::Odd => LCR::Parity::Odd, Parity::Even => LCR::Parity::Even, Parity::Mark => LCR::Parity::Mark, @@ -475,7 +466,7 @@ impl<'a> MmioUart8250<'a> { /// /// Simply return a u8 to indicate 1 or 1.5/2 bits pub fn get_stop_bit(&self) -> u8 { - ((self.reg.read_lcr() & 0b100) >> 2) + 1 + self.reg.lcr.read(LCR::STOP_BITS) + 1 } /// set stop bit, only 1 and 2 can be used as `stop_bit` @@ -503,8 +494,8 @@ impl<'a> MmioUart8250<'a> { /// Sets FCR bitflags #[inline] - pub fn set_fcr(&self, fcr: FCR) { - self.reg.write_fcr(fcr.bits()) + pub fn set_fcr(&self, fcr: FieldValue) { + self.reg.iir_fcr.write(fcr) } /// Gets LCR bitflags @@ -521,95 +512,83 @@ impl<'a> MmioUart8250<'a> { /// Gets MCR bitflags #[inline] - pub fn mcr(&self) -> MCR { - MCR::from_bits_truncate(self.reg.read_mcr()) + pub fn mcr(&self) -> LocalRegisterCopy { + self.reg.mcr.extract() } /// Sets MCR bitflags #[inline] - pub fn set_mcr(&self, mcr: MCR) { - self.reg.write_mcr(mcr.bits()) - } - - /// Get LSR bitflags - #[inline] - fn lsr(&self) -> LSR { - LSR::from_bits_truncate(self.reg.read_lsr()) + pub fn set_mcr(&self, mcr: FieldValue) { + self.reg.mcr.write(mcr) } /// get whether there is an error in received FIFO pub fn is_received_fifo_error(&self) -> bool { - self.lsr().contains(LSR::RFE) + self.reg.lsr.is_set(LSR::RFE) } /// Gets whether data holding registers are empty, i.e. the UART has finished transmitting all /// the data it has been given. pub fn is_data_holding_registers_empty(&self) -> bool { - self.lsr().contains(LSR::DHRE) + self.reg.lsr.is_set(LSR::DHRE) } /// Gets whether transmitter holding register is empty, i.e. the UART is ready to be given more /// data to transmit. pub fn is_transmitter_holding_register_empty(&self) -> bool { - self.lsr().contains(LSR::THRE) + self.reg.lsr.is_set(LSR::THRE) } pub fn is_break_interrupt(&self) -> bool { - self.lsr().contains(LSR::BI) + self.reg.lsr.is_set(LSR::BI) } pub fn is_framing_error(&self) -> bool { - self.lsr().contains(LSR::FE) + self.reg.lsr.is_set(LSR::FE) } pub fn is_parity_error(&self) -> bool { - self.lsr().contains(LSR::PE) + self.reg.lsr.is_set(LSR::PE) } pub fn is_overrun_error(&self) -> bool { - self.lsr().contains(LSR::OE) + self.reg.lsr.is_set(LSR::OE) } pub fn is_data_ready(&self) -> bool { - self.lsr().contains(LSR::DR) - } - - /// Get MSR bitflags - #[inline] - fn msr(&self) -> MSR { - MSR::from_bits_truncate(self.reg.read_msr()) + self.reg.lsr.is_set(LSR::DR) } pub fn is_carrier_detect(&self) -> bool { - self.msr().contains(MSR::CD) + self.reg.msr.is_set(MSR::CD) } pub fn is_ring_indicator(&self) -> bool { - self.msr().contains(MSR::RI) + self.reg.msr.is_set(MSR::RI) } pub fn is_data_set_ready(&self) -> bool { - self.msr().contains(MSR::DSR) + self.reg.msr.is_set(MSR::DSR) } pub fn is_clear_to_send(&self) -> bool { - self.msr().contains(MSR::CTS) + self.reg.msr.is_set(MSR::CTS) } pub fn is_delta_data_carrier_detect(&self) -> bool { - self.msr().contains(MSR::DDCD) + self.reg.msr.is_set(MSR::DDCD) } pub fn is_trailing_edge_ring_indicator(&self) -> bool { - self.msr().contains(MSR::TERI) + self.reg.msr.is_set(MSR::TERI) } pub fn is_delta_data_set_ready(&self) -> bool { - self.msr().contains(MSR::DDSR) + self.reg.msr.is_set(MSR::DDSR) } pub fn is_delta_clear_to_send(&self) -> bool { - self.msr().contains(MSR::DCTS) + self.reg.msr.is_set(MSR::DCTS) } } From 15f58020a2bdd0fae444bae096a65ab700fd673e Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 13:22:29 +0100 Subject: [PATCH 06/10] Export tock-registers enums directly rather than mapping them. --- uart8250/src/uart.rs | 76 ++++++++------------------------------------ 1 file changed, 13 insertions(+), 63 deletions(-) diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index ab31877..f088e5a 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -137,6 +137,8 @@ register_bitfields![ FifoInfo OFFSET(6) NUMBITS(2) [ /// No FIFO on chip. None = 0, + /// Reserved value. + Reserved = 1, /// FIFO enabled but not functioning. EnabledNotFunctioning = 2, /// FIFO enabled. @@ -149,6 +151,7 @@ register_bitfields![ TransmitterHoldingRegisterEmpty = 1, ReceivedDataAvailable = 2, ReceiverLineStatus = 3, + Reserved = 4, Timeout = 6, ], /// Interrupt pending flag. @@ -172,32 +175,9 @@ register_bitfields![ ], ]; -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum ChipFifoInfo { - NoFifo, - Reserved, - EnabledNoFunction, - Enabled, -} - -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum InterruptType { - ModemStatus, - TransmitterHoldingRegisterEmpty, - ReceivedDataAvailable, - ReceiverLineStatus, - Timeout, - Reserved, -} - -#[derive(Copy, Clone, Debug, Eq, PartialEq)] -pub enum Parity { - No, - Odd, - Even, - Mark, - Space, -} +pub type ChipFifoInfo = IIR::FifoInfo::Value; +pub type InterruptType = IIR::InterruptType::Value; +pub type Parity = LCR::Parity::Value; /// An error encountered which trying to transmit data. #[derive(Copy, Clone, Debug, Eq, PartialEq)] @@ -388,12 +368,7 @@ impl<'a> MmioUart8250<'a> { /// Read IIR\[7:6\] to get FIFO status pub fn read_fifo_status(&self) -> ChipFifoInfo { - match self.reg.iir_fcr.read_as_enum(IIR::FifoInfo) { - Some(IIR::FifoInfo::Value::None) => ChipFifoInfo::NoFifo, - Some(IIR::FifoInfo::Value::EnabledNotFunctioning) => ChipFifoInfo::EnabledNoFunction, - Some(IIR::FifoInfo::Value::Enabled) => ChipFifoInfo::Enabled, - None => ChipFifoInfo::Reserved, - } + self.reg.iir_fcr.read_as_enum(IIR::FifoInfo).unwrap() } /// get whether 64 Byte fifo (16750 only) is enabled (IIR\[5\]) @@ -407,20 +382,10 @@ impl<'a> MmioUart8250<'a> { if iir.is_set(IIR::InterruptPending) { None } else { - match iir.read_as_enum(IIR::InterruptType) { - Some(IIR::InterruptType::Value::ModemStatus) => Some(InterruptType::ModemStatus), - Some(IIR::InterruptType::Value::TransmitterHoldingRegisterEmpty) => { - Some(InterruptType::TransmitterHoldingRegisterEmpty) - } - Some(IIR::InterruptType::Value::ReceivedDataAvailable) => { - Some(InterruptType::ReceivedDataAvailable) - } - Some(IIR::InterruptType::Value::ReceiverLineStatus) => { - Some(InterruptType::ReceiverLineStatus) - } - Some(IIR::InterruptType::Value::Timeout) => Some(InterruptType::Timeout), - None => Some(InterruptType::Reserved), - } + Some( + iir.read_as_enum(IIR::InterruptType) + .unwrap_or(IIR::InterruptType::Value::Reserved), + ) } } @@ -436,30 +401,15 @@ impl<'a> MmioUart8250<'a> { /// get parity of used data protocol pub fn get_parity(&self) -> Parity { - match self - .reg + self.reg .lcr .read_as_enum(LCR::Parity) .expect("Invalid Parity! Please check your UART.") - { - LCR::Parity::Value::No => Parity::No, - LCR::Parity::Value::Odd => Parity::Odd, - LCR::Parity::Value::Even => Parity::Even, - LCR::Parity::Value::Mark => Parity::Mark, - LCR::Parity::Value::Space => Parity::Space, - } } /// set parity pub fn set_parity(&self, parity: Parity) { - let parity = match parity { - Parity::No => LCR::Parity::No, - Parity::Odd => LCR::Parity::Odd, - Parity::Even => LCR::Parity::Even, - Parity::Mark => LCR::Parity::Mark, - Parity::Space => LCR::Parity::Space, - }; - self.reg.lcr.modify(parity); + self.reg.lcr.modify(LCR::Parity.val(parity as u8)); } /// get stop bit of used data protocol From d7a05f663375ec31d21ed53644f18f870d1fac97 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 13:32:08 +0100 Subject: [PATCH 07/10] Move register bitfield definitions to registers module. --- uart8250/src/registers.rs | 169 ++++++++++++++++++++++++++++++++++++- uart8250/src/uart.rs | 170 +------------------------------------- 2 files changed, 169 insertions(+), 170 deletions(-) diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index cc1f8b8..e3c3bb7 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -1,8 +1,7 @@ -use crate::uart::{FCR, IER, IIR, LCR, LSR, MCR, MSR}; use core::u8; use tock_registers::{ interfaces::{Readable, Writeable}, - register_structs, + register_bitfields, register_structs, registers::{Aliased, ReadOnly, ReadWrite}, }; @@ -40,6 +39,172 @@ register_structs! { } } +register_bitfields![ + u8, + + /// Interrupt Enable Register + pub IER [ + /// Enable Received Data Available Interrupt + RDAI OFFSET(0) NUMBITS(1) [], + /// Enable Transmitter Holding Register Empty Interrupt + THREI OFFSET(1) NUMBITS(1) [], + /// Enable Receiver Line Status Interrupt + RLSI OFFSET(2) NUMBITS(1) [], + /// Enable Modem Status Interrupt + MSI OFFSET(3) NUMBITS(1) [], + /// Enable Sleep Mode (16750) + SM OFFSET(4) NUMBITS(1) [], + /// Enable Low Power Mode (16750) + LPM OFFSET(5) NUMBITS(1) [], + ], + + /// Line Control Register + pub LCR [ + /// Divisor Latch Access Bit + DLAB OFFSET(7) NUMBITS(1) [], + /// Set Break Enable + SBE OFFSET(6) NUMBITS(1) [], + /// Parity + Parity OFFSET(3) NUMBITS(3) [ + /// No parity + No = 0, + /// Odd parity + Odd = 1, + /// Even parity + Even = 3, + /// Mark + Mark = 5, + /// Space + Space = 7, + ], + /// Number of stop bits + STOP_BITS OFFSET(2) NUMBITS(1) [ + /// One stop bit + One = 0, + /// 1.5 or 2 stop bits + Two = 1, + ], + /// Word length + WORD_LENGTH OFFSET(0) NUMBITS(2) [ + /// 5 bit word length + Bits5 = 0, + /// 6 bit word length + Bits6 = 1, + /// 7 bit word length + Bits7 = 2, + /// 8 bit word length + Bits8 = 3, + ], + ], + + /// Line Status Register + pub LSR [ + /// Data Ready + DR OFFSET(0) NUMBITS(1) [], + /// Overrun Error + OE OFFSET(1) NUMBITS(1) [], + /// Parity Error + PE OFFSET(2) NUMBITS(1) [], + /// Framing Error + FE OFFSET(3) NUMBITS(1) [], + /// Break Interrupt + BI OFFSET(4) NUMBITS(1) [], + /// Transmitter Holding Register Empty + THRE OFFSET(5) NUMBITS(1) [], + /// Data Holding Regiters Empty + DHRE OFFSET(6) NUMBITS(1) [], + /// Error in Received FIFO + RFE OFFSET(7) NUMBITS(1) [], + ], + + /// Modem Status Register + pub MSR [ + /// Delta Clear To Send + DCTS OFFSET(0) NUMBITS(1) [], + /// Delta Data Set Ready + DDSR OFFSET(1) NUMBITS(1) [], + /// Trailing Edge Ring Indicator + TERI OFFSET(2) NUMBITS(1) [], + /// Delta Data Carrier Detect + DDCD OFFSET(3) NUMBITS(1) [], + /// Clear To Send + CTS OFFSET(4) NUMBITS(1) [], + /// Data Set Ready + DSR OFFSET(5) NUMBITS(1) [], + /// Ring Indicator + RI OFFSET(6) NUMBITS(1) [], + /// Carrier Detect + CD OFFSET(7) NUMBITS(1) [], + ], + + /// FIFO Control Register + pub FCR [ + /// Interrupt trigger level. + InterruptTriggerLevel OFFSET(6) NUMBITS(2) [ + /// Interrupt trigger level is 1 byte. + Bytes1 = 0, + /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. + Bytes4Or16 = 1, + /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. + Bytes8Or32 = 2, + /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. + Bytes14Or56 = 3, + ], + /// Enable 64 byte FIFO (16750) + Enable64Byte OFFSET(5) NUMBITS(1) [], + /// DMA mode select + DmaMode OFFSET(3) NUMBITS(1) [], + /// Clear transmit FIFO + ClearTx OFFSET(2) NUMBITS(1) [], + /// Clear receive FIFO + ClearRx OFFSET(1) NUMBITS(1) [], + /// Enable FIFOs. + Enable OFFSET(0) NUMBITS(1) [], + ], + + /// Interrupt Identification Register + pub IIR [ + FifoInfo OFFSET(6) NUMBITS(2) [ + /// No FIFO on chip. + None = 0, + /// Reserved value. + Reserved = 1, + /// FIFO enabled but not functioning. + EnabledNotFunctioning = 2, + /// FIFO enabled. + Enabled = 3, + ], + /// 64 byte FIFO enabled (16750 only). + Fifo64Byte OFFSET(5) NUMBITS(1) [], + InterruptType OFFSET(1) NUMBITS(3) [ + ModemStatus = 0, + TransmitterHoldingRegisterEmpty = 1, + ReceivedDataAvailable = 2, + ReceiverLineStatus = 3, + Reserved = 4, + Timeout = 6, + ], + /// Interrupt pending flag. + InterruptPending OFFSET(0) NUMBITS(1) [], + ], + + /// Modem Control Register (bitflags) + pub MCR [ + /// Autoflow control enabled (16750) + AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [], + /// Loopback mode + LOOPBACK_MODE OFFSET(4) NUMBITS(1) [], + /// Auxiliary output 2 + AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [], + /// Auxiliary output 1 + AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [], + /// Request to Send + RTS OFFSET(1) NUMBITS(1) [], + /// Data Terminal Ready + DTR OFFSET(0) NUMBITS(1) [], + ], +]; + impl Registers { /// Constructs a new instance of the UART registers starting at the given base address. pub unsafe fn from_base_address(base_address: usize) -> &'static mut Self { diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index f088e5a..aea2b15 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -4,176 +4,10 @@ use core::fmt::{self, Display, Formatter}; use tock_registers::{ fields::FieldValue, interfaces::{ReadWriteable, Readable, Writeable}, - register_bitfields, LocalRegisterCopy, + LocalRegisterCopy, }; -use crate::registers::Registers; - -register_bitfields![ - u8, - - /// Interrupt Enable Register - pub IER [ - /// Enable Received Data Available Interrupt - RDAI OFFSET(0) NUMBITS(1) [], - /// Enable Transmitter Holding Register Empty Interrupt - THREI OFFSET(1) NUMBITS(1) [], - /// Enable Receiver Line Status Interrupt - RLSI OFFSET(2) NUMBITS(1) [], - /// Enable Modem Status Interrupt - MSI OFFSET(3) NUMBITS(1) [], - /// Enable Sleep Mode (16750) - SM OFFSET(4) NUMBITS(1) [], - /// Enable Low Power Mode (16750) - LPM OFFSET(5) NUMBITS(1) [], - ], - - /// Line Control Register - pub LCR [ - /// Divisor Latch Access Bit - DLAB OFFSET(7) NUMBITS(1) [], - /// Set Break Enable - SBE OFFSET(6) NUMBITS(1) [], - /// Parity - Parity OFFSET(3) NUMBITS(3) [ - /// No parity - No = 0, - /// Odd parity - Odd = 1, - /// Even parity - Even = 3, - /// Mark - Mark = 5, - /// Space - Space = 7, - ], - /// Number of stop bits - STOP_BITS OFFSET(2) NUMBITS(1) [ - /// One stop bit - One = 0, - /// 1.5 or 2 stop bits - Two = 1, - ], - /// Word length - WORD_LENGTH OFFSET(0) NUMBITS(2) [ - /// 5 bit word length - Bits5 = 0, - /// 6 bit word length - Bits6 = 1, - /// 7 bit word length - Bits7 = 2, - /// 8 bit word length - Bits8 = 3, - ], - ], - - /// Line Status Register - pub LSR [ - /// Data Ready - DR OFFSET(0) NUMBITS(1) [], - /// Overrun Error - OE OFFSET(1) NUMBITS(1) [], - /// Parity Error - PE OFFSET(2) NUMBITS(1) [], - /// Framing Error - FE OFFSET(3) NUMBITS(1) [], - /// Break Interrupt - BI OFFSET(4) NUMBITS(1) [], - /// Transmitter Holding Register Empty - THRE OFFSET(5) NUMBITS(1) [], - /// Data Holding Regiters Empty - DHRE OFFSET(6) NUMBITS(1) [], - /// Error in Received FIFO - RFE OFFSET(7) NUMBITS(1) [], - ], - - /// Modem Status Register - pub MSR [ - /// Delta Clear To Send - DCTS OFFSET(0) NUMBITS(1) [], - /// Delta Data Set Ready - DDSR OFFSET(1) NUMBITS(1) [], - /// Trailing Edge Ring Indicator - TERI OFFSET(2) NUMBITS(1) [], - /// Delta Data Carrier Detect - DDCD OFFSET(3) NUMBITS(1) [], - /// Clear To Send - CTS OFFSET(4) NUMBITS(1) [], - /// Data Set Ready - DSR OFFSET(5) NUMBITS(1) [], - /// Ring Indicator - RI OFFSET(6) NUMBITS(1) [], - /// Carrier Detect - CD OFFSET(7) NUMBITS(1) [], - ], - - /// FIFO Control Register - pub FCR [ - /// Interrupt trigger level. - InterruptTriggerLevel OFFSET(6) NUMBITS(2) [ - /// Interrupt trigger level is 1 byte. - Bytes1 = 0, - /// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively. - Bytes4Or16 = 1, - /// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively. - Bytes8Or32 = 2, - /// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively. - Bytes14Or56 = 3, - ], - /// Enable 64 byte FIFO (16750) - Enable64Byte OFFSET(5) NUMBITS(1) [], - /// DMA mode select - DmaMode OFFSET(3) NUMBITS(1) [], - /// Clear transmit FIFO - ClearTx OFFSET(2) NUMBITS(1) [], - /// Clear receive FIFO - ClearRx OFFSET(1) NUMBITS(1) [], - /// Enable FIFOs. - Enable OFFSET(0) NUMBITS(1) [], - ], - - /// Interrupt Identification Register - pub IIR [ - FifoInfo OFFSET(6) NUMBITS(2) [ - /// No FIFO on chip. - None = 0, - /// Reserved value. - Reserved = 1, - /// FIFO enabled but not functioning. - EnabledNotFunctioning = 2, - /// FIFO enabled. - Enabled = 3, - ], - /// 64 byte FIFO enabled (16750 only). - Fifo64Byte OFFSET(5) NUMBITS(1) [], - InterruptType OFFSET(1) NUMBITS(3) [ - ModemStatus = 0, - TransmitterHoldingRegisterEmpty = 1, - ReceivedDataAvailable = 2, - ReceiverLineStatus = 3, - Reserved = 4, - Timeout = 6, - ], - /// Interrupt pending flag. - InterruptPending OFFSET(0) NUMBITS(1) [], - ], - - /// Modem Control Register (bitflags) - pub MCR [ - /// Autoflow control enabled (16750) - AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [], - /// Loopback mode - LOOPBACK_MODE OFFSET(4) NUMBITS(1) [], - /// Auxiliary output 2 - AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [], - /// Auxiliary output 1 - AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [], - /// Request to Send - RTS OFFSET(1) NUMBITS(1) [], - /// Data Terminal Ready - DTR OFFSET(0) NUMBITS(1) [], - ], -]; +use crate::registers::{Registers, FCR, IER, IIR, LCR, LSR, MCR, MSR}; pub type ChipFifoInfo = IIR::FifoInfo::Value; pub type InterruptType = IIR::InterruptType::Value; From 2b2deafe333f5043f14f722fa1d04a2875aca593 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 14:42:38 +0100 Subject: [PATCH 08/10] Remove some methods from public interface. Clients should not need to access registers directly; if they need functionality which is not currently exposed then it should be added to this crate. Also removed register access methods, as they didn't really add anything. --- uart8250/src/registers.rs | 45 +--------------------- uart8250/src/uart.rs | 78 +++++++++++++++++++-------------------- 2 files changed, 40 insertions(+), 83 deletions(-) diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index e3c3bb7..c48ebca 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -1,6 +1,5 @@ use core::u8; use tock_registers::{ - interfaces::{Readable, Writeable}, register_bitfields, register_structs, registers::{Aliased, ReadOnly, ReadWrite}, }; @@ -27,14 +26,14 @@ register_structs! { /// | +6 | x | Read | MSR | Modem Status Register | /// | +7 | x | Read/Write | SR | Scratch Register | pub Registers { - (0x00 => thr_rbr_dll: ReadWrite), + (0x00 => pub thr_rbr_dll: ReadWrite), (0x01 => pub ier_dlh: ReadWrite), (0x02 => pub iir_fcr: Aliased), (0x03 => pub lcr: ReadWrite), (0x04 => pub mcr: ReadWrite), (0x05 => pub lsr: ReadOnly), (0x06 => pub msr: ReadOnly), - (0x07 => scratch: ReadWrite), + (0x07 => pub scratch: ReadWrite), (0x08 => @END), } } @@ -210,44 +209,4 @@ impl Registers { pub unsafe fn from_base_address(base_address: usize) -> &'static mut Self { &mut *(base_address as *mut crate::registers::Registers) } - - /// write THR (offset + 0) - /// - /// Write Transmitter Holding Buffer to send data - /// - /// > ## Transmitter Holding Buffer/Receiver Buffer - /// > - /// > Offset: +0 . The Transmit and Receive buffers are related, and often even use the very same memory. This is also one of the areas where later versions of the 8250 chip have a significant impact, as the later models incorporate some internal buffering of the data within the chip before it gets transmitted as serial data. The base 8250 chip can only receive one byte at a time, while later chips like the 16550 chip will hold up to 16 bytes either to transmit or to receive (sometimes both... depending on the manufacturer) before you have to wait for the character to be sent. This can be useful in multi-tasking environments where you have a computer doing many things, and it may be a couple of milliseconds before you get back to dealing with serial data flow. - /// > - /// > These registers really are the "heart" of serial data communication, and how data is transferred from your software to another computer and how it gets data from other devices. Reading and Writing to these registers is simply a matter of accessing the Port I/O address for the respective UART. - /// > - /// > If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register. - #[inline] - pub fn write_thr(&self, value: u8) { - self.thr_rbr_dll.set(value) - } - - /// read RBR (offset + 0) - /// - /// Read Receiver Buffer to get data - #[inline] - pub fn read_rbr(&self) -> u8 { - self.thr_rbr_dll.get() - } - - /// write DLL (offset + 0) - /// - /// set divisor latch low byte in the register - #[inline] - pub fn write_dll(&self, value: u8) { - self.thr_rbr_dll.set(value) - } - - /// write DLH (offset + 1) - /// - /// set divisor latch high byte in the register - #[inline] - pub fn write_dlh(&self, value: u8) { - self.ier_dlh.set(value) - } } diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index aea2b15..1d24b3f 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -4,10 +4,9 @@ use core::fmt::{self, Display, Formatter}; use tock_registers::{ fields::FieldValue, interfaces::{ReadWriteable, Readable, Writeable}, - LocalRegisterCopy, }; -use crate::registers::{Registers, FCR, IER, IIR, LCR, LSR, MCR, MSR}; +use crate::registers::{Registers, FCR, IER, IIR, LCR, LSR, MSR}; pub type ChipFifoInfo = IIR::FifoInfo::Value; pub type InterruptType = IIR::InterruptType::Value; @@ -57,11 +56,13 @@ impl<'a> MmioUart8250<'a> { self.set_divisor(clock, baud_rate); // Disable DLAB and set word length 8 bits, no parity, 1 stop bit - self.set_lcr(LCR::Parity::No + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); + self.reg + .lcr + .write(LCR::Parity::No + LCR::STOP_BITS::One + LCR::WORD_LENGTH::Bits8); // Enable FIFO - self.set_fcr(FCR::Enable::SET); + self.reg.iir_fcr.write(FCR::Enable::SET); // No modem control - self.set_mcr(FieldValue::::new(0, 0, 0)); + self.reg.mcr.write(FieldValue::::new(0, 0, 0)); // Enable received_data_available_interrupt self.enable_received_data_available_interrupt(); // Enable transmitter_holding_register_empty_interrupt @@ -84,7 +85,7 @@ impl<'a> MmioUart8250<'a> { /// Returns `None` when data is not ready (RBR\[0\] != 1) pub fn read_byte(&self) -> Option { if self.is_data_ready() { - Some(self.reg.read_rbr()) + Some(self.reg.thr_rbr_dll.get()) } else { None } @@ -93,20 +94,47 @@ impl<'a> MmioUart8250<'a> { /// Writes a byte to the UART. pub fn write_byte(&self, byte: u8) -> Result<(), TransmitError> { if self.is_transmitter_holding_register_empty() { - self.reg.write_thr(byte); + self.reg.thr_rbr_dll.set(byte); Ok(()) } else { Err(TransmitError::BufferFull) } } - /// Set divisor latch according to clock and baud_rate, then set DLAB to false + /// Sets DLAB to true, sets divisor latch according to clock and baud_rate, then sets DLAB to + /// false. + /// + /// > ## Divisor Latch Bytes + /// > + /// > Offset: +0 and +1 . The Divisor Latch Bytes are what control the baud rate of the modem. As you might guess from the name of this register, it is used as a divisor to determine what baud rate that the chip is going to be transmitting at. + /// + /// Used clock 1.8432 MHz as example, first divide 16 and get 115200. Then use the formula to get divisor latch value: + /// + /// *DivisorLatchValue = 115200 / BaudRate* + /// + /// This gives the following table: + /// + /// | Baud Rate | Divisor (in decimal) | Divisor Latch High Byte | Divisor Latch Low Byte | + /// | --------- | -------------------- | ----------------------- | ---------------------- | + /// | 50 | 2304 | $09 | $00 | + /// | 110 | 1047 | $04 | $17 | + /// | 220 | 524 | $02 | $0C | + /// | 300 | 384 | $01 | $80 | + /// | 600 | 192 | $00 | $C0 | + /// | 1200 | 96 | $00 | $60 | + /// | 2400 | 48 | $00 | $30 | + /// | 4800 | 24 | $00 | $18 | + /// | 9600 | 12 | $00 | $0C | + /// | 19200 | 6 | $00 | $06 | + /// | 38400 | 3 | $00 | $03 | + /// | 57600 | 2 | $00 | $02 | + /// | 115200 | 1 | $00 | $01 | #[inline] pub fn set_divisor(&self, clock: usize, baud_rate: usize) { self.enable_divisor_latch_accessible(); let divisor = clock / (16 * baud_rate); - self.reg.write_dll(divisor as u8); - self.reg.write_dlh((divisor >> 8) as u8); + self.reg.thr_rbr_dll.set(divisor as u8); + self.reg.ier_dlh.set((divisor >> 8) as u8); self.disable_divisor_latch_accessible(); } @@ -276,36 +304,6 @@ impl<'a> MmioUart8250<'a> { } } - /// Sets FCR bitflags - #[inline] - pub fn set_fcr(&self, fcr: FieldValue) { - self.reg.iir_fcr.write(fcr) - } - - /// Gets LCR bitflags - #[inline] - pub fn lcr(&self) -> LocalRegisterCopy { - self.reg.lcr.extract() - } - - /// Sets LCR bitflags - #[inline] - pub fn set_lcr(&self, lcr: FieldValue) { - self.reg.lcr.write(lcr) - } - - /// Gets MCR bitflags - #[inline] - pub fn mcr(&self) -> LocalRegisterCopy { - self.reg.mcr.extract() - } - - /// Sets MCR bitflags - #[inline] - pub fn set_mcr(&self, mcr: FieldValue) { - self.reg.mcr.write(mcr) - } - /// get whether there is an error in received FIFO pub fn is_received_fifo_error(&self) -> bool { self.reg.lsr.is_set(LSR::RFE) From 8c432837af85835796a8ddae21672fe4e12746ba Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 15:53:33 +0100 Subject: [PATCH 09/10] Fix typo. --- uart8250/src/registers.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uart8250/src/registers.rs b/uart8250/src/registers.rs index c48ebca..a934aeb 100644 --- a/uart8250/src/registers.rs +++ b/uart8250/src/registers.rs @@ -110,7 +110,7 @@ register_bitfields![ BI OFFSET(4) NUMBITS(1) [], /// Transmitter Holding Register Empty THRE OFFSET(5) NUMBITS(1) [], - /// Data Holding Regiters Empty + /// Data Holding Registers Empty DHRE OFFSET(6) NUMBITS(1) [], /// Error in Received FIFO RFE OFFSET(7) NUMBITS(1) [], From 42bce6f2f5831fcc6101fdebf0f40853005b6f12 Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Wed, 6 Apr 2022 16:06:34 +0100 Subject: [PATCH 10/10] Set DLAB directly. --- uart8250/src/uart.rs | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/uart8250/src/uart.rs b/uart8250/src/uart.rs index 1d24b3f..c1a3d99 100644 --- a/uart8250/src/uart.rs +++ b/uart8250/src/uart.rs @@ -131,11 +131,15 @@ impl<'a> MmioUart8250<'a> { /// | 115200 | 1 | $00 | $01 | #[inline] pub fn set_divisor(&self, clock: usize, baud_rate: usize) { - self.enable_divisor_latch_accessible(); + // Enable DLAB. + self.reg.lcr.modify(LCR::DLAB::SET); + let divisor = clock / (16 * baud_rate); self.reg.thr_rbr_dll.set(divisor as u8); self.reg.ier_dlh.set((divisor >> 8) as u8); - self.disable_divisor_latch_accessible(); + + // Disable DLAB. + self.reg.lcr.modify(LCR::DLAB::CLEAR); } /// get whether low power mode (16750) is enabled (IER\[5\]) @@ -251,16 +255,6 @@ impl<'a> MmioUart8250<'a> { } } - /// enable DLAB - fn enable_divisor_latch_accessible(&self) { - self.reg.lcr.modify(LCR::DLAB::SET) - } - - /// disable DLAB - fn disable_divisor_latch_accessible(&self) { - self.reg.lcr.modify(LCR::DLAB::CLEAR) - } - /// get parity of used data protocol pub fn get_parity(&self) -> Parity { self.reg