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Design PU for lookup table #172

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ryukzak opened this issue Jul 28, 2021 · 0 comments
Open
3 tasks

Design PU for lookup table #172

ryukzak opened this issue Jul 28, 2021 · 0 comments
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enhancement New feature or request hs Haskell v Verilog

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@ryukzak
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ryukzak commented Jul 28, 2021

Many applicationы of nitta require performing mathematical functions from one argument like sqrt, sin, cos, etc. We can perform them in hardware, but also we can do it by making a lookup table.

For that purpose, we need to design a specific processor unit with a lookup table inside.

For that, we need:

  • Design hardware of PU (shifts and masks of input data for different functions and how to do it in a programmable way), how many signals we need for that, should we use external memory for it
  • Design application-level functions with control over precisions of functions (actually, we can not store data for 32 bits of input data), e.g., how many informative bits we take from input and how many to output, how to round them
  • Design PU model, which should not only scheduling process but also prepare specific configuration

Notes:

  • Maybe, preparing input/output data of lookup table can be implemented in other PU (shift or mask PU)
  • Number of signals for table selection can be dependent on an algorithm or restricted by microarchitecture
@ryukzak ryukzak added enhancement New feature or request hs Haskell v Verilog labels Jul 28, 2021
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enhancement New feature or request hs Haskell v Verilog
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