Multiple SPIs lead to errors

[BasicEC]

Steps to reproduse:

1. Define two SPI for busnetwork in Main.hs:

defMicroarch ioSync = defineNetwork "net1" ioSync $ do
    addCustom "fram1" (framWithSize 16) FramIO
    addCustom "fram2" (framWithSize 32) FramIO
    add "shift" ShiftIO
    add "mul" MultiplierIO
    add "accum" AccumIO
    add "div" DividerIO
    add "spi" $
        SPISlave
            { slave_mosi = InputPortTag "mosi"
            , slave_miso = OutputPortTag "miso"
            , slave_sclk = InputPortTag "sclk"
            , slave_cs = InputPortTag "cs"
            }
    add "r_spi" $
        SPISlave
            { slave_mosi = InputPortTag "r_mosi"
            , slave_miso = OutputPortTag "r_miso"
            , slave_sclk = InputPortTag "r_sclk"
            , slave_cs = InputPortTag "r_cs"
            }

2. run example

$ stack build
$ stack exec nitta -- examples/teacup.lua -p=8080

3. Complete synthesis and go to the testbench tab: