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Copy pathhet.cfg
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het.cfg
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// This system is similar to a 6-core, 2.4GHz Westmere with 10 Niagara-like cores attached to the L3
sys = {
lineSize = 64;
frequency = 2400;
cores = {
beefy = {
type = "OOO";
cores = 6;
icache = "l1i_beefy";
dcache = "l1d_beefy";
};
wimpy = {
type = "Simple";
cores = 10;
icache = "l1i_wimpy";
dcache = "l1d_wimpy";
};
};
caches = {
l1d_beefy = {
caches = 6;
size = 32768;
array = {
type = "SetAssoc";
ways = 8;
};
latency = 4;
};
l1i_beefy = {
caches = 6;
size = 32768;
array = {
type = "SetAssoc";
ways = 4;
};
latency = 3;
};
l2_beefy = {
caches = 6;
size = 262144;
latency = 7;
array = {
type = "SetAssoc";
ways = 8;
};
children = "l1i_beefy|l1d_beefy";
};
l1d_wimpy = {
caches = 10;
size = 8192;
latency = 2;
array = {
type = "SetAssoc";
ways = 4;
};
};
l1i_wimpy = {
caches = 10;
size = 16384;
latency = 3;
array = {
type = "SetAssoc";
ways = 8;
};
};
l3 = {
caches = 1;
banks = 6;
size = 12582912;
latency = 27;
array = {
type = "SetAssoc";
hash = "H3";
ways = 16;
};
children = "l2_beefy l1i_wimpy|l1d_wimpy";
};
};
mem = {
type = "DDR";
controllers = 4;
tech = "DDR3-1066-CL8";
};
};
sim = {
phaseLength = 10000;
maxTotalInstrs = 5000000000L;
statsPhaseInterval = 1000;
printHierarchy = true;
// attachDebugger = True;
};
process0 = {
command = "$ZSIMAPPSPATH/build/speccpu2006/401.bzip2/401.bzip2 $ZSIMAPPSPATH/inputs/speccpu2006/401.bzip2/ref/input.source 64";
};
process1 = {
command = "$ZSIMAPPSPATH/build/parsec/blackscholes/blackscholes 15 2000000";
startFastForwarded = True;
};