-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathMotorControl.rpt
814 lines (760 loc) · 29.3 KB
/
MotorControl.rpt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
Loading plugins phase: Elapsed time ==> 0s.204ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -d CY8C4245AXI-483 -s C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 0s.926ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.136ms
<CYPRESSTAG name="Synthesis results...">
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |
======================================================================
Compiling: MotorControl.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -dcpsoc3 MotorControl.v -verilog
======================================================================
======================================================================
Compiling: MotorControl.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -dcpsoc3 MotorControl.v -verilog
======================================================================
======================================================================
Compiling: MotorControl.v
Program : vlogfe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -dcpsoc3 -verilog MotorControl.v
======================================================================
vlogfe V6.3 IR 41: Verilog parser
Sun Aug 16 20:07:24 2020
======================================================================
Compiling: MotorControl.v
Program : vpp
Options : -yv2 -q10 MotorControl.v
======================================================================
vpp V6.3 IR 41: Verilog Pre-Processor
Sun Aug 16 20:07:24 2020
vpp: No errors.
Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'MotorControl.ctl'.
vlogfe: No errors.
======================================================================
Compiling: MotorControl.v
Program : tovif
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -dcpsoc3 -verilog MotorControl.v
======================================================================
tovif V6.3 IR 41: High-level synthesis
Sun Aug 16 20:07:25 2020
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\codegentemp\MotorControl.ctl'.
Linking 'C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\codegentemp\MotorControl.v'.
tovif: No errors.
======================================================================
Compiling: MotorControl.v
Program : topld
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -dcpsoc3 -verilog MotorControl.v
======================================================================
topld V6.3 IR 41: Synthesis and optimization
Sun Aug 16 20:07:25 2020
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\codegentemp\MotorControl.ctl'.
Linking 'C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\codegentemp\MotorControl.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing one to tmpOE__dirA_net_0
Aliasing tmpOE__pwmA_net_0 to tmpOE__dirA_net_0
Aliasing tmpOE__dirB_net_0 to tmpOE__dirA_net_0
Aliasing tmpOE__pwmB_net_0 to tmpOE__dirA_net_0
Aliasing tmpOE__BlueLED_net_0 to tmpOE__dirA_net_0
Removing Lhs of wire one[6] = tmpOE__dirA_net_0[1]
Removing Lhs of wire tmpOE__pwmA_net_0[9] = tmpOE__dirA_net_0[1]
Removing Lhs of wire tmpOE__dirB_net_0[15] = tmpOE__dirA_net_0[1]
Removing Lhs of wire tmpOE__pwmB_net_0[21] = tmpOE__dirA_net_0[1]
Removing Lhs of wire tmpOE__BlueLED_net_0[27] = tmpOE__dirA_net_0[1]
------------------------------------------------------
Aliased 0 equations, 5 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Substituting virtuals - pass 1:
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum default expansion cost was set at 3.
----------------------------------------------------------
topld: No errors.
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya "-.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj" -dcpsoc3 MotorControl.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 0s.586ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.3.0.1445, Family: PSoC3, Started at: Sunday, 16 August 2020 20:07:25
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\sabri\Documents\PSoC Creator\Test\MotorControl.cydsn\MotorControl.cyprj -d CY8C4245AXI-483 MotorControl.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.012ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">
------------------------------------------------------------
Design Equations
------------------------------------------------------------
<CYPRESSTAG name="Pin listing">
------------------------------------------------------------
Pin listing
------------------------------------------------------------
Pin : Name = dirA(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => dirA(0)__PA ,
pad => dirA(0)_PAD );
Properties:
{
}
Pin : Name = pwmA(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => pwmA(0)__PA ,
pad => pwmA(0)_PAD );
Properties:
{
}
Pin : Name = dirB(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => dirB(0)__PA ,
pad => dirB(0)_PAD );
Properties:
{
}
Pin : Name = pwmB(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => pwmB(0)__PA ,
pad => pwmB(0)_PAD );
Properties:
{
}
Pin : Name = BlueLED(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 1
IO Voltage: 0
PORT MAP (
pa_out => BlueLED(0)__PA ,
pad => BlueLED(0)_PAD );
Properties:
{
}
</CYPRESSTAG>
<CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
</CYPRESSTAG>
<CYPRESSTAG name="Datapath listing">
</CYPRESSTAG>
<CYPRESSTAG name="Status register listing">
</CYPRESSTAG>
<CYPRESSTAG name="StatusI register listing">
</CYPRESSTAG>
<CYPRESSTAG name="Sync listing">
</CYPRESSTAG>
<CYPRESSTAG name="Control register listing">
</CYPRESSTAG>
<CYPRESSTAG name="Count7 listing">
</CYPRESSTAG>
<CYPRESSTAG name="DRQ listing">
</CYPRESSTAG>
<CYPRESSTAG name="Interrupt listing">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>
------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------
Resource Type : Used : Free : Max : % Used
============================================================
Digital Clocks : 0 : 4 : 4 : 0.00 %
Interrupts : 0 : 32 : 32 : 0.00 %
IO : 7 : 29 : 36 : 19.44 %
Segment LCD : 0 : 1 : 1 : 0.00 %
CapSense : 0 : 1 : 1 : 0.00 %
Die Temp : 0 : 1 : 1 : 0.00 %
Serial Communication (SCB) : 0 : 2 : 2 : 0.00 %
Timer/Counter/PWM : 0 : 4 : 4 : 0.00 %
UDB : : : :
Macrocells : 0 : 32 : 32 : 0.00 %
Unique P-terms : 0 : 64 : 64 : 0.00 %
Total P-terms : 0 : : :
Datapath Cells : 0 : 4 : 4 : 0.00 %
Status Cells : 0 : 4 : 4 : 0.00 %
Control Cells : 0 : 4 : 4 : 0.00 %
Comparator/Opamp : 0 : 2 : 2 : 0.00 %
LP Comparator : 0 : 2 : 2 : 0.00 %
SAR ADC : 0 : 1 : 1 : 0.00 %
DAC : : : :
7-bit IDAC : 0 : 1 : 1 : 0.00 %
8-bit IDAC : 0 : 1 : 1 : 0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.094ms
Tech Mapping phase: Elapsed time ==> 0s.170ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
<CYPRESSTAG name="FFB & IO Pre Placement">
<CYPRESSTAG name="Placement" icon="FILE_RPT_PLACEMENT">
Cell : Block
=========================================================================
dirA(0) : [IOP=(2)][IoId=(0)]
pwmA(0) : [IOP=(2)][IoId=(2)]
dirB(0) : [IOP=(2)][IoId=(1)]
pwmB(0) : [IOP=(2)][IoId=(3)]
BlueLED(0) : [IOP=(0)][IoId=(3)]
ClockGenBlock : CLK_GEN_[FFB(CLK_GEN,0)]
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Real Analog Placement">
Elapsed time ==> 0.2995924s
</CYPRESSTAG>
Analog Placement phase: Elapsed time ==> 0s.852ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
<CYPRESSTAG name="Analog Routing">
Route success=True, Iterations=1 Elapsed=0.0013191 secs
</CYPRESSTAG>
Analog Routing phase: Elapsed time ==> 0s.001ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Analog Code Generation phase: Elapsed time ==> 0s.053ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2076: Total run-time: 0.4 sec.
</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary">
No PLDs were packed.
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.026ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.306ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">
------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------
Resource Type : Count : Avg Inputs : Avg Outputs
========================================================
UDB : 0 : 0.00 : 0.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">
------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
UDB [UDB=(0,0)] is empty.
UDB [UDB=(0,1)] is empty.
UDB [UDB=(1,0)] is empty.
UDB [UDB=(1,1)] is empty.
Intr container @ [IntrContainer=(0)]: empty
Port 0 contains the following IO cells:
[IoId=3]:
Pin : Name = BlueLED(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 1
IO Voltage: 0
PORT MAP (
pa_out => BlueLED(0)__PA ,
pad => BlueLED(0)_PAD );
Properties:
{
}
Port 1 contains the following IO cells:
Port 2 contains the following IO cells:
[IoId=0]:
Pin : Name = dirA(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => dirA(0)__PA ,
pad => dirA(0)_PAD );
Properties:
{
}
[IoId=1]:
Pin : Name = dirB(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => dirB(0)__PA ,
pad => dirB(0)_PAD );
Properties:
{
}
[IoId=2]:
Pin : Name = pwmA(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => pwmA(0)__PA ,
pad => pwmA(0)_PAD );
Properties:
{
}
[IoId=3]:
Pin : Name = pwmB(0)
Attributes:
In Group/Port: True
In Sync Option: AUTO
Out Sync Option: NOSYNC
Interrupt generated: False
Interrupt mode: NONE
Drive mode: CMOS_OUT
VTrip: EITHER
Slew: FAST
Input Sync needed: False
Output Sync needed: False
SC shield enabled: False
POR State: ANY
LCD Mode: COMMON
Register Mode: RegComb
CaSense Mode: NEITHER
Treat as pin: True
Is OE Registered: False
Uses Analog: False
Can contain Digital: True
Is SIO: False
SIO Output Buf: NONREGULATED
SIO Input Buf: SINGLE_ENDED
SIO HiFreq: LOW
SIO Hyst: DISABLED
SIO Vtrip: MULTIPLIER_0_5
SIO Multiplier Index: 0
SIO RefSel: VCC_IO
Required Capabilities: DIGITAL
Initial Value: 0
IO Voltage: 0
PORT MAP (
pa_out => pwmB(0)__PA ,
pad => pwmB(0)_PAD );
Properties:
{
}
Port 3 contains the following IO cells:
Port 4 contains the following IO cells:
ARM group 0: empty
Clock group 0:
Clock Block @ F(Clock,0):
m0s8clockblockcell: Name =ClockBlock
PORT MAP (
hfclk => ClockBlock_HFClk ,
imo => ClockBlock_IMO ,
ext => ClockBlock_ExtClk ,
sysclk => ClockBlock_SysClk ,
ilo => ClockBlock_ILO ,
lfclk => ClockBlock_LFClk ,
dsi_in_0 => ClockBlock_Routed1 );
Properties:
{
}
LCD group 0: empty
PICU group 0: empty
LPCOMP group 0: empty
SCB group 0: empty
CSD group 0: empty
CSIDAC8 group 0: empty
CSIDAC7 group 0: empty
TCPWM group 0: empty
OA group 0: empty
TEMP group 0: empty
SARADC group 0: empty
CLK_GEN group 0:
M0S8 Clock Gen Block @ F(CLK_GEN,0):
m0s8clockgenblockcell: Name =ClockGenBlock
PORT MAP (
);
Properties:
{
}
LPCOMPBLOCK group 0: empty
PASSBLOCK group 0: empty
WCO group 0: empty
SRSS group 0: empty
CPUSS group 0: empty
EXCO group 0: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">
------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
| | | Interrupt | | |
Port | Pin | Fixed | Type | Drive Mode | Name | Connections
-----+-----+-------+-----------+------------------+------------+------------
0 | 3 | * | NONE | CMOS_OUT | BlueLED(0) |
-----+-----+-------+-----------+------------------+------------+------------
2 | 0 | * | NONE | CMOS_OUT | dirA(0) |
| 1 | * | NONE | CMOS_OUT | dirB(0) |
| 2 | * | NONE | CMOS_OUT | pwmA(0) |
| 3 | * | NONE | CMOS_OUT | pwmB(0) |
----------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.032ms
Digital Placement phase: Elapsed time ==> 1s.517ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
"C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\dev\psoc4/psoc4a/route_arch-rrg.cydata" --vh2-path "MotorControl_r.vh2" --pcf-path "MotorControl.pco" --des-name "MotorControl" --dsf-path "MotorControl.dsf" --sdc-path "MotorControl.sdc" --lib-path "MotorControl_r.lib"
Routing successful.
Digital Routing phase: Elapsed time ==> 1s.217ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 0s.410ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.060ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Timing report is in MotorControl_timing.html.
Static timing analysis phase: Elapsed time ==> 0s.538ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.383ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 5s.375ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 5s.450ms
API generation phase: Elapsed time ==> 13s.492ms
Dependency generation phase: Elapsed time ==> 0s.106ms
Cleanup phase: Elapsed time ==> 0s.001ms