info.yaml

# Tiny Tapeout project information
project:
  title:        "GOA - grogu on ASIC"
  author:       "Simone Corbetta"
  discord:      "scorbetta"
  description:  "Single neuron w/ fixed-point arithmetic"
  language:     "Verilog"
  clock_hz:     25

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_scorbetta_goa"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:        
    - "FIXED_POINT_ADD.v"
    - "FIXED_POINT_ABS.v"
    - "FIXED_POINT_MUL.v"
    - "FIXED_POINT_CHANGE_SIGN.v"
    - "FIXED_POINT_COMP.v"
    - "FIXED_POINT_ACT_FUN.v"
    - "RW_REG.v"
    - "RO_REG.v"
    - "DELTA_REG.v"
    - "REGPOOL.v"
    - "D_FF_EN.v"
    - "PISO_BUFFER.v"
    - "SIPO_BUFFER.v"
    - "SCI_SLAVE.v"
    - "COUNTER.v"
    - "EDGE_DETECTOR.v"
    - "NEURON_CONTROL_ENGINE.v"
    - "NEURON.v"
    - "NEURON_WRAPPER.v"
    - "tt_um_scorbetta_goa.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "FPGA clock"
  ui[1]: "Active-low FPGA reset"
  ui[2]: "Loopback data"
  ui[3]: ""
  ui[4]: ""
  ui[5]: ""
  ui[6]: "Debug select [0]"
  ui[7]: "Debug select [1]"

  # Outputs
  uo[0]: "Shared debug output dbug_out[0]"
  uo[1]: "Shared debug output dbug_out[1]"
  uo[2]: "Shared debug output dbug_out[2]"
  uo[3]: "Shared debug output dbug_out[3]"
  uo[4]: "Shared debug output dbug_out[4]"
  uo[5]: "Shared debug output dbug_out[5]"
  uo[6]: "Shared debug output dbug_out[6]"
  uo[7]: "Shared debug output dbug_out[7]"

  # Bidirectional pins
  uio[0]: "SCI_CSN"
  uio[1]: "SCI_REQ"
  uio[2]: "SCI_RESP"
  uio[3]: "SCI_ACK"
  uio[4]: ""
  uio[5]: ""
  uio[6]: ""
  uio[7]: ""

# Do not change!
yaml_version: 6