- Design fix

- Test fix
- Makefile fix

Author: scorbetta

src/tt_um_scorbetta_goa.v

@@ -30,15 +30,21 @@ module tt_um_scorbetta_goa
     input wire          rst_n // reset_n - low to reset
 );
 
-    wire [7:0] counter;
+    wire [7:0]  counter;
+    wire        tt_rstn_i;
+    wire        fpga_rstn_i;
+
+    // Keep the design under reset if not enabled
+    assign tt_rstn_i    = ena & rst_n;
+    assign fpga_rstn_i  = ena & ui_in[`UI_IN_RESET];
 
     // Use main clock to check power
     COUNTER #(
         .WIDTH  (8)
     )
     COUNTER (
         .CLK        (clk),
-        .RSTN       (rst_n),
+        .RSTN       (tt_rstn_i),
         .EN         (ena),
         .VALUE      (counter),
         .OVERFLOW   () // Unused
@@ -50,7 +56,7 @@ module tt_um_scorbetta_goa
     // User design uses a custom clock, generated by remote FPGA
     NEURON_WRAPPER NEURON_WRAPPER (
         .CLK                (ui_in[`UI_IN_CLOCK]),
-        .RSTN               (ui_in[`UI_IN_RESET]),
+        .RSTN               (fpga_rstn_i),
         .SCI_CSN            (ui_in[`UI_IN_SCI_CSN]),
         .SCI_REQ            (ui_in[`UI_IN_SCI_REQ]),
         .SCI_RESP           (uo_out[`UO_OUT_SCI_RESP]),

test/Makefile

@@ -1,22 +1,21 @@
 .PHONY: clean
 
-VERILOG_SOURCES = 
+VERILOG_SOURCES = tb.v
 SRC_DIR = $(PWD)/../src
 IVERILOG_ARGS =
 COCOTB_PREFIX = $(shell cocotb-config --prefix)
 
 ifneq ($(GATES),yes)
 
 VERILOG_SOURCES += $(shell ls $(SRC_DIR)/*.v | tr '\n' ' ' )
-VERILOG_SOURCES += tb.v
 IVERILOG_ARGS += -DCOCOTB_SIM=1 -s tb -I$(SRC_DIR) -g2012
 
 else
 
 VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
 VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
 VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
-IVERILOG_ARGS += -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=\#1
+IVERILOG_ARGS += -Ttyp -DFUNCTIONAL -DSIM -DUNIT_DELAY=\#1
 
 endif
 

test/tb.v

@@ -59,10 +59,6 @@ module tb
 );
 
     tt_um_scorbetta_goa DUT (
-`ifdef GL_TEST
-        .VPWR       (1'b1),
-        .VGND       (1'b0),
-`endif
         .ui_in      ({ ui_in_7, ui_in_6, ui_in_5, ui_in_4, ui_in_3, ui_in_2, ui_in_1, ui_in_0 }),
         .uo_out     ({ uo_out_7, uo_out_6, uo_out_5, uo_out_4, uo_out_3, uo_out_2, uo_out_1, uo_out_0 }),
         .uio_in     ({ uio_in_7, uio_in_6, uio_in_5, uio_in_4, uio_in_3, uio_in_2, uio_in_1, uio_in_0 }),
@@ -75,7 +71,7 @@ module tb
 
     initial begin
         $dumpfile("dump.vcd");
-        $dumpvars(0, tb.DUT);
+        $dumpvars(0, tb);
     end
 endmodule
 

test/test.py

@@ -43,20 +43,33 @@ async def test(dut):
     dut.rst_n.value = 0
     dut.ui_in_1.value = 0 ;#UI_IN_RESET
     dut.ui_in_2.value = 1 ;#UI_IN_SCI_CSN
+    dut.ui_in_3.value = 0 ;#UI_IN_SCI_REQ
     dut.ui_in_4.value = 0 ;#UI_IN_LOAD_IN
+    dut.ui_in_5.value = 0 ;#UI_IN_LOAD_VALUE_IN
     dut.ui_in_6.value = 0 ;#UI_IN_SHIFT_OUT
     dut.ui_in_7.value = 0 ;#UI_IN_START
+    dut.ena.value = 0
 
     # Reset procedure
     for cycle in range(4):
         await RisingEdge(dut.clk)
     dut.rst_n.value = 1
     dut.ui_in_1.value = 1 ;#UI_IN_RESET
 
+    # Shim delay
+    for cycle in range(10):
+        await RisingEdge(dut.clk)
+
+    # Enable design
+    dut.ena.value = 1
+
     # Shim delay
     for cycle in range(4):
         await RisingEdge(dut.clk)
 
+    # Formally, we need to wait for neuron to be ready
+    await wait_for_value(dut.ui_in_0, dut.uo_out_3, 1)
+
     # From this point on, we use the clock generated from the FPGA as reference. Detailed interface
     # mapping through top-level GPIOs
     #   CLK             -> DUT.ui_in[0]  -> tb.ui_in_0
@@ -146,16 +159,8 @@ async def test(dut):
         for _ in range(2):
             await RisingEdge(dut.ui_in_0)
 
-        # Verify accumulator
-        threshold = 0.10
-        dut_result = Fxp(val=f'0b{str(dut.DUT.NEURON_WRAPPER.NEURON.biased_acc_out.value.binstr)}', signed=True, n_word=width, n_frac=frac_bits, config=fxp_get_config())
-        abs_err = fxp_abs_err(golden_model_acc, dut_result)
-        quant_err = float(abs_err) / float(fxp_lsb) / fxp_quants
-        #assert(quant_err <= threshold),print(f'Results for ACC differ more than {threshold*100}% LSBs: dut_result={dut_result},golden_result={golden_model_acc},abs_err={abs_err},quant_error={quant_err}')
-        if quant_err > threshold:
-            print(f'warn: Test #{test} - Results for ACC differ more than {threshold*100}% LSBs: dut_result={dut_result},golden_result={golden_model_acc},abs_err={abs_err},quant_error={quant_err}')
-
         # Verify output
+        threshold = 0.10
         dut_result_bin = ''
         dut.ui_in_6.value = 1
         for bdx in reversed(range(8)):