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ERRATA.md

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AWS EC2 FPGA HDK+SDK Errata

Shell v1.4 (04261818)

Shell_04261818_Errata

HDK

  • Multiple SDE instances per CL is not supported in this release. Support is planned for a future release.
  • DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
  • Combinatorial loops in CL designs are not supported.

2019.1

  • Vivado compile_simlib command fails to generate the following verilog IP libraries for the following simulators.
Library(verilog) Simulator
sync_ip Cadence IES
hdmi_gt_controller_v1_0_0 Synopsys VCS
  • We are working with Xilinx to provide a fix for these.

SDK

SDAccel (For additional restrictions see SDAccel ERRATA)

  • Virtual Ethernet is not supported when using SDAccel
  • DRAM Data retention is not supported for kernels that provision less than 4 DDRs
  • Combinatorial loops in CL designs are not supported.