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Currently, we have mixed memory command with memory data the better way to implement and pipeline the design is to separate memory commands from memory data and make them independent so we can also design a simple MSHR and have multiple memory requests on the fly. At this moment for the sake of simplification, we have serialized all the memory accesses.
By just breaking down the memory accesses into two nodes or make a centralized memory unit with separate channels for read and write we can have better parallelization.
The text was updated successfully, but these errors were encountered:
Currently, there is a serialized implementation of memory arbiter for load and store. But this node only makes all the accesses serialize. The implementation can be used as a baseline
Currently, we have mixed memory command with memory data the better way to implement and pipeline the design is to separate memory commands from memory data and make them independent so we can also design a simple MSHR and have multiple memory requests on the fly. At this moment for the sake of simplification, we have serialized all the memory accesses.
By just breaking down the memory accesses into two nodes or make a centralized memory unit with separate channels for read and write we can have better parallelization.
The text was updated successfully, but these errors were encountered: