diff --git a/MANIFEST.in b/MANIFEST.in index f31ea88..7cb6db7 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -1 +1 @@ -include svreal.sv +include svreal/svreal.sv diff --git a/setup.py b/setup.py index dae75af..f580d45 100644 --- a/setup.py +++ b/setup.py @@ -1,7 +1,7 @@ from setuptools import setup name = 'svreal' -version = '0.1.4' +version = '0.1.5' DESCRIPTION = '''\ Library for working with fixed-point numbers in SystemVerilog\ diff --git a/svreal/__init__.py b/svreal/__init__.py index 0c7d2f0..8e0e362 100644 --- a/svreal/__init__.py +++ b/svreal/__init__.py @@ -1 +1,6 @@ -from .files import get_svreal_header +from pathlib import Path + +PACK_DIR = Path(__file__).resolve().parent + +def get_svreal_header(): + return PACK_DIR / 'svreal.sv' \ No newline at end of file diff --git a/svreal/files.py b/svreal/files.py deleted file mode 100644 index d13679e..0000000 --- a/svreal/files.py +++ /dev/null @@ -1,20 +0,0 @@ -from pathlib import Path - -TOP_DIR = Path(__file__).resolve().parent.parent - -def get_file(path): - return Path(TOP_DIR, path) - -def get_dir(path): - # alias for get_file - return get_file(path) - -def get_files(*args): - return [get_file(path) for path in args] - -def get_dirs(*args): - # alias for get_files - return get_files(*args) - -def get_svreal_header(): - return get_file('svreal.sv') diff --git a/svreal.sv b/svreal/svreal.sv similarity index 100% rename from svreal.sv rename to svreal/svreal.sv diff --git a/tests/common.py b/tests/common.py index c0a544c..fdb6352 100644 --- a/tests/common.py +++ b/tests/common.py @@ -5,6 +5,22 @@ # AHA imports from fault.subprocess_run import subprocess_run +TEST_DIR = Path(__file__).resolve().parent + +def get_file(path): + return Path(TEST_DIR, path) + +def get_dir(path): + # alias for get_file + return get_file(path) + +def get_files(*args): + return [get_file(path) for path in args] + +def get_dirs(*args): + # alias for get_files + return get_files(*args) + def pytest_sim_params(metafunc, simulators=None): if simulators is None: simulators = ['vcs', 'vivado', 'ncsim', 'iverilog'] diff --git a/tests/test_arith.py b/tests/test_arith.py index 7875a67..9a80a96 100644 --- a/tests/test_arith.py +++ b/tests/test_arith.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -70,9 +70,9 @@ def run_iteration(a_i, b_i): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_arith.sv')], + ext_srcs=[get_file('test_arith.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_clog2.py b/tests/test_clog2.py index fded23e..ab9c23e 100644 --- a/tests/test_clog2.py +++ b/tests/test_clog2.py @@ -6,8 +6,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -49,8 +49,8 @@ def run_iteration(in_): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_clog2.sv')], + ext_srcs=[get_file('test_clog2.sv')], inc_dirs=[get_svreal_header().parent], ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_comp.py b/tests/test_comp.py index d8055ae..27e12e3 100644 --- a/tests/test_comp.py +++ b/tests/test_comp.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -71,9 +71,9 @@ def run_iteration(a_i, b_i): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_comp.sv')], + ext_srcs=[get_file('test_comp.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_const.py b/tests/test_const.py index c1a7c48..0bc7794 100644 --- a/tests/test_const.py +++ b/tests/test_const.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -55,10 +55,10 @@ def test_const(simulator, defines): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_const.sv')], + ext_srcs=[get_file('test_const.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, parameters=parameters, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_conv.py b/tests/test_conv.py index f7f1e5b..59c1fb7 100644 --- a/tests/test_conv.py +++ b/tests/test_conv.py @@ -6,8 +6,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -60,9 +60,9 @@ def run_iteration(r2i_i, i2r_i=0): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_conv.sv')], + ext_srcs=[get_file('test_conv.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_dff.py b/tests/test_dff.py index e328394..dbba1ff 100644 --- a/tests/test_dff.py +++ b/tests/test_dff.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -74,10 +74,10 @@ def test_dff(simulator, defines): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_dff.sv')], + ext_srcs=[get_file('test_dff.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, parameters={'init': 1.23}, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_hier.py b/tests/test_hier.py index d86cfd2..06c89c7 100644 --- a/tests/test_hier.py +++ b/tests/test_hier.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -32,9 +32,9 @@ def test_hier(simulator, defines): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_hier.sv')], + ext_srcs=[get_file('test_hier.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_iface.py b/tests/test_iface.py index 4d2f2ea..bded6e3 100644 --- a/tests/test_iface.py +++ b/tests/test_iface.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc, simulators=['ncsim', 'vcs', 'vivado']) @@ -35,8 +35,8 @@ def test_iface(simulator, defines): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_iface_core.sv'), - get_file('tests/test_iface.sv')], + ext_srcs=[get_file('test_iface_core.sv'), + get_file('test_iface.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, diff --git a/tests/test_iface_synth.py b/tests/test_iface_synth.py index 63f76b4..f0ae037 100644 --- a/tests/test_iface_synth.py +++ b/tests/test_iface_synth.py @@ -1,14 +1,15 @@ # svreal imports -from .common import pytest_synth_params, run_synth -from svreal.files import get_file, get_dir, get_svreal_header +from .common import pytest_synth_params, run_synth, get_file, get_dir +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_synth_params(metafunc) def test_synth(synth): run_synth(synth=synth, - src_files=[get_file('tests/test_iface_core.sv'), - get_file('tests/test_iface_synth.sv')], + src_files=[get_file('test_iface_core.sv'), + get_file('test_iface_synth.sv')], hdr_files=[get_svreal_header()], top='test_iface_synth', - cwd=get_dir('tests/tmp/test_iface_synth')) \ No newline at end of file + cwd=get_dir('tmp/test_iface_synth') + ) diff --git a/tests/test_ite.py b/tests/test_ite.py index 6482408..2500a25 100644 --- a/tests/test_ite.py +++ b/tests/test_ite.py @@ -3,8 +3,8 @@ import fault # svreal imports -from .common import pytest_sim_params -from svreal.files import get_file, get_svreal_header +from .common import pytest_sim_params, get_file +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_sim_params(metafunc) @@ -55,9 +55,9 @@ def run_iteration(a_i, b_i, cond_i): tester.compile_and_run( target='system-verilog', simulator=simulator, - ext_srcs=[get_file('tests/test_ite.sv')], + ext_srcs=[get_file('test_ite.sv')], inc_dirs=[get_svreal_header().parent], defines=defines, ext_model_file=True, tmp_dir=True - ) \ No newline at end of file + ) diff --git a/tests/test_synth.py b/tests/test_synth.py index b58d145..79b901b 100644 --- a/tests/test_synth.py +++ b/tests/test_synth.py @@ -1,13 +1,14 @@ # svreal imports -from .common import pytest_synth_params, run_synth -from svreal.files import get_file, get_dir, get_svreal_header +from .common import pytest_synth_params, run_synth, get_file, get_dir +from svreal import get_svreal_header def pytest_generate_tests(metafunc): pytest_synth_params(metafunc) def test_synth(synth): run_synth(synth=synth, - src_files=[get_file('tests/test_synth.sv')], + src_files=[get_file('test_synth.sv')], hdr_files=[get_svreal_header()], top='test_synth', - cwd=get_dir('tests/tmp/test_synth')) + cwd=get_dir('tmp/test_synth') + )