@@ -199,6 +199,82 @@ module asrv32_soc #(parameter CLK_FREQ_MHZ=12, PC_RESET=32'h00_00_00_00, TRAP_AD
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.o_timer_interrupt(o_timer_interrupt),
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.o_software_interrupt(o_software_interrupt)
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);
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+ // DEVICE 2 : UART instantiation
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+ uart #( .CLOCK_FREQ(CLK_FREQ_MHZ*1_000_000), // UART (TX only) [memory-mapped to >=h50,<hA0 (MSB=1)]
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+ .BAUD_RATE( // UART Baud rate
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+ `ifdef ICARUS
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+ 2_000_000 // faster simulation
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+ `else
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+ 9600 // 9600 Baud
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+ `endif ),
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+ .UART_TX_DATA(32'h8000_0050 ), // memory-mapped address for TX
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+ .UART_TX_BUSY(32'h8000_0054 ), // memory-mapped address to check if TX is busy (has ongoing request)
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+ .UART_RX_BUFFER_FULL(32'h8000_0058 ), // memory-mapped address to check if a read has completed
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+ .UART_RX_DATA(32'h8000_005C ), // memory-mapped address for RX
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+ .DBIT(8 ), // UART Data Bits
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+ .SBIT(1 ) // UART Stop Bits
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+ ) uart
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+ (
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+ .clk(i_clk),
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+ .rst_n(!i_rst),
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+ .uart_rw_address(o_device2_data_addr), // read/write address (access the memory-mapped registers for controlling UART)
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+ .uart_wdata(o_device2_wdata[7 :0 ]), // TX data
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+ .uart_wr_en(o_device2_wr_en), // write-enable
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+ .uart_rx(uart_rx), // UART RX line
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+ .uart_tx(uart_tx), // UART TX line
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+ .uart_rdata(i_device2_rdata[7 :0 ]), // data read from memory-mapped register
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+ .o_ack_data(i_device2_ack_data), // request to access UART
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+ .i_stb_data(o_device2_stb_data) // acknowledge by UART
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+ );
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+
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+ // DEVICE 3 : I2C instantiation
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+ i2c #(.main_clock(CLK_FREQ_MHZ*1_000_000), // SCCB mode(no pullups resistors needed) [memory-mapped to >=A0,<F0 (MSB=1)]
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+ .freq( // i2c freqeuncy
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+ `ifdef ICARUS
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+ 2_000_000 // faster simulation
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+ `else
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+ 100_000 // 100KHz
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+ `endif ),
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+ .addr_bytes(1 ), // addr_bytes=number of bytes of an address
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+ .I2C_START(32'h8000_00A0 ), // write-only memory-mapped address to start i2c (write the i2c slave address)
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+ .I2C_WRITE(32'h8000_00A4 ), // write-only memory-mapped address for sending data to slave
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+ .I2C_READ(32'h8000_00A8 ), // read-only memory-mapped address to read data received from slave (this will also continue reading from slave)
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+ .I2C_BUSY(32'h8000_00AC ), // read-only memory-mapped address to check if i2c is busy (cannot accept request)
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+ .I2C_ACK(32'h8000_00B0 ), // read-only memory-mapped address to check if last access has benn acknowledge by slave
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+ .I2C_READ_DATA_READY(32'h8000_00B4 ), // read-only memory-mapped address to check if data to be received from slave is ready
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+ .I2C_STOP(32'h8000_00B8 ) // write-only memory-mapped address to stop i2c (this is persistent thus must be manually turned off after stopping i2c)
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+ ) i2c
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+ (
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+ .clk(i_clk),
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+ .rst_n(!i_rst),
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+ .i2c_rw_address(o_device3_data_addr), // read/write address (access the memory-mapped registers for controlling i2c)
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+ .i2c_wdata(o_device3_wdata[7 :0 ]), // data to be written to slave or to memory-mapped registers of i2c
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+ .i2c_rdata(i_device3_rdata[7 :0 ]), // data retrieved from slave or from the memory-mapped registers of i2c
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+ .i2c_wr_en(o_device3_wr_en), // write-enable
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+ .i_stb_data(o_device3_stb_data), // request to access i2c
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+ .o_ack_data(i_device3_ack_data), // acknowledge by i2c
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+ .scl(i2c_scl), // i2c bidrectional clock line
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+ .sda(i2c_sda) // i2c bidrectional data line
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+ );
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+
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+ // DEVICE 4 : GPIO instantiation
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+ gpio #( // General-Purpose Input-Ouput
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+ .GPIO_MODE(32'h8000_00F0 ), // set if GPIO will be read(0) or write(1)
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+ .GPIO_READ(32'h8000_00F4 ), // read GPIO value
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+ .GPIO_WRITE(32'h8000_00F8 ), // write to GPIO
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+ .GPIO_COUNT(12 )
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+ ) gpio (
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+ .clk(i_clk),
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+ .rst_n(!i_rst),
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+ .gpio_rw_address(o_device4_data_addr), // read/write address of memory-mapped register
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+ .gpio_wdata(o_device4_wdata[GPIO_COUNT-1 :0 ]), // write data to memory-mapped register
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+ .gpio_rdata(i_device4_rdata[GPIO_COUNT-1 :0 ]), // read data from memory-mapped register
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+ .gpio_wr_en(o_device4_wr_en), // write-enable
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+ .i_stb_data(o_device4_stb_data), // request to access GPIO
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+ .o_ack_data(i_device4_ack_data), // acknowledge by GPIO
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+ // GPIO
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+ .gpio(gpio_pins) // gpio pins
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+ );
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endmodule
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