From c24540cf32baffde1c57060dfb02665545195587 Mon Sep 17 00:00:00 2001
From: E4tHam <ethan@sifferman.dev>
Date: Sun, 19 Sep 2021 15:39:55 -0700
Subject: [PATCH] organization and practices

---
 .vscode/settings.json |  2 +-
 rtl/ffs.v             | 27 +++++++++++++++------------
 sim/tb.v              |  2 +-
 3 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/.vscode/settings.json b/.vscode/settings.json
index f1dd353..0aaeca3 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -1,5 +1,5 @@
 {
-    "verilog.linting.iverilog.runAtFileLocation": true,
+    "verilog.linting.iverilog.runAtFileLocation": false,
     "verilog.linting.iverilog.arguments": "-Wall -g2012 -DLINTER=1",
     "verilog.linting.linter": "iverilog"
 }
diff --git a/rtl/ffs.v b/rtl/ffs.v
index 1205b72..df0f726 100644
--- a/rtl/ffs.v
+++ b/rtl/ffs.v
@@ -70,6 +70,7 @@ module ffs_m #(
             if ( USE_X )    assign right_out = right_valid ? 1'b0 : 1'bx;
             else            assign right_out = 1'b0;
         end
+        // right recursive call
         if ( RIGHT_INPUT_WIDTH > 1 ) begin : right_recursion
             wire [RIGHT_INPUT_WIDTH-1:0] right_in = in[ 0 +: RIGHT_INPUT_WIDTH ];
             ffs_m #(RIGHT_INPUT_WIDTH,SIDE,USE_X) ffs (
@@ -80,18 +81,20 @@ module ffs_m #(
         end
 
         // combine left and right back together
-        case ({ ((2'b01&USE_X)<<1) | (2'b01&SIDE) })
-            2'b00: assign out = left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
-                                ( right_out );
-            2'b01: assign out = right_valid ? ( right_out )                     :
-                                ( left_out + RIGHT_INPUT_WIDTH );
-            2'b10: assign out = left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
-                                right_valid ? ( right_out )                     :
-                                {OUTPUT_WIDTH{1'bx}};
-            2'b11: assign out = right_valid ? ( right_out )                     :
-                                left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
-                                {OUTPUT_WIDTH{1'bx}};
-        endcase
+        if      ( !USE_X && !SIDE ) assign out =
+            left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
+            ( right_out );
+        else if ( !USE_X &&  SIDE ) assign out =
+            right_valid ? ( right_out )                     :
+            ( left_out + RIGHT_INPUT_WIDTH );
+        else if (  USE_X && !SIDE ) assign out =
+            left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
+            right_valid ? ( right_out )                     :
+            {OUTPUT_WIDTH{1'bx}};
+        else if (  USE_X && SIDE ) assign out =
+            right_valid ? ( right_out )                     :
+            left_valid  ? ( left_out + RIGHT_INPUT_WIDTH )  :
+            {OUTPUT_WIDTH{1'bx}};
 
     endgenerate
 
diff --git a/sim/tb.v b/sim/tb.v
index 4740c48..085bd8b 100644
--- a/sim/tb.v
+++ b/sim/tb.v
@@ -3,7 +3,7 @@
 
 
 `ifdef LINTER
-    `include "../rtl/ffs.v"
+    `include "rtl/ffs.v"
 `endif