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Merge pull request #544 from sifive/add-l2lim
Add support for L2 LIM. Update BSP files.
2 parents 5a2f019 + 5358731 commit c840632

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‎.gitmodules

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Original file line numberDiff line numberDiff line change
@@ -157,3 +157,6 @@
157157
[submodule "software/example-l2pf"]
158158
path = software/example-l2pf
159159
url = https://github.com/sifive/example-l2pf.git
160+
[submodule "software/example-lim"]
161+
path = software/example-lim
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url = https://github.com/sifive/example-lim.git

‎README.md

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Original file line numberDiff line numberDiff line change
@@ -153,6 +153,8 @@ operating systems to RISC-V.
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- Demonstrates usage of Sifive L2 performance monitor counter APIs to capture L2 cache event logs.
154154
- example-l2pf
155155
- Example for usage and measuring effectiveness of SiFive L2 Prefetcher.
156+
- example-lim
157+
- Demonstrates how to designate a function to be linked into the LIM (Loosely-Integrated Memory).
156158
- example-freertos-minimal
157159
- A simple FreeRTOS skeleton to build your FreeRTOS application.
158160
- example-freertos-blinky

‎bsp/freedom-e310-arty/metal.default.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ PHDRS
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ram PT_LOAD;
2525
itim_init PT_LOAD;
2626
text PT_LOAD;
27+
lim_init PT_LOAD;
2728
}
2829

2930
SECTIONS
@@ -179,10 +180,28 @@ SECTIONS
179180
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
180181
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
181182

183+
/* LIM SECTION
184+
*
185+
* The following sections contain data which is copied from read-only
186+
* memory into a loosely integrated memory (LIM), which is shared with L2
187+
* cache, during pre-main program initialization.
188+
*
189+
* Generally, the data copied into the LIM should be performance-critical
190+
* functions which benefit from low instruction-fetch latency.
191+
*/
192+
193+
.lim : ALIGN(8) {
194+
*(.lim .lim.*)
195+
} >ram AT>rom :lim_init
196+
197+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
198+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
199+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
200+
182201
/* TEXT SECTION
183202
*
184203
* The following section contains the code of the program, excluding
185-
* everything that's been allocated into the ITIM already
204+
* everything that's been allocated into the ITIM/LIM already
186205
*/
187206

188207
.text : {

‎bsp/freedom-e310-arty/metal.freertos.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ PHDRS
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ram PT_LOAD;
2828
itim_init PT_LOAD;
2929
text PT_LOAD;
30+
lim_init PT_LOAD;
3031
}
3132

3233
SECTIONS
@@ -190,10 +191,28 @@ SECTIONS
190191
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
191192
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
192193

194+
/* LIM SECTION
195+
*
196+
* The following sections contain data which is copied from read-only
197+
* memory into a loosely integrated memory (LIM), which is shared with L2
198+
* cache, during pre-main program initialization.
199+
*
200+
* Generally, the data copied into the LIM should be performance-critical
201+
* functions which benefit from low instruction-fetch latency.
202+
*/
203+
204+
.lim : ALIGN(8) {
205+
*(.lim .lim.*)
206+
} >ram AT>rom :lim_init
207+
208+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
209+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
210+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
211+
193212
/* TEXT SECTION
194213
*
195214
* The following section contains the code of the program, excluding
196-
* everything that's been allocated into the ITIM already
215+
* everything that's been allocated into the ITIM/LIM already
197216
*/
198217

199218
.text : {

‎bsp/freedom-e310-arty/metal.ramrodata.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ PHDRS
2828
ram PT_LOAD;
2929
itim_init PT_LOAD;
3030
text PT_LOAD;
31+
lim_init PT_LOAD;
3132
}
3233

3334
SECTIONS
@@ -172,10 +173,28 @@ SECTIONS
172173
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
173174
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
174175

176+
/* LIM SECTION
177+
*
178+
* The following sections contain data which is copied from read-only
179+
* memory into a loosely integrated memory (LIM), which is shared with L2
180+
* cache, during pre-main program initialization.
181+
*
182+
* Generally, the data copied into the LIM should be performance-critical
183+
* functions which benefit from low instruction-fetch latency.
184+
*/
185+
186+
.lim : ALIGN(8) {
187+
*(.lim .lim.*)
188+
} >ram AT>rom :lim_init
189+
190+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
191+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
192+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
193+
175194
/* TEXT SECTION
176195
*
177196
* The following section contains the code of the program, excluding
178-
* everything that's been allocated into the ITIM already
197+
* everything that's been allocated into the ITIM/LIM already
179198
*/
180199

181200
.text : {

‎bsp/freedom-e310-arty/metal.scratchpad.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ PHDRS
2525
ram PT_LOAD;
2626
itim_init PT_LOAD;
2727
text PT_LOAD;
28+
lim_init PT_LOAD;
2829
}
2930

3031
SECTIONS
@@ -172,10 +173,28 @@ SECTIONS
172173
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
173174
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
174175

176+
/* LIM SECTION
177+
*
178+
* The following sections contain data which is copied from read-only
179+
* memory into a loosely integrated memory (LIM), which is shared with L2
180+
* cache, during pre-main program initialization.
181+
*
182+
* Generally, the data copied into the LIM should be performance-critical
183+
* functions which benefit from low instruction-fetch latency.
184+
*/
185+
186+
.lim : ALIGN(8) {
187+
*(.lim .lim.*)
188+
} >ram AT>ram :lim_init
189+
190+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
191+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
192+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
193+
175194
/* TEXT SECTION
176195
*
177196
* The following section contains the code of the program, excluding
178-
* everything that's been allocated into the ITIM already
197+
* everything that's been allocated into the ITIM/LIM already
179198
*/
180199

181200
.text : {

‎bsp/qemu-sifive-e31/metal.default.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ PHDRS
2323
ram PT_LOAD;
2424
itim_init PT_LOAD;
2525
text PT_LOAD;
26+
lim_init PT_LOAD;
2627
}
2728

2829
SECTIONS
@@ -178,10 +179,28 @@ SECTIONS
178179
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
179180
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
180181

182+
/* LIM SECTION
183+
*
184+
* The following sections contain data which is copied from read-only
185+
* memory into a loosely integrated memory (LIM), which is shared with L2
186+
* cache, during pre-main program initialization.
187+
*
188+
* Generally, the data copied into the LIM should be performance-critical
189+
* functions which benefit from low instruction-fetch latency.
190+
*/
191+
192+
.lim : ALIGN(8) {
193+
*(.lim .lim.*)
194+
} >ram AT>rom :lim_init
195+
196+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
197+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
198+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
199+
181200
/* TEXT SECTION
182201
*
183202
* The following section contains the code of the program, excluding
184-
* everything that's been allocated into the ITIM already
203+
* everything that's been allocated into the ITIM/LIM already
185204
*/
186205

187206
.text : {

‎bsp/qemu-sifive-e31/metal.freertos.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ PHDRS
2626
ram PT_LOAD;
2727
itim_init PT_LOAD;
2828
text PT_LOAD;
29+
lim_init PT_LOAD;
2930
}
3031

3132
SECTIONS
@@ -189,10 +190,28 @@ SECTIONS
189190
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
190191
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
191192

193+
/* LIM SECTION
194+
*
195+
* The following sections contain data which is copied from read-only
196+
* memory into a loosely integrated memory (LIM), which is shared with L2
197+
* cache, during pre-main program initialization.
198+
*
199+
* Generally, the data copied into the LIM should be performance-critical
200+
* functions which benefit from low instruction-fetch latency.
201+
*/
202+
203+
.lim : ALIGN(8) {
204+
*(.lim .lim.*)
205+
} >ram AT>rom :lim_init
206+
207+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
208+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
209+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
210+
192211
/* TEXT SECTION
193212
*
194213
* The following section contains the code of the program, excluding
195-
* everything that's been allocated into the ITIM already
214+
* everything that's been allocated into the ITIM/LIM already
196215
*/
197216

198217
.text : {

‎bsp/qemu-sifive-e31/metal.ramrodata.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ PHDRS
2727
ram PT_LOAD;
2828
itim_init PT_LOAD;
2929
text PT_LOAD;
30+
lim_init PT_LOAD;
3031
}
3132

3233
SECTIONS
@@ -171,10 +172,28 @@ SECTIONS
171172
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
172173
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
173174

175+
/* LIM SECTION
176+
*
177+
* The following sections contain data which is copied from read-only
178+
* memory into a loosely integrated memory (LIM), which is shared with L2
179+
* cache, during pre-main program initialization.
180+
*
181+
* Generally, the data copied into the LIM should be performance-critical
182+
* functions which benefit from low instruction-fetch latency.
183+
*/
184+
185+
.lim : ALIGN(8) {
186+
*(.lim .lim.*)
187+
} >ram AT>rom :lim_init
188+
189+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
190+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
191+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
192+
174193
/* TEXT SECTION
175194
*
176195
* The following section contains the code of the program, excluding
177-
* everything that's been allocated into the ITIM already
196+
* everything that's been allocated into the ITIM/LIM already
178197
*/
179198

180199
.text : {

‎bsp/qemu-sifive-e31/metal.scratchpad.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ PHDRS
2424
ram PT_LOAD;
2525
itim_init PT_LOAD;
2626
text PT_LOAD;
27+
lim_init PT_LOAD;
2728
}
2829

2930
SECTIONS
@@ -171,10 +172,28 @@ SECTIONS
171172
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
172173
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
173174

175+
/* LIM SECTION
176+
*
177+
* The following sections contain data which is copied from read-only
178+
* memory into a loosely integrated memory (LIM), which is shared with L2
179+
* cache, during pre-main program initialization.
180+
*
181+
* Generally, the data copied into the LIM should be performance-critical
182+
* functions which benefit from low instruction-fetch latency.
183+
*/
184+
185+
.lim : ALIGN(8) {
186+
*(.lim .lim.*)
187+
} >ram AT>ram :lim_init
188+
189+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
190+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
191+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
192+
174193
/* TEXT SECTION
175194
*
176195
* The following section contains the code of the program, excluding
177-
* everything that's been allocated into the ITIM already
196+
* everything that's been allocated into the ITIM/LIM already
178197
*/
179198

180199
.text : {

‎bsp/qemu-sifive-s51/metal.default.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ PHDRS
2323
ram PT_LOAD;
2424
itim_init PT_LOAD;
2525
text PT_LOAD;
26+
lim_init PT_LOAD;
2627
}
2728

2829
SECTIONS
@@ -178,10 +179,28 @@ SECTIONS
178179
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
179180
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
180181

182+
/* LIM SECTION
183+
*
184+
* The following sections contain data which is copied from read-only
185+
* memory into a loosely integrated memory (LIM), which is shared with L2
186+
* cache, during pre-main program initialization.
187+
*
188+
* Generally, the data copied into the LIM should be performance-critical
189+
* functions which benefit from low instruction-fetch latency.
190+
*/
191+
192+
.lim : ALIGN(8) {
193+
*(.lim .lim.*)
194+
} >ram AT>rom :lim_init
195+
196+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
197+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
198+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
199+
181200
/* TEXT SECTION
182201
*
183202
* The following section contains the code of the program, excluding
184-
* everything that's been allocated into the ITIM already
203+
* everything that's been allocated into the ITIM/LIM already
185204
*/
186205

187206
.text : {

‎bsp/qemu-sifive-s51/metal.freertos.lds

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ PHDRS
2626
ram PT_LOAD;
2727
itim_init PT_LOAD;
2828
text PT_LOAD;
29+
lim_init PT_LOAD;
2930
}
3031

3132
SECTIONS
@@ -189,10 +190,28 @@ SECTIONS
189190
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
190191
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );
191192

193+
/* LIM SECTION
194+
*
195+
* The following sections contain data which is copied from read-only
196+
* memory into a loosely integrated memory (LIM), which is shared with L2
197+
* cache, during pre-main program initialization.
198+
*
199+
* Generally, the data copied into the LIM should be performance-critical
200+
* functions which benefit from low instruction-fetch latency.
201+
*/
202+
203+
.lim : ALIGN(8) {
204+
*(.lim .lim.*)
205+
} >ram AT>rom :lim_init
206+
207+
PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
208+
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
209+
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );
210+
192211
/* TEXT SECTION
193212
*
194213
* The following section contains the code of the program, excluding
195-
* everything that's been allocated into the ITIM already
214+
* everything that's been allocated into the ITIM/LIM already
196215
*/
197216

198217
.text : {

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