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Ease of reflashing subsequent times #2
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Sorry, but no it's a one time update currently. In theory a project could implement the Panologic Ethernet loader, but no existing projects do. Additionally the Ethernet update only updates the "bit file" and some projects such as panog2_nes also need other data (NES ROMS) to be programmed into the "unused" flash to be useful. So for now unless you just want to program run Tom's raytracer you pretty much still need a JTAG programmer. The aren't all that expensive, but of course you also need to deal with the cable. |
It would be pretty easy to make an Ethernet flashing system using LiteX.
LiteX SoCs are already frequently used in multibitstream systems (IE where
a system boots a golden bitstream, checks if a user bitstream is valid or
if to enter flash mode and then boots into it), support ethernet, tftp
loading multiple files and spiflash writing.
See foboot (https://github.com/im-tomu/foboot) for an similar style thing
based around USB and iCE40 (with ECP5 support in progress).
Someone just needs to pull all the threads together....
…On Sat, Jan 25, 2020, 5:46 PM Skip Hansen ***@***.***> wrote:
Sorry, but no it's a one time update currently. In theory a project could
implement the Panologic Ethernet loader, but no existing projects do.
Additionally the Ethernet update only updates the "bit file" and some
projects such as panog2_nes also need other data (NES ROMS) to be
programmed into the "unused" flash to be useful.
So for now unless you just want to program run Tom's raytracer you pretty
much still need a JTAG programmer. The aren't all that expensive, but of
course you also need to deal with the cable.
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Thanks for the pointer Tim, I'll take a look. |
More of a question than an issue, so please bear with me.
I got into FPGAs from the MiSTer project, and was intrigued to see how large the (G2) Pano Logic’s FPGA is, even though it doesn’t have a conventional CPU to easily handle things like USB controllers. With that said, I’m definitely on the “end user” side of things. I don’t know anything about actually programming a FPGA, but I would enjoy trying out the NES core and any new developments that follow, just for the heck of it. I’m just trying to wrap my head around the process here.
So, let’s say get a G2 and I use this project with my Linux laptop to load the NES core into the main bitstream over my LAN. Will I then be able to do this a second time to change what’s in the main bitstream, assuming I leave the golden bitstream alone, or would I then need to open it up and take the JTAG route? I’ve never used JTAG either, but I’m fairly certain I’d be able to pull it off if I absolutely need to.
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