diff --git a/.github/dependabot.yaml b/.github/dependabot.yaml new file mode 100644 index 0000000..0cb7b34 --- /dev/null +++ b/.github/dependabot.yaml @@ -0,0 +1,8 @@ +version: 2 +updates: + - package-ecosystem: github-actions + directory: "/" + schedule: + interval: "weekly" + open-pull-requests-limit: 10 + rebase-strategy: disabled diff --git a/.github/workflows/eventlist.yml b/.github/workflows/eventlist.yml index 47989e7..0d3ec66 100644 --- a/.github/workflows/eventlist.yml +++ b/.github/workflows/eventlist.yml @@ -18,27 +18,22 @@ concurrency: group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: true -env: - go_version: 1.19.3 - jobs: build: if: | github.event_name != 'release' || startsWith(github.ref, 'refs/tags/tools/eventlist/') - strategy: - matrix: - os: [ubuntu-20.04] name: 'Build' - runs-on: ${{ matrix.os }} + runs-on: ubuntu-latest steps: - name: Check out repository code uses: actions/checkout@v3 - - name: Install go ${{ env.go_version }} + - name: Install Go uses: actions/setup-go@v3 with: - go-version: ${{ env.go_version }} + go-version-file: tools/eventlist/go.mod + check-latest: true - name: Initialize CodeQL if: github.event_name != 'release' @@ -47,20 +42,10 @@ jobs: languages: go queries: security-and-quality - - name: Create build folder - run: mkdir build - working-directory: ./tools/eventlist - - - name: Generate version information - run: | - go install github.com/josephspurrier/goversioninfo/cmd/goversioninfo - go generate - working-directory: ./tools/eventlist - - name: Build linux-amd64 executable run: | - GOOS=linux GOARCH=amd64 go build -o linux-amd64/eventlist ./.. - working-directory: ./tools/eventlist/build + ./make.sh build -os linux -arch amd64 -outdir build/linux-amd64 + working-directory: ./tools/eventlist - name: Perform CodeQL Analysis if: github.event_name != 'release' @@ -68,12 +53,12 @@ jobs: - name: Build remaining executables run: | - GOOS=linux GOARCH=arm64 go build -o linux-arm64/eventlist ./.. - GOOS=darwin GOARCH=amd64 go build -o darwin-amd64/eventlist ./.. - GOOS=darwin GOARCH=arm64 go build -o darwin-arm64/eventlist ./.. - GOOS=windows GOARCH=amd64 go build -o windows-amd64/eventlist.exe ./.. - working-directory: ./tools/eventlist/build - + ./make.sh build -os linux -arch arm64 -outdir build/linux-arm64 + ./make.sh build -os darwin -arch amd64 -outdir build/darwin-amd64 + ./make.sh build -os darwin -arch arm64 -outdir build/darwin-arm64 + ./make.sh build -os windows -arch amd64 -outdir build/windows-amd64 + ./make.sh build -os windows -arch arm64 -outdir build/windows-arm64 + working-directory: ./tools/eventlist - name: Archive eventlist uses: actions/upload-artifact@v3 @@ -115,23 +100,29 @@ jobs: retention-days: 1 if-no-files-found: error + - name: Archive eventlist + uses: actions/upload-artifact@v3 + with: + name: eventlist-windows-arm64 + path: ./tools/eventlist/build/windows-arm64 + retention-days: 1 + if-no-files-found: error + lint: if: github.event_name == 'pull_request' name: Lint timeout-minutes: 10 - strategy: - matrix: - os: [ubuntu-20.04] - runs-on: ${{ matrix.os }} + runs-on: ubuntu-latest steps: - - name: Setup go ${{ env.go_version }} - uses: actions/setup-go@v3 - with: - go-version: ${{ env.go_version }} - - name: Check out repository code uses: actions/checkout@v3 + - name: Install Go + uses: actions/setup-go@v3 + with: + go-version-file: tools/eventlist/go.mod + check-latest: true + - name: golangci-lint uses: golangci/golangci-lint-action@v3 with: @@ -142,18 +133,16 @@ jobs: format: if: github.event_name != 'pull_request' name: Format - strategy: - matrix: - os: [ubuntu-20.04] - runs-on: ${{ matrix.os }} + runs-on: ubuntu-latest steps: - name: Check out repository code uses: actions/checkout@v3 - - name: Install go ${{ env.go_version }} + - name: Install Go uses: actions/setup-go@v3 with: - go-version: ${{ env.go_version }} + go-version-file: tools/eventlist/go.mod + check-latest: true - name: Create build folder run: mkdir build @@ -167,25 +156,23 @@ jobs: vulnerability-check: name: "Vulnerability check" - strategy: - matrix: - platform: [ubuntu-latest] - runs-on: ${{ matrix.platform }} + runs-on: ubuntu-latest steps: - name: Check out repository code uses: actions/checkout@v3 - - name: Install go ${{ env.go_version }} + - name: Install Go uses: actions/setup-go@v3 with: - go-version: ${{ env.go_version }} + go-version-file: tools/eventlist/go.mod + check-latest: true - name: Install govulncheck - run: go install golang.org/x/vuln/cmd/govulncheck@latest + run: go install golang.org/x/vuln/cmd/govulncheck@v0.1.0 - name: Run vulnerability check run: | - echo "$(govulncheck ./... 2>&1 | tee vulnerability_report.out)" + echo "$(govulncheck ./... 2>&1 | tee vulnerability_report.out)" test -n "$(grep 'No vulnerabilities found.' vulnerability_report.out)" working-directory: ./tools/eventlist @@ -196,17 +183,18 @@ jobs: needs: [ build ] strategy: matrix: - os: [ubuntu-20.04, windows-2019, macos-12] + os: [ubuntu-latest, windows-latest, macos-latest] name: 'Test (${{ matrix.os }})' runs-on: ${{ matrix.os }} steps: - name: Check out repository code uses: actions/checkout@v3 - - name: Install go ${{ env.go_version }} + - name: Install Go uses: actions/setup-go@v3 with: - go-version: ${{ env.go_version }} + go-version-file: tools/eventlist/go.mod + check-latest: true - name: Create build folder run: mkdir build @@ -231,24 +219,24 @@ jobs: if: github.event_name != 'release' name: "Publish Tests Results" needs: [ test ] - runs-on: ubuntu-20.04 + runs-on: ubuntu-latest steps: - name: Download unit test report windows uses: actions/download-artifact@v3 with: - name: unit-test-result-windows-2019 + name: unit-test-result-windows-latest path: testreports/ - name: Download unit test report linux uses: actions/download-artifact@v3 with: - name: unit-test-result-ubuntu-20.04 + name: unit-test-result-ubuntu-latest path: testreports/ - name: Download unit test report macos uses: actions/download-artifact@v3 with: - name: unit-test-result-macos-12 + name: unit-test-result-macos-latest path: testreports/ - name: publish test results @@ -263,19 +251,17 @@ jobs: github.event_name != 'release' || startsWith(github.ref, 'refs/tags/tools/eventlist/') needs: [ build ] - strategy: - matrix: - os: [ubuntu-20.04] name: 'Coverage check' - runs-on: ${{ matrix.os }} + runs-on: ubuntu-latest steps: - name: Check out repository code uses: actions/checkout@v3 - - name: Install go ${{ env.go_version }} + - name: Install Go uses: actions/setup-go@v3 with: - go-version: ${{ env.go_version }} + go-version-file: tools/eventlist/go.mod + check-latest: true - name: Create build folder run: mkdir build @@ -309,16 +295,19 @@ jobs: mkdir -p release/eventlist-darwin-amd64/docs mkdir -p release/eventlist-darwin-arm64/docs mkdir -p release/eventlist-windows-amd64/docs + mkdir -p release/eventlist-windows-arm64/docs cp LICENSE release/eventlist-linux-amd64/ cp LICENSE release/eventlist-linux-arm64/ cp LICENSE release/eventlist-darwin-amd64/ cp LICENSE release/eventlist-darwin-arm64/ cp LICENSE release/eventlist-windows-amd64/ + cp LICENSE release/eventlist-windows-arm64/ cp tools/eventlist/docs/* release/eventlist-linux-amd64/docs/ cp tools/eventlist/docs/* release/eventlist-linux-arm64/docs/ cp tools/eventlist/docs/* release/eventlist-darwin-amd64/docs/ cp tools/eventlist/docs/* release/eventlist-darwin-arm64/docs/ cp tools/eventlist/docs/* release/eventlist-windows-amd64/docs/ + cp tools/eventlist/docs/* release/eventlist-windows-arm64/docs/ - name: Download eventlist linux uses: actions/download-artifact@v3 @@ -350,9 +339,20 @@ jobs: name: eventlist-windows-amd64 path: release/eventlist-windows-amd64/ + - name: Download eventlist windows + uses: actions/download-artifact@v2 + with: + name: eventlist-windows-arm64 + path: release/eventlist-windows-arm64/ + - name: Zip folders run: | + # Ensure executable eventlist due to this limitation + # https://github.com/actions/upload-artifact#permission-loss + chmod +x */eventlist* + zip -r eventlist-windows-amd64.zip eventlist-windows-amd64/eventlist.exe eventlist-windows-amd64/docs eventlist-windows-amd64/LICENSE + zip -r eventlist-windows-arm64.zip eventlist-windows-arm64/eventlist.exe eventlist-windows-arm64/docs eventlist-windows-arm64/LICENSE tar -czvf eventlist-linux-amd64.tar.gz eventlist-linux-amd64/eventlist eventlist-linux-amd64/docs eventlist-linux-amd64/LICENSE tar -czvf eventlist-linux-arm64.tar.gz eventlist-linux-arm64/eventlist eventlist-linux-arm64/docs eventlist-linux-arm64/LICENSE tar -czvf eventlist-darwin-amd64.tar.gz eventlist-darwin-amd64/eventlist eventlist-darwin-amd64/docs eventlist-darwin-amd64/LICENSE @@ -362,6 +362,7 @@ jobs: - name: Calculate checksums run: | sha256sum eventlist-windows-amd64.zip --text > eventlist-checksums.txt + sha256sum eventlist-windows-arm64.zip --text >> eventlist-checksums.txt sha256sum eventlist-linux-amd64.tar.gz --text >> eventlist-checksums.txt sha256sum eventlist-linux-arm64.tar.gz --text >> eventlist-checksums.txt sha256sum eventlist-darwin-amd64.tar.gz --text >> eventlist-checksums.txt diff --git a/.github/workflows/gh-pages.yml b/.github/workflows/gh-pages.yml new file mode 100644 index 0000000..86c9f13 --- /dev/null +++ b/.github/workflows/gh-pages.yml @@ -0,0 +1,46 @@ +# Simple workflow for deploying static content to GitHub Pages +name: Deploy static content to GitHub Pages + +on: + # Runs on pushes targeting the default branch + push: + branches: [gh-pages] + + # Allows you to run this workflow manually from the Actions tab + workflow_dispatch: + +# Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages +permissions: + contents: read + pages: write + id-token: write + +# Allow only one concurrent deployment, skipping runs queued between the run in-progress and latest queued. +# However, do NOT cancel in-progress runs as we want to allow these production deployments to complete. +concurrency: + group: "pages" + cancel-in-progress: false + +jobs: + # Single deploy job since we're just deploying + deploy: + environment: + name: github-pages + url: ${{ steps.deployment.outputs.page_url }} + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + + - name: Setup Pages + uses: actions/configure-pages@v3 + + - name: Upload artifact + uses: actions/upload-pages-artifact@v1 + with: + # Upload entire repository + path: '.' + + - name: Deploy to GitHub Pages + id: deployment + uses: actions/deploy-pages@v1 diff --git a/.github/workflows/pack.yaml b/.github/workflows/pack.yaml index 1be0650..39ec242 100644 --- a/.github/workflows/pack.yaml +++ b/.github/workflows/pack.yaml @@ -5,16 +5,26 @@ on: branches: [ main ] paths: - '.github/workflows/pack.yml' + - 'ARM.CMSIS-View.pdsc' + - 'gen_pack.sh' - 'Documentation/**' - 'Doxygen/**' - 'EventRecorder/**' + - 'Examples/**' + - 'Fault/**' + - 'Schema/**' pull_request: branches: [ main ] paths: - '.github/workflows/pack.yml' + - 'ARM.CMSIS-View.pdsc' + - 'gen_pack.sh' - 'Documentation/**' - 'Doxygen/**' - 'EventRecorder/**' + - 'Examples/**' + - 'Fault/**' + - 'Schema/**' release: types: [published] diff --git a/.gitignore b/.gitignore index aa3f276..ea804d3 100644 --- a/.gitignore +++ b/.gitignore @@ -6,14 +6,27 @@ *.so *.dylib -Local_Release +# macOS +.DS_Store + +# Generated Files Documentation/html -Doxygen/view.dxy +/Doxygen/src/history.txt +/Doxygen/view.dxy /PACK.xsd -/output/ARM.CMSIS-View.1.1.2-dev4+ge8d94f5.pack /output /build -/Doxygen/src/history.md +/Examples/**/*.cbuild.yml +/Examples/**/*.cprj +/Examples/**/RTE/_**/* +/Examples/**/.clangd +/Examples/**/*.cbuild-idx.yml +/Examples/**/*.uvgui*.* +/Examples/**/DebugConfig/*.dbgconf +/Examples/**/out +/Examples/**/tmp +/Examples/**/Listings +/Examples/**/Objects # Test binary, built with `go test -c` *.test @@ -29,3 +42,4 @@ __debug_bin *.bak *.syso *.log +*~ diff --git a/ARM.CMSIS-View.pdsc b/ARM.CMSIS-View.pdsc index e0e1ac0..6ccf8b9 100644 --- a/ARM.CMSIS-View.pdsc +++ b/ARM.CMSIS-View.pdsc @@ -1,69 +1,135 @@ - + ARM CMSIS-View Debugger visualization of software events and statistics - http://www.keil.com/pack/ + https://www.keil.com/pack/ LICENSE https:/github.com/arm-software/CMSIS-View.git Active development ... + Event Recorder: + - Update conditions to prevent simultaneous selection of CMSIS-View::Event Recorder and Compiler::Event Recorder components + - Update Event Statistic example to support CMSIS-Toolbox v2.0.0 + Fault component: + - Extend section name for fault information, for easier absolute addressing via the linker script + - Update Fault example for Cortex-M33 (B-U585I-IOT02A) with improved GCC support and add support for building with CMSIS-Toolbox v2.0.0 + - Update Fault example for AVH Cortex-M7 to support CMSIS-Toolbox v2.0.0 + + Debugger visualization of software events and statistics + + - Cortex-M processor based device: one of CM0, CM0+, CM1, CM3, CM4, CM7, SC000, SC3000, ARMv8M Baseline and Mainline, ARMv8.1M Mainline + Cortex-M processor based device: Cortex-M0/M0+/M1/M3/M4/M7/M23/M33/M35P/M55/M85, ARMV8MBL/ML, Star-MC1, SC000/300 - + + + - - - - + + + + + + + Conditions for Event Recorder + + + + + Conditions for Fault Record + + + - - Event Recording and Component Viewer via Debug Access Port (DAP) + + Event Recording via Debug Access Port (DAP) - #define RTE_Compiler_EventRecorder - #define RTE_Compiler_EventRecorder_DAP + #define RTE_CMSIS_View_EventRecorder + #define RTE_CMSIS_View_EventRecorder_DAP - + - - Event Recording and Component Viewer via Debug Access Port (DAP) and Semihosting + + Event Recording via Debug Access Port (DAP) and Semihosting - #define RTE_Compiler_EventRecorder - #define RTE_Compiler_EventRecorder_DAP - #define RTE_Compiler_EventRecorder_Semihosting + #define RTE_CMSIS_View_EventRecorder + #define RTE_CMSIS_View_EventRecorder_DAP + #define RTE_CMSIS_View_EventRecorder_Semihosting - + + + Fault Storage + + #define RTE_CMSIS_View_Fault_Storage + + + + + + + + + + + Fault Record (Output decoded fault information via EventRecorder) + + #define RTE_CMSIS_View_Fault_Record + + + + + + + + + + + Example that shows the usage of start/stop events for statistical code profiling with the Event Statistics window. + + + + + + + Example that shows the usage of Fault component on an Cortex-M33 with TrustZone. + + + + + + + diff --git a/Doxygen/check_links.sh b/Doxygen/check_links.sh index a6b7033..b20e52a 100755 --- a/Doxygen/check_links.sh +++ b/Doxygen/check_links.sh @@ -3,7 +3,7 @@ set -o pipefail DIRNAME=$(dirname $(realpath $0)) -REQUIRED_GEN_PACK_LIB="0.6.0" +REQUIRED_GEN_PACK_LIB="0.7.0" ############ gen-pack library ########### diff --git a/Doxygen/gen_doc.sh b/Doxygen/gen_doc.sh index edda54c..356eb85 100755 --- a/Doxygen/gen_doc.sh +++ b/Doxygen/gen_doc.sh @@ -10,24 +10,11 @@ set -o pipefail # Set version of gen pack library -REQUIRED_GEN_PACK_LIB="0.6.0" +REQUIRED_GEN_PACK_LIB="0.7.0" DIRNAME=$(dirname $(readlink -f $0)) -DOXYGEN=$(which doxygen 2>/dev/null) REQ_DXY_VERSION="1.9.2" - -if [[ ! -f "${DOXYGEN}" ]]; then - echo "Doxygen not found!" >&2 - echo "Did you miss to add it to PATH?" - exit 1 -else - version=$("${DOXYGEN}" --version | sed -E 's/.*([0-9]+\.[0-9]+\.[0-9]+).*/\1/') - echo "Doxygen is ${DOXYGEN} at version ${version}" - if [[ "${version}" != "${REQ_DXY_VERSION}" ]]; then - echo "Doxygen required to be at version ${REQ_DXY_VERSION}!" >&2 - exit 1 - fi -fi +PACK_CHANGELOG_MODE="tag" ############ DO NOT EDIT BELOW ########### @@ -62,6 +49,7 @@ function load_lib() { load_lib find_git +find_doxygen "${REQ_DXY_VERSION}" if [ -z $VERSION ]; then VERSION_FULL=$(git_describe "pack/") @@ -76,8 +64,8 @@ sed -e "s/{projectNumber}/${VERSION}/" view.dxy.in > view.dxy git_changelog -f html -p "pack/" > src/history.txt -echo "\"${DOXYGEN}\" view.dxy" -"${DOXYGEN}" view.dxy +echo "\"${UTILITY_DOXYGEN}\" view.dxy" +"${UTILITY_DOXYGEN}" view.dxy if [[ $2 != 0 ]]; then mkdir -p "${DIRNAME}/../Documentation/html/search/" diff --git a/Doxygen/src/EventRecorder.md b/Doxygen/src/EventRecorder.md index 4b87fe1..efde4fb 100644 --- a/Doxygen/src/EventRecorder.md +++ b/Doxygen/src/EventRecorder.md @@ -1,4 +1,4 @@ -# Event Recorder {#evr} +# Event Recorder {#evr} ## Overview {#about_evr} @@ -10,7 +10,7 @@ of the debugger. During program execution, the debugger reads the content of the **event buffer** using a standard debug unit that is connected via JTAG or SWD to the CoreSight Debug Access Port (DAP). The **Event Recorder** requires no trace hardware and can be therefore used on any Cortex-M processor. -![Event Recorder](./images/EventRecorderOverview.png "Event Recorder") +![Event Recorder](./images/EventRecorderOverview.png "Event Recorder block diagram with exemplary output in an IDE") - \subpage er_theory explains in details how the Event Recorder collects event data, generates time stamps, and transfers this information via a debug unit to a host computer. - \subpage er_use provides instructions on how to enable Event Recorder in a project. @@ -18,29 +18,29 @@ During program execution, the debugger reads the content of the **event buffer** **Benefits of the Event Recorder:** - Visibility to the dynamic execution of an application at little (memory) cost. - Adding RTOS awareness to a development tool does not require complex DLL programming. - - For Arm Cortex-M3/M4/M7/M33 processor based devices, Event Recorder functions will not disable interrupts. + - For Arm Cortex-M3/M4/M7/M33/M55/M85 processor based devices, Event Recorder functions will not disable interrupts. - Adding \ref printf_redirect "printf re-targeting" for devices without - ITM, such as Arm Cortex-M0/M0+/M23. - - Fast time-deterministic execution of event recorder functions with minimal code and timing overhead. + ITM, such as Arm Cortex-M0/M0+/M23. + - Fast time-deterministic execution of event recorder functions with minimal code and timing overhead. - No need for a debug or release build as the event annotations can remain in production code. - Saving the event data in local memory ensures fast recording. - Collecting the data from the on-chip memory is done using simple read commands. These commands work on all Cortex-M - processor based devices and require only JTAG or - SWD connectivity to the debug adapter. - - Using the DWT Cycle Count register for creating time stamps reduces code overhead (available on Arm Cortex-M3/M4/M7/M33). + processor based devices and require only JTAG or + SWD connectivity to the debug adapter. + - Using the DWT Cycle Count register for creating time stamps reduces code overhead (available on Arm Cortex-M3/M4/M7/M33/M55/M85). \page er_theory Theory of operation This section describes how the **Event Recorder** collects event data, generates time stamps, and transfers this information via a debug unit to a host computer. The **Event Recorder** is implemented in the target application using the software component -**Compiler:Event Recorder** which adds the source file *EventRecorder.c* to the application. Each event is stored in a 16-byte structure that is composed of a 16-bit *id*, 32-bit time stamp, two 32-bit data values and consistency check values. +**CMSIS-View:Event Recorder** which adds the source file *EventRecorder.c* to the application. Each event is stored in a 16-byte structure that is composed of a 16-bit *id*, 32-bit time stamp, two 32-bit data values and consistency check values. -To store these events, a circular buffer is provided that can store a minimum of 8 events. The size of this circular buffer is configurable with the +To store these events, a circular buffer is provided that can store a minimum of 8 events. The size of this circular buffer is configurable with the `#define EVENT_RECORD_COUNT`. ## Event id {#event_id} - + The \ref EventRecorder_Data functions get a parameter `id` that is composed of *level*, *component number*, and *message number* as shown below: | *id* | bits | Description @@ -55,8 +55,8 @@ The *level* specifies the category of the event message and can be used for filt | *level* | Message relates to ... |----------------------------|---------------------------------------------------- | \ref EventLevelError = 0 | Run-time error -| \ref EventLevelAPI = 1 | API function call -| \ref EventLevelOp = 2 | Internal operation +| \ref EventLevelAPI = 1 | API function call +| \ref EventLevelOp = 2 | Internal operation | \ref EventLevelDetail = 3 | Additional detailed information of operations The *component number* specifies the software component that the event message belongs to and can be also used for filtering: @@ -65,7 +65,8 @@ The *component number* specifies the software component that the event message b |---------------------------|---------------------------------------------------- | 0x0 .. 0x3F (0 .. 63) | software components of the user application | 0x40 .. 0x7F (64 .. 127) | third party middleware components -| 0x80 .. 0xEE (128 .. 238) | MDK middleware components +| 0x80 .. 0xED (128 .. 237) | MDK-Middleware components +| 0xEE (238) | Fault component | 0xEF (239) | Start/Stop events for Event Statistic information | 0xF0 .. 0xFC (240 .. 253) | RTOS kernel | 0xFD (253) | Inter-process communication layer (multiprocessor systems) @@ -79,15 +80,18 @@ The following sections describe: ## Configuration {#er_config} -Selecting the software component **Compiler:Event Recorder** to a project will add the file *EventRecorderConf.h* that is used to define the configuration parameters of the Event Recorder. It uses Configuration Wizard Annotations that show a graphical representation of the settings in MDK: +Adding the software component **CMSIS-View:Event Recorder** to a project will copy the file *EventRecorderConf.h* into the project that is used to define the configuration parameters of the **Event Recorder**. It uses [Configuration Wizard Annotations](https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/configWizard.html). + +For example, IDEs can show a graphical representation of the settings: ![EventRecorderConf.h in Configuration Wizard View](./images/config_wizard.png "EventRecorderConf.h in Configuration Wizard View") -
+  + |Option |\#define |Description |------------------------------------|-------------------------|----------- |Number of Records |`EVENT_RECORD_COUNT` |Specifies the number or records stored in the Event Record Buffer. Each record is 16 bytes. -|Time Stamp Source |`EVENT_TIMESTAMP_SOURCE` |Specifies the timer that is used as time base. Refer to Time stamp source below for more information. +|Time Stamp Source |`EVENT_TIMESTAMP_SOURCE` |Specifies the timer that is used as time base. Refer to **Time stamp source** below for more information. |Time Stamp Clock Frequency [Hz] |`EVENT_TIMESTAMP_FREQ` |Specifies the initial timer clock frequency. \note @@ -111,7 +115,7 @@ The following time stamp sources can be selected: Invalid Time Stamp Source selected in EventRecorderConf.h! ``` - When using the **CMSIS-RTOS2 System Timer**, it is strongly recommended to set up the - Time Stamp Clock Frequency [Hz] (see above) to the correct value to avoid display problems in the Event Recorder + **Time Stamp Clock Frequency [Hz]** (see above) to the correct value to avoid display problems in the Event Recorder and System Analyzer windows. ### Configure for targets without DWT Cycle Counter{#noDWT} @@ -126,8 +130,6 @@ For applications that do not use the SysTick timer, you may configure EventRecor #define EVENT_TIMESTAMP_FREQ 25000000U // processor core clock (input frequency to SysTick) ``` -The example project \ref scvd_CM0_SysTick shows this configuration. - **CMSIS-RTOS2 System Timer** For applications that use a CMSIS-RTOS2 compliant RTOS (SysTick timer used by RTOS), you may configure EventRecorderConf.h with: @@ -136,50 +138,47 @@ For applications that use a CMSIS-RTOS2 compliant RTOS (SysTick timer used by RT #define EVENT_TIMESTAMP_FREQ 25000000U // processor core clock (input frequency to SysTick) ``` -The example project \ref scvd_CM0_RTOS shows this configuration. - ### DWT Cycle Counter with µVision simulator{#simulation} The DWT Cycle Counter can be simulated with the following debug initialization file, for example Debug_Sim.ini: ``` MAP 0xE0001000, 0xE0001007 READ WRITE - + signal void DWT_CYCCNT (void) { while (1) { rwatch(0xE0001004); _WWORD(0xE0001004, states); } } - + DWT_CYCCNT() ``` -Refer to the \ref MyComponent to see how it is used in a µVision project. - ## Resource requirements{#er_req} -**Technical data of Event Recorder firmware** +### Technical data of Event Recorder firmware Target: Cortex-M3 using DWT cycle counter as timer -|Parameter | ARMCC V5.06 | ARMCC V5.06 | ARMCC V6.13.1 | ARMCC V6.13.1 -|:---------------------------------|--------------|--------------|---------------|-------------- -|Compiler options | -O3 | -O3 -Otime | -Os | -O3 -|ROM size | < 1.5k bytes | < 2.0k bytes | < 1.7k bytes | < 3.4k bytes -|RAM size @8 records (min) | 292 bytes | 292 bytes | 292 bytes | 292 bytes -|RAM size @64 records (default) | 1188 bytes | 1188 bytes | 1188 bytes | 1188 bytes -|\ref EventRecord2 (id+8bytes) | 256 cycles | 238 cycles | 197 cycles | 184 cycles -|\ref EventRecord4 (id+16bytes) | 448 cycles | 429 cycles | 343 cycles | 319 cycles -|\ref EventRecordData (id+8bytes) | 346 cycles | 307 cycles | 276 cycles | 252 cycles -|\ref EventRecordData (id+16bytes) | 540 cycles | 507 cycles | 425 cycles | 397 cycles -|\ref EventRecordData (id+24bytes) | 714 cycles | 683 cycles | 554 cycles | 519 cycles -|\ref EventRecordData (id+32bytes) | 888 cycles | 862 cycles | 685 cycles | 643 cycles - -\note ROM size is specified for image with all Event Recorder functions being used. -\note RAM size can be calculated as `164 + 16 * (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)`. -\note Timing measured in simulator (zero cycle memory, no interrupts). Function parameter in application is not considered. - -**Usage of records by Event Recorder functions** +|Parameter | ARMCC V6.13.1 | ARMCC V6.13.1 +|:---------------------------------|---------------|-------------- +|Compiler options | -Os | -O3 +|ROM size | < 1.7k bytes | < 3.4k bytes +|RAM size @8 records (min) | 292 bytes | 292 bytes +|RAM size @64 records (default) | 1188 bytes | 1188 bytes +|\ref EventRecord2 (id+8bytes) | 197 cycles | 184 cycles +|\ref EventRecord4 (id+16bytes) | 343 cycles | 319 cycles +|\ref EventRecordData (id+8bytes) | 276 cycles | 252 cycles +|\ref EventRecordData (id+16bytes) | 425 cycles | 397 cycles +|\ref EventRecordData (id+24bytes) | 554 cycles | 519 cycles +|\ref EventRecordData (id+32bytes) | 685 cycles | 643 cycles + +\note +- ROM size is specified for image with all Event Recorder functions being used. +- RAM size can be calculated as `164 + 16 * (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)`. +- Timing was measured in simulator (zero cycle memory, no interrupts). Function parameter in application is not considered. + +### Usage of records by Event Recorder functions |Function | Number of Records used |:---------------------------------|----------------------------- @@ -187,9 +186,10 @@ Target: Cortex-M3 using DWT cycle counter as timer |\ref EventRecord4 | 2 |\ref EventRecordData | (event data length + 7) / 8 + \page er_use Using Event Recorder -The following steps enable the MDK debugger views for static information \a and dynamic events. +\note The following steps explain how to enable views for static information \a and dynamic events in the µVision debugger. Other tools might use different ways to accomplish this. **For User Code:** -# \ref Add_Event_Recorder. @@ -199,9 +199,9 @@ The following steps enable the MDK debugger views for static information \a and -# Add \ref Event_Annotations in the C source to be able to stream dynamic event information. -# Create an \ref SCVD_Format "SCVD file" to \ref Format_Event_Information that matches with application code. -**For MDK-Middleware, Keil RTX5, and FreeRTOS:** +**For Pre-annotated Software Components:** -The software packs for MDK Middleware, CMSIS, CMSIS-FreeRTOS already contain the relevant *.SCVD files and the related event annotations in the C source code. +The software packs for MDK-Middleware, CMSIS, CMSIS-FreeRTOS already contain the relevant *.SCVD files and the related event annotations in the C source code. -# \ref Add_Event_Recorder to the project. -# Select a \ref Debug_Variants "Debug" variant for the middleware component to enable event information (for RTX5 select **Source** variant). @@ -209,20 +209,20 @@ The software packs for MDK Middleware, CMSIS, CMSIS-FreeRTOS already contain the ## Add Event Recorder Component{#Add_Event_Recorder} To use the Event Recorder in an application, you need to: - - Select the software component Compiler:Event Recorder using the RTE management dialog.
+ - Select the software component **CMSIS-View:Event Recorder** using the RTE management dialog.
![Select Event Recorder](./images/SelEventRecorder.png) \note Usually, you select the **DAP** variant. If you are using a simulation model (FastModel or Arm Virtual Hardware), you can select \ref er_semihosting to write the Event Recorder data into a file on the PC. - Include the EventRecorder.h header file and add the event recorder initialization function to the source code: - ``` + ```C : - #include "EventRecorder.h" // Keil::Compiler:Event Messaging + #include "EventRecorder.h" // ARM::CMSIS-View:Event Recorder : int main (void) { : HAL_Init(); // configure hardware abstraction layer - SystemClock_Config(); // configure system clock - MemoryBus_Config(); // configure external memory bus + SystemClock_Config(); // configure system clock + MemoryBus_Config(); // configure external memory bus EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder : // other application code @@ -232,15 +232,14 @@ To use the Event Recorder in an application, you need to: \note - By default, the Event Recorder uses the DWT Cycle Counter as a time stamp source. This is not available on Cortex-M0/M0+/M23. Change the \ref er_config "configuration" to use an alternative timer instead. -- For Keil RTX5 (version 5.4.0 and above), no call to \ref EventRecorderInitialize is required. Instead enable Event Recorder Configuration - Global Initialization in the RTX_Config.h file. Refer to the +- For Keil RTX5 (version 5.4.0 and above), no call to \ref EventRecorderInitialize is required. Instead enable **Event Recorder Configuration - Global Initialization** in the RTX_Config.h file. Refer to the CMSIS-RTOS2 - RTX v5 Implementation for more information. ## Locate Event Recorder in uninitialized memory{#place_uninit_memory} For uninterrupted recording of program resets, the RAM for the Event Recorder component should be placed to a memory -region that is not cleared (or initialized) by a system restart (reset), and which differs from the RAM area that is used for -Flash programming. +region that is not cleared (or initialized) by a system restart (reset). \note Make sure that you use normal, non-cacheable, and non-shareable memory for Event Recorder data. @@ -252,30 +251,67 @@ The memory required for the Event Recorder data is calculated with the formula: ``` In this example we configure `0x800` bytes (as it is easier) which can hold more than 64 records. -### Create memory region{#evr_create_mem} +### Create memory region {#evr_create_mem} -To setup this uninitialized RAM, use either a -linker script -or configure it in µVision following these steps: +To setup this uninitialized RAM, use either \ref evr_create_mem_ls or \ref evr_create_mem_uv procedure. + +#### Create memory region using linker script {#evr_create_mem_ls} + +If the linker script does not contain provisions for uninitialized memory section then, for respective toolchain, add the necessary section like described below: + +##### Arm Compiler {#evr_create_mem_ls_ac} + +for the **Arm Compiler** toolchain add the following code snippet to the linker script (.sct file), in the part specifying RAM sections (usually before Heap section): + + ``` + RW_NOINIT UNINIT 0x800 { + * (.bss.noinit*) + } + ``` + +> Note: \ is the physical address in RAM where the section will start + +> Note: 0x800 is the size of the section, adjust that as necessary + +##### GCC {#evr_create_mem_ls_gcc} + +for the **GCC** toolchain add the following code snippet to the linker script (.ld file), in the part specifying RAM sections (usually before Heap section): + + ``` + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit*) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + ``` + +> Note: this code snippet expects defined RAM memory region, if RAM region is not defined then adapt the script accordingly + +### Create memory region using µVision {#evr_create_mem_uv} + +To setup this uninitialized RAM in the µVision, follow the steps below: 1. In the **Options for Target** dialog, on the **Utilities** tab, click on **Settings** for "Use Target Driver for Flash Programming". Note the "RAM for Algorithm" area:
![RAM for Algorithm"](./images/ram_for_algorithm_area.png) - + 2. In the **Options for Target** dialog, define a Read/Write memory area that is not initialized and which does not overlap with the area from the first step.
For example, split IRAM1 into two regions. Reduce size of IRAM1 by 0x800 and create an IRAM2 area with start 0x2001F800 and size 0x800. Enable **NoInit** for this IRAM2 region.
![Create RAM area](./images/create_iram2.png) -3. In the Options for Component Class 'Compiler' dialog (opens with right-click on **EventRecorder.c** in the **Project** window), on the **Memory** tab, assign **Zero Initialized Data** to the IRAM2 region. +3. In the **Options for Component Class 'CMSIS-View'** dialog (opens with right-click on **EventRecorder.c** in the **Project** window), on the **Memory** tab, assign **Zero Initialized Data** to the IRAM2 region. ![Create RAM area](./images/er_memory_location.png) - + 4. Build the application to place the Event Recorder data buffers to uninitialized RAM. You may verify the generated scatter file: ``` ; ************************************************************* ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* - + LR_IROM1 0x00000000 0x00040000 { ; load region size_region ER_IROM1 0x00000000 0x00040000 { ; load address = execution address *.o (RESET, +First) @@ -290,21 +326,20 @@ For example, split IRAM1 into two regions. Reduce size of IRAM1 by 0x800 and cre } } ``` - + \note - If the Event Recorder data buffer is not in uninitialized memory, the **Command** window of the debugger displays: "Warning: Event Recorder not located in uninitialized memory!". -- Knowledgebase article 4012 explains how to create - custom memory areas in uVision. +- Knowledgebase article 4012 explains how to create custom memory areas in uVision. - If your RAM is not big enough to separate the Event Recorder area from the Flash programming area, make sure that you enable "Reset and Run" for the **Download Function**: \image html reset_and_run.png - If this still produces broken Event Recorder records after a reset, a power-cycle of the target system will help. - + ## Time Stamp Settings{#initial_timestamp} -To avoid display problems in System Analyzer, set the Time Stamp Clock Frequency [Hz] to the initially expected +To avoid display problems in System Analyzer, set the **Time Stamp Clock Frequency [Hz]** to the initially expected value: ![Event Recorder Configuration Wizard](./images/config_wizard.png) @@ -331,35 +366,35 @@ To to stream dynamic event information, insert calls to the \ref EventRecorder_D - \ref EventRecord4 to record up to four 32-bit integer values. These \ref EventRecorder_Data functions receive as first parameter an *id* event identifier used for filtering and displaying. The macro \ref EventID may be used to compose *id* values to include *level* and *component* numbers. - + **Example:** -``` -#include "EventRecorder.h" // Keil::Compiler:Event Messaging - +```C +#include "EventRecorder.h" // ARM::CMSIS-View:Event Recorder + int some_error = 0; // error flag char string[10] = "MyTest"; // some test string - + void MyFunction (int parameter) { EventRecord2 (1+EventLevelAPI, parameter, 0); // Event at Start ; if (some_error) { EventRecord2 (2+EventLevelError, 0, 0); // Event at Error - return; + return; } EventRecordData (3+EventLevelOp, string, sizeof(string)); // Event at Finish return; } - + int main (void) { EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder - + MyFunction (0x10); some_error = 1; // set error flag MyFunction (0x60); } ``` -When executing this example in the µVision debugger, use the menu command View - Analysis Windows - Event Recorder to +When executing this example in the µVision debugger, use the menu command **View - Analysis Windows - Event Recorder** to open the Event Recorder window. This should show the following output: ![Output shown in Event Recorder window](./images/EventOutput1.png "Output shown in Event Recorder window") @@ -370,22 +405,22 @@ You may create an \ref SCVD_Format "*.SCVD (Software Component View Description) matches the application. The event output is created using the \ref elem_events. **SCVD file example** -``` +```xml - + - + - - + + - + ``` @@ -397,34 +432,34 @@ The Event Recorder displays the events as shown below. ![Event Recorder output formatted with *.SCVD file](./images/EventOutput2.png "Event Recorder output formatted with *.SCVD file") -The described groups and events also show up in the filter dialog. +The described groups and events also show up in the filter dialog. ![Event Recorder Filter dialog](./images/EventRecorderFilter.png "Event Recorder Filter dialog") ## Software Component Variants{#Debug_Variants} -The software packs for MDK Middleware and CMSIS already contain SCVD files that match the related event annotations in the C -source code. However, you need to select the right component Variant. For MDK Middleware, you need to select +The software packs for MDK-Middleware and CMSIS already contain SCVD files that match the related event annotations in the C +source code. However, you need to select the right component **Variant**. For MDK-Middleware, you need to select the **Debug** variants, whereas for Keil RTX5, you need to add the **Source** variant. - -The example below enables event recording for the MDK-Middleware File System component: + +The example below enables event recording for the MDK-Middleware **File System** component: ![Select debug variant](./images/SelSWComp.png "Select debug variant") ## Redirecting printf output{#printf_redirect} The Event Recorder can be used to retarget printf output. This is especially interesting for targets without -ITM, such as Cortex-M0/M0+/M23. Steps to enable this: - -# In the Manage Run-Time Environment window, set the component Compiler:I/O:STDOUT to use **Variant** *EVR*. - -# Select the component Compiler:Event Recorder or use the **Resolve** button. +ITM, such as Cortex-M0/M0+/M23. Steps to enable this: + -# In the Manage Run-Time Environment window, set the component **CMSIS-Compiler:I/O:STDOUT** to use **Variant** *EVR*. + -# Select the component **CMSIS-View:Event Recorder** or use the **Resolve** button. -# In the user code, include *EventRecorder.h* and call the `EventRecorderInitialize()` function in `main()`. - -Refer to the example Retarget STDOUT via Event Recorder in "I/O Retargeting". + +Refer to the example [Retarget STDOUT via Event Recorder](https://arm-software.github.io/CMSIS-Compiler/latest/Retarget_Examples_er.html). ## Event filtering{#er_filtering} Filtering for events reduces the amount of data transmitted from the target to the debugger. To filter for events, use the -button Configure Target Event Recording: +button **Configure Target Event Recording**: \image html filter_button.png @@ -440,19 +475,16 @@ a host computer that is running a debugger. Examples of these facilities include keyboard input, screen output, and disk I/O. For example, you can use this mechanism to enable functions in the C library, such as `printf` and `scanf`, to use the screen and keyboard of the host instead of having a screen and keyboard on the target system. -With the Event Recorder, you can use semihosting with models to write the events into a file on your PC. This works with Arm -FastModels, Fixed Virtual Platforms, and Virtual Hardware alike. - -The file that is written is called *EventRecorder.log* and is a binary file that is available in the root directory of the µVision project. A tool to read and decode the binary data is being developed. +With the Event Recorder, you can use semihosting with models to write the events into a file on your PC. This works with [Arm +Fast Models](https://developer.arm.com/Tools%20and%20Software/Fast%20Models), [Arm Fixed Virtual Platforms](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms), and [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware) alike. -While the file is written to the hard drive of your PC, you can still use the Event Recorder window in µVision to see the -events coming in. +The file that is written is called *EventRecorder.log* and is a binary file that is available in the root directory of your project. Use \ref evntlst to read and decode the binary data. \note -- The semihosting variant will not work with real target hardware. Instead, program execution will hit a breakpoint and stop - there. - Your model needs to be configured for semihosting (refer to the documentation of your modeling technology on how to do that). - You can specify a different name for the log file by specifying a define called `EVENT_LOG_FILENAME`. -- Once you start a new debug session, the log file will be overwritten. While in debug, new messages will be appended to the +- In µVision, once you start a new debug session, the log file will be overwritten. While in debug, new messages will be appended to the currently open log file. +- In µVision, the semihosting variant will not work with real target hardware. Instead, program execution will hit a breakpoint and stop there. +- In µVision, you can still use the Event Recorder window in µVision to see the events coming in while the file is written to the hard drive of your PC. diff --git a/Doxygen/src/EventRecorder_fn.txt b/Doxygen/src/EventRecorder_fn.txt index 67b17fe..aacd034 100644 --- a/Doxygen/src/EventRecorder_fn.txt +++ b/Doxygen/src/EventRecorder_fn.txt @@ -162,8 +162,6 @@ The macro \ref EventID generates an \em id value that combines \em level, \em co The \em level value should be set to \ref EventLevelError, \ref EventLevelAPI, \ref EventLevelOp, or \ref EventLevelDetail. The \em id value is used by the functions \ref EventRecordData, \ref EventRecord2, and \ref EventRecord4. - -The example \ref MyComponent shows the usage of \ref EventID in combination with a help system. */ /** @@ -293,7 +291,7 @@ EventRecorderEnable (EventRecordError+EventRecordAPI, // Record group A and \endcode Code example - - Refer to \ref es_use + - Refer to \ref scvd_evt_stat */ @@ -416,7 +414,7 @@ This function is called by \ref EventRecorderInitialize to initialize the timer For time stamp source \ref TimeStampSource "User Timer (Power-On Reset)" this function is only called for the first call to \ref EventRecorderInitialize. \note -MDK is using currently a fixed frequency that is defined by \c EVENT_TIMESTAMP_FREQ. +µVision is using currently a fixed frequency that is defined by \c EVENT_TIMESTAMP_FREQ. */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ diff --git a/Doxygen/src/Fault.md b/Doxygen/src/Fault.md new file mode 100644 index 0000000..3d4817f --- /dev/null +++ b/Doxygen/src/Fault.md @@ -0,0 +1,169 @@ +# Exception Fault Analysis {#fault} + +## Overview {#about_fault} + +The software components under **CMSIS-View:Fault** provide infrastructure and [API (function calls)](modules.html) to store, record, and analyze the Cortex-M Exception Fault information. +Arm Cortex-M processors raise an exception fault on critical system failures such as illegal memory write or read, access to an disabled peripheral, execution of an invalid instruction, or division by zero: + +- The component **CMSIS-View:Fault:Storage** can be used to save an exception fault information for later analysis. +- The component **CMSIS-View:Fault:Record** decodes a saved exception fault information and records this information using the **Event Recorder**. + +A typical execution flow is shown in the diagram below. + +![Exception Fault Analysis](./images/ArmFault.png "Exception Fault Analysis") + +- \subpage flt_theory explains in details how the Fault component stores fault information and how it can be used for further analysis. +- \subpage flt_use provides instructions on how to enable Fault component in a project. + +**Application Note** + +An application note is available that describes the Cortex-M fault exceptions from the programmers view and explains their usage during the software development cycle: [KAN209 - Using Cortex-M3/M4/M7 Fault Exceptions](https://developer.arm.com/documentation/kan209/latest). + +\page flt_theory Theory of operation + +This section describes how the **Fault** component operates and how the fault information can be analyzed. + +The **Fault** component is implemented in the target application using the software component **CMSIS-View:Fault:Storage** which adds the source file *ARM_FaultStorage.c* to the application. +This source file provides an \ref ARM_FaultSave function which is used to save the fault information into an uninitialized part of the RAM which can then be analyzed on-chip, or on a host computer using a debugger. When using semihosting, cloud storage, or another remote location for storing the log file, you can do post-processing using \ref evntlst. + +## Fault information storage + +Fault information is stored in an \ref ARM_FaultInfo structure, residing in uninitialized RAM memory, when the \ref ARM_FaultSave function is executed from an exception handler. + +## Fault information analysis + +To see and analyze the details of a fault, there are the following options: +- Fault information can be decoded and written to the Event Recorder by calling the function \ref ARM_FaultRecord (Event Recorder has to be operational). This is an exemplary output in µVision: + ![Fault information with Event Recorder](./images/Fault_CM33_EvR_MemManage.png "Fault information with Event Recorder") +- Fault information can be decoded and written to the standard output by calling the function \ref ARM_FaultPrint (this function is implemented in a user template and can be changed by the user): + ![Fault information with STDIO](./images/Fault_STDIO_MemManage.png "Fault information with STDIO") +- Fault information can be inspected in a debug session by viewing it in the Component Viewer (screenshot showing µVision): + ![Fault information with Component Viewer](./images/Fault_CM33_CV_MemManage.png "Fault information with Component Viewer") + +## Resource requirements {#flt_req} + +This section contains the the technical data of the Fault component firmware. + +### RAM + +The Fault component uses the \ref ARM_FaultInfo structure to save information when the fault occurs. The size depends on the Arm Cortex-M core for which the code was compiled: + +- If the Arm Cortex-M core contains Fault Registers (e.g. Cortex-M33), the \ref ARM_FaultInfo structure requires **140 bytes** of uninitialized RAM memory. +- If the Arm Cortex-M core does not contain Fault Registers (e.g. Cortex-M0), the \ref ARM_FaultInfo structure requires **104 bytes** of uninitialized RAM memory. + +### ROM + +The functions of the Fault component require the following amounts of ROM memory: + +- The\ref ARM_FaultSave function requires up to **0.5 KB** of ROM memory. +- The \ref ARM_FaultRecord function requires approximately up to **1.5 KB** of ROM memory. +- The \ref ARM_FaultPrint function requires approximately up to **2.5 KB** of ROM memory. + +\page flt_use Using Fault component + +The following steps explain how to enable Fault component using the µVision. Other tools might use different ways to accomplish this. + +**For User Code:** + -# \ref flt_add_component. + -# \ref flt_place_uninit_memory "Locate fault information in uninitialized memory" to be preserved over system reset. + +## Add Fault Storage (and Record) Component {#flt_add_component} + +To use the Fault component in an application, you need to: + - Select the software components **CMSIS-View:Fault:Storage**, **CMSIS-View:Fault:Record** and **CMSIS-View:Event Recorder** using the RTE management dialog.
+ ![Select Fault](./images/Fault_set_comp.png) + - Include the *ARM_Fault.h* header and *EventRecorder.h* header files in your source code + - Add fault handlers that jump to \ref ARM_FaultSave function + - Check if a fault has occurred and output fault information to Event Recorder or STDIO and analyze it, or analyze fault information in a Component Viewer window in a debug session + + Code example: +```c +#include "EventRecorder.h" +#include "ARM_Fault.h" + +__attribute__((naked)) void HardFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} + +int main() { + SystemCoreClockUpdate(); // System core clock update + + EventRecorderInitialize (EventRecordAll, 1U); // Initialize and start Event Recorder + EventRecorderClockUpdate(); // Update Event Recorder timestamp clock + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + ARM_FaultRecord(); // Output decoded fault information via Event Recorder + EventRecorderStop(); // Stop Event Recorder + } + + // ... + + while (1) { + __NOP(); + } +} +``` + +## Locate fault information in uninitialized memory {#flt_place_uninit_memory} + +For preservation of the saved fault information after system reset, RAM for the \ref ARM_FaultInfo structure should be placed to a memory +region that is not cleared (or initialized) by a system restart (reset). + +\note Make sure that you use normal, non-cacheable, and non-shareable memory for fault information data. + +For size of this memory section take a look at \ref flt_req. + +### Create memory region {#flt_create_mem} + +To setup this uninitialized RAM, use either \ref flt_create_mem_ls or \ref flt_create_mem_uv procedure. + +#### Create memory region using linker script {#flt_create_mem_ls} + +If the linker script does not contain provisions for uninitialized memory section then, for respective toolchain, add the necessary section like described below: + +##### Arm Compiler {#flt_create_mem_ls_ac} + +for the **Arm Compiler** toolchain add the following code snippet to the linker script (.sct file), in the part specifying RAM sections (usually before Heap section): + + ``` + RW_NOINIT UNINIT 0x800 { + * (.bss.noinit*) + } + ``` + +> Note: \ is the physical address in RAM where the section will start + +> Note: 0x800 is the size of the section covering also default Event Recorder data, adjust that as necessary + +##### GCC {#flt_create_mem_ls_gcc} + +for the **GCC** toolchain add the following code snippet to the linker script (.ld file), in the part specifying RAM sections (usually before Heap section): + + ``` + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit*) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + ``` + +> Note: this code snippet expects defined RAM memory region, if RAM region is not defined then adapt the script accordingly + +### Create memory region using µVision {#flt_create_mem_uv} + +To setup this uninitialized RAM in the µVision, follow the steps below: + +1. In the **Options for Target** dialog, define a Read/Write Memory Area that is not initialized, by splitting available internal RAM into 2 areas.
+ For example, split IRAM1 into two regions. Reduce size of IRAM1 to 0x800 and create an IRAM2 area with remaining of the available RAM. Enable **NoInit** for the IRAM1 region.
+ ![Create RAM area](./images/Fault_create_iram2.png) + + +2. In the **Options for Component Class 'CMSIS-View'** dialog (opens with right-click on **ARM_FaultStorage.c** in the **Project** window), on the **Memory** tab, assign **Zero Initialized Data** to the IRAM1 region.
+ ![Create RAM area](./images/Fault_memory_location.png) + +3. Build the application to place the \ref ARM_FaultInfo structure to uninitialized RAM. diff --git a/Doxygen/src/Fault_fn.txt b/Doxygen/src/Fault_fn.txt new file mode 100644 index 0000000..b91ab3c --- /dev/null +++ b/Doxygen/src/Fault_fn.txt @@ -0,0 +1,222 @@ +/** +\defgroup Fault Fault +\brief Store, record, and analyze Cortex-M Exception Fault information. +\details +For an overview see \ref fault "Exception Fault Analysis". + +This section contains the functions of the component CMSIS-View:Fault that store, record, and analyze the Cortex-M Exception Fault information. + +@{ +*/ + +/** +\defgroup Fault_Storage Fault Storage +\brief Functions that store the Cortex-M Exception Fault information into memory. +\details +For an overview see \ref fault "Exception Fault Analysis". + +This section contains the functions of the component CMSIS-View:Fault:Storage that store the Cortex-M Exception Fault information in uninitialized RAM memory +and auxiliary functions. + +@{ +*/ + +/** +\defgroup Fault_Storage_Macros Macros +\brief Fault Storage macro definitions +@{ +*/ + +/** ARM Fault major version used in \ref ARM_FaultInfo_t.Version major */ +#define ARM_FAULT_FAULT_INFO_VER_MAJOR (1U) + +/** ARM Fault minor version used in \ref ARM_FaultInfo_t.Version minor */ +#define ARM_FAULT_FAULT_INFO_VER_MINOR (0U) + +/** @} Fault_Storage_Macros */ + +typedef struct {} ARM_FaultInfo_t; + +const char ARM_FaultVersion[]; +ARM_FaultInfo_t ARM_FaultInfo; + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultClear +\details + +\b Code \b Example +\code +#include "ARM_Fault.h" + +int main (void) { + + ARM_FaultClear(); // Clear fault information + + // ... +} +\endcode + +*/ + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultOccurred +\details +Call during startup to check if a fault occurred and if fault information is available, for example decode the fault information using \ref ARM_FaultPrint or \ref ARM_FaultRecord functions. + +\b Code \b Example +\code +#include "EventRecorder.h" +#include "ARM_Fault.h" + +int main() { + + EventRecorderInitialize (EventRecordAll, 1U); // Initialize and start Event Recorder + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + ARM_FaultPrint(); // Output decoded fault information via STDIO + ARM_FaultRecord(); // Output decoded fault information via Event Recorder + EventRecorderStop(); // Stop Event Recorder + } + + // ... +} +\endcode + +*/ + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultSave +\details +Call from a fault handler to save current fault information into uninitialized RAM memory. + +Make sure that function is called without changing the Stack Pointer (SP) and Link Register (LR) registers. +This is usually done by branching directly to this function from the fault handler. + +This function does not use stack or heap memories. + +\b Code \b Example +\code +#include "ARM_Fault.h" + +__attribute__((naked)) void HardFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} + +__attribute__((naked)) void MemManage_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} + +__attribute__((naked)) void BusFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} + +__attribute__((naked)) void UsageFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +\endcode + +*/ + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultExit +\details +The default implementation will do a system reset. + +If a system reset is not desired, you need to provide a custom implementation of this function with the desired functionality. + +\b Code \b Example of overriding \ref ARM_FaultExit function not to reset the system but to loop endlessly +\code +#include "ARM_Fault.h" + +__attribute__((naked)) void ARM_FaultExit (void) { + __ASM volatile ( + "b .\n" + ); +} +\endcode + +*/ + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultPrint +\details +To use \ref ARM_FaultPrint, add the ARM_FaultPrint template implementation to the project. + +\b Code \b Example +\code +#include +#include "ARM_Fault.h" + +int main() { + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + ARM_FaultPrint(); // Output decoded fault information via STDIO + } + + // ... +} +\endcode + +*/ + +/** @} Fault_Storage */ + +/** +\defgroup Fault_Record Fault Record +\brief Decode and record the Cortex-M Exception Fault information via \ref evr "Event Recorder". +\details +For an overview see \ref fault "Exception Fault Analysis". + +This section contains the function of the component CMSIS-View:Fault:Record that decodes and records the Cortex-M Exception Fault information using the \ref evr "Event Recorder". + +@{ +*/ + +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/** + +\fn ARM_FaultRecord +\details +Decode stored fault information and send information using \ref evr "Event Recorder" events. + +\b Code \b Example +\code +#include "EventRecorder.h" +#include "ARM_Fault.h" + +int main() { + + EventRecorderInitialize (EventRecordAll, 1U); // Initialize and start Event Recorder + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + ARM_FaultRecord(); // Output decoded fault information via Event Recorder + EventRecorderStop(); // Stop Event Recorder + } + + // ... +} +\endcode + +*/ + +/** @} Fault_Record */ + +/** @} Fault */ diff --git a/Doxygen/src/cmp_viewer.md b/Doxygen/src/cmp_viewer.md index 3b07f5b..633d94a 100644 --- a/Doxygen/src/cmp_viewer.md +++ b/Doxygen/src/cmp_viewer.md @@ -3,7 +3,7 @@ ## Overview {#about_cmp_viewer} The \cviewer reads specific memory locations from the target hardware using a standard debug unit -(for example a ULINK debug adapter) that is connected via JTAG or SWD to the CoreSight Debug Access Port (DAP). +that is connected via JTAG or SWD to the CoreSight Debug Access Port (DAP). The address of these memory locations is typically defined by symbols that represent variables, arrays, or starting point of linked lists. The *.SCVD file specifies these symbols and customizes the formatting in the \cviewer window of the debugger. @@ -15,22 +15,22 @@ linked lists. The *.SCVD file specifies these symbols and customizes the formatt - Visibility to the static user relevant information of an software component or application program with no additional software overhead in the target application. - The information is obtained via debug symbols from target memory using simple read commands via - JTAG or SWD + JTAG or SWD. connectivity to a debug adapter. - Debug adapters that support hot plugging allow to show the current status of the application software in case of failures. -## Using Component Viewer {#cv_use} +## Component Viewer Usage Example {#cv_use} -The following steps enable the MDK debugger views for static information of software components. +The following steps enable views for static information of software components in the µVision debugger. Other tools might use different ways to accomplish this. **For User Code:** -# Create an \ref SCVD_Format "SCVD file" to display \ref cv_static_information. -# Add the SCVD file to µVision as described in \manscvd. -# Use the µVision debugger windows as described in \cviewer. -For MDK Middleware, Keil RTX5, and FreeRTOS: +**For Pre-annotated software components:** -The software packs for MDK Middleware, CMSIS, CMSIS-FreeRTOS already contain the relevant *.SCVD files. +The software packs for MDK-Middleware, CMSIS, and CMSIS-FreeRTOS already contain the relevant *.SCVD files. - Add the SCVD file of the desired software component to µVision as described in \manscvd. - Use the µVision debugger windows as described in \cviewer. @@ -43,14 +43,14 @@ The \ref SCVD_Format "*.SCVD file" can be used to format static information of t Example code that is stored in the file **MyTest.c** (the file name is important for static variables). -``` +```C static int some_error = 1; char string[10] = "MyTest"; ``` The following **MyTest.scvd** file reads static program information from the variables in the above code snippet: -``` +```xml @@ -70,7 +70,9 @@ The following **MyTest.scvd** file reads static program information from the var ``` -In the µVision Debugger this \ref SCVD_Format "*.SCVD file" is specified in the dialog **Options for Target -> Debug -> +**Adding the file in the µVision debugger** + +In the µVision debugger, this \ref SCVD_Format "*.SCVD file" is specified in the dialog **Options for Target -> Debug -> Manage Component Viewer Description Files**. Click on **Add Component Viewer Description File** and add the related *.SCVD file. ![Manage *.SCVD files](./images/Manage_MyTest_SCVD.png "Manage *.SCVD files") diff --git a/Doxygen/src/ev_stat.md b/Doxygen/src/ev_stat.md index 84e2329..5e67e0f 100644 --- a/Doxygen/src/ev_stat.md +++ b/Doxygen/src/ev_stat.md @@ -7,114 +7,22 @@ debug adapter can be used to record execution timing and number of calls for ann \image html EventStatistics_wo_Energy.png "Event Statistics for user code" -Energy profiling is of annotated code sections is possible using ULINKplus. +Energy profiling is of annotated code sections is possible using ULINKplus. When combined with power measurement, the Event Statistics window displays the energy consumption of the code section with min/man/average values: \image html EventStatistics_w_Energy.png "User code energy profiling" -For more information, refer to \ref es_use. +For more information, refer to the \ref scvd_evt_stat example. **Benefits of Event Statistics:** - Collect statistical data about the code execution (time and energy). - Log files enable comparisons between different build runs in continuous integration (CI) environments. - Improve overall code quality and energy profile (especially relevant for battery driven applications). -## Using Event Statistics{#es_use} - -The following steps enable the MDK debugger views for \estatistics on timing, number of calls, and current consumption. - -To use \estatistics in the application code: - -# Follow the first two steps in \ref er_use. - -# Annotate the C source with \ref Event_Execution_Statistic. - -\ref Event_Execution_Statistic functions may be placed throughout the application source code to measure execution performance between -corresponding start and stop events: - -- EventStartG (slot) or EventStartGv (slot, val1, val2) functions define the start point of an execution slot. -- EventStopG (slot) or EventStopGv (slot, val1, val2) functions define the stop point of an execution slot. - -The \estatistics window shows collected data about execution time, number of calls, and (when using ULINKplus) the current consumption -for each execution slot. - -For the minimum and maximum time or current consumption it also shows for start and stop events the: -- C source file name and line number of event calls via EventStartG (slot) or EventStopG (slot). -- Integer values val1 and val2 of event calls via EventStartGv (slot, val1, val2) or EventStopGv (slot, val1, val2). - -Each execution slot is identified by the function name group letter G = {A, B, C, D} and a slot number (0 to 15). \ref er_filtering may be used to control the recording of each group. -A call to EventStopG or EventStopGv with slot=15 stops measurement for all slots in a group and may be used at global exits of an execution block. - -The following code is from the \ref scvd_evt_stat example project that is part of the Keil::ARM_Compiler pack: - -**Code example** - -``` -#define TABLE_SIZE 1000 -float sin_table[TABLE_SIZE]; - -// Calculate table with sine values -void CalcSinTable (void) { - unsigned int i, max_i; - float f = 0.0; - - max_i = TABLE_SIZE - (rand () % 500); - EventStartAv (15, max_i, 0); // Start group A, slot 15, passing the max_i variable - for (i = 0; i < max_i; i++) { - if (i == 200) { - EventStartAv (0, max_i, 0); // Start group A, slot 0, passing the max_i variable - } - - sin_table[i] = sinf(f); - f = f + (3.141592 / TABLE_SIZE); - - if (i == 800) { // Measure 800 table entries - EventStopA (0); // Stop group A, slot 0 - } - } - - EventStopA (15); // Stop group A, slot 15 (stops also slots 0..14) -} - -... - -int main (void) { - - SystemCoreClockUpdate(); // System Initialization - - EventRecorderInitialize(EventRecordAll, 1U); // Initialize and start Event Recorder - - EventStartC (0); // start measurement event group C, slot 0 - - for (j = 0; j < 1000; j++) { - CalcSinTable (); // calculate table with sinus values - - EventStartB(0); // start group B, slot 0 - MaxSqrtSum = rand () / 65536; // limit for sqrt calculation - num = FindSqrtSum ((float) MaxSqrtSum); // return number of sqrt operations - EventStopBv(0, MaxSqrtSum, num); // stop group B, slot 0, output values: MaxSqrtSum, num - } - - EventStopC(0); // stop measurement event group C, slot 0 - - for (;;) {} -} -``` - -Build and run the example project which uses the µVision simulator (available in all versions of MDK). In a debug session, -\erecorder, displays the following output: - -\image html er_with_statistics_annotated.png "Event Recorder with Start/Stop events and values" - -The \estatistics window shows the statistical data about the code execution: - -\image html es_start_stop_wo_energy_annotated.png "Event Statistics" - -For more information on the usage of the functions, refer to the -Event Execution Statistics API. - ## Display current consumption{#es_display_energy} -Using a ULINKplus debug adapter, you can also record and analyze the +Using a ULINKplus debug adapter, you can also record and analyze the energy that has been consumed in each execution slot. Using the above example on a hardware target with a ULINKplus, you get the -following displays in the \estatistics window (the \erecorder window does not change): +following display in the \estatistics window of µVision (the \erecorder window does not change): \image html es_start_stop_w_energy.png "Event Statistics displaying the energy consumption" diff --git a/Doxygen/src/eventlist.md b/Doxygen/src/eventlist.md new file mode 100644 index 0000000..8eaee96 --- /dev/null +++ b/Doxygen/src/eventlist.md @@ -0,0 +1,75 @@ +# eventlist {#evntlst} + +## Overview {#about_evntlst} + +Eventlist is a command line tool for processing Event Recorder data stored to a log file. + +The utility is a Go application that is available for all major operating systems and is run from the command line. Refer to the +source code for more information including the invocation details. + +## Analyze Events + +It is used in the example project \ref scvd_evt_stat. Build and run the example. Then run `eventlist -s EventRecorder.log` in a terminal to create the human readable output: + +```txt + Start/Stop event statistic + -------------------------- + +Event count total min max average first last +----- ----- ----- --- --- ------- ----- ---- +A(0) 10000 31.44509s 1.69997ms 3.80041ms 3.14451ms 3.29962ms 3.59964ms + Min: Start: 31.94980000 val1=0x000001f5, val2=0x00000000 Stop: 31.95149997 val1=0x10004d43, val2=0x0000003c + Max: Start: 84.70757283 val1=0x000003a5, val2=0x00000000 Stop: 84.71137324 val1=0x10004d43, val2=0x00000038 + +A(15) 10000 169.75100s 2.49964ms 42.78648s 16.97510ms 3.99995ms 4.30004ms + Min: Start: 81.87697318 val1=0x000001f8, val2=0x00000000 Stop: 81.87947282 val1=0x10004d43, val2=0x0000003c + Max: Start: 37.41299154 val1=0x0000032f, val2=0x00000000 Stop: 80.19947314 val1=0x10004d43, val2=0x0000003c + +B(0) 10000 10.83677s 0.00000s 169.29161ms 1.08368ms 1.60016ms 1.00010ms + Min: Start: 1.76679986 val1=0x10004d43, val2=0x0000005c Stop: 1.76679986 val1=0x0000018e, val2=0x00000047 + Max: Start: 37.24369993 val1=0x10004d43, val2=0x0000005c Stop: 37.41299154 val1=0x000066bf, val2=0x00000487 + +C(0) 1 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s + Min: Start: 0.00000000 val1=0x10004d43, val2=0x00000057 Stop: 180.67371888 val1=0x10004d43, val2=0x00000062 + Max: Start: 0.00000000 val1=0x10004d43, val2=0x00000057 Stop: 180.67371888 val1=0x10004d43, val2=0x00000062 +``` + +### Adding Context + +When adding the AXF file and the [SCVD file](https://arm-software.github.io/CMSIS-View/main/SCVD_Format.html) to the `eventlist` command, the context of the program is shown. + +Run `eventlist -a ./out/EventStatistic/Debug/AVH/Debug+AVH.axf -I ./EventRecorder.scvd ./EventRecorder.log` in a terminal window. The output should look like the following: + +```txt + : + +53947 180.66841874 EvCtrl StartAv(15) v1=776 v2=0 +53948 180.66911914 EvCtrl StartAv(0) v1=776 v2=0 +53949 180.67271878 EvCtrl StopA(15) File=./EventStatistic/main.c(60) +53950 180.67271878 EvCtrl StartB(0) File=./EventStatistic/main.c(92) +53951 180.67371888 EvCtrl StopBv(0) v1=15150 v2=802 +53952 180.67371888 EvCtrl StopC(0) File=./EventStatistic/main.c(98) + + Start/Stop event statistic + -------------------------- + +Event count total min max average first last +----- ----- ----- --- --- ------- ----- ---- +A(0) 10000 31.44509s 1.69997ms 3.80041ms 3.14451ms 3.29962ms 3.59964ms + Min: Start: 31.94980000 v1=501 v2=0 Stop: 31.95149997 File=./EventStatistic/main.c(60) + Max: Start: 84.70757283 v1=933 v2=0 Stop: 84.71137324 File=./EventStatistic/main.c(56) + +A(15) 10000 169.75100s 2.49964ms 42.78648s 16.97510ms 3.99995ms 4.30004ms + Min: Start: 81.87697318 v1=504 v2=0 Stop: 81.87947282 File=./EventStatistic/main.c(60) + Max: Start: 37.41299154 v1=815 v2=0 Stop: 80.19947314 File=./EventStatistic/main.c(60) + +B(0) 10000 10.83677s 0.00000s 169.29161ms 1.08368ms 1.60016ms 1.00010ms + Min: Start: 1.76679986 File=./EventStatistic/main.c(92) Stop: 1.76679986 v1=398 v2=71 + Max: Start: 37.24369993 File=./EventStatistic/main.c(92) Stop: 37.41299154 v1=26303 v2=1159 + +C(0) 1 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s + Min: Start: 0.00000000 File=./EventStatistic/main.c(87) Stop: 180.67371888 File=./EventStatistic/main.c(98) + Max: Start: 0.00000000 File=./EventStatistic/main.c(87) Stop: 180.67371888 File=./EventStatistic/main.c(98) +``` + +Customizing the SCVD file enable you to create application specific output that can be easily read and analyzed for debugging purposes. \ No newline at end of file diff --git a/Doxygen/src/examples.md b/Doxygen/src/examples.md new file mode 100644 index 0000000..45ff200 --- /dev/null +++ b/Doxygen/src/examples.md @@ -0,0 +1,160 @@ +# Examples {#ExampleProjects} + +These examples show the usage of the \subpage er_examples and \subpage flt_examples. + +\page er_examples Event Recorder + +This example shows you how to utilize Event Recorder in own application software. +This example project is based on an Arm Cortex-M processor and uses the [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox) for project build, and runs on [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/overview/html/index.html) processor simulation. + +Example Project | Description +:----------------------------------------------|:----------------------------------------- +\subpage scvd_evt_stat "SCVD Event Statistics" | Shows the usage of start/stop events for statistical code profiling. + +\page flt_examples Fault component + +These examples show you how to utilize Fault component in own application software. + +Example Project | Description +:----------------------------------------------|:----------------------------------------- +\subpage flt_example_CM7 "VHT_MPS2_Cortex-M7" | Shows the usage of Fault component on an Cortex-M7. This example runs on [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/overview/html/index.html) processor simulation. +\subpage flt_example_CM33 "B-U585I-IOT02A" | Shows the usage of Fault component on an Cortex-M33 with TrustZone. This example runs on STMicroelectronics [**B-U585I-IOT02A**](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) evaluation board. + + +\page scvd_evt_stat Event Statistics + +This example project shows how to use start/stop events with the Event Recorder. + +The start/stop events allow to measure execution times with different slots (0 - 15) in four different groups (A - D). The +call to 'EventStart' starts a timer slot; the call to 'EventStop' stops the related timer. A call to EventStop with slot 15 +stops the timers of all slots in the specific group. + +This demo application does some time consuming calculations that are recorded. It runs in simulation and does not require any +hardware to be present. + +**main.c File** + +```c +#include "RTE_Components.h" // Component selection +#include CMSIS_device_header // defined in the RTE_Components.h file + +#include "EventRecorder.h" + +#include +#include +#include + +#define TABLE_SIZE 1000 +float sin_table[TABLE_SIZE]; + +// Calculate table with sine values +void CalcSinTable (void) { + unsigned int i, max_i; + float f = 0.0; + + max_i = TABLE_SIZE - (rand () % 500); + EventStartAv (15, max_i, 0); // Start group A, slot 15, passing the max_i variable + for (i = 0; i < max_i; i++) { + if (i == 200) { + EventStartAv (0, max_i, 0); // Start group A, slot 0, passing the max_i variable + } + + sin_table[i] = sinf(f); + f = f + (3.141592 / TABLE_SIZE); + + if (i == 800) { // Measure 800 table entries + EventStopA (0); // Stop group A, slot 0 + } + } + + EventStopA (15); // Stop group A, slot 15 (stops also slots 0..14) +} + +// Return number of sqrt operations to exceed sum +unsigned int FindSqrtSum (float max_sum) { + unsigned int i; + float sqrt_sum; + + sqrt_sum = 0.0; + for (i = 0; i < 10000; i++) { + sqrt_sum += sqrtf((float) i); + if (sqrt_sum > max_sum) { + return (i); + } + } + return (i); +} + +unsigned int j, num, MaxSqrtSum; + + +int main (void) { + + SystemCoreClockUpdate(); // System Initialization + + EventRecorderInitialize (EventRecordAll, 1U); // Initialize and start Event Recorder + EventRecorderClockUpdate(); + EventStartC (0); // start measurement event group C, slot 0 + printf ("Started\n"); + for (j = 0; j < 10000; j++) { + CalcSinTable (); // calculate table with sinus values + + EventStartB(0); // start group B, slot 0 + MaxSqrtSum = rand () / 65536; // limit for sqrt calculation + num = FindSqrtSum ((float) MaxSqrtSum); // return number of sqrt operations + EventStopBv(0, MaxSqrtSum, num); // stop group B, slot 0, output values: MaxSqrtSum, num + } + + EventStopC(0); // stop measurement event group C, slot 0 + + while (1) { + __NOP(); + } +} +``` + +**Build and run** + +This example project does not require an IDE and can be built using the CMSIS-Toolbox. + +Clone this repository or download it as a ZIP file onto your computer. Follow the instructions in the `README.md` file to build and run the project. Use the \ref evntlst application to analyze the outcomes. + + +\page flt_example_CM7 VHT_MPS2_Cortex-M7 + +This example project shows **Exception Fault Analysis** using **Arm Cortex-M7** simulated by [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/simulation/html/Using.html) with the **VHT_MPS2_Cortex-M7** model simulator. + +**Build and run** + +This example project does not require an IDE and can be built using the [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox). + +Clone this repository or download it as a ZIP file onto your computer. Follow the instructions in the \subpage flt_example_CM7_readme "README.md" file to build and run the project. + +**Screenshots** + +User Interface \image html Fault_CM7_UI.png + +**EventRecorder.log** containing saved Memory Management fault information, processed with **eventlist** utility \image html Fault_CM7_eventlist_MemManage.png + + +\page flt_example_CM33 B-U585I-IOT02A + +This example project shows **Exception Fault Analysis** using **Arm Cortex-M33** running on a STMicroelectronics [**B-U585I-IOT02A**](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) evaluation board. + +**Build and run** + +This example project requires the [**Keil MDK**](https://www.keil.com/mdk5). + +Clone this repository or download it as a ZIP file onto your computer. Follow the instructions in the \subpage flt_example_CM33_readme "README.md" file to build and run the project. + +**Screenshots** + +User Interface \image html Fault_CM33_UI.png + +**Component View** when no fault was saved yet \image html Fault_CM33_CV_NoFault.png + +**Component View** when Memory Management fault has occurred \image html Fault_CM33_CV_MemManage.png + +**Event Recorder** messages when Memory Management fault was decoded and output to Event Recorder \image html Fault_CM33_EvR_MemManage.png + +**Serial Terminal** output when Memory Management fault was decoded and output to STDIO \image html Fault_CM33_STDIO_MemManage.png diff --git a/Doxygen/src/images/ARM_FaultPrint.PNG b/Doxygen/src/images/ARM_FaultPrint.PNG new file mode 100644 index 0000000..037594d Binary files /dev/null and b/Doxygen/src/images/ARM_FaultPrint.PNG differ diff --git a/Doxygen/src/images/ARM_FaultRecord.PNG b/Doxygen/src/images/ARM_FaultRecord.PNG new file mode 100644 index 0000000..d456b16 Binary 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0000000..edac7bf Binary files /dev/null and b/Doxygen/src/images/Fault_set_comp.png differ diff --git a/Doxygen/src/images/SelEventRecorder.png b/Doxygen/src/images/SelEventRecorder.png index ad00338..a0c59fb 100644 Binary files a/Doxygen/src/images/SelEventRecorder.png and b/Doxygen/src/images/SelEventRecorder.png differ diff --git a/Doxygen/src/images/er_memory_location.png b/Doxygen/src/images/er_memory_location.png index 3832965..37329e2 100644 Binary files a/Doxygen/src/images/er_memory_location.png and b/Doxygen/src/images/er_memory_location.png differ diff --git a/Doxygen/src/main.md b/Doxygen/src/main.md index 9599d39..c671c7e 100644 --- a/Doxygen/src/main.md +++ b/Doxygen/src/main.md @@ -1,637 +1,36 @@ \mainpage -**CMSIS-View** equips software developers with methodologies, software components and utilities that provide visibility into internal operation of embedded applications and software components. +**CMSIS-View** offers software developers methodologies, software components, and utilities that provide visibility into internal operation of embedded applications and software components. -With CMSIS-View developers can collect time-accurate event-based information as well as see the real-time program execution status. The data can be observed in real-time in an IDE or can be saved as a log file during program execution. It allows to analyze execution flows, debug potential issues, and measure execution times. - -Key elements of CMSIS-View are: -- \ref er_use "Event Recorder" - is an embedded software component that provides an [API (function calls)](modules.html) for event annotations in the code. -- \ref SCVD_Format "SCVD file specification" defines the content that is displayed. +With the software components of CMSIS-View, developers can collect time-accurate event-based information, display program execution status, and analyze fault exceptions. It allows to analyze execution flows, debug potential issues, and measure execution times. The data can be observed in real-time in an IDE or can be saved as a log file during program execution. A **Software Component Viewer Description** (*.SCVD) file in \ref SCVD_Format (XML) defines the content that is displayed in the **Component Viewer** and **Event Recorder**. In addition, using the Event Recorder API, you can annotate your code so that you can get statistical data on the time spent in a loop or on the energy consumption -(ULINKplus required). +(ULINKplus required). -The debugger can load multiple *.SCVD files as typically each software component has an individual description file. +Key elements of CMSIS-View are: + +- \ref er_use "Event Recorder" - is an embedded software component that provides an [API (function calls)](modules.html) for event annotations in the code. +- \ref evntlst, a command line tool for processing Event Recorder log files. +- \ref fault with infrastructure and functions to store, record, and analyze exception fault information. # Content {#content} This user's guide contains the following chapters: - - \subpage rev_hist : lists CMSIS-View releases - - \subpage evr : explores the features and operation of the **Event Recorder** including - configuration, technical data, and theory of operation. - - \subpage ev_stat : describes how to use Event Statistics to create statistical data on code execution and power consumption. - - \subpage cmp_viewer : explains the use of Component Viewer. - - \subpage SCVD_Format : describes the format of the Software Component View Description (*.SCVD) files that define the output of the MDK debugger views. - - \subpage ExampleProjects are available demonstrating standard use cases. - - **[API References](modules.html)** describes the API and the functions of the **Event Recorder** in details. - -\page ExampleProjects Examples - -The software pack Keil:ARM_Compiler contains several example projects that show the usage of Component Viewer and Event Recorder. These example projects contain Software Component Viewer Description (*.SCVD) files. Use the \packinstaller to copy the projects to working folder. Build the selected project and enter a debug session. All projects run in simulation and do not require hardware. - -These examples show you how to utilize \cviewer and \erecorder in own application software. All example projects are based on an Arm Cortex-M processors and are configured to use processor simulation. Additional instructions have been added to the project descriptions. - -The following SCVD example projects are available: - -Example Project | Description -:------------------------------------------------------|:----------------------------------------- -\subpage simple_scvd "SCVD Simple Example" | Simple example that shows how to display two variables in the \cviewer. -\subpage complex_scvd "SCVD Complex Example" | More complex \cviewer example. -\subpage MyComponent "SCVD in MyComponent" | Example showing \cviewer and \erecorder and how to create links to documentation and include SCVD files in software packs. -\subpage scvd_evt_stat "SCVD Event Statistics" | Example that shows the usage of start/stop events for statistical code profiling with the \estatistics window. -\subpage scvd_evt_state "SCVD Event State" | Example that uses state information to display time-line information in the System Analyzer window. -\subpage scvd_CM0_SysTick "SCVD Cortex-M0 SysTick" | Example that shows the Event Recorder with SysTick timer as time source (for Cortex-M0/M0+/M23) -\subpage scvd_CM0_RTOS "SCVD Cortex-M0 RTOS" | Example that shows the Event Recorder with RTOS System Timer as time source (for Cortex-M0/M0+/M23) - - -\page simple_scvd SCVD Simple Example - -If you just want to display execution status information, you only require \cviewer. Use the example project **Simple SCVD Example** as an introduction to the \cviewer. - -The example shows: -- a simple *.scvd file -- how to build a hierarchy in the output -- the use of \ref format_specifiers "Format Specifiers" - -The output shows the values of two structure members (in HEX and decimal). The \token{low} member is an integer running from -\token{[0..30]}, while the \token{hi} member is the square of \token{low}. The output shows the values as decimal and HEX on -different rows. - -![Values of structure](./images/My1stViewer.png "Values of structure") - -Simple Example - -The following code creates a type called "MyGeneralType" that emulates the program structure \token{MyType} defined in -\em main.c. The object that is to be displayed searches for the symbol \em mysymbol and shows the items \em hi and \em low in -the viewer window: - -**main.c File** - -``` -#include "RTE_Components.h" // Component selection -#include CMSIS_device_header // Device header - -typedef struct { // type definition - uint32_t hi; // offset 0 - uint32_t low; // offset 4 -} MyType; - -extern volatile MyType mysymbol; // avoid compiler 6 warning - -MyType volatile mysymbol; // symbol definition - -int main(void) { - uint32_t i; - - while (1) { - for( i=0; i<=30; i++ ) { - mysymbol.hi = i*i; - mysymbol.low = i; - } - } -} -``` - -**Simple_View.scvd File** -``` - - - - - - - - - - - - - - - - - - - - - - - - - - - -``` - -The Simple_View.scvd file has been added to the project as described in \manscvd. - -**Build and run** - --# Open the project "Simple SCVD Example" from Pack Installer (search for \em uVision \em Simulator in the **Boards** tab). --# Compile and run the application. --# Open the window **View - Watch Windows - My First Viewer** and watch the values change while the program runs. - -![Menu in View - Watch Windows](./images/My1stViewerMenu.png "Menu in View - Watch Windows") - -\page complex_scvd SCVD Complex Example - -Use the example project **Complex SCVD Example** for more advanced topics. - -This example is more complex than \ref simple_scvd and shows: -- The use of \ref scvd_expression and conditional computing for various XML elements -- The use of the built-in variable \token{_count} -- The use of \refelem{readlist} and \refelem{elem_listout,list} for looping through arrays - -The example uses the structures \token{TypeA}, \token{TypeG}, and \token{TypeArray} defined in the project and creates a -static output showing initial member values and characteristics. - -**main.c File** - -``` -#include "RTE_Components.h" // Component selection -#include CMSIS_device_header - -// Type 'A' -typedef struct TypeA { - uint32_t Nummer; - uint32_t Status; - uint32_t Size; -} TypeA; - -// Type 'G' -typedef struct TypeG { - uint32_t Nummer; - uint32_t Cluster; - uint32_t ClusterSize; - uint32_t Status; -} TypeG; - -// Type Array -typedef struct TypeArray { - void *type_ref; - char id[2]; - uint16_t attr; -} TypeArray; - -static TypeA type_a0 = { 0xA01, 0xA02, 0xA03 }; -static TypeA type_a1 = { 0xA11, 0xA12, 0xA13 }; -static TypeG type_g0 = { 0xF01, 0xF02, 0xF03, 0xF04 }; -static TypeG type_g1 = { 0xF11, 0xF12, 0xF13, 0xF14 }; -static TypeG type_g2 = { 0xF21, 0xF22, 0xF23, 0xF24 }; - -static int32_t x0; - -extern TypeArray type_array[]; -TypeArray type_array[] = { - { &x0, "A0", 1 }, - { &type_g0, "G0", 2 }, - { &type_g1, "G1", 2 }, - { &type_a1, "A1", 1 }, - { &type_g2, "G2", 2 }, -}; - -int main (void) { - - type_array[0].type_ref = &type_a0; - while (1) { - __NOP(); - } -} -``` - -**Complex_view.scvd File** - -``` - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TArray[i].idx=TypeA._count; - - - - - TArray[i].idx=TypeG._count; - - - - - - - TypeG[i].TotalSize = TypeG[i].Cluster * TypeG[i].ClusterSize; - - - j=TArray._count; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -``` - -**Build and run** - --# Open the project "Complex SCVD Example" from Pack Installer (search for \em uVision \em Simulator in the **Boards** tab). --# Compile and run the application --# Open the window **View - Watch Windows - Array and Structure Types** and verify the output - -![Array and Structure Types](./images/My2ndViewer.png "Array and Structure Types") - -\page MyComponent SCVD in MyComponent - -MyComponent implements a data transfer using the functions \c MyComp_initialize, \c MyComp_send, and \c MyComp_receive. -During operation, the component calls event functions that provide event data for recording by the Event Recorder. - -This example shows how to: - - \ref add_event_annotations "add event annotations" to a software component - - \ref create_scvd "create an SCVD file" for status and event displays in the MDK debugger - - \ref create_doxy "create Doxygen documentation" that utilizes the MDK context help system - - \ref create_pack "create a software pack" using the CMSIS-Pack standard - - -# Add Event Annotations {#add_event_annotations} - -It is possible to add \ref Event_Annotations pragmatical as explained in the section \ref er_use. However, for more complex -software components, it makes sense to use a structured approach as described in the following. - -Event annotation should deliver meaningful information about the dynamic execution of a software component and can be grouped -into the following categories using level information in the \ref EventID. - - \ref EventLevelError indicates when an event relates to run-time errors in the component. - - \ref EventLevelAPI should be used when an event relates to API function calls. - - \ref EventLevelOp refers to events that related to internal operations. - - \ref EventLevelDetail allows to provided events with additional detailed information of operations. - -Instead of using the general purpose \ref EventRecorder_Data functions, specify component specific functions that can be -tagged with an \ref EventID. These component specific functions are calling then the \ref EventRecorder_Data functions. - -The event recorder functions for the MyComponent software component are using severity level information in their -\ref EventID "EventIDs" (refer to the file EvrMyComponent.h in the example project): - -``` -#define EvtMyCo_No 0x0A /// < Number of the component with short name 'EvtMyCo_No' - -// Event id list for "MyComponent" -#define EvtMyCo_InitEntry EventID (EventLevelAPI, EvtMyCo_No, 0x00) -#define EvtMyCo_InitStatus EventID (EventLevelAPI, EvtMyCo_No, 0x01) -#define EvtMyCo_SendNoData EventID (EventLevelError, EvtMyCo_No, 0x0A) -#define EvtMyCo_SendComplete EventID (EventLevelOp, EvtMyCo_No, 0x0B) -#define EvtMyCo_SendFailed EventID (EventLevelError, EvtMyCo_No, 0x0C) -#define EvtMyCo_ReceiveNoData EventID (EventLevelError, EvtMyCo_No, 0x15) -#define EvtMyCo_ReceiveComplete EventID (EventLevelAPI, EvtMyCo_No, 0x16) -#define EvtMyCo_ReceiveFailed EventID (EventLevelError, EvtMyCo_No, 0x17) -``` - -The \ref EventID also contains information about the component number (to identify the event) and the specific message number -that is used to display additional information in the Event Recorder window. - - -# Create an SCVD file {#create_scvd} - -The SCVD file for MyComponent uses this message number information to display the correct messages in Event Recorder. - -``` - - - - - - - - - - - - - - -``` - -
- -![Event Recorder displaying the event annotations](./images/MyComponentEvents_withAnnotations.png "Event Recorder displaying the event annotations") - -# Generate documentation {#create_doxy} - -Software components are frequently a black-box to the application programmer and event annotations need additional -descriptions that interlinks with API related documentation. - -Doxygen is frequently used to generate API documentation. Using this -approach, event annotations can be documented in a similar way. Once the software component is framed as a -\ref create_pack "CMSIS-Pack", the documentation for event annotations opens using hyperlinks in the Event Recorder. - -A full documentation of the software component is available in the software pack that is built in the next step. You will -find the Doxygen source code in ./SCVD_Examples/MyComponent/Doxygen. Run the script \c gen_doc.bat to create the -documentation. - -# Create a pack {#create_pack} - -Open-CMSIS-Pack describes a mechanism to deliver -software components, device parameters, and evaluation board support. The XML-based package description file (PDSC) describes -the content of a software pack (file collection) that may include: - - Source code, header files, and software libraries - - Documentation and source code templates - - Device parameters along with startup code and programming algorithms - - Example projects - -For the software component "MyComponent", as pack is available in the directory ./SCVD_Examples/MyComponent_Pack. -Double-click MyVendor.MyComponent.1.0.0.pack to install it on your system. It contains one software component called -:MyVendor:MyComponent with related documentation. - -\image html mycomponent.png "MyComponent in the Manage Run-time Environment window" - -The PDSC file is very simple. It declares a single software component that comes with source files, SCVD and HTML -documentation: -``` - - MyComponent software component example - - - - - - - -``` - -An example project called "MyComponent Pack Example" is also part of the pack. It is basically the same example as -\ref MyComponent, only that it is using the "MyComponent" software component. - -If you build and run the example, you will see that the events that are recorded now contain hyperlinks that bring up the -related documentation. - -![Event recorder links to related documentation](./images/er_doxygen_links.png "Event recorder links to related documentation") - -With this, you can create re-usable software components that can be equipped with Event Recorder -information and related documentation. This is useful if you intend to share the software component within your company or -with third parties. - -\page scvd_evt_stat SCVD Event Statistics - -This example project shows how to use start/stop events with the Event Recorder. For further details refer to \ref es_use. - -The start/stop events allow to measure execution times with different slots (0 - 15) in four different groups (A - D). The -call to 'EventStart' starts a timer slot; the call to 'EventStop' stops the related timer. A call to EventStop with slot 15 -stops the timers of all slots in the specific group. - -This demo application does some time consuming calculations that are recorded. It runs in simulation and does not require any -hardware to be present. - -**main.c File** - -``` -#include "RTE_Components.h" -#include CMSIS_device_header - -#ifndef RTE_Compiler_EventRecorder -#warning This example requires the Event Recorder component -#endif - -#include "EventRecorder.h" -#include -#include - -#define TABLE_SIZE 1000 -float sin_table[TABLE_SIZE]; - -// Calculate table with sine values -void CalcSinTable (void) { - unsigned int i, max_i; - float f = 0.0; - - max_i = TABLE_SIZE - (rand () % 500); - EventStartAv (15, max_i, 0); // Start group A, slot 15, passing the max_i variable - for (i = 0; i < max_i; i++) { - if (i == 200) { - EventStartAv (0, max_i, 0); // Start group A, slot 0, passing the max_i variable - } - - sin_table[i] = sinf(f); - f = f + (3.141592 / TABLE_SIZE); - - if (i == 800) { // Measure 800 table entries - EventStopA (0); // Stop group A, slot 0 - } - } - - EventStopA (15); // Stop group A, slot 15 (stops also slots 0..14) -} - -// Return number of sqrt operations to exceed sum -unsigned int FindSqrtSum (float max_sum) { - unsigned int i; - float sqrt_sum; - - sqrt_sum = 0.0; - for (i = 0; i < 10000; i++) { - sqrt_sum += sqrtf((float) i); - if (sqrt_sum > max_sum) { - return (i); - } - } - return (i); -} - -unsigned int j, num, MaxSqrtSum; - -int main (void) { - - SystemCoreClockUpdate(); // System Initialization - - EventRecorderInitialize(EventRecordAll, 1U); // Initialize and start Event Recorder - - EventStartC (0); // start measurement event group C, slot 0 - - for (j = 0; j < 1000; j++) { - CalcSinTable (); // calculate table with sinus values - - EventStartB(0); // start group B, slot 0 - MaxSqrtSum = rand () / 65536; // limit for sqrt calculation - num = FindSqrtSum ((float) MaxSqrtSum); // return number of sqrt operations - EventStopBv(0, MaxSqrtSum, num); // stop group B, slot 0, output values: MaxSqrtSum, num - } - - EventStopC(0); // stop measurement event group C, slot 0 - - for (;;) {} -} -``` - -**Build and run** - --# Open the project "SCVD Event Statistic" from Pack Installer (search for \em uVision \em Simulator in the **Boards** tab). --# Compile and run the application. --# Open the windows View - Analysis Windows - \erecorder and View - Analysis Windows - \estatistics to verify the output. - -![Event Recorder with Start/Stop events and values](./images/er_with_statistics.png "Event Recorder with Start/Stop events and values") - -
- -![Event Statistics](./images/es_start_stop_wo_energy.png "Event Statistics") - -\page scvd_evt_state SCVD Event State - -This example project shows how to display state information with the Event Recorder. -The application itself implements a event_state thread that is started with two instances. -The event state thread itself makes state transitions that are recorded. - -**Source code of the event state thread (from MyEventComponent.c)** -``` -void event_state (void *argument) { - unsigned int i, h, name; - - name = (unsigned int) argument; - h = name + 0x10000000; - - osDelay(100); - EvrMyC1_Create (h, name); - for (i=0; i < 2; i++) { - osDelay(100); - EvrMyC1_Active (h); - osDelay(100); - EvrMyC1_Waiting (h); - osDelay(100); - EvrMyC1_Idle (h); - osDelay(100); - } - - EvrMyC1_Clear (h); - osDelay(100); - EvrMyC1_Delete (h); - : -} -``` - -**Start of the event state thread (from main.c)** - -``` -char *name1 = "MyName1"; -char *name2 = "MyName2"; - -osThreadId_t event_state1_id; -osThreadId_t event_state2_id; - -int main (void) { - - EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder - - osKernelInitialize(); // initialize CMSIS-RTOS - event_state1_id = osThreadNew(event_state, name1 /* "Instance 1" */, NULL); - event_state2_id = osThreadNew(event_state, name2 /* "Instance 2" */, NULL); - osKernelStart (); -} -``` - -The application itself uses the MyEventComponent.scvd file to describe the state. Refer to the element \refelem{elem_group_component_state,state} for more information. - - -**Build and run** - --# Open the project "SCVD Event State" from Pack Installer (search for \em uVision \em Simulator in the **Boards** tab). --# Compile and run the application. --# Open the windows View - Analysis Windows - \erecorder and View - Analysis Windows - System Analyzer to verify the output. - -![System Analyzer with event state information](./images/estat_SA.png "System Analyzer with event state information") - -
- -![Event Recorder with event state information](./images/estat_ER.png "Event Recorder with event state information") - -\page scvd_CM0_SysTick SCVD Cortex-M0 SysTick - -This example projects shows the Event Recorder with SysTick timer as time source (for Cortex-M0/M0+/M23). -Refer to \ref noDWT "Configure for targets without DWT Cycle Counter" for more information. - -**Build and run** - --# Open the project "SCVD Cortex-M0 SysTick" from Pack Installer (search for *uVision Simulator* in the **Boards** tab). --# Compile and run the application. --# Open the windows View - Analysis Windows - \erecorder to verify the output. - -![Event Recorder with with SysTick timer as time source](./images/CM0_SysTick.png "Event Recorder with with SysTick timer as time source") - -\page scvd_CM0_RTOS SCVD Cortex-M0 RTOS - -This example projects shows the Event Recorder with CMSIS-RTOS2 System Timer as time source (for Cortex-M0/M0+/M23). -Refer to \ref noDWT "Configure for targets without DWT Cycle Counter" for more information. -**Build and run** +- \subpage rev_hist : lists CMSIS-View releases +- \subpage evr : explores the features and operation of the **Event Recorder** including + configuration, technical data, and theory of operation. +- \subpage ev_stat : describes how to use Event Statistics to create statistical data on code execution and power consumption. +- \subpage evntlst : shows the usage of `eventlist`, a command line tool for processing Event Recorder records stored to a log file. +- \subpage cmp_viewer : explains the use of Component Viewer. +- \subpage SCVD_Format : describes the format of the Software Component View Description (*.SCVD) files that define the content that is displayed. +- \subpage fault : infrastructure and functions to store, record, and analyze the Cortex-M Exception Fault information. +- \subpage ExampleProjects are available demonstrating standard use cases. +- **[API References](modules.html)** describes the API and the functions of the **Event Recorder** and **Fault components** in details. --# Open the project "SCVD Cortex-M0 RTOS" from Pack Installer (search for \em uVision \em Simulator in the **Boards** tab). --# Compile and run the application. --# Open the windows View - Analysis Windows - \erecorder and View - Analysis Windows - System Analyzer to verify the output. +# License {#license} -![Event Recorder with with CMSIS-RTOS2 System Timer as time source](./images/CM0_RTOS.png "Event Recorder with with CMSIS-RTOS2 System Timer as time source") +CMSIS-View is provided free of charge by Arm under the Apache 2.0 License. diff --git a/Doxygen/src/scvd_format.txt b/Doxygen/src/scvd_format.txt index 1e85621..bf00521 100644 --- a/Doxygen/src/scvd_format.txt +++ b/Doxygen/src/scvd_format.txt @@ -1,9 +1,9 @@ /* ========================================================================================================================== */ /** -\page SCVD_Format SCVD File Format +\page SCVD_Format SCVD file format -The SCVD (Software Component View Description) files are formatted in XML and based on the schema file \b Component_Viewer.xsd. -The schema file \b Component_Viewer.xsd is part of the Keil MDK installation and available in the folder ..\\UV4. +The SCVD (Software Component View Description) files are formatted in XML and based on the schema file +Component_Viewer.xsd. The SCVD file format is described in the following sections: - \subpage xml_elements : specifies the structure and top level elements of an SCVD file. @@ -13,26 +13,23 @@ The SCVD file format is described in the following sections: - \subpage builtin_function : lists built-in functions that can be used for calculating stack memory usage, accessing CPU registers or application program symbols. - \subpage value_output : shows how to format output data for display in the \cviewer or \erecorder. +\section scvd_validate SCVD file validation +The schema file +Component_Viewer.xsd. +specifies the XML format. Use this schema file together with XML tools for validating an *.scvd file. -\section scvd_validate SCVD File Validation +\section scvd_in_debug Using SCVD files in a debugger -An *.SCVD file is validated with the following steps: - --# The schema file Component_Viewer.xsd specifies the XML format. Use this schema file together with XML tools to check correctness of an *.scvd file. --# Start the uVision Debugger and verify that no error messages are displayed in the debug command window and when opening the software component watch window. - -\section scvd_in_debug Using SCVD Files in the Debugger - -To use a *.SCVD file in the uVision Debugger: - - Add the SCVD file to uVision as described in Manage Component Viewer Description Files. +The following steps explain how to use an *.SCVD file in the µVision Debugger. Other tools might require different steps: + - Add the SCVD file to µVision as described in Manage Component Viewer Description Files. - Use the debug windows as described in \cviewer. -\section scvd_in_packs SCVD Files in Software Packs +\section scvd_in_packs SCVD files in software packs Software components which are part of Software Packs may add related *.SCVD files directly in the Package Description file (*.pdsc) using the \ element category \token{other}. In the *.pdsc file example below \token{Network.scvd} is added to the debugger when the component \token{:Network:Core} is selected. For details, refer to -CMSIS-Pack - Pack Description (*.PDSC) Format. +CMSIS-Pack - Pack Description (*.PDSC) Format. \code @@ -48,7 +45,7 @@ In the *.pdsc file example below \token{Network.scvd} is added to the debugger w /* ========================================================================================================================== */ /** -\page xml_elements XML Elements +\page xml_elements XML elements The top level elements of an SCVD file are: - \subpage elem_component_viewer "" — the root element enclosing all other elements @@ -716,11 +713,6 @@ Define variables, calculations, and the viewer output for a software component. 0..* - -\b Example: - -See \ref complex_scvd - */ /* ========================================================================================================================== */ @@ -2273,7 +2265,7 @@ The SCVD interpreter has the following ways to define local variables that can b -\section predefined_variable Predefined Variables +\section predefined_variable Predefined variables Predefined variables can be used without a declaration or definition. @@ -2302,7 +2294,7 @@ The element \refelem{read} accesses variables or arrays from the target system. \b Example: -The following example code is an excerpt from the FreeRTOS source code. The CMSIS-RTOS complaint FreeRTOS implementation is available as Software Pack from www.keil.com/pack. +The following example code is an excerpt from the FreeRTOS source code. The CMSIS-RTOS compliant FreeRTOS implementation is available as a Software Pack. C Code: \code @@ -2349,7 +2341,7 @@ C Code: \endcode -\page builtin_function Built-in Functions +\page builtin_function Built-in functions The SCVD interpreter has the following built-in functions for calculation of stack memory usage, access to CPU registers and application program symbols. @@ -2703,7 +2695,7 @@ The following statements in the SCVD file output the number of elements of each /* ========================================================================================================================== */ /** -\page value_output Value Output +\page value_output Value output The elements \refelem{event} and \refelem{item} use the attributes \b property and \b value to output information in the \cviewer or \erecorder. The string data of these attributes may contain \ref format_specifiers "format specifiers" to output @@ -3106,7 +3098,7 @@ The example shows the %-sign output in the \em Property column. \subsection alert_bold alert and bold output -The following example is based on the \ref simple_scvd and shows how to emphasis output with the \b bold and \b alert attribute of the +The following example shows how to emphasis output with the \b bold and \b alert attribute of the \ref elem_item "" element. *.SCVD file @@ -3154,7 +3146,7 @@ The value "Low [hex]" is shown in red and \b bold (both attributes are set). \subsection print_spec Dynamic output formats -The following example is based on the \ref simple_scvd and shows how to dynamically change the output format of an \ref elem_item "" element +The following example shows how to dynamically change the output format of an \ref elem_item "" element using a \ref elem_print "" child element. *.SCVD file diff --git a/Doxygen/view.dxy.in b/Doxygen/view.dxy.in index e5627b8..b27a429 100644 --- a/Doxygen/view.dxy.in +++ b/Doxygen/view.dxy.in @@ -44,7 +44,7 @@ PROJECT_NUMBER = "Version {projectNumber}" # for a project that appears at the top of each page and should give viewer a # quick idea about the purpose of the project. Keep the description short. -PROJECT_BRIEF = "Debugger Views for Status and Event Information" +PROJECT_BRIEF = "Record program events, display status information, and analyze execution faults" # With the PROJECT_LOGO tag one can specify a logo or an icon that is included # in the documentation. The maximum height of the logo should not exceed 55 @@ -653,7 +653,7 @@ INLINE_INFO = YES # name. If set to NO, the members will appear in declaration order. # The default value is: YES. -SORT_MEMBER_DOCS = YES +SORT_MEMBER_DOCS = NO # If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief # descriptions of file, namespace and class members alphabetically by member @@ -890,11 +890,18 @@ INPUT = src/main.md \ src/history.txt \ src/EventRecorder.md \ src/ev_stat.md \ + src/eventlist.md \ + src/examples.md \ src/cmp_viewer.md \ src/EventRecorder_fn.txt \ + src/Fault.md \ + src/Fault_fn.txt \ src/scvd_format.txt \ ../EventRecorder/Include/EventRecorder.h \ - ../EventRecorder/Config/EventRecorderConf.h + ../EventRecorder/Config/EventRecorderConf.h \ + ../Fault/Include/ARM_Fault.h \ + ../Examples/Fault/B-U585I-IOT02A/README.md \ + ../Examples/Fault/VHT_MPS2_Cortex-M7/README.md # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses @@ -1016,8 +1023,8 @@ EXCLUDE_SYMBOLS = # that contain example code fragments that are included (see the \include # command). -EXAMPLE_PATH = ..\EventRecorder\Source \ - ..\EventRecorder\Include \ +EXAMPLE_PATH = ../EventRecorder/Source \ + ../EventRecorder/Include \ # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and @@ -2306,7 +2313,8 @@ INCLUDE_FILE_PATTERNS = # recursively expanded use the := operator instead of the = operator. # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. -PREDEFINED = __DOXYGEN__ +PREDEFINED = __DOXYGEN__ \ + ARM_FAULT_FAULT_REGS_EXIST # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The diff --git a/EventRecorder/Source/EventRecorder.c b/EventRecorder/Source/EventRecorder.c index e290c01..8454934 100644 --- a/EventRecorder/Source/EventRecorder.c +++ b/EventRecorder/Source/EventRecorder.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022 Arm Limited. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,6 +22,10 @@ #include "RTE_Components.h" #include CMSIS_device_header +#if (__CORTEX_M >= 3U) +#include +#endif + #include #include "EventRecorder.h" #include "EventRecorderConf.h" @@ -46,7 +50,9 @@ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #elif defined (__GNUC__) /* GNU Compiler */ - #define __NO_INIT __attribute__ ((section (".bss.noinit"))) + #define __NO_INIT __attribute__ ((section (".noinit"))) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __NO_INIT __attribute__ ((section (".noinit"))) #else #warning "No compiler specific solution for __NO_INIT. __NO_INIT is ignored." #define __NO_INIT @@ -137,12 +143,12 @@ typedef struct { // [31]: Toggle bit } EventRecord_t; -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting /* Event Record Types (Log) */ -#define EVENT_TYPE_DATA 0x0001U // EventRecordData -#define EVENT_TYPE_VAL2 0x0002U // EventRecord2 -#define EVENT_TYPE_VAL4 0x0003U // EventRecord4 +#define EVENT_TYPE_DATA 0x0001U // EventRecordData +#define EVENT_TYPE_VAL2 0x0002U // EventRecord2 +#define EVENT_TYPE_VAL4 0x0003U // EventRecord4 /* Event Record Header (Log) */ typedef struct __PACKED { @@ -252,7 +258,7 @@ __USED const EventRecorderInfo_t EventRecorderInfo = #if (__CORTEX_M < 3U) -__STATIC_INLINE uint8_t atomic_inc8 (uint8_t *mem) { +__STATIC_INLINE uint8_t atomic_inc_8 (uint8_t *mem) { uint32_t primask = __get_PRIMASK(); uint8_t ret; @@ -266,7 +272,7 @@ __STATIC_INLINE uint8_t atomic_inc8 (uint8_t *mem) { return ret; } -__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { +__STATIC_INLINE uint32_t atomic_inc_32 (uint32_t *mem) { uint32_t primask = __get_PRIMASK(); uint32_t ret; @@ -280,27 +286,20 @@ __STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { return ret; } -__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { - uint32_t primask = __get_PRIMASK(); - uint8_t ret; - - __disable_irq(); - ret = *mem; - *mem = val; - if (primask == 0U) { - __enable_irq(); - } - - return ret; -} - -__STATIC_INLINE uint32_t atomic_wr32 (uint32_t *mem, uint32_t val) { +__STATIC_INLINE uint32_t atomic_cmp_xch_32 (uint32_t *mem, uint32_t *expected, uint32_t desired) { uint32_t primask = __get_PRIMASK(); + uint32_t val; uint32_t ret; __disable_irq(); - ret = *mem; - *mem = val; + val = *mem; + if (val == *expected) { + *mem = desired; + ret = 1U; + } else { + *expected = val; + ret = 0U; + } if (primask == 0U) { __enable_irq(); } @@ -310,185 +309,39 @@ __STATIC_INLINE uint32_t atomic_wr32 (uint32_t *mem, uint32_t val) { #else /* (__CORTEX_M >= 3U) */ -//lint ++flb - -#if defined(__CC_ARM) -static __asm uint8_t atomic_inc8 (uint8_t *mem) { - mov r2,r0 -1 - ldrexb r0,[r2] - adds r1,r0,#1 - strexb r3,r1,[r2] - cbz r3,%F2 - b %B1 -2 - bx lr -} -#else -__STATIC_INLINE uint8_t atomic_inc8 (uint8_t *mem) { - register uint32_t val, res; - register uint8_t ret; - - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrexb %[ret],[%[mem]]\n\t" - "adds %[val],%[ret],#1\n\t" - "strexb %[res],%[val],[%[mem]]\n\t" - "cbz %[res],2f\n\t" - "b 1b\n" - "2:" - : [ret] "=&l" (ret), - [val] "=&l" (val), - [res] "=&l" (res) - : [mem] "l" (mem) - : "cc", "memory" - ); - - return ret; -} -#endif - -#if defined(__CC_ARM) -static __asm uint32_t atomic_inc32 (uint32_t *mem) { - mov r2,r0 -1 - ldrex r0,[r2] - adds r1,r0,#1 - strex r3,r1,[r2] - cbz r3,%F2 - b %B1 -2 - bx lr -} -#else -__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { - register uint32_t val, res; - register uint32_t ret; - - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrex %[ret],[%[mem]]\n\t" - "adds %[val],%[ret],#1\n\t" - "strex %[res],%[val],[%[mem]]\n\t" - "cbz %[res],2f\n\t" - "b 1b\n" - "2:" - : [ret] "=&l" (ret), - [val] "=&l" (val), - [res] "=&l" (res) - : [mem] "l" (mem) - : "cc", "memory" - ); - - return ret; +__STATIC_INLINE uint8_t atomic_inc_8 (uint8_t *mem) { + return (atomic_fetch_add_explicit((_Atomic uint8_t *)mem, 1U, memory_order_relaxed)); } -#endif -#if defined(__CC_ARM) -static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { - mov r2,r0 -1 - ldrexb r0,[r2] - strexb r3,r1,[r2] - cbz r3,%F2 - b %B1 -2 - bx lr +__STATIC_INLINE uint32_t atomic_inc_32 (uint32_t *mem) { + return (atomic_fetch_add_explicit((_Atomic uint32_t *)mem, 1U, memory_order_relaxed)); } -#else -__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { - register uint32_t res; - register uint8_t ret; - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrexb %[ret],[%[mem]]\n\t" - "strexb %[res],%[val],[%[mem]]\n\t" - "cbz %[res],2f\n\t" - "b 1b\n" - "2:" - : [ret] "=&l" (ret), - [res] "=&l" (res) - : [mem] "l" (mem), - [val] "l" (val) - : "memory" - ); - - return ret; +__STATIC_INLINE uint32_t atomic_cmp_xch_32 (uint32_t *mem, uint32_t *expected, uint32_t desired) { + return((uint32_t)atomic_compare_exchange_weak_explicit((_Atomic uint32_t *)mem, + expected, + desired, + memory_order_acq_rel, + memory_order_relaxed)); } -#endif - -#if defined(__CC_ARM) -static __asm uint32_t atomic_wr32 (uint32_t *mem, uint32_t val) { - mov r2,r0 -1 - ldrex r0,[r2] - strex r3,r1,[r2] - cbz r3,%F2 - b %B1 -2 - bx lr -} -#else -__STATIC_INLINE uint32_t atomic_wr32 (uint32_t *mem, uint32_t val) { - register uint32_t res; - register uint32_t ret; - - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrex %[ret],[%[mem]]\n\t" - "strex %[res],%[val],[%[mem]]\n\t" - "cbz %[res],2f\n\t" - "b 1b\n" - "2:" - : [ret] "=&l" (ret), - [res] "=&l" (res) - : [mem] "l" (mem), - [val] "l" (val) - : "memory" - ); - - return ret; -} -#endif - -//lint --flb #endif __STATIC_INLINE uint32_t GetContext (void) { - return ((uint32_t)atomic_inc8(&EventStatus.context)); + return ((uint32_t)atomic_inc_8(&EventStatus.context)); } __STATIC_INLINE uint32_t GetRecordIndex (void) { - return (atomic_inc32(&EventStatus.record_index)); -} - -__STATIC_INLINE uint32_t UpdateTS (uint32_t ts) { - return (atomic_wr32(&EventStatus.ts_last, ts)); -} - -static uint8_t TS_OverflowLock; - -__STATIC_INLINE uint8_t LockTS_Overflow (void) { - return (atomic_wr8(&TS_OverflowLock, 1U)); -} - -__STATIC_INLINE void UnlockTS_Overflow (void) { - (void) (atomic_wr8(&TS_OverflowLock, 0U)); + return (atomic_inc_32(&EventStatus.record_index)); } __STATIC_INLINE void IncrementRecordsWritten (void) { - (void)atomic_inc32(&EventStatus.records_written); + (void)atomic_inc_32(&EventStatus.records_written); } __STATIC_INLINE void IncrementRecordsDumped (void) { - (void)atomic_inc32(&EventStatus.records_dumped); + (void)atomic_inc_32(&EventStatus.records_dumped); } @@ -501,7 +354,8 @@ __STATIC_INLINE uint32_t LockRecord (uint32_t *mem, uint32_t info) { __disable_irq(); val = *mem; if ((val & EVENT_RECORD_LOCKED) == 0U) { - val = (val & EVENT_RECORD_TBIT) | info; + val = (info | EVENT_RECORD_LOCKED) | + (val & EVENT_RECORD_TBIT); *mem = val; } else { val = 0U; @@ -509,156 +363,55 @@ __STATIC_INLINE uint32_t LockRecord (uint32_t *mem, uint32_t info) { if (primask == 0U) { __enable_irq(); } + __COMPILER_BARRIER(); return val; } -__STATIC_INLINE uint32_t UnlockRecord (uint32_t *mem, uint32_t info) { - uint32_t primask = __get_PRIMASK(); +__STATIC_INLINE void UnlockRecord (uint32_t *mem, uint32_t info) { uint32_t val; - uint32_t ret; - - __disable_irq(); - val = *mem; - if ((val & EVENT_RECORD_LOCKED) != 0U) { - *mem = info; - ret = 1U; - } else { - ret = 0U; - } - if (primask == 0U) { - __enable_irq(); - } - return ret; + __COMPILER_BARRIER(); + val = info & ~EVENT_RECORD_LOCKED; + *mem = val; } #else /* (__CORTEX_M >= 3U) */ -//lint ++flb - -#if defined(__CC_ARM) -static __asm uint32_t LockRecord (uint32_t *mem, uint32_t info) { - mov r2,r0 -1 - ldrex r0,[r2] - lsls r3,r0,#__cpp(32 - INT_LOG2(EVENT_RECORD_LOCKED)) - bcc %F2 - clrex - movs r0,#0 - bx lr -2 - and r0,r0,#__cpp(EVENT_RECORD_TBIT) - orrs r0,r1 - strex r3,r0,[r2] - cbz r3,%F3 - b %B1 -3 - bx lr -} -#else __STATIC_INLINE uint32_t LockRecord (uint32_t *mem, uint32_t info) { - register uint32_t val, res, tmp; - - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrex %[val],[%[mem]]\n\t" - "lsls %[tmp],%[val],%[Ln]\n\t" - "bcc 2f\n\t" - "clrex\n\t" - "movs %[val],#0\n\t" - "b 3f\n" - "2:\n\t" -#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) - "lsrs %[val],%[val],%[Tp]\n\t" - "lsls %[val],%[val],%[Tp]\n\t" -#else - "and %[val],%[val],%[Tbit]\n\t" -#endif - "orrs %[val],%[info]\n\t" - "strex %[res],%[val],[%[mem]]\n\t" - "cbz %[res],3f\n\t" - "b 1b\n" - "3:" - : [val] "=&l" (val), - [res] "=&l" (res), - [tmp] "=&l" (tmp) - : [mem] "l" (mem), - [info] "l" (info), - [Ln] "I" (32 - INT_LOG2(EVENT_RECORD_LOCKED)), -#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) - [Tp] "I" (INT_LOG2(EVENT_RECORD_TBIT)) -#else - [Tbit] "I" (EVENT_RECORD_TBIT) -#endif - : "cc", "memory" - ); - - return val; -} -#endif - -#if defined(__CC_ARM) -static __asm uint32_t UnlockRecord (uint32_t *mem, uint32_t info) { - mov r2,r0 -1 - ldrex r0,[r2] - lsls r0,r0,#__cpp(32 - INT_LOG2(EVENT_RECORD_LOCKED)) - bcs %F2 - clrex - movs r0,#0 - bx lr -2 - strex r3,r1,[r2] - cbz r3,%F3 - b %B1 -3 - movs r0,#1 -4 - bx lr + uint32_t val; + uint32_t val_new; + + val = *mem; + do { + if ((val & EVENT_RECORD_LOCKED) != 0U) { + //lint -e{904} "Return statement before end of function" + return 0U; + } + val_new = (info | EVENT_RECORD_LOCKED) | + (val & EVENT_RECORD_TBIT); + } while (!atomic_compare_exchange_weak_explicit((_Atomic uint32_t *)mem, + &val, + val_new, + memory_order_acquire, + memory_order_relaxed)); + + return val_new; } -#else -__STATIC_INLINE uint32_t UnlockRecord (uint32_t *mem, uint32_t info) { - register uint32_t val, res, ret; - - __ASM volatile ( - ".syntax unified\n" - "1:\n\t" - "ldrex %[val],[%[mem]]\n\t" - "lsls %[val],%[val],%[Ln]\n\t" - "bcs 2f\n\t" - "clrex\n\t" - "movs %[ret],#0\n\t" - "b 4f\n" - "2:\n\t" - "strex %[res],%[info],[%[mem]]\n\t" - "cbz %[res],3f\n\t" - "b 1b\n" - "3:\n\t" - "movs %[ret],#1\n" - "4:" - : [ret] "=&l" (ret), - [val] "=&l" (val), - [res] "=&l" (res) - : [mem] "l" (mem), - [info] "l" (info), - [Ln] "I" (32 - INT_LOG2(EVENT_RECORD_LOCKED)) - : "cc", "memory" - ); - return ret; +__STATIC_INLINE void UnlockRecord (uint32_t *mem, uint32_t info) { + uint32_t val; + + val = info & ~EVENT_RECORD_LOCKED; + (void)atomic_exchange_explicit((_Atomic uint32_t *)mem, val, memory_order_release); } -#endif - -//lint --flb #endif /* Semihosting */ -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting #ifndef EVENT_LOG_FILENAME #define EVENT_LOG_FILENAME "EventRecorder.log" @@ -675,6 +428,8 @@ static __asm int32_t semihosting_call (uint32_t operation, void *args) { bkpt 0xab bx lr } +#elif defined(__ICCARM__) +#define semihosting_call __semihosting #else __STATIC_INLINE int32_t semihosting_call (uint32_t operation, void *args) { //lint --e{438} "Last value assigned to variable not used" @@ -684,52 +439,45 @@ __STATIC_INLINE int32_t semihosting_call (uint32_t operation, void *args) { register uint32_t __r1 __ASM("r1") = (uint32_t)args; __ASM volatile ( - "bkpt 0xab" : "=r"(__r0) : "r"(__r0), "r"(__r1) : + "bkpt 0xab" : "=r"(__r0) : "r"(__r0), "r"(__r1) : "memory" ); - + return (int32_t)__r0; } #endif typedef int32_t FILEHANDLE; -static FILEHANDLE FileHandle = -1; +static FILEHANDLE FileHandle __NO_INIT; static FILEHANDLE sys_open (const char *name, uint32_t openmode) { - //lint --e{446} "side effect in initializer" - //lint --e{934} "Taking address of near auto variable" + //lint --e{446} "side effect in initializer" + //lint --e{934} "Taking address of near auto variable" struct { const char *name; uint32_t openmode; size_t len; } args = { name, openmode, strlen(name) }; - (void)args.name; - (void)args.openmode; - (void)args.len; return semihosting_call(SYS_OPEN, &args); } /* static int32_t sys_close (FILEHANDLE fh) { - //lint --e{934} "Taking address of near auto variable" + //lint --e{934} "Taking address of near auto variable" struct { FILEHANDLE fh; } args = { fh }; - (void)args.fh; return semihosting_call(SYS_CLOSE, &args); } */ static int32_t sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len) { - //lint --e{934} "Taking address of near auto variable" + //lint --e{934} "Taking address of near auto variable" struct { FILEHANDLE fh; const uint8_t *buf; uint32_t len; } args = { fh, buf, len }; - (void)args.fh; - (void)args.buf; - (void)args.len; return semihosting_call(SYS_WRITE, &args); } @@ -755,28 +503,23 @@ static uint32_t EventRecordItem (uint32_t id, uint32_t ts, uint32_t val1, uint32 i = GetRecordIndex(); record = &EventBuffer[i & (EVENT_RECORD_COUNT - 1U)]; seq = ((i / EVENT_RECORD_COUNT) << EVENT_RECORD_SEQ_POS) & EVENT_RECORD_SEQ_MASK; - info = id | + info = id | seq | ((ts >> 3) & EVENT_RECORD_MSB_TS) | ((val1 >> 2) & EVENT_RECORD_MSB_VAL1) | ((val2 >> 1) & EVENT_RECORD_MSB_VAL2) | - EVENT_RECORD_VALID | - EVENT_RECORD_LOCKED; + EVENT_RECORD_VALID; info = LockRecord(&record->info, info); if ((info & EVENT_RECORD_LOCKED) != 0U) { - info ^= EVENT_RECORD_LOCKED; info ^= EVENT_RECORD_TBIT; tbit = info & EVENT_RECORD_TBIT; record->ts = (ts & ~EVENT_RECORD_TBIT) | tbit; record->val1 = (val1 & ~EVENT_RECORD_TBIT) | tbit; record->val2 = (val2 & ~EVENT_RECORD_TBIT) | tbit; - if ((UnlockRecord(&record->info, info)) != 0U) { - IncrementRecordsWritten(); - //lint -e{904} "Return statement before end of function" - return 1U; - } else { - break; - } + UnlockRecord(&record->info, info); + IncrementRecordsWritten(); + //lint -e{904} "Return statement before end of function" + return 1U; } } @@ -785,8 +528,8 @@ static uint32_t EventRecordItem (uint32_t id, uint32_t ts, uint32_t val1, uint32 } -#ifdef RTE_Compiler_EventRecorder_Semihosting - +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting + /** Record an event with variable data size to a log file \param[in] id event identifier (component number, message number) @@ -797,14 +540,14 @@ static uint32_t EventRecordItem (uint32_t id, uint32_t ts, uint32_t val1, uint32 static void EventRecordData_Log (uint32_t id, const void *data, uint32_t len, uint64_t ts) { - //lint --e{934} "Taking address of near auto variable" + //lint --e{934} "Taking address of near auto variable" struct { EventRecordHead_t head; EventRecordData_t record; } event; event.head.type = EVENT_TYPE_DATA; - event.head.length = (uint16_t)(sizeof(event.record) + len); + event.head.length = (uint16_t)(sizeof(event.record) + len); event.record.ts = ts; event.record.info.id = (uint16_t)id; //lint -e{9034} "Expression assigned to a narrower or different essential type" @@ -826,7 +569,7 @@ static void EventRecordData_Log (uint32_t id, static void EventRecord2_Log (uint32_t id, uint32_t val1, uint32_t val2, uint64_t ts) { - //lint --e{934} "Taking address of near auto variable" + //lint --e{934} "Taking address of near auto variable" struct { EventRecordHead_t head; EventRecord2_t record; @@ -843,7 +586,7 @@ static void EventRecord2_Log (uint32_t id, (void)sys_write(FileHandle, (uint8_t *)&event, sizeof(event)); } - + /** Record an event with four 32-bit data values a log file \param[in] id event identifier (component number, message number) @@ -856,7 +599,7 @@ static void EventRecord2_Log (uint32_t id, static void EventRecord4_Log (uint32_t id, uint32_t val1, uint32_t val2, uint32_t val3, uint32_t val4, uint64_t ts) { - //lint --e{934} "Taking address of near auto variable" + //lint --e{934} "Taking address of near auto variable" struct { EventRecordHead_t head; EventRecord4_t record; @@ -879,7 +622,7 @@ static void EventRecord4_Log (uint32_t id, #endif -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting /** Get timestamp and handle overflow @@ -887,28 +630,41 @@ static void EventRecord4_Log (uint32_t id, \return timestamp (64-bit) */ static uint64_t EventGetTS64 (void) { + //lint --e{934} "Taking address of near auto variable" + //lint --e{438} "Last value assigned to variable not used" uint32_t ts; uint32_t ts_last; - uint32_t ts_last_prev; uint32_t ts_overflow; + ts_last = *((volatile uint32_t *)&EventStatus.ts_last); + __DMB(); do { ts_overflow = *((volatile uint32_t *)&EventStatus.ts_overflow); - ts_last = *((volatile uint32_t *)&EventStatus.ts_last); ts = EventRecorderTimerGetCount(); if (ts < ts_last) { - if (LockTS_Overflow() == 0U) { + uint32_t primask = __get_PRIMASK(); + uint32_t ts_latest; + uint32_t ts_updated; + __disable_irq(); + ts_latest = *((volatile uint32_t *)&EventStatus.ts_last); + if (ts_latest == ts_last) { + EventStatus.ts_last = ts; EventStatus.ts_overflow++; - UnlockTS_Overflow(); + __DMB(); + ts_updated = 1U; + } else { + ts_updated = 0U; } - ts_overflow++; - } else { - if (TS_OverflowLock != 0U) { - ts_overflow++; + if (primask == 0U) { + __enable_irq(); } + if (ts_updated == 0U) { + continue; + } + ts_overflow++; + break; } - ts_last_prev = UpdateTS(ts); - } while (ts_last != ts_last_prev); + } while (atomic_cmp_xch_32(&EventStatus.ts_last, &ts_last, ts) == 0U); return (ts | ((uint64_t)ts_overflow << 32)); } @@ -921,21 +677,37 @@ static uint64_t EventGetTS64 (void) { \return timestamp (32-bit) */ static uint32_t EventGetTS (void) { + //lint --e{934} "Taking address of near auto variable" + //lint --e{438} "Last value assigned to variable not used" uint32_t ts; uint32_t ts_last; - uint32_t ts_last_prev; + ts_last = *((volatile uint32_t *)&EventStatus.ts_last); do { - ts_last = *((volatile uint32_t *)&EventStatus.ts_last); ts = EventRecorderTimerGetCount(); if (ts < ts_last) { - if (LockTS_Overflow() == 0U) { + uint32_t primask = __get_PRIMASK(); + uint32_t ts_latest; + uint32_t ts_updated; + __disable_irq(); + ts_latest = *((volatile uint32_t *)&EventStatus.ts_last); + if (ts_latest == ts_last) { + EventStatus.ts_last = ts; EventStatus.ts_overflow++; - UnlockTS_Overflow(); + __DMB(); + ts_updated = 1U; + } else { + ts_updated = 0U; + } + if (primask == 0U) { + __enable_irq(); + } + if (ts_updated == 0U) { + continue; } + break; } - ts_last_prev = UpdateTS(ts); - } while (ts_last != ts_last_prev); + } while (atomic_cmp_xch_32(&EventStatus.ts_last, &ts_last, ts) == 0U); return (ts); } @@ -1178,7 +950,7 @@ uint32_t EventRecorderInitialize (uint32_t recording, uint32_t start) { EventStatus.records_written = 0U; EventStatus.records_dumped = 0U; memset(&EventBuffer[0], 0, sizeof(EventBuffer)); -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting FileHandle = sys_open(EVENT_LOG_FILENAME, MODE_wb); #endif } else { @@ -1204,7 +976,6 @@ uint32_t EventRecorderInitialize (uint32_t recording, uint32_t start) { EventStatus.ts_freq = freq; EventStatus.ts_last = 0U; EventStatus.ts_overflow = 0U; - TS_OverflowLock = 0U; } else { #if (EVENT_TIMESTAMP_SOURCE == 0) #if ((__CORTEX_M >= 3U) && (__CORTEX_M != 23U)) @@ -1226,7 +997,6 @@ uint32_t EventRecorderInitialize (uint32_t recording, uint32_t start) { EventStatus.ts_freq = freq; EventStatus.ts_last = 0U; EventStatus.ts_overflow = 0U; - TS_OverflowLock = 0U; #else ret = 1U; #endif @@ -1238,7 +1008,7 @@ uint32_t EventRecorderInitialize (uint32_t recording, uint32_t start) { (void)EventRecorderEnable(EventRecordAll, EvtStatistics_No, EvtStatistics_No); (void)EventRecorderEnable(EventRecordOp, EvtPrintf_No, EvtPrintf_No); -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord2_Log(ID_EVENT_INIT & EVENT_RECORD_ID_MASK, EventStatus.init_count, EventStatus.ts_freq, ts64); ts = (uint32_t)ts64; @@ -1327,7 +1097,7 @@ uint32_t EventRecorderStart (void) { } EventStatus.state = 1U; -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord2_Log(ID_EVENT_START & EVENT_RECORD_ID_MASK, 0U, 0U, ts64); ts = (uint32_t)ts64; @@ -1353,7 +1123,7 @@ uint32_t EventRecorderStop (void) { } EventStatus.state = 0U; -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord2_Log(ID_EVENT_STOP & EVENT_RECORD_ID_MASK, 0U, 0U, ts64); ts = (uint32_t)ts64; @@ -1375,7 +1145,7 @@ uint32_t EventRecorderClockUpdate (void) { EventStatus.ts_freq = EventRecorderTimerGetFreq(); -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord2_Log(ID_EVENT_CLOCK & EVENT_RECORD_ID_MASK, EventStatus.ts_freq, 0U, ts64); ts = (uint32_t)ts64; @@ -1414,7 +1184,7 @@ uint32_t EventRecordData (uint32_t id, const void *data, uint32_t len) { return 1U; } -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecordData_Log(id, data, len, ts64); ts = (uint32_t)ts64; @@ -1496,7 +1266,7 @@ uint32_t EventRecord2 (uint32_t id, uint32_t val1, uint32_t val2) { return 1U; } -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord2_Log(id, val1, val2, ts64); ts = (uint32_t)ts64; @@ -1532,7 +1302,7 @@ uint32_t EventRecord4 (uint32_t id, return 1U; } -#ifdef RTE_Compiler_EventRecorder_Semihosting +#ifdef RTE_CMSIS_View_EventRecorder_Semihosting uint64_t ts64 = EventGetTS64(); EventRecord4_Log(id, val1, val2, val3, val4, ts64); ts = (uint32_t)ts64; diff --git a/Examples/EventStatistic/EventStatistic.cdefault.yml b/Examples/EventStatistic/EventStatistic.cdefault.yml deleted file mode 100644 index 4dbf4e6..0000000 --- a/Examples/EventStatistic/EventStatistic.cdefault.yml +++ /dev/null @@ -1,34 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.4/tools/projmgr/schemas/cdefault.schema.json - -default: - - build-types: - - type: Debug - compiler: AC6 - misc: - - C*: - - -O1 - - -g - - -Wno-macro-redefined - - -Wno-pragma-pack - - -Wno-parentheses-equality - - C: - - -std=c99 - - ASM: - - -masm=auto - - Link: - - --entry=Reset_Handler - - type: Release - compiler: AC6 - misc: - - C*: - - -O3 - - -Wno-macro-redefined - - -Wno-pragma-pack - - -Wno-parentheses-equality - - C: - - -std=c99 - - ASM: - - -masm=auto - - Link: - - --entry=Reset_Handler diff --git a/Examples/EventStatistic/EventStatistic.cproject.yml b/Examples/EventStatistic/EventStatistic.cproject.yml index 6f89867..9292609 100644 --- a/Examples/EventStatistic/EventStatistic.cproject.yml +++ b/Examples/EventStatistic/EventStatistic.cproject.yml @@ -1,25 +1,26 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.4/tools/projmgr/schemas/cproject.schema.json - project: - # packs: - # - pack: ARM::CMSIS - - components: - - component: ARM::Device:Definition - - component: ARM::Device:Startup&Baremetal - - component: ARM::CMSIS:CORE - - - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-View groups: - group: Documentation - files: - - file: ./README.md - - group: main files: - - file: ./main.c - - group: ScatterFile + - file: README.md + + - group: Source Files files: - - file: ./RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct - + - file: main.c + + components: + - component: CMSIS:CORE + + - component: CMSIS-View:Event Recorder&Semihosting + + - component: Native Driver:Timeout + - component: Native Driver:SysCounter + - component: Native Driver:SysTimer + + - component: Device:Definition + - component: Device:Startup&Baremetal diff --git a/Examples/EventStatistic/EventStatistic.csolution.yml b/Examples/EventStatistic/EventStatistic.csolution.yml index 97df489..cf147b2 100644 --- a/Examples/EventStatistic/EventStatistic.csolution.yml +++ b/Examples/EventStatistic/EventStatistic.csolution.yml @@ -1,11 +1,11 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.4/tools/projmgr/schemas/csolution.schema.json - solution: + + created-for: CMSIS-Toolbox@2.0.0 + cdefault: + packs: - - pack: ARM::CMSIS - - pack: Keil::ARM_Compiler + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0 - - pack: ARM::V2M_MPS3_SSE_300_BSP@1.2.0 target-types: - type: AVH device: ARM::SSE-300-MPS3 @@ -13,9 +13,15 @@ solution: endian: little fpu: "off" trustzone: off - misc: - - Link: - - '--diag_suppress 6314,6848' + + build-types: + - type: Release + debug: off + optimize: size + + - type: Debug + debug: on + optimize: none projects: - project: ./EventStatistic.cproject.yml diff --git a/Examples/EventStatistic/README.md b/Examples/EventStatistic/README.md index f347bf2..1b323c1 100644 --- a/Examples/EventStatistic/README.md +++ b/Examples/EventStatistic/README.md @@ -1,125 +1,121 @@ -# Event Statistic Example +# Event Statistic Example This project shows how to use start/stop events with the Event Recorder that allow to measure execution times with: -- different slots (0 - 15) -- different groups (A - D) - + +- different slots (0 - 15) +- different groups (A - D) + The following API calls control this time recording: + - `EventStart` starts a timer slot. -- `EventStop` stops the related timer. +- `EventStop` stops the related timer. - `EventStop` with slot 15 stops the timers of all slots for the specified group. Refer to [Using Event Statistics](https://arm-software.github.io/CMSIS-View/main/ev_stat.html#es_use) for more information. This demo application does some time consuming calculations that are recorded -and can be displayed in the Event Statistics window. +and can be displayed in the Event Statistics window. ->Note: -This example runs on Arm Virtual Hardware on the [VHT_MPS3_Corstone_SSE-300 model](https://arm-software.github.io/AVH/main/simulation/html/Using.html) and does not require any hardware. +>Note: +This example runs on Arm Virtual Hardware on the [VHT_MPS3_Corstone_SSE-300 model](https://arm-software.github.io/AVH/main/simulation/html/Using.html) and does not require any hardware. ## Prerequisites Tools: -- [**CMSIS-Toolbox 1.0.0 or higher**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox) -- [**Keil MDK 5.37 or higher**](https://www.keil.com/mdk5) - - Arm Compiler 6 (part of MDK) - - Arm Virtual Hardware for MPS3 platform with Corstone-300 (part of MDK-Professional) -- [**eventlist**](https://github.com/ARM-software/CMSIS-View/releases/latest) utility from this repository + - [**CMSIS-Toolbox v2.0.0**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) or newer + - [**Keil MDK v5.38**](https://www.keil.com/mdk5) or newer containing: + - Arm Compiler 6 (part of MDK) + - Arm Virtual Hardware for MPS3 platform with Corstone-300 (part of MDK-Professional) + - [**eventlist**](https://github.com/ARM-software/CMSIS-View/releases/latest) utility from this repository As an alternative the example runs also on [**AMI Arm Virtual Hardware**](https://aws.amazon.com/marketplace/search/results?searchTerms=Arm+Virtual+Hardware) available via the AWS Marketplace as this image contains all relevant tools. ## Compile Project -You may need to install missing software packs with this command sequence: - -```txt -> csolution list packs -s .\EventStatistic.csolution.yml -m >packs.txt -> cpackget add -f packs.txt -``` - -The following commands convert and build the project: +The following commands convert and build the project with build type `Debug` and target type `AVH`: -```txt -> csolution convert -s .\EventStatistic.csolution.yml - -> cbuild .\EventStatistic.Debug+AVH.cprj +```sh +cbuild EventStatistic.csolution.yml --update-rte -p -c .Debug+AVH ``` -> NOTE: The `*.cprj` file may be also imported into Keil MDK for execution. - ## Execute The following command runs the example for 60 seconds (parameter *--simlimit*) on the VHT simulation model: -```txt -> C:/Keil_v5/ARM/VHT/VHT_MPS3_Corstone_SSE-300 -f vht_config.txt --simlimit=60 -C cpu0.semihosting-enable=1 -a ./out/EventStatistic/AVH/Debug/EventStatistic.Debug+AVH.axf +```sh +VHT_MPS3_Corstone_SSE-300 -f vht_config.txt --simlimit=60 out/EventStatistic/AVH/Debug/EventStatistic.axf ``` -When using `cpu0.semihosting-enable=1` the file `EventRecorder.log` is generated that contains the events that are generated during execution. This file is the input for the `eventlist` utility. ## Analyze Events This file can be analyzed using the `eventlist` utility with the following command: -```txt -> eventlist -s EventRecorder.log +```sh +eventlist -s EventRecorder.log Start/Stop event statistic -------------------------- Event count total min max average first last ----- ----- ----- --- --- ------- ----- ---- -A(0) 10000 31.44509s 1.69997ms 3.80041ms 3.14451ms 3.29962ms 3.59964ms - Min: Start: 31.94980000 val1=0x000001f5, val2=0x00000000 Stop: 31.95149997 val1=0x10004d43, val2=0x0000003c - Max: Start: 84.70757283 val1=0x000003a5, val2=0x00000000 Stop: 84.71137324 val1=0x10004d43, val2=0x00000038 +A(0) 1000 3.15054s 1.79081ms 3.84733ms 3.15054ms 3.28370ms 2.54044ms + Min: Start: 1.06694371 val1=0x000001f5, val2=0x00000000 Stop: 1.06873452 val1=0x10004e5d, val2=0x0000003c + Max: Start: 0.57401429 val1=0x000003d3, val2=0x00000000 Stop: 0.57786162 val1=0x10004e5d, val2=0x00000038 -A(15) 10000 169.75100s 2.49964ms 42.78648s 16.97510ms 3.99995ms 4.30004ms - Min: Start: 81.87697318 val1=0x000001f8, val2=0x00000000 Stop: 81.87947282 val1=0x10004d43, val2=0x0000003c - Max: Start: 37.41299154 val1=0x0000032f, val2=0x00000000 Stop: 80.19947314 val1=0x10004d43, val2=0x0000003c +A(15) 1000 4.14074s 2.51858ms 5.83115ms 4.14074ms 4.01147ms 3.26821ms + Min: Start: 1.06621594 val1=0x000001f5, val2=0x00000000 Stop: 1.06873452 val1=0x10004e5d, val2=0x0000003c + Max: Start: 1.83631161 val1=0x000003e8, val2=0x00000000 Stop: 1.84214276 val1=0x10004e5d, val2=0x0000003c -B(0) 10000 10.83677s 0.00000s 169.29161ms 1.08368ms 1.60016ms 1.00010ms - Min: Start: 1.76679986 val1=0x10004d43, val2=0x0000005c Stop: 1.76679986 val1=0x0000018e, val2=0x00000047 - Max: Start: 37.24369993 val1=0x10004d43, val2=0x0000005c Stop: 37.41299154 val1=0x000066bf, val2=0x00000487 +B(0) 1000 1.02458s 9.44000µs 1.70736ms 1.02458ms 1.57731ms 707.89000µs + Min: Start: 1.93540476 val1=0x10004e5d, val2=0x0000005c Stop: 1.93541420 val1=0x00000004, val2=0x00000003 + Max: Start: 3.49351979 val1=0x10004e5d, val2=0x0000005c Stop: 3.49522715 val1=0x00007fe5, val2=0x0000053d -C(0) 1 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s - Min: Start: 0.00000000 val1=0x10004d43, val2=0x00000057 Stop: 180.67371888 val1=0x10004d43, val2=0x00000062 - Max: Start: 0.00000000 val1=0x10004d43, val2=0x00000057 Stop: 180.67371888 val1=0x10004d43, val2=0x00000062 +C(0) 1 5.17924s 5.17924s 5.17924s 5.17924s 5.17924s 5.17924s + Min: Start: 0.00001219 val1=0x10004e5d, val2=0x00000057 Stop: 5.17925291 val1=0x10004e5d, val2=0x00000067 + Max: Start: 0.00001219 val1=0x10004e5d, val2=0x00000057 Stop: 5.17925291 val1=0x10004e5d, val2=0x00000067 ``` When adding the AXF file and the [SCVD file](https://arm-software.github.io/CMSIS-View/main/SCVD_Format.html) to the `eventlist` command the context of the program is shown -``` -> eventlist -a .\out\EventStatistic\AVH\Debug\EventStatistic.Debug+AVH.axf -I ...\Local\Arm\Packs\Keil\ARM_Compiler\1.7.2\EventRecorder.scvd .\EventRecorder.log + +```sh +eventlist -a out/EventStatistic/AVH/Debug/EventStatistic.axf -I $CMSIS_PACK_ROOT/ARM/CMSIS-View/1.0.0/EventRecorder/EventRecorder.scvd EventRecorder.log : -53947 180.66841874 EvCtrl StartAv(15) v1=776 v2=0 -53948 180.66911914 EvCtrl StartAv(0) v1=776 v2=0 -53949 180.67271878 EvCtrl StopA(15) File=./EventStatistic/main.c(60) -53950 180.67271878 EvCtrl StartB(0) File=./EventStatistic/main.c(92) -53951 180.67371888 EvCtrl StopBv(0) v1=15150 v2=802 -53952 180.67371888 EvCtrl StopC(0) File=./EventStatistic/main.c(98) + 5391 5.17525179 EvCtrl StartAv(15) v1=617 v2=0 + 5392 5.17597956 EvCtrl StartAv(0) v1=617 v2=0 + 5393 5.17852000 EvCtrl StopA(15) File=./EventStatistic/main.c(60) + 5394 5.17852488 EvCtrl StartB(0) File=./EventStatistic/main.c(92) + 5395 5.17923277 EvCtrl StopBv(0) v1=8659 v2=553 + 5396 5.17925291 EvCtrl StopC(0) File=./EventStatistic/main.c(103) Start/Stop event statistic -------------------------- Event count total min max average first last ----- ----- ----- --- --- ------- ----- ---- -A(0) 10000 31.44509s 1.69997ms 3.80041ms 3.14451ms 3.29962ms 3.59964ms - Min: Start: 31.94980000 v1=501 v2=0 Stop: 31.95149997 File=./EventStatistic/main.c(60) - Max: Start: 84.70757283 v1=933 v2=0 Stop: 84.71137324 File=./EventStatistic/main.c(56) +A(0) 1000 3.15054s 1.79081ms 3.84733ms 3.15054ms 3.28370ms 2.54044ms + Min: Start: 1.06694371 v1=501 v2=0 Stop: 1.06873452 File=./EventStatistic/main.c(60) + Max: Start: 0.57401429 v1=979 v2=0 Stop: 0.57786162 File=./EventStatistic/main.c(56) -A(15) 10000 169.75100s 2.49964ms 42.78648s 16.97510ms 3.99995ms 4.30004ms - Min: Start: 81.87697318 v1=504 v2=0 Stop: 81.87947282 File=./EventStatistic/main.c(60) - Max: Start: 37.41299154 v1=815 v2=0 Stop: 80.19947314 File=./EventStatistic/main.c(60) +A(15) 1000 4.14074s 2.51858ms 5.83115ms 4.14074ms 4.01147ms 3.26821ms + Min: Start: 1.06621594 v1=501 v2=0 Stop: 1.06873452 File=./EventStatistic/main.c(60) + Max: Start: 1.83631161 v1=1000 v2=0 Stop: 1.84214276 File=./EventStatistic/main.c(60) -B(0) 10000 10.83677s 0.00000s 169.29161ms 1.08368ms 1.60016ms 1.00010ms - Min: Start: 1.76679986 File=./EventStatistic/main.c(92) Stop: 1.76679986 v1=398 v2=71 - Max: Start: 37.24369993 File=./EventStatistic/main.c(92) Stop: 37.41299154 v1=26303 v2=1159 +B(0) 1000 1.02458s 9.44000µs 1.70736ms 1.02458ms 1.57731ms 707.89000µs + Min: Start: 1.93540476 File=./EventStatistic/main.c(92) Stop: 1.93541420 v1=4 v2=3 + Max: Start: 3.49351979 File=./EventStatistic/main.c(92) Stop: 3.49522715 v1=32741 v2=1341 -C(0) 1 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s 180.67372s - Min: Start: 0.00000000 File=./EventStatistic/main.c(87) Stop: 180.67371888 File=./EventStatistic/main.c(98) - Max: Start: 0.00000000 File=./EventStatistic/main.c(87) Stop: 180.67371888 File=./EventStatistic/main.c(98) +C(0) 1 5.17924s 5.17924s 5.17924s 5.17924s 5.17924s 5.17924s + Min: Start: 0.00001219 File=./EventStatistic/main.c(87) Stop: 5.17925291 File=./EventStatistic/main.c(103) + Max: Start: 0.00001219 File=./EventStatistic/main.c(87) Stop: 5.17925291 File=./EventStatistic/main.c(103) ``` +When using Windows Command Prompt use the following command: +```sh +eventlist -a out/EventStatistic/AVH/Debug/EventStatistic.axf -I %CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.0/EventRecorder/EventRecorder.scvd EventRecorder.log +``` - +> Note: If CMSIS-View v1.0.0 pack is not installed, in the previous command replace corresponding path with the path of the latest installed pack + (for example replace "%CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.0/EventRecorder/" with "%CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.1/EventRecorder/") \ No newline at end of file diff --git a/Examples/EventStatistic/RTE/Compiler/EventRecorderConf.h b/Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h similarity index 56% rename from Examples/EventStatistic/RTE/Compiler/EventRecorderConf.h rename to Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h index 34458c7..c6b921d 100644 --- a/Examples/EventStatistic/RTE/Compiler/EventRecorderConf.h +++ b/Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h @@ -1,11 +1,24 @@ -/*------------------------------------------------------------------------------ - * MDK - Component ::Event Recorder - * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Name: EventRecorderConf.h - * Purpose: Event Recorder Configuration + * Purpose: Event Recorder software component configuration options * Rev.: V1.1.0 - *----------------------------------------------------------------------------*/ + */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- @@ -27,7 +40,7 @@ // Time Stamp Clock Frequency [Hz] <0-1000000000> // Defines initial time stamp clock frequency (0 when not used) -#define EVENT_TIMESTAMP_FREQ 0 +#define EVENT_TIMESTAMP_FREQ 0U // diff --git a/Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 b/Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 new file mode 100644 index 0000000..9802f2a --- /dev/null +++ b/Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h index 78d909d..5bf4c86 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021 Arm Limited. All rights reserved. + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,84 +17,68 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::Drivers:USART #define RTE_USART0 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::Drivers:USART #define RTE_USART1 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] // Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC #define RTE_ISRAM0_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] // Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC #define RTE_ISRAM1_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] // Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC #define RTE_SRAM_MPC 1 -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] // Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC #define RTE_QSPI_MPC 1 -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] // Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC #define RTE_PPC_SSE300_MAIN0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN0] -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] // Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC #define RTE_PPC_SSE300_MAIN_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP0] -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] // Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC #define RTE_PPC_SSE300_MAIN_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1] -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] // Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC #define RTE_PPC_SSE300_PERIPH0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH0] -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] // Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC #define RTE_PPC_SSE300_PERIPH1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH1] -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC #define RTE_PPC_SSE300_PERIPH_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP0] -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC #define RTE_PPC_SSE300_PERIPH_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP1] -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC #define RTE_PPC_SSE300_PERIPH_EXP2 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2] -// Flash device emulated by SRAM [Driver_Flash0] +// Flash device emulated by SRAM [Driver_Flash0] // Configuration settings for Driver_Flash0 in component ::Drivers:Flash #define RTE_FLASH0 1 -// Flash device emulated by SRAM [Driver_Flash0] -// I2C SBCon [Driver_I2C0] +// I2C SBCon [Driver_I2C0] // Configuration settings for Driver_I2C0 in component ::Drivers:I2C #define RTE_I2C0 1 -// I2C SBCon [Driver_I2C0] #endif /* __RTE_DEVICE_H */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..5bf4c86 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 1 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 1 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 1 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h index 5ad6fb6..bfc348f 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,7 +17,7 @@ #ifndef __CMSIS_DRIVER_CONFIG_H__ #define __CMSIS_DRIVER_CONFIG_H__ -#include "system_core_init.h" +#include "system_SSE300MPS3.h" #include "device_cfg.h" #include "device_definition.h" #include "platform_base_address.h" diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h index d3591f2..2ff3eaa 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. * * Licensed under the Apache License Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -33,6 +33,14 @@ #define MPS3_IO_S #define MPS3_IO_DEV MPS3_IO_DEV_S +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + /* ARM UART Controller PL011 */ #define UART0_CMSDK_S #define UART0_CMSDK_DEV UART0_CMSDK_DEV_S @@ -93,10 +101,6 @@ #define GPIO3_CMSDK_S #define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S -/* ARM MPS3 IO FPGAIO driver structures */ -#define ARM_MPS3_IO_FPGAIO_S -#define ARM_MPS3_IO_FPGAIO_DEV ARM_MPS3_IO_FPGAIO_DEV_S - /* System Watchdogs */ #define SYSWDOG_ARMV8_M_S #define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S @@ -142,4 +146,4 @@ #define SPI1_PL022_DEV SPI1_PL022_DEV_S -#endif /* __DEVICE_CFG_H__ */ \ No newline at end of file +#endif /* __DEVICE_CFG_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 new file mode 100644 index 0000000..343c63d --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 @@ -0,0 +1,78 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* + * Place the CMSE Veneers (containing the SG instruction) after the code, in + * a separate 32 bytes aligned region so that the SAU can programmed to just + * set this region as Non-Secure Callable. The maximum size of this + * executable region makes it only used the space left over by the ER_CODE + * region so that you can rely on code+veneer size combined will not exceed + * the S_CODE_SIZE value. We also substract from the available space the + * area used to align this section on 32 bytes boundary (for SAU conf). + */ + ER_CODE_CMSE_VENEER +0 ALIGN 32 { + *(Veneer$$CMSE) + } + /* + * This dummy region ensures that the next one will be aligned on a 32 bytes + * boundary, so that the following region will not be mistakenly configured + * as Non-Secure Callable by the SAU. + */ + ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h index c5c3ee7..b813097 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h @@ -16,8 +16,8 @@ /** * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for MPS3 SSE-300 + - * Ethos-U55 AN547 platform. + * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 + + * Ethos-U55 platform. */ #ifndef __PLATFORM_BASE_ADDRESS_H__ @@ -32,7 +32,7 @@ #define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ #define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ #define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ +#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */ #define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ /* Non-Secure Subsystem peripheral region */ #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ @@ -43,14 +43,14 @@ #define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ #define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ #define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ -#define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ -#define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ -#define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ -#define DMA_0_BASE_NS 0x41200000 /* DMA 0 Non-Secure base address */ -#define DMA_1_BASE_NS 0x41201000 /* DMA 1 Non-Secure base address */ -#define DMA_2_BASE_NS 0x41202000 /* DMA 2 Non-Secure base address */ -#define DMA_3_BASE_NS 0x41203000 /* DMA 3 Non-Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */ +#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */ #define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ #define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ #define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ @@ -71,7 +71,8 @@ #define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ /* Non-Secure MSTEXPPIHL Peripheral region */ #define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter registers Non-Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ #define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ #define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ #define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ @@ -81,6 +82,10 @@ #define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ #define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ #define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ +#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */ +#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */ +#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */ +#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */ #define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ #define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ #define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ @@ -105,7 +110,7 @@ #define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ #define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ #define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ +#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */ #define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ /* Secure Subsystem peripheral region */ #define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ @@ -119,14 +124,14 @@ #define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ #define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ #define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ -#define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ -#define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ -#define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ -#define DMA_0_BASE_S 0x51200000 /* DMA 0 Secure base address */ -#define DMA_1_BASE_S 0x51201000 /* DMA 1 Secure base address */ -#define DMA_2_BASE_S 0x51202000 /* DMA 2 Secure base address */ -#define DMA_3_BASE_S 0x51203000 /* DMA 3 Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */ +#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */ +#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */ +#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */ +#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */ #define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ #define USB_BASE_S 0x51500000 /* USB Secure base address */ #define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ @@ -157,7 +162,8 @@ #define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ /* Secure MSTEXPPIHL Peripheral region */ #define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter registers Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ #define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ #define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ #define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ @@ -167,6 +173,10 @@ #define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ #define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ #define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ +#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */ +#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */ +#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */ +#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */ #define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ #define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ #define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ @@ -192,9 +202,9 @@ #define ITCM_SIZE (0x00080000) /* 512 kB */ #define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00200000) /* 2 MB */ -#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -#define ISRAM1_SIZE (0x00200000) /* 2 MB */ +#define SRAM_SIZE (0x00100000) /* 1 MB */ +#define ISRAM0_SIZE (0x00100000) /* 1 MB */ +#define ISRAM1_SIZE (0x00100000) /* 1 MB */ #define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ #define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ #define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 new file mode 100644 index 0000000..b813097 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2019-2021 Arm Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file platform_base_address.h + * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 + + * Ethos-U55 platform. + */ + +#ifndef __PLATFORM_BASE_ADDRESS_H__ +#define __PLATFORM_BASE_ADDRESS_H__ + +/* ======= Defines peripherals memory map addresses ======= */ +/* Non-secure memory map addresses */ +#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ +#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ +#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ +#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ +#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ +#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ +#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ +#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */ +#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ +/* Non-Secure Subsystem peripheral region */ +#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ +#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ +#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ +/* Non-Secure MSTEXPPILL Peripheral region */ +#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ +#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ +#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ +#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */ +#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */ +#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ +#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ +#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ +#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ +#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ +#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ +#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ +#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ +/* Non-Secure Subsystem peripheral region */ +#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ +#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ +#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ +#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ +#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ +#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ +#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ +#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ +#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ +/* Non-Secure MSTEXPPIHL Peripheral region */ +#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ +#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ +#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ +#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ +#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ +#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ +#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ +#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ +#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ +#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ +#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */ +#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */ +#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */ +#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */ +#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ +#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ +#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ +#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ +#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ +#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ +#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ +#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ +#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ +#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ +#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ +#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ +#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ +#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ +#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ + +/* Secure memory map addresses */ +#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ +#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ +#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ +#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ +#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ +#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ +#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ +#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */ +#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ +/* Secure Subsystem peripheral region */ +#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ +#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ +#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ +#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ +#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ +#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ +/* Secure MSTEXPPILL Peripheral region */ +#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ +#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ +#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ +#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */ +#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */ +#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */ +#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */ +#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */ +#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ +#define USB_BASE_S 0x51500000 /* USB Secure base address */ +#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ +#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ +#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ +#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ +#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ +#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ +#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ +#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ +#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ +/* Secure Subsystem peripheral region */ +#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ +#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ +#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ +#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ +#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ +#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ +#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ +#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ +#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ +#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ +#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ +#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ +#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ +#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ +#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ +#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ +/* Secure MSTEXPPIHL Peripheral region */ +#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ +#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ +#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ +#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ +#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ +#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ +#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ +#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ +#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ +#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ +#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */ +#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */ +#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */ +#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */ +#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ +#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ +#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ +#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ +#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ +#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ +#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ +#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ +#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ +#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ +#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ +#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ +#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ +#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ +#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ + +/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ +#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller + * Access from Non-secure software is only allowed + * if AIRCR.BFHFNMINS is set to 1 */ + +/* Memory size definitions */ +#define ITCM_SIZE (0x00080000) /* 512 kB */ +#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ +#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ +#define SRAM_SIZE (0x00100000) /* 1 MB */ +#define ISRAM0_SIZE (0x00100000) /* 1 MB */ +#define ISRAM1_SIZE (0x00100000) /* 1 MB */ +#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ +#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ +#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ + +/* Defines for Driver MPC's */ +/* SRAM -- 2 MB */ +#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) +#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) +#define MPC_SRAM_RANGE_OFFSET_NS (0x0) +#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) +#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) +#define MPC_SRAM_RANGE_OFFSET_S (0x0) + +/* QSPI -- 8 MB*/ +#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) +#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) +#define MPC_QSPI_RANGE_OFFSET_NS (0x0) +#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) +#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) +#define MPC_QSPI_RANGE_OFFSET_S (0x0) + +/* ISRAM0 -- 2 MB*/ +#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) +#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) +#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) +#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) +#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) +#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) + +/* ISRAM1 -- 2 MB*/ +#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) +#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) +#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) +#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) +#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) +#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) + +/* DDR4 -- 2GB (8 * 256 MB) */ +#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) +#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) +#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) +#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) +#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) +#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) +#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) +#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) +#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) + +#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h index 0271e8d..32ac16b 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021 Arm Limited + * Copyright (c) 2016-2022 Arm Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -37,13 +37,8 @@ #define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) #define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) -/* Non-Secure regions */ -#define NS_CODE_START ( NS_ROM_ALIAS ) -#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) -#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) - -#define NS_DATA_START ( NS_RAM_ALIAS ) -#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) -#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) #endif /* __REGION_DEFS_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h index b2e272c..e789786 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 Arm Limited + * Copyright (c) 2018-2022 Arm Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,21 +28,15 @@ /* Secure Code */ #define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00040000) /* 256 kB */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ /* Secure Data */ #define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Non-Secure Code */ -#define NS_ROM_ALIAS (0x01000000) /* SRAM_BASE_NS */ -#define TOTAL_NS_ROM_SIZE (0x00040000) /* 256 kB */ - -/* Non-Secure Data */ -#define NS_RAM_ALIAS (0x21000000) /* ISRAM0_BASE_NS */ -#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ /* Heap and Stack sizes for secure and nonsecure applications */ #define HEAP_SIZE (0x00000400) /* 1 KiB */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h new file mode 100644 index 0000000..4158869 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h @@ -0,0 +1,322 @@ +#ifndef REGIONS_SSE-300-MPS3_H +#define REGIONS_SSE-300-MPS3_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// ROM Configuration +// ======================= +// + +// RAM Configuration +// ======================= +// ITCM_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __RAM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00080000 +#define __RAM0_SIZE 0x00080000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// SRAM_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x01000000 +#define __RAM1_BASE 0x01000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM1_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// DTCM0_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM2_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM2_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM2_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM2_NOINIT 0 +// + +// DTCM1_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20020000 +#define __RAM3_BASE 0x20020000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM3_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM3_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM3_NOINIT 0 +// + +// DTCM2_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20040000 +#define __RAM4_BASE 0x20040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM4_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM4_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM4_NOINIT 0 +// + +// DTCM3_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20060000 +#define __RAM5_BASE 0x20060000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM5_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM5_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM5_NOINIT 0 +// + +// ISRAM0_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21000000 +#define __RAM6_BASE 0x21000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM6_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM6_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM6_NOINIT 0 +// + +// ISRAM1_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21100000 +#define __RAM7_BASE 0x21100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM7_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM7_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM7_NOINIT 0 +// + +// QSPI_SRAM_NS +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x28000000 +#define __RAM8_BASE 0x28000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM8_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM8_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM8_NOINIT 0 +// + +// ITCM_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x10000000 +#define __RAM9_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00080000 +#define __RAM9_SIZE 0x00080000 +// Default region +// Enables memory region globally for the application. +#define __RAM9_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM9_NOINIT 0 +// + +// SRAM_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __RAM10_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM10_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM10_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM10_NOINIT 0 +// + +// DTCM0_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30000000 +#define __RAM11_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM11_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM11_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM11_NOINIT 0 +// + +// DTCM1_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30020000 +#define __RAM12_BASE 0x30020000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM12_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM12_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM12_NOINIT 0 +// + +// DTCM2_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30040000 +#define __RAM13_BASE 0x30040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM13_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM13_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM13_NOINIT 0 +// + +// DTCM3_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30060000 +#define __RAM14_BASE 0x30060000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM14_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM14_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM14_NOINIT 0 +// + +// ISRAM0_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM15_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM15_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM15_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM15_NOINIT 0 +// + +// ISRAM1_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31100000 +#define __RAM16_BASE 0x31100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM16_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM16_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM16_NOINIT 0 +// + +// QSPI_SRAM_S +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x38000000 +#define __RAM17_BASE 0x38000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM17_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM17_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM17_NOINIT 0 +// + +// + + +#endif /* REGIONS_SSE-300-MPS3_H */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c index e53ddd3..d1e59d7 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c @@ -21,7 +21,7 @@ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b */ -#include "cmsis.h" +#include "SSE300MPS3.h" /*---------------------------------------------------------------------------- Exception / Interrupt Handler Function Prototype diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 new file mode 100644 index 0000000..d1e59d7 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK __NO_RETURN handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TIMER0_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_Handler) +DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) +DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TIMER0_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_Handler, /* 27: TIMER 3 Handler */ + CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ + CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c index e4ace70..d2f28b7 100644 --- a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -59,28 +59,28 @@ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); #endif -/* CMSIS System Initialization */ #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set + * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU + * into retention state + */ + PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; #endif #ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif -/* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __ISB(); + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); -/* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set - CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU - into retention state */ -#define CPDLPSTATE_ADDR (0xE001E300UL) -#define CPDLPSTATE *(volatile unsigned int *) CPDLPSTATE_ADDR - CPDLPSTATE &= 0xFFFFFF00UL; } diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..1d8c3b6 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set + * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU + * into retention state + */ + PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +} diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h new file mode 100644 index 0000000..feba5e9 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#ifndef __SYSTEM_CORE_INIT_H__ +#define __SYSTEM_CORE_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ + +/** + * \brief Initializes the system + */ +extern void SystemInit(void); + +/** + * \brief Restores system core clock + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 new file mode 100644 index 0000000..feba5e9 --- /dev/null +++ b/Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#ifndef __SYSTEM_CORE_INIT_H__ +#define __SYSTEM_CORE_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ + +/** + * \brief Initializes the system + */ +extern void SystemInit(void); + +/** + * \brief Restores system core clock + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/Examples/EventStatistic/cdefault.yml b/Examples/EventStatistic/cdefault.yml new file mode 100644 index 0000000..30c0b64 --- /dev/null +++ b/Examples/EventStatistic/cdefault.yml @@ -0,0 +1,17 @@ +default: + + compiler: AC6 + + misc: + - for-compiler: AC6 + C-CPP: + - -ffunction-sections + C: + - -std=gnu11 + ASM: + - -masm=auto + Link: + - --entry=Reset_Handler + - --map + - --info summarysizes + - --diag_suppress 6314 diff --git a/Examples/EventStatistic/main.c b/Examples/EventStatistic/main.c index dc56a57..2efefb3 100644 --- a/Examples/EventStatistic/main.c +++ b/Examples/EventStatistic/main.c @@ -86,18 +86,20 @@ int main (void) { EventRecorderClockUpdate(); EventStartC (0); // start measurement event group C, slot 0 printf ("Started\n"); - for (j = 0; j < 10000; j++) { + for (j = 0; j < 1000; j++) { CalcSinTable (); // calculate table with sinus values EventStartB(0); // start group B, slot 0 MaxSqrtSum = rand () / 65536; // limit for sqrt calculation num = FindSqrtSum ((float) MaxSqrtSum); // return number of sqrt operations EventStopBv(0, MaxSqrtSum, num); // stop group B, slot 0, output values: MaxSqrtSum, num + + if (j % 10 == 0) { + printf("Progress: %3d%%\r", j/10+1); + } } + printf ("Finished \n"); EventStopC(0); // stop measurement event group C, slot 0 - - while (1) { - __NOP(); - } + return 0; } diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/NonSecure/FrameworkCubeMX.gpdsc b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/NonSecure/FrameworkCubeMX.gpdsc new file mode 100644 index 0000000..0101ffe --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/NonSecure/FrameworkCubeMX.gpdsc @@ -0,0 +1,70 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 04/05/2023 07:21:19 + + + + + STM32CubeMX Environment + + $P../Board/$B/STM32CubeMX + + $SMDK/CubeMX/STM32CubeMxLauncher.exe + $D + #P + $SMDK/CubeMX/TZ + $B + + + + + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/main.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/main.h new file mode 100644 index 0000000..5d6c099 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/main.h @@ -0,0 +1,103 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined ( __ICCARM__ ) +# define CMSE_NS_CALL __cmse_nonsecure_call +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_CALL __attribute((cmse_nonsecure_call)) +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* Function pointer declaration in non-secure*/ +#if defined ( __ICCARM__ ) +typedef void (CMSE_NS_CALL *funcptr)(void); +#else +typedef void CMSE_NS_CALL (*funcptr)(void); +#endif + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define T_SWCLK_Pin GPIO_PIN_14 +#define T_SWCLK_GPIO_Port GPIOA +#define T_SWO_Pin GPIO_PIN_3 +#define T_SWO_GPIO_Port GPIOB +#define USER_Button_Pin GPIO_PIN_13 +#define USER_Button_GPIO_Port GPIOC +#define LED_RED_Pin GPIO_PIN_6 +#define LED_RED_GPIO_Port GPIOH +#define LED_GREEN_Pin GPIO_PIN_7 +#define LED_GREEN_GPIO_Port GPIOH +#define T_VCP_RX_Pin GPIO_PIN_10 +#define T_VCP_RX_GPIO_Port GPIOA +#define T_SWDIO_Pin GPIO_PIN_13 +#define T_SWDIO_GPIO_Port GPIOA +#define T_VCP_TX_Pin GPIO_PIN_9 +#define T_VCP_TX_GPIO_Port GPIOA + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/partition_stm32u585xx.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/partition_stm32u585xx.h new file mode 100644 index 0000000..9745ed5 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/partition_stm32u585xx.h @@ -0,0 +1,675 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file partition_stm32u585xx.h + * @author MCD Application Team + * @brief CMSIS STM32U585xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2021 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* USER CODE END Header */ + +#ifndef PARTITION_STM32U585XX_H +#define PARTITION_STM32U585XX_H +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ +/* USER CODE BEGIN 0 */ +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ + +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 +/* USER CODE END 0 */ +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ +/* USER CODE BEGIN 1 */ +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ +/* USER CODE END 1 */ +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state +// PVD_AVD_IRQn <0=> Secure state +// RTC_IRQn <0=> Secure state +// RTC_S_IRQn <0=> Secure state +// TAMP_IRQn <0=> Secure state +// RAMCFG_IRQn <0=> Secure state +// FLASH_IRQn <0=> Secure state +// FLASH_S_IRQn <0=> Secure state +// GTZC_IRQn <0=> Secure state +// RCC_IRQn <0=> Secure state +// RCC_S_IRQn <0=> Secure state +// EXTI0_IRQn <0=> Secure state +// EXTI1_IRQn <0=> Secure state +// EXTI2_IRQn <0=> Secure state +// EXTI3_IRQn <0=> Secure state +// EXTI4_IRQn <0=> Secure state +// EXTI5_IRQn <0=> Secure state +// EXTI6_IRQn <0=> Secure state +// EXTI7_IRQn <0=> Secure state +// EXTI8_IRQn <0=> Secure state +// EXTI9_IRQn <0=> Secure state +// EXTI10_IRQn <0=> Secure state +// EXTI11_IRQn <0=> Secure state +// EXTI12_IRQn <0=> Secure state +// EXTI13_IRQn <0=> Secure state +// EXTI14_IRQn <0=> Secure state +// EXTI15_IRQn <0=> Secure state +// IWDG_IRQn <0=> Secure state +// SAES_IRQn <0=> Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state +// ADC1_IRQn <0=> Secure state +// DAC1_IRQn <0=> Secure state +// FDCAN1_IT0_IRQn <0=> Secure state +// FDCAN1_IT1_IRQn <0=> Secure state +// TIM1_BRK_IRQn <0=> Secure state +// TIM1_UP_IRQn <0=> Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state +// TIM1_CC_IRQn <0=> Secure state +// TIM2_IRQn <0=> Secure state +// TIM3_IRQn <0=> Secure state +// TIM4_IRQn <0=> Secure state +// TIM5_IRQn <0=> Secure state +// TIM6_IRQn <0=> Secure state +// TIM7_IRQn <0=> Secure state +// TIM8_BRK_IRQn <0=> Secure state +// TIM8_UP_IRQn <0=> Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state +// TIM8_CC_IRQn <0=> Secure state +// I2C1_EV_IRQn <0=> Secure state +// I2C1_ER_IRQn <0=> Secure state +// I2C2_EV_IRQn <0=> Secure state +// I2C2_ER_IRQn <0=> Secure state +// SPI1_IRQn <0=> Secure state +// SPI2_IRQn <0=> Secure state +// USART1_IRQn <0=> Secure state +// USART2_IRQn <0=> Secure state +// USART3_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state +// UART5_IRQn <0=> Secure state +// LPUART1_IRQn <0=> Secure state +// LPTIM1_IRQn <0=> Secure state +// LPTIM2_IRQn <0=> Secure state +// TIM15_IRQn <0=> Secure state +// TIM16_IRQn <0=> Secure state +// TIM17_IRQn <0=> Secure state +// COMP_IRQn <0=> Secure state +// OTG_FS_IRQn <0=> Secure state +// CRS_IRQn <0=> Secure state +// FMC_IRQn <0=> Secure state +// OCTOSPI1_IRQn <0=> Secure state +// PWR_S3WU_IRQn <0=> Secure state + +// SDMMC1_IRQn <0=> Secure state +// SDMMC2_IRQn <0=> Secure state + +// GPDMA1_Channel8_IRQn <0=> Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state +// I2C3_EV_IRQn <0=> Secure state +// I2C3_ER_IRQn <0=> Secure state +// SAI1_IRQn <0=> Secure state +// SAI2_IRQn <0=> Secure state +// TSC_IRQn <0=> Secure state +// AES_IRQn <0=> Secure state + +// RNG_IRQn <0=> Secure state +// FPU_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..108) + +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..125 + +// HASH_IRQn <0=> Secure state +// PKA_IRQn <0=> Secure state +// LPTIM3_IRQn <0=> Secure state +// SPI3_IRQn <0=> Secure state +// I2C4_ER_IRQn <0=> Secure state +// I2C4_EV_IRQn <0=> Secure state +// MDF1_FLT0_IRQn <0=> Secure state +// MDF1_FLT1_IRQn <0=> Secure state +// MDF1_FLT2_IRQn <0=> Secure state +// MDF1_FLT3_IRQn <0=> Secure state +// UCPD1_IRQn <0=> Secure state +// ICACHE_IRQn <0=> Secure state +// OTFDEC1_IRQn <0=> Secure state +// OTFDEC2_IRQn <0=> Secure state +// LPTIM4_IRQn <0=> Secure state +// DCACHE1_IRQn <0=> Secure state +// ADF1_IRQn <0=> Secure state +// ADC4_IRQn <0=> Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state +// DMA2D_IRQn <0=> Secure state +// DCMI_PSSI_IRQn <0=> Secure state +// OCTOSPI2_IRQn <0=> Secure state +// MDF1_FLT4_IRQn <0=> Secure state +// MDF1_FLT5_IRQn <0=> Secure state +// CORDIC_IRQn <0=> Secure state +// FMAC_IRQn <0=> Secure state + +*/ + +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* USER CODE BEGIN 2 */ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} +/* USER CODE END 2 */ +#endif /* PARTITION_STM32U585XX_H */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_hal_conf.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_hal_conf.h new file mode 100644 index 0000000..d74e7c8 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_hal_conf.h @@ -0,0 +1,506 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_CONF_H +#define STM32U5xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +#define HAL_GTZC_MODULE_ENABLED +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OTFDEC_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +#define HAL_ICACHE_MODULE_ENABLED +/*#define HAL_DCACHE_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ + +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768UL /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32u5xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GPU2D_REGISTER_CALLBACKS 0U /* GPU2D register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32u5xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32u5xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32u5xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_DCACHE_MODULE_ENABLED + #include "stm32u5xx_hal_dcache.h" +#endif /* HAL_DCACHE_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED + #include "stm32u5xx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32u5xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32u5xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED +#include "stm32u5xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32u5xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32u5xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32u5xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32u5xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32u5xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32u5xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32u5xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32u5xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32u5xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32u5xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32u5xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32u5xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32u5xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32u5xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32u5xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32u5xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32u5xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32u5xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32u5xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32u5xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32u5xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32u5xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32u5xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32u5xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32u5xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32u5xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32u5xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32u5xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32u5xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32u5xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32u5xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32u5xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32u5xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32u5xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32u5xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32u5xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32u5xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32u5xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32u5xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32u5xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32u5xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32u5xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED + #include "stm32u5xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32u5xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED + #include "stm32u5xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32u5xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32u5xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_CONF_H */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_it.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_it.h new file mode 100644 index 0000000..278027e --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_it.h @@ -0,0 +1,63 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32U5xx_IT_H +#define __STM32U5xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +/* USER CODE BEGIN EFP */ +extern void HardFault_Handler (void); +extern void MemManage_Handler (void); +extern void BusFault_Handler (void); +extern void UsageFault_Handler (void); +extern void SecureFault_Handler (void); +extern void DebugMon_Handler (void); +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32U5xx_IT_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/MX_Device.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/MX_Device.h new file mode 100644 index 0000000..8216c2d --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/MX_Device.h @@ -0,0 +1,141 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 04/05/2023 07:21:21 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSIDIV_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSICalibrationValue 16 +#define MX_HSE_VALUE 16000000 +#define MX_SYSCLKFreq_VALUE 160000000 +#define MX_HCLKFreq_Value 160000000 +#define MX_FCLKCortexFreq_Value 160000000 +#define MX_CortexFreq_Value 160000000 +#define MX_AHBFreq_Value 160000000 +#define MX_APB1Freq_Value 160000000 +#define MX_APB2Freq_Value 160000000 +#define MX_APB1TimFreq_Value 160000000 +#define MX_APB2TimFreq_Value 160000000 +#define MX_ADCFreq_Value 16000000 +#define MX_I2C1Freq_Value 160000000 +#define MX_I2C2Freq_Value 160000000 +#define MX_I2C3Freq_Value 160000000 +#define MX_MSI_VALUE 4000000 +#define MX_SPI1Freq_Value 160000000 +#define MX_SPI2Freq_Value 160000000 +#define MX_SPI3Freq_Value 160000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 4000000 +#define MX_LPTIM2Freq_Value 160000000 +#define MX_RTCFreq_Value 32000 +#define MX_MCO1PinFreq_Value 160000000 +#define MX_CRSFreq_Value 48000000 +#define MX_SWPMI1Freq_Value 4000000 +#define MX_SAI1Freq_Value 258000000 +#define MX_SAI2Freq_Value 258000000 +#define MX_LPUART1Freq_Value 160000000 +#define MX_UART4Freq_Value 160000000 +#define MX_UART5Freq_Value 160000000 +#define MX_USART1Freq_Value 160000000 +#define MX_USART2Freq_Value 160000000 +#define MX_USART3Freq_Value 160000000 + +/*-------------------------------- CORTEX_M33_S --------------------------------*/ + +#define MX_CORTEX_M33_S 1 + +/*-------------------------------- GTZC_S --------------------------------*/ + +#define MX_GTZC_S 1 + +/*-------------------------------- ICACHE --------------------------------*/ + +#define MX_ICACHE 1 + +/*-------------------------------- NVIC1 --------------------------------*/ + +#define MX_NVIC1 1 + +/*-------------------------------- PWR --------------------------------*/ + +#define MX_PWR 1 + +/*-------------------------------- SYS_S --------------------------------*/ + +#define MX_SYS_S 1 + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PC13 - USER_Button */ +#define MX_PC13_Pin PC13 +#define MX_PC13_GPIOx GPIOC +#define MX_PC13_GPIO_PuPd GPIO_NOPULL +#define MX_PC13_GPIO_Pin GPIO_PIN_13 +#define MX_PC13_GPIO_Mode GPIO_MODE_INPUT +#define MX_PC13_PinAttribute CortexM33NS + +#define MX_USER_Button_Pin MX_PC13_Pin +#define MX_USER_Button_GPIOx MX_PC13_GPIOx +#define MX_USER_Button_GPIO_PuPd MX_PC13_GPIO_PuPd +#define MX_USER_Button_GPIO_Pin MX_PC13_GPIO_Pin +#define MX_USER_Button_GPIO_Mode MX_PC13_GPIO_Mode +#define MX_USER_Button_PinAttribute MX_PC13_PinAttribute + +/* Pin PH7 - LED_GREEN */ +#define MX_PH7_GPIO_Speed GPIO_SPEED_FREQ_HIGH +#define MX_PH7_Pin PH7 +#define MX_PH7_GPIOx GPIOH +#define MX_PH7_PinState GPIO_PIN_SET +#define MX_PH7_GPIO_PuPd GPIO_NOPULL +#define MX_PH7_GPIO_Pin GPIO_PIN_7 +#define MX_PH7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP +#define MX_PH7_PinAttribute CortexM33NS + +#define MX_LED_GREEN_GPIO_Speed MX_PH7_GPIO_Speed +#define MX_LED_GREEN_Pin MX_PH7_Pin +#define MX_LED_GREEN_GPIOx MX_PH7_GPIOx +#define MX_LED_GREEN_PinState MX_PH7_PinState +#define MX_LED_GREEN_GPIO_PuPd MX_PH7_GPIO_PuPd +#define MX_LED_GREEN_GPIO_Pin MX_PH7_GPIO_Pin +#define MX_LED_GREEN_GPIO_ModeDefaultOutputPP MX_PH7_GPIO_ModeDefaultOutputPP +#define MX_LED_GREEN_PinAttribute MX_PH7_PinAttribute + +/* Pin PH6 - LED_RED */ +#define MX_PH6_GPIO_Speed GPIO_SPEED_FREQ_HIGH +#define MX_PH6_Pin PH6 +#define MX_PH6_GPIOx GPIOH +#define MX_PH6_PinState GPIO_PIN_SET +#define MX_PH6_GPIO_PuPd GPIO_NOPULL +#define MX_PH6_GPIO_Pin GPIO_PIN_6 +#define MX_PH6_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP +#define MX_PH6_PinAttribute CortexM33NS + +#define MX_LED_RED_GPIO_Speed MX_PH6_GPIO_Speed +#define MX_LED_RED_Pin MX_PH6_Pin +#define MX_LED_RED_GPIOx MX_PH6_GPIOx +#define MX_LED_RED_PinState MX_PH6_PinState +#define MX_LED_RED_GPIO_PuPd MX_PH6_GPIO_PuPd +#define MX_LED_RED_GPIO_Pin MX_PH6_GPIO_Pin +#define MX_LED_RED_GPIO_ModeDefaultOutputPP MX_PH6_GPIO_ModeDefaultOutputPP +#define MX_LED_RED_PinAttribute MX_PH6_PinAttribute + +#endif /* __MX_DEVICE_H */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/main.c b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/main.c new file mode 100644 index 0000000..c28c168 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/main.c @@ -0,0 +1,405 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "ARM_Fault.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* Non-secure Vector table to jump to (internal Flash Bank2 here) */ +/* Caution: address must correspond to non-secure internal Flash where is */ +/* mapped in the non-secure vector table */ +#define VTOR_TABLE_NS_START_ADDR 0x08100000UL +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +static void NonSecure_Init(void); +static void SystemPower_Config(void); +static void MX_GPIO_Init(void); +static void MX_GTZC_S_Init(void); +static void MX_ICACHE_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/** + * This functions takes 1 ms to execute + * (it executes for 1 ms on an MCU where the 'loop' takes 4 cycles, + * it works correctly for all compiler optimization levels) + */ +static __attribute__((noinline)) void wait_1ms (void) { + __ASM volatile ( /* 1 ms delay */ + ".syntax unified\n\t" /* Use unified syntax */ + ".global SystemCoreClock\n\t" /* Global variable SystemCoreClock */ + "ldr r0,=SystemCoreClock\n\t" /* Load the memory address of the SystemCoreClock global variable */ + "ldr r0,[r0,#0]\n\t" /* Load the SystemCoreClock value */ + "ldr r1,=4000\n\t" /* 4 cycles per loop * 1000 ms in a second */ + "udiv r0,r0,r1\n\t" /* Number of required loops for 1ms */ + "loop: \n\r" /* Loop (duration is 4 cycles), 1 cycles less then duration of instructions due to dual-issue pipeline */ + "nop \n\t" /* No Operation (1 cycle) */ + "subs r0,1\n\t" /* Subtract 1 from counter (1 cycle) */ + "bne loop\n\t" /* Loop if counter is not 0 (3 cycles) */ + ); +} + +/** + * Override default HAL_GetTick function + */ +uint32_t HAL_GetTick (void) { + static uint32_t ticks = 0U; + + wait_1ms(); + ticks++; + + return ticks; +} + +/** + * Override default HAL_InitTick function + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + + UNUSED(TickPriority); + + return HAL_OK; +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* SAU/IDAU, FPU and interrupts secure/non-secure allocation setup done */ +/* in SystemInit() based on partition_stm32u585xx.h file's definitions. */ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the System Power */ + SystemPower_Config(); + /* GTZC initialisation */ + MX_GTZC_S_Init(); + + /* USER CODE BEGIN SysInit */ + SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk | // Enable SecureFault + SCB_SHCSR_USGFAULTENA_Msk; // Enable UsageFault + + // BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault + SCB->AIRCR = (SCB->AIRCR & ~SCB_AIRCR_VECTKEYSTAT_Msk) | 0x05FA0000 | SCB_AIRCR_BFHFNMINS_Msk; + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ICACHE_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /*************** Setup and jump to non-secure *******************************/ + + NonSecure_Init(); + + /* Non-secure software does not return, this code is not executed */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief Non-secure call function + * This function is responsible for Non-secure initialization and switch + * to non-secure state + * @retval None + */ +static void NonSecure_Init(void) +{ + funcptr_NS NonSecure_ResetHandler; + + SCB_NS->VTOR = VTOR_TABLE_NS_START_ADDR; + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS((*(uint32_t *)VTOR_TABLE_NS_START_ADDR)); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_NS)(*((uint32_t *)((VTOR_TABLE_NS_START_ADDR) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); +} + +/** + * @brief Power Configuration + * @retval None + */ +static void SystemPower_Config(void) +{ + + /* + * Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); + + /* + * Switch to SMPS regulator instead of LDO + */ + if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) + { + Error_Handler(); + } +/* USER CODE BEGIN PWR */ +/* USER CODE END PWR */ +} + +/** + * @brief GTZC_S Initialization Function + * @param None + * @retval None + */ +static void MX_GTZC_S_Init(void) +{ + + /* USER CODE BEGIN GTZC_S_Init 0 */ + + /* USER CODE END GTZC_S_Init 0 */ + + MPCBB_ConfigTypeDef MPCBB_Area_Desc = {0}; + + /* USER CODE BEGIN GTZC_S_Init 1 */ + + /* USER CODE END GTZC_S_Init 1 */ + if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_RNG, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK) + { + Error_Handler(); + } + MPCBB_Area_Desc.SecureRWIllegalMode = GTZC_MPCBB_SRWILADIS_ENABLE; + MPCBB_Area_Desc.InvertSecureState = GTZC_MPCBB_INVSECSTATE_NOT_INVERTED; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[0] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[1] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[2] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[3] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[4] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[5] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[6] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[7] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[8] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[9] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[10] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[11] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[12] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[13] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[14] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[15] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[16] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[17] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[18] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[19] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[20] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[21] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[22] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[23] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[24] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[25] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[26] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[27] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[28] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[29] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[30] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[31] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[16] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[17] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[18] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[19] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[20] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[21] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[22] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[23] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[24] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[25] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[26] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[27] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[28] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[29] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[30] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[31] = 0x00000000; + MPCBB_Area_Desc.AttributeConfig.MPCBB_LockConfig_array[0] = 0x00000000; + if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_Area_Desc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN GTZC_S_Init 2 */ + + /* USER CODE END GTZC_S_Init 2 */ + +} + +/** + * @brief ICACHE Initialization Function + * @param None + * @retval None + */ +static void MX_ICACHE_Init(void) +{ + + /* USER CODE BEGIN ICACHE_Init 0 */ + + /* USER CODE END ICACHE_Init 0 */ + + /* USER CODE BEGIN ICACHE_Init 1 */ + + /* USER CODE END ICACHE_Init 1 */ + + /** Enable instruction cache in 1-way (direct mapped cache) + */ + if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) + { + Error_Handler(); + } + if (HAL_ICACHE_Enable() != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ICACHE_Init 2 */ + + /* USER CODE END ICACHE_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /*IO attributes management functions */ + HAL_GPIO_ConfigPinAttributes(USER_Button_GPIO_Port, USER_Button_Pin, GPIO_PIN_NSEC); + + /*IO attributes management functions */ + HAL_GPIO_ConfigPinAttributes(GPIOH, LED_RED_Pin|LED_GREEN_Pin, GPIO_PIN_NSEC); + + /*IO attributes management functions */ + HAL_GPIO_ConfigPinAttributes(GPIOA, T_VCP_RX_Pin|T_VCP_TX_Pin, GPIO_PIN_NSEC); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/secure_nsc.c b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/secure_nsc.c new file mode 100644 index 0000000..338b568 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/secure_nsc.c @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file Secure/Src/secure_nsc.c + * @author MCD Application Team + * @brief This file contains the non-secure callable APIs (secure world) + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* USER CODE BEGIN Non_Secure_CallLib */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "secure_nsc.h" +/** @addtogroup STM32U5xx_HAL_Examples + * @{ + */ + +/** @addtogroup Templates + * @{ + */ + +/* Global variables ----------------------------------------------------------*/ +void *pSecureFaultCallback = NULL; /* Pointer to secure fault callback in Non-secure */ +void *pSecureErrorCallback = NULL; /* Pointer to secure error callback in Non-secure */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Secure registration of non-secure callback. + * @param CallbackId callback identifier + * @param func pointer to non-secure function + * @retval None + */ +CMSE_NS_ENTRY void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func) +{ + if(func != NULL) + { + switch(CallbackId) + { + case SECURE_FAULT_CB_ID: /* SecureFault Interrupt occurred */ + pSecureFaultCallback = func; + break; + case GTZC_ERROR_CB_ID: /* GTZC Interrupt occurred */ + pSecureErrorCallback = func; + break; + default: + /* unknown */ + break; + } + } +} + +/** + * @} + */ + +/** + * @} + */ +/* USER CODE END Non_Secure_CallLib */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_hal_msp.c b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_hal_msp.c new file mode 100644 index 0000000..8cc705d --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_hal_msp.c @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_GTZC1_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_it.c b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_it.c new file mode 100644 index 0000000..5226ca6 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/stm32u5xx_it.c @@ -0,0 +1,105 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32u5xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32u5xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ +__attribute__((naked)) void HardFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +__attribute__((naked)) void MemManage_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +__attribute__((naked)) void BusFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +__attribute__((naked)) void UsageFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +__attribute__((naked)) void SecureFault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +__attribute__((naked)) void DebugMon_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ + +/******************************************************************************/ +/* STM32U5xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32u5xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/system_stm32u5xx_s.c b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/system_stm32u5xx_s.c new file mode 100644 index 0000000..1dba4bc --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure/Src/system_stm32u5xx_s.c @@ -0,0 +1,399 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in secure application when the system implements + * the TrustZone-M security. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 8 + *----------------------------------------------------------------------------- + * PLL1_P | 7 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL2_SRC | NA + *----------------------------------------------------------------------------- + * PLL2_M | NA + *----------------------------------------------------------------------------- + * PLL2_N | NA + *----------------------------------------------------------------------------- + * PLL2_P | NA + *----------------------------------------------------------------------------- + * PLL2_Q | NA + *----------------------------------------------------------------------------- + * PLL2_R | NA + *----------------------------------------------------------------------------- + * PLL3_SRC | NA + *----------------------------------------------------------------------------- + * PLL3_M | NA + *----------------------------------------------------------------------------- + * PLL3_N | NA + *----------------------------------------------------------------------------- + * PLL3_P | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "stm32u5xx.h" +#include "partition_stm32u5xx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + RCC->CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC->PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32u5xxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange; + float_t fracn1, pllvco; + + /* Get MSI Range frequency--------------------------------------------------*/ + if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x00: /* No clock sent to PLL*/ + pllvco = (float_t)0U; + break; + + case 0x02: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = ((float_t)msirange / (float_t)pllm); + break; + } + + pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U); + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); + SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr); + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value (HCLK) + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure_nsclib/secure_nsc.h b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure_nsclib/secure_nsc.h new file mode 100644 index 0000000..85ceec0 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Board/B-U585I-IOT02A/STM32CubeMX/Secure_nsclib/secure_nsc.h @@ -0,0 +1,46 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file Secure_nsclib/secure_nsc.h + * @author MCD Application Team + * @brief Header for secure non-secure callable APIs list + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* USER CODE BEGIN Non_Secure_CallLib_h */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef SECURE_NSC_H +#define SECURE_NSC_H + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief non-secure callback ID enumeration definition + */ +typedef enum +{ + SECURE_FAULT_CB_ID = 0x00U, /*!< System secure fault callback ID */ + GTZC_ERROR_CB_ID = 0x01U /*!< GTZC secure error callback ID */ +} SECURE_CallbackIDTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func); + +#endif /* SECURE_NSC_H */ +/* USER CODE END Non_Secure_CallLib_h */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Debug.ini b/Examples/Fault/B-U585I-IOT02A/Debug.ini new file mode 100644 index 0000000..ebaed2a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Debug.ini @@ -0,0 +1,25 @@ +/*---------------------------------------------------------------------------- + * Name: Debug.ini + * Purpose: Debugger initialization script + *----------------------------------------------------------------------------*/ + +FUNC void OnResetExec (void) { /* This function executes upon software RESET */ + /* Allow debugger access to non-secure Internal Flash (for reading osRtxConfig and EventRecorderInfo structures) */ + _WDWORD(0xE000EDD8, 0x00000000); /* SAU RNR: Region = 0 */ + _WDWORD(0xE000EDDC, 0x08100000); /* SAU RBAR: Base address = 0x08100000 (start of non-secure Internal Flash as configured by SECWM2_PSTRT and SECWM2_PEND Flash Option Bytes) */ + _WDWORD(0xE000EDE0, 0x081FFFE1); /* SAU RLAR: Limit address = 0x081FFFFF (end of non-secure Internal Flash as configured by SECWM2_PSTRT and SECWM2_PEND Flash Option Bytes), NSC = 0, ENABLE = 1 */ + _WDWORD(0xE000EDD0, 0x00000001); /* SAU CTRL: enable SAU */ + + /* Clear first part of non-secure SRAM3 to clear any RTOS states */ + MEMSET(0x20040000, 0x10000, 0); +} + +LOAD "..\\Secure\\Objects\\Fault_S.axf" incremental +LOAD "..\\NonSecure\\Objects\\Fault_NS.axf" incremental + +RESET /* Reset the CPU */ + +OnResetExec(); /* Call this function on initial hardware reset */ + + /* Go To start of the main function in the Non-Secure application */ +G, \\Fault_NS\../Board/B-U585I-IOT02A/STM32CubeMX/NonSecure/Src/main.c\main diff --git a/Examples/Fault/B-U585I-IOT02A/Fault.csolution.yml b/Examples/Fault/B-U585I-IOT02A/Fault.csolution.yml new file mode 100644 index 0000000..2452271 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Fault.csolution.yml @@ -0,0 +1,22 @@ +solution: + + created-for: CMSIS-Toolbox@2.0.0 + cdefault: + + packs: + - pack: Keil::STM32U5xx_DFP@2.1.0 + - pack: Keil::B-U585I-IOT02A_BSP@1.0.0 + + target-types: + - type: HW + board: STMicroelectronics::B-U585I-IOT02A + device: STMicroelectronics::STM32U585AIIx + + build-types: + - type: Debug + debug: on + optimize: none + + projects: + - project: ./Secure/Fault_S.cproject.yml + - project: ./NonSecure/Fault_NS.cproject.yml diff --git a/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw b/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw new file mode 100644 index 0000000..d8693cf --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw @@ -0,0 +1,21 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\Secure\Fault_S.uvprojx + 1 + 1 + + + + .\NonSecure\Fault_NS.uvprojx + 1 + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw.uvgui b/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw.uvgui new file mode 100644 index 0000000..e97e25d --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Fault.uvmpw.uvgui @@ -0,0 +1,1797 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1200 + + + + + + 1 + 0 + + 100 + 0 + + <1>..\README.md + 0 + 1 + 1 + 0 + + 0 + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Flash.ini b/Examples/Fault/B-U585I-IOT02A/Flash.ini new file mode 100644 index 0000000..c68e32e --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Flash.ini @@ -0,0 +1,7 @@ +/*---------------------------------------------------------------------------- + * Name: Flash.ini + * Purpose: Debugger flashing script + *----------------------------------------------------------------------------*/ + +LOAD "..\\Secure\\Objects\\Fault_S.axf" incremental +LOAD "..\\NonSecure\\Objects\\Fault_NS.axf" incremental diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultPrint.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultPrint.c new file mode 100644 index 0000000..845451e --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultPrint.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARM_Fault.h" + +#include + +// General defines +#ifndef EXC_RETURN_SPSEL +#define EXC_RETURN_SPSEL (1UL << 2) +#endif + +// Armv8/8.1-M Mainline architecture related defines +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) +#ifndef SAU_SFSR_LSERR_Msk +#define SAU_SFSR_LSERR_Msk (1UL << 7) // SAU SFSR: LSERR Mask +#endif +#ifndef SAU_SFSR_SFARVALID_Msk +#define SAU_SFSR_SFARVALID_Msk (1UL << 6) // SAU SFSR: SFARVALID Mask +#endif +#ifndef SAU_SFSR_LSPERR_Msk +#define SAU_SFSR_LSPERR_Msk (1UL << 5) // SAU SFSR: LSPERR Mask +#endif +#ifndef SAU_SFSR_INVTRAN_Msk +#define SAU_SFSR_INVTRAN_Msk (1UL << 4) // SAU SFSR: INVTRAN Mask +#endif +#ifndef SAU_SFSR_AUVIOL_Msk +#define SAU_SFSR_AUVIOL_Msk (1UL << 3) // SAU SFSR: AUVIOL Mask +#endif +#ifndef SAU_SFSR_INVER_Msk +#define SAU_SFSR_INVER_Msk (1UL << 2) // SAU SFSR: INVER Mask +#endif +#ifndef SAU_SFSR_INVIS_Msk +#define SAU_SFSR_INVIS_Msk (1UL << 1) // SAU SFSR: INVIS Mask +#endif +#ifndef SAU_SFSR_INVEP_Msk +#define SAU_SFSR_INVEP_Msk (1UL) // SAU SFSR: INVEP Mask +#endif +#endif + +// ARM_FaultPrint function ----------------------------------------------------- + +/** + Output decoded fault information via STDIO. + Should be called when system is running in normal operating mode with + standard input/output fully functional. +*/ +void ARM_FaultPrint (void) { + int8_t fault_info_valid; + + /* Check if there is available valid fault information */ + fault_info_valid = (int8_t)ARM_FaultOccurred(); + + // Output: Header and version information + printf("\n --- Fault (v%s) ---\n\n", (const char *)ARM_FaultVersion); + + // Output: Message if fault info is invalid + if (fault_info_valid == 0) { + printf("\n No fault saved yet or fault information is invalid!\n\n"); + return; + } + + // Output: Fault count + printf(" Fault count: %u\n\n", (unsigned int)ARM_FaultInfo.Count); + + // Output: Exception which saved the fault information + printf(" Exception Handler: "); + + if (ARM_FaultInfo.Content.TZ_Enabled != 0U) { + if (ARM_FaultInfo.Content.TZ_SaveMode != 0U) { + printf("Secure - "); + } else { + printf("Non-Secure - "); + } + } + + switch (ARM_FaultInfo.ExceptionState.xPSR & IPSR_ISR_Msk) { + case 3: + printf("HardFault"); + break; + case 4: + printf("MemManage fault"); + break; + case 5: + printf("BusFault"); + break; + case 6: + printf("UsageFault"); + break; + case 7: + printf("SecureFault"); + break; + default: + printf("unknown, exception number = %u", (unsigned int)(ARM_FaultInfo.ExceptionState.xPSR & IPSR_ISR_Msk)); + break; + } + printf("\n"); + +#if (ARM_FAULT_ARCH_ARMV8x_M != 0) + // Output: state in which the fault occurred + if (ARM_FaultInfo.Content.TZ_Enabled != 0U) { + printf(" State: "); + + if (ARM_FaultInfo.Content.TZ_FaultMode != 0U) { + printf("Secure"); + } else { + printf("Non-Secure"); + } + printf("\n"); + } +#endif + + // Output: Mode in which the fault occurred + printf(" Mode: "); + + if ((ARM_FaultInfo.ExceptionState.EXC_RETURN & EXC_RETURN_SPSEL) == 0U) { + printf("Handler"); + } else { + printf("Thread"); + } + printf("\n"); + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) // If fault registers exist + /* Output: Decoded HardFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_hfsr = ARM_FaultInfo.FaultRegisters.HFSR; + + if ((scb_hfsr & (SCB_HFSR_VECTTBL_Msk | + SCB_HFSR_FORCED_Msk | + SCB_HFSR_DEBUGEVT_Msk )) != 0U) { + + printf(" Fault: HardFault - "); + + if ((scb_hfsr & SCB_HFSR_VECTTBL_Msk) != 0U) { + printf("Bus error on vector read"); + } + if ((scb_hfsr & SCB_HFSR_FORCED_Msk) != 0U) { + printf("Escalated fault (original fault was disabled or it caused another lower priority fault)"); + } + if ((scb_hfsr & SCB_HFSR_DEBUGEVT_Msk) != 0U) { + printf("Breakpoint hit with Debug Monitor disabled"); + } + printf("\n"); + } + } + + /* Output: Decoded MemManage fault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_mmfar = ARM_FaultInfo.FaultRegisters.MMFAR; + + if ((scb_cfsr & (SCB_CFSR_IACCVIOL_Msk | + SCB_CFSR_DACCVIOL_Msk | + SCB_CFSR_MUNSTKERR_Msk | +#ifdef SCB_CFSR_MLSPERR_Msk + SCB_CFSR_MLSPERR_Msk | +#endif + SCB_CFSR_MSTKERR_Msk )) != 0U) { + + printf(" Fault: MemManage - "); + + if ((scb_cfsr & SCB_CFSR_IACCVIOL_Msk) != 0U) { + printf("Instruction execution failure due to MPU violation or fault"); + } + if ((scb_cfsr & SCB_CFSR_DACCVIOL_Msk) != 0U) { + printf("Data access failure due to MPU violation or fault"); + } + if ((scb_cfsr & SCB_CFSR_MUNSTKERR_Msk) != 0U) { + printf("Exception exit unstacking failure due to MPU access violation"); + } + if ((scb_cfsr & SCB_CFSR_MSTKERR_Msk) != 0U) { + printf("Exception entry stacking failure due to MPU access violation"); + } +#ifdef SCB_CFSR_MLSPERR_Msk + if ((scb_cfsr & SCB_CFSR_MLSPERR_Msk) != 0U) { + printf("Floating-point lazy stacking failure due to MPU access violation"); + } +#endif + if ((scb_cfsr & SCB_CFSR_MMARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_mmfar); + } + printf("\n"); + } + } + + /* Output: Decoded BusFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_bfar = ARM_FaultInfo.FaultRegisters.BFAR; + + if ((scb_cfsr & (SCB_CFSR_IBUSERR_Msk | + SCB_CFSR_PRECISERR_Msk | + SCB_CFSR_IMPRECISERR_Msk | + SCB_CFSR_UNSTKERR_Msk | +#ifdef SCB_CFSR_LSPERR_Msk + SCB_CFSR_LSPERR_Msk | +#endif + SCB_CFSR_STKERR_Msk )) != 0U) { + + printf(" Fault: BusFault - "); + + if ((scb_cfsr & SCB_CFSR_IBUSERR_Msk) != 0U) { + printf("Instruction prefetch failure due to bus fault"); + } + if ((scb_cfsr & SCB_CFSR_PRECISERR_Msk) != 0U) { + printf("Data access failure due to bus fault (precise)"); + } + if ((scb_cfsr & SCB_CFSR_IMPRECISERR_Msk) != 0U) { + printf("Data access failure due to bus fault (imprecise)"); + } + if ((scb_cfsr & SCB_CFSR_UNSTKERR_Msk) != 0U) { + printf("Exception exit unstacking failure due to bus fault"); + } + if ((scb_cfsr & SCB_CFSR_STKERR_Msk) != 0U) { + printf("Exception entry stacking failure due to bus fault"); + } +#ifdef SCB_CFSR_LSPERR_Msk + if ((scb_cfsr & SCB_CFSR_LSPERR_Msk) != 0U) { + printf("Floating-point lazy stacking failure due to bus fault"); + } +#endif + if ((scb_cfsr & SCB_CFSR_BFARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_bfar); + } + printf("\n"); + } + } + + /* Output Decoded UsageFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + + if ((scb_cfsr & (SCB_CFSR_UNDEFINSTR_Msk | + SCB_CFSR_INVSTATE_Msk | + SCB_CFSR_INVPC_Msk | + SCB_CFSR_NOCP_Msk | +#ifdef SCB_CFSR_STKOF_Msk + SCB_CFSR_STKOF_Msk | +#endif + SCB_CFSR_UNALIGNED_Msk | + SCB_CFSR_DIVBYZERO_Msk )) != 0U) { + + printf(" Fault: UsageFault - "); + + if ((scb_cfsr & SCB_CFSR_UNDEFINSTR_Msk) != 0U) { + printf("Execution of undefined instruction"); + } + if ((scb_cfsr & SCB_CFSR_INVSTATE_Msk) != 0U) { + printf("Execution of Thumb instruction with Thumb mode turned off"); + } + if ((scb_cfsr & SCB_CFSR_INVPC_Msk) != 0U) { + printf("Invalid exception return value"); + } + if ((scb_cfsr & SCB_CFSR_NOCP_Msk) != 0U) { + printf("Coprocessor instruction with coprocessor disabled or non-existent"); + } +#ifdef SCB_CFSR_STKOF_Msk + if ((scb_cfsr & SCB_CFSR_STKOF_Msk) != 0U) { + printf("Stack overflow"); + } +#endif + if ((scb_cfsr & SCB_CFSR_UNALIGNED_Msk) != 0U) { + printf("Unaligned load/store"); + } + if ((scb_cfsr & SCB_CFSR_DIVBYZERO_Msk) != 0U) { + printf("Divide by 0"); + } + printf("\n"); + } + } + +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) + /* Output: Decoded SecureFault information */ + if (ARM_FaultInfo.Content.SecureFaultRegs != 0U) { + uint32_t scb_sfsr = ARM_FaultInfo.FaultRegisters.SFSR; + uint32_t scb_sfar = ARM_FaultInfo.FaultRegisters.SFAR; + + if ((scb_sfsr & (SAU_SFSR_INVEP_Msk | + SAU_SFSR_INVIS_Msk | + SAU_SFSR_INVER_Msk | + SAU_SFSR_AUVIOL_Msk | + SAU_SFSR_INVTRAN_Msk | + SAU_SFSR_LSPERR_Msk | + SAU_SFSR_LSERR_Msk )) != 0U) { + + printf(" Fault: SecureFault - "); + + if ((scb_sfsr & SAU_SFSR_INVEP_Msk) != 0U) { + printf("Invalid entry point due to invalid attempt to enter Secure state"); + } + if ((scb_sfsr & SAU_SFSR_INVIS_Msk) != 0U) { + printf("Invalid integrity signature in exception stack frame found on unstacking"); + } + if ((scb_sfsr & SAU_SFSR_INVER_Msk) != 0U) { + printf("Invalid exception return due to mismatch on EXC_RETURN.DCRS or EXC_RETURN.ES"); + } + if ((scb_sfsr & SAU_SFSR_AUVIOL_Msk) != 0U) { + printf("Attribution unit violation due to Non-secure access to Secure address space"); + } + if ((scb_sfsr & SAU_SFSR_INVTRAN_Msk) != 0U) { + printf("Invalid transaction caused by domain crossing branch not flagged as such"); + } + if ((scb_sfsr & SAU_SFSR_LSPERR_Msk) != 0U) { + printf("Lazy stacking preservation failure due to SAU or IDAU violation"); + } + if ((scb_sfsr & SAU_SFSR_LSERR_Msk) != 0U) { + printf("Lazy stacking activation or deactivation failure"); + } + if ((scb_sfsr & SAU_SFSR_SFARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_sfar); + } + printf("\n"); + } + } +#endif +#endif + + /* Output: Program Counter */ + /* Output here is named PC (Program Counter) since in most situations stacked Return Address will be + the address of the instruction which caused the fault, there are some exceptions (asynchronous faults) + but these are for the sake of simplicity not taken into account here */ + printf(" Program Counter: "); + + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf("0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.ReturnAddress); + } else { + printf("unknown (was not stacked)\n"); + } + + /* Output: Registers */ + /* Registers R4 .. R11 values might be either: stacked (if additional state context (TrustZone only) + was stacked) or values as they were when fault handler started execution */ + printf("\n Registers:\n"); + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf(" - R0: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R0); + printf(" - R1: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R1); + printf(" - R2: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R2); + printf(" - R3: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R3); + } else { + printf(" - R0 .. R3: unknown (were not stacked)\n"); + } + + /* Output: R4 .. R11 */ + printf(" - R4: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R4); + printf(" - R5: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R5); + printf(" - R6: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R6); + printf(" - R7: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R7); + printf(" - R8: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R8); + printf(" - R9: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R9); + printf(" - R10: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R10); + printf(" - R11: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R11); + + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf(" - R12: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R12); + printf(" - LR: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.LR); + printf(" - Return Address: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.ReturnAddress); + printf(" - xPSR: 0x%08X\n\n", (unsigned int)ARM_FaultInfo.Registers.xPSR); + } else { + printf(" - R12: unknown (was not stacked)\n"); + printf(" - LR: unknown (was not stacked)\n"); + printf(" - Return Address: unknown (was not stacked)\n"); + printf(" - xPSR: unknown (was not stacked)\n"); + } + + printf(" - MSP: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.MSP); + if (ARM_FaultInfo.Content.LimitRegs != 0U) { + printf(" - MSPLIM: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.MSPLIM); + } + printf(" - PSP: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.PSP); + if (ARM_FaultInfo.Content.LimitRegs != 0U) { + printf(" - PSPLIM: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.PSPLIM); + } + + /* Output: Exception State */ + printf("\n Exception State:\n"); + printf(" - xPSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.ExceptionState.xPSR); + printf(" - Exception Return: 0x%08X\n", (unsigned int)ARM_FaultInfo.ExceptionState.EXC_RETURN); + printf("\n"); + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + /* Output: Fault Registers (if they exist) */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + printf(" Fault Registers:\n"); + + printf(" - CFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.CFSR); + printf(" - HFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.HFSR); + printf(" - DFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.DFSR); + printf(" - MMFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.MMFAR); + printf(" - BFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.BFAR); + printf(" - AFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.AFSR); + + if (ARM_FaultInfo.Content.SecureFaultRegs != 0U) { + printf(" - SFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.SFSR); + printf(" - SFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.SFAR); + } + +#if (ARM_FAULT_ARCH_ARMV8_1M_MAIN != 0) + if (ARM_FaultInfo.Content.RAS_FaultReg != 0U) { + printf(" - RFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.RFSR); + } +#endif + + printf("\n"); + } +#else + /* Output: Message if fault registers do not exist */ + printf(" Fault Registers do not exist!\n\n"); +#endif +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.c new file mode 100644 index 0000000..5655800 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARM_FaultTrigger.h" + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "../Secure/interface.h" // Secure functions interface header + +// ARM_FaultTrigger function --------------------------------------------------- + +/** + Trigger a fault. + \param[in] fault_id Fault ID of the fault to be triggered +*/ +void ARM_FaultTrigger (uint32_t fault_id) { + volatile uint32_t val; + void (*ptr_func) (void); + + switch (fault_id) { + case ARM_FAULT_ID_MEM_DATA: // Trigger Non-Secure MemManage fault - data access + val = *((uint32_t *)0x20040000); // Read from address not allowed by the MPU (non-privileged access not allowed) + break; + + case ARM_FAULT_ID_BUS_DATA: // Trigger Non-Secure BusFault - data access + val = *((uint32_t *)0x200C0000); // Read from invalid RAM address + break; + + case ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION: // Trigger Non-Secure UsageFault - undefined instruction + __ASM volatile ( + ".syntax unified\n" + ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 + ); + break; + + case ARM_FAULT_ID_USG_DIV_0: // Trigger Non-Secure UsageFault - divide by 0 + val = 0U; + val = 123/val; + break; + + case ARM_FAULT_ID_SEC_DATA: // Trigger Secure BusFault - data access + val = *((uint32_t *)0x30000000); // Read from Secure RAM address + break; + + case ARM_FAULT_ID_SEC_INSTRUCTION: // Trigger Secure BusFault - instruction execution + ptr_func = (void (*) (void))(0xC000000); + ptr_func(); // Call function from Secure Flash address + break; + + case ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION: // Trigger Secure - UsageFault - undefined instruction + Secure_TriggerFault(fault_id); // Call Secure function that will trigger a fault + break; + + default: + break; + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.h b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.h new file mode 100644 index 0000000..eb87301 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +// Fault IDs for fault triggering +#define ARM_FAULT_ID_MEM_DATA (1U) +#define ARM_FAULT_ID_BUS_DATA (2U) +#define ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION (3U) +#define ARM_FAULT_ID_USG_DIV_0 (4U) +#define ARM_FAULT_ID_SEC_DATA (5U) +#define ARM_FAULT_ID_SEC_INSTRUCTION (6U) +#define ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION (7U) + +// ARM_FaultTrigger function --------------------------------------------------- + +/// Trigger a fault. +/// \param[in] fault_id Fault Id of the fault to be triggered +extern void ARM_FaultTrigger (uint32_t fault_id); diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault.c new file mode 100644 index 0000000..683a74a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault.c @@ -0,0 +1,75 @@ +/*---------------------------------------------------------------------------- + * Name: Fault.c + * Purpose: Fault example program + *----------------------------------------------------------------------------*/ + +#include + +#include "main.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "cmsis_os2.h" +#include "../Secure/interface.h" // Secure functions interface header + +#include "ARM_Fault.h" +#include "ARM_FaultTrigger.h" + +#include "EventRecorder.h" + +extern osThreadId_t tid_AppThread; +extern osThreadId_t tid_FaultTriggerThread; + +/* Global Thread IDs (for debug) */ +osThreadId_t tid_AppThread; +osThreadId_t tid_FaultTriggerThread; + +/*--------------------------------------------------------------------------- + * Application thread + *---------------------------------------------------------------------------*/ +static __NO_RETURN void AppThread (void *argument) { + + (void)argument; + + for (;;) { + osDelay(500U); + HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_RESET); + osDelay(500U); + HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_SET); + } +} + +/*--------------------------------------------------------------------------- + * Fault trigger thread + *---------------------------------------------------------------------------*/ +static __NO_RETURN void FaultTriggerThread (void *argument) { + char ch; + + (void)argument; + + // Display user interface message + printf("\r\n--- Fault example ---\r\n\r\n"); + printf("To trigger a fault please input a corresponding number:\r\n"); + printf(" - 1: Non-Secure fault, Non-Secure data access Memory Management fault\r\n"); + printf(" - 2: Non-Secure fault, Non-Secure data access Bus fault\r\n"); + printf(" - 3: Non-Secure fault, Non-Secure undefined instruction Usage fault\r\n"); + printf(" - 4: Non-Secure fault, Non-Secure divide by 0 Usage fault\r\n"); + printf(" - 5: Secure fault, Non-Secure data access from Secure RAM memory\r\n"); + printf(" - 6: Secure fault, Non-Secure instruction execution from Secure Flash memory\r\n"); + printf(" - 7: Secure fault, Secure undefined instruction Usage fault\r\n"); + printf("Input>"); + + for (;;) { + ch = (char)getchar(); // Read character from console (blocking) + ARM_FaultTrigger((uint32_t)(ch - '0')); // Trigger a fault + } +} + +/*--------------------------------------------------------------------------- + * Application initialization + *---------------------------------------------------------------------------*/ +void AppInitialize (void) { + tid_AppThread = osThreadNew(AppThread, NULL, NULL); + tid_FaultTriggerThread = osThreadNew(FaultTriggerThread, NULL, NULL); +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.cproject.yml b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.cproject.yml new file mode 100644 index 0000000..c26a171 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.cproject.yml @@ -0,0 +1,51 @@ +project: + + processor: + trustzone: non-secure + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler + - pack: ARM::CMSIS-View + + groups: + - group: Documentation + files: + - file: ../README.md + + - group: Source Files + files: + - file: Fault.c + - file: ARM_FaultTrigger.c + - file: ARM_FaultPrint.c + - file: retarget_stdio.c + + - group: CMSE_Library + files: + - file: $cmse-lib(Fault_S)$ + + components: + - component: CMSIS:CORE + - component: CMSIS:RTOS2:Keil RTX5&Source_NS + + - component: CMSIS-Compiler:I/O:STDERR&User + - component: CMSIS-Compiler:I/O:STDOUT&User + - component: CMSIS-Compiler:I/O:STDIN&User + + - component: CMSIS-View:Event Recorder&DAP + - component: CMSIS-View:Fault:Record + - component: CMSIS-View:Fault:Storage + + - component: Device:STM32Cube Framework:STM32CubeMX + + - component: Device:STM32Cube HAL:Common + - component: Device:STM32Cube HAL:Cortex + - component: Device:STM32Cube HAL:DMA + - component: Device:STM32Cube HAL:Flash + - component: Device:STM32Cube HAL:GPIO + - component: Device:STM32Cube HAL:GTZC + - component: Device:STM32Cube HAL:PWR + - component: Device:STM32Cube HAL:RCC + - component: Device:STM32Cube HAL:UART + + - component: Device:Startup&Source C diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvguix b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvguix new file mode 100644 index 0000000..2f143ed --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvguix @@ -0,0 +1,3614 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1200 + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvoptx b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvoptx new file mode 100644 index 0000000..bfc7c40 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvoptx @@ -0,0 +1,437 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + B-U585I-IOT02A + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + ..\Debug.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + EVENTREC_CNF + -l0 -a1 -s0 -fFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF007800000000FFFF000000000000000000000000000000000000000000000080044000000000FFFF0000000000000000000000000000000000000000000000800000 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (6010=1753,178,2230,774,0)(6018=-1,-1,-1,-1,0)(6019=1756,188,1945,524,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=2346,23,2604,754,0)(6015=2591,23,2849,645,0)(6003=2840,24,3422,560,0)(6000=2599,83,3052,415,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U002000123156501320323443 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BE12477) -L00(0) -TO131090 -TC160000000 -TT10000000 -TP21 -TDS800D -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FF1STM32U5xx_2M_0C00.FLM -FS1C000000 -FL1200000 -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800 -FS08000000 -FL0200000 -FF1STM32U5xx_2M_0C00 -FS1C000000 -FL1200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM)) + + + + + ..\..\..\FaultRecorder\FaultRecorder.scvd + + 1 + + + C:\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.9.0 + 1 + + + C:\ARM\PACK\ARM\CMSIS-View\1.0.1\EventRecorder\EventRecorder.scvd + ARM.CMSIS-View.1.0.1 + 1 + + + C:\ARM\PACK\ARM\CMSIS-View\1.0.1\Fault\ARM_Fault.scvd + ARM.CMSIS-View.1.0.1 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + C:\Lint\lint-nt.exe + + 0 + 0 + 59 + .\Lint\MISRA_C_2012_Config.lnt + MISRA_C_2012_Config + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Documentation + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\README.md + README.md + 0 + 0 + + + + + Source Files + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + .\Fault.c + Fault.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\ARM_FaultTrigger.c + ARM_FaultTrigger.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\ARM_FaultPrint.c + ARM_FaultPrint.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + .\retarget_stdio.c + retarget_stdio.c + 0 + 0 + + + + + :STM32CubeMX_NS:Common Sources + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Src\main.c + main.c + 0 + 0 + + + 3 + 7 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Inc\stm32u5xx_it.h + stm32u5xx_it.h + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Src\stm32u5xx_it.c + stm32u5xx_it.c + 0 + 0 + + + 3 + 9 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure_nsclib\secure_nsc.h + secure_nsc.h + 0 + 0 + + + 3 + 10 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\STM32CubeMX.ioc + STM32CubeMX.ioc + 0 + 0 + + + + + CMSE Library + 0 + 0 + 0 + 0 + + 4 + 11 + 5 + 0 + 0 + 0 + ..\Secure\interface.h + interface.h + 0 + 0 + + + 4 + 12 + 3 + 0 + 0 + 0 + ..\Secure\Objects\Fault_S_CMSE_Lib.o + Fault_S_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS-Compiler + 0 + 0 + 0 + 1 + + + + ::CMSIS-View + 1 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvprojx b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvprojx new file mode 100644 index 0000000..2981a30 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.uvprojx @@ -0,0 +1,956 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + B-U585I-IOT02A + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 6190000::V6.19::ARMCLANG + 1 + + + STM32U585AIIx + STMicroelectronics + Keil.STM32U5xx_DFP.2.1.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00040000) IRAM2(0x20040000,0x00080000) IROM(0x08000000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800 -FS08000000 -FL0200000 -FF1STM32U5xx_2M_0C00 -FS1C000000 -FL1200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM)) + 0 + $$Device:STM32U585AIIx$Drivers\CMSIS\Device\ST\STM32U5xx\Include\stm32u5xx.h + + + + + + + + + + $$Device:STM32U585AIIx$CMSIS\SVD\STM32U5xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Fault_NS + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + ..\Flash.ini + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8100000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20040000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + RTE_Compiler_EventRecorder, RTE_Compiler_EventRecorder_DAP + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + .\RTE\Device\STM32U585AIIx\stm32u585xx_flash_ns.sct + + + + + + + + + + + Documentation + + + README.md + 5 + ..\README.md + + + + + Source Files + + + Fault.c + 1 + .\Fault.c + + + ARM_FaultTrigger.c + 1 + .\ARM_FaultTrigger.c + + + ARM_FaultPrint.c + 1 + .\ARM_FaultPrint.c + + + retarget_stdio.c + 1 + .\retarget_stdio.c + + + + + :STM32CubeMX_NS:Common Sources + + + main.c + 1 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Src\main.c + + + stm32u5xx_it.h + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Inc\stm32u5xx_it.h + + + stm32u5xx_it.c + 1 + ..\Board\B-U585I-IOT02A\STM32CubeMX\NonSecure\Src\stm32u5xx_it.c + + + secure_nsc.h + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure_nsclib\secure_nsc.h + + + STM32CubeMX.ioc + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\STM32CubeMX.ioc + + + + + CMSE Library + + + interface.h + 5 + ..\Secure\interface.h + + + Fault_S_CMSE_Lib.o + 3 + ..\Secure\Objects\Fault_S_CMSE_Lib.o + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS-Compiler + + + ::CMSIS-View + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -Weverything + + + + + + + + + + -Weverything + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 + + + + + + + + RTE\CMSIS-View\EventRecorderConf.h + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\STM32U585AIIx\startup_stm32u585xx.c + + + + + + + + RTE\Device\STM32U585AIIx\startup_stm32u585xx.s + + + + + + RTE\Device\STM32U585AIIx\stm32u585xx_flash_ns.sct + + + + + + + + RTE\Device\STM32U585AIIx\system_stm32u5xx_ns.c + + + + + + + + + + + + + Fault_NS + 1 + Fault_NS + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h new file mode 100644 index 0000000..f4709e0 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 2 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 new file mode 100644 index 0000000..9802f2a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..737078a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c.base@5.1.1 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c.base@5.1.1 new file mode 100644 index 0000000..737078a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c.base@5.1.1 @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..0f904a2 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 0 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 0 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 0 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 0 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 0 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 0 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 0 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 0 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 0 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 0 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 0 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h.base@5.5.2 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h.base@5.5.2 new file mode 100644 index 0000000..4d2f501 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.h.base@5.5.2 @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c new file mode 100644 index 0000000..8ad665a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c @@ -0,0 +1,394 @@ +/****************************************************************************** + * @file startup_stm32u585xx.c + * @brief CMSIS-Core Device Startup File for STM32U585xx Device + * @version V1.0.0 + * @date 23. February 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32u5xx.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void WWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PVD_PVM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TAMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RAMCFG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GTZC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPUART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM16_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM17_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTG_FS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CRS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWR_S3WU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PKA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UCPD1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCACHE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADF1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2D_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCMI_PSSI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CORDIC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMAC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + WWDG_IRQHandler, /* Window WatchDog */ + PVD_PVM_IRQHandler, /* PVD/PVM through EXTI Line detection interrupt */ + RTC_IRQHandler, /* RTC non-secure interrupt */ + RTC_S_IRQHandler, /* RTC secure interrupt */ + TAMP_IRQHandler, /* Tamper non-secure interrupt */ + RAMCFG_IRQHandler, /* RAMCFG global interrupt */ + FLASH_IRQHandler, /* FLASH non-secure global interrupt */ + FLASH_S_IRQHandler, /* FLASH secure global interrupt */ + GTZC_IRQHandler, /* Global TrustZone Controller interrupt */ + RCC_IRQHandler, /* RCC non-secure global interrupt */ + RCC_S_IRQHandler, /* RCC secure global interrupt */ + EXTI0_IRQHandler, /* EXTI Line0 interrupt */ + EXTI1_IRQHandler, /* EXTI Line1 interrupt */ + EXTI2_IRQHandler, /* EXTI Line2 interrupt */ + EXTI3_IRQHandler, /* EXTI Line3 interrupt */ + EXTI4_IRQHandler, /* EXTI Line4 interrupt */ + EXTI5_IRQHandler, /* EXTI Line5 interrupt */ + EXTI6_IRQHandler, /* EXTI Line6 interrupt */ + EXTI7_IRQHandler, /* EXTI Line7 interrupt */ + EXTI8_IRQHandler, /* EXTI Line8 interrupt */ + EXTI9_IRQHandler, /* EXTI Line9 interrupt */ + EXTI10_IRQHandler, /* EXTI Line10 interrupt */ + EXTI11_IRQHandler, /* EXTI Line11 interrupt */ + EXTI12_IRQHandler, /* EXTI Line12 interrupt */ + EXTI13_IRQHandler, /* EXTI Line13 interrupt */ + EXTI14_IRQHandler, /* EXTI Line14 interrupt */ + EXTI15_IRQHandler, /* EXTI Line15 interrupt */ + IWDG_IRQHandler, /* IWDG global interrupt */ + SAES_IRQHandler, /* Secure AES global interrupt */ + GPDMA1_Channel0_IRQHandler, /* GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQHandler, /* GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQHandler, /* GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQHandler, /* GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQHandler, /* GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQHandler, /* GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQHandler, /* GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQHandler, /* GPDMA1 Channel 7 global interrupt */ + ADC1_IRQHandler, /* ADC1 global interrupt */ + DAC1_IRQHandler, /* DAC1 global interrupt */ + FDCAN1_IT0_IRQHandler, /* FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQHandler, /* FDCAN1 interrupt 1 */ + TIM1_BRK_IRQHandler, /* TIM1 Break interrupt */ + TIM1_UP_IRQHandler, /* TIM1 Update interrupt */ + TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQHandler, /* TIM1 Capture Compare interrupt */ + TIM2_IRQHandler, /* TIM2 global interrupt */ + TIM3_IRQHandler, /* TIM3 global interrupt */ + TIM4_IRQHandler, /* TIM4 global interrupt */ + TIM5_IRQHandler, /* TIM5 global interrupt */ + TIM6_IRQHandler, /* TIM6 global interrupt */ + TIM7_IRQHandler, /* TIM7 global interrupt */ + TIM8_BRK_IRQHandler, /* TIM8 Break interrupt */ + TIM8_UP_IRQHandler, /* TIM8 Update interrupt */ + TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQHandler, /* TIM8 Capture Compare interrupt */ + I2C1_EV_IRQHandler, /* I2C1 Event interrupt */ + I2C1_ER_IRQHandler, /* I2C1 Error interrupt */ + I2C2_EV_IRQHandler, /* I2C2 Event interrupt */ + I2C2_ER_IRQHandler, /* I2C2 Error interrupt */ + SPI1_IRQHandler, /* SPI1 global interrupt */ + SPI2_IRQHandler, /* SPI2 global interrupt */ + USART1_IRQHandler, /* USART1 global interrupt */ + USART2_IRQHandler, /* USART2 global interrupt */ + USART3_IRQHandler, /* USART3 global interrupt */ + UART4_IRQHandler, /* UART4 global interrupt */ + UART5_IRQHandler, /* UART5 global interrupt */ + LPUART1_IRQHandler, /* LPUART1 global interrupt */ + LPTIM1_IRQHandler, /* LPTIM1 global interrupt */ + LPTIM2_IRQHandler, /* LPTIM2 global interrupt */ + TIM15_IRQHandler, /* TIM15 global interrupt */ + TIM16_IRQHandler, /* TIM16 global interrupt */ + TIM17_IRQHandler, /* TIM17 global interrupt */ + COMP_IRQHandler, /* COMP1 and COMP2 through EXTI Lines interrupt */ + OTG_FS_IRQHandler, /* USB OTG FS global interrupt */ + CRS_IRQHandler, /* CRS global interrupt */ + FMC_IRQHandler, /* FMC global interrupt */ + OCTOSPI1_IRQHandler, /* OctoSPI1 global interrupt */ + PWR_S3WU_IRQHandler, /* PWR wake up from Stop3 interrupt */ + SDMMC1_IRQHandler, /* SDMMC1 global interrupt */ + SDMMC2_IRQHandler, /* SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQHandler, /* GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQHandler, /* GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQHandler, /* GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQHandler, /* GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQHandler, /* GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQHandler, /* GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQHandler, /* GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQHandler, /* GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQHandler, /* I2C3 event interrupt */ + I2C3_ER_IRQHandler, /* I2C3 error interrupt */ + SAI1_IRQHandler, /* Serial Audio Interface 1 global interrupt */ + SAI2_IRQHandler, /* Serial Audio Interface 2 global interrupt */ + TSC_IRQHandler, /* Touch Sense Controller global interrupt */ + AES_IRQHandler, /* AES global interrupt */ + RNG_IRQHandler, /* RNG global interrupt */ + FPU_IRQHandler, /* FPU global interrupt */ + HASH_IRQHandler, /* HASH global interrupt */ + PKA_IRQHandler, /* PKA global interrupt */ + LPTIM3_IRQHandler, /* LPTIM3 global interrupt */ + SPI3_IRQHandler, /* SPI3 global interrupt */ + I2C4_ER_IRQHandler, /* I2C4 Error interrupt */ + I2C4_EV_IRQHandler, /* I2C4 Event interrupt */ + MDF1_FLT0_IRQHandler, /* MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQHandler, /* MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQHandler, /* MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQHandler, /* MDF1 Filter 3 global interrupt */ + UCPD1_IRQHandler, /* UCPD1 global interrupt */ + ICACHE_IRQHandler, /* Instruction cache global interrupt */ + OTFDEC1_IRQHandler, /* OTFDEC1 global interrupt */ + OTFDEC2_IRQHandler, /* OTFDEC2 global interrupt */ + LPTIM4_IRQHandler, /* LPTIM4 global interrupt */ + DCACHE1_IRQHandler, /* Data cache global interrupt */ + ADF1_IRQHandler, /* ADF interrupt */ + ADC4_IRQHandler, /* ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQHandler, /* LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQHandler, /* LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQHandler, /* LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQHandler, /* LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQHandler, /* DMA2D global interrupt */ + DCMI_PSSI_IRQHandler, /* DCMI/PSSI global interrupt */ + OCTOSPI2_IRQHandler, /* OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQHandler, /* MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQHandler, /* MDF1 Filter 5 global interrupt */ + CORDIC_IRQHandler, /* CORDIC global interrupt */ + FMAC_IRQHandler /* FMAC global interrupt */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 new file mode 100644 index 0000000..8ad665a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 @@ -0,0 +1,394 @@ +/****************************************************************************** + * @file startup_stm32u585xx.c + * @brief CMSIS-Core Device Startup File for STM32U585xx Device + * @version V1.0.0 + * @date 23. February 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32u5xx.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void WWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PVD_PVM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TAMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RAMCFG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GTZC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPUART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM16_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM17_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTG_FS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CRS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWR_S3WU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PKA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UCPD1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCACHE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADF1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2D_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCMI_PSSI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CORDIC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMAC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + WWDG_IRQHandler, /* Window WatchDog */ + PVD_PVM_IRQHandler, /* PVD/PVM through EXTI Line detection interrupt */ + RTC_IRQHandler, /* RTC non-secure interrupt */ + RTC_S_IRQHandler, /* RTC secure interrupt */ + TAMP_IRQHandler, /* Tamper non-secure interrupt */ + RAMCFG_IRQHandler, /* RAMCFG global interrupt */ + FLASH_IRQHandler, /* FLASH non-secure global interrupt */ + FLASH_S_IRQHandler, /* FLASH secure global interrupt */ + GTZC_IRQHandler, /* Global TrustZone Controller interrupt */ + RCC_IRQHandler, /* RCC non-secure global interrupt */ + RCC_S_IRQHandler, /* RCC secure global interrupt */ + EXTI0_IRQHandler, /* EXTI Line0 interrupt */ + EXTI1_IRQHandler, /* EXTI Line1 interrupt */ + EXTI2_IRQHandler, /* EXTI Line2 interrupt */ + EXTI3_IRQHandler, /* EXTI Line3 interrupt */ + EXTI4_IRQHandler, /* EXTI Line4 interrupt */ + EXTI5_IRQHandler, /* EXTI Line5 interrupt */ + EXTI6_IRQHandler, /* EXTI Line6 interrupt */ + EXTI7_IRQHandler, /* EXTI Line7 interrupt */ + EXTI8_IRQHandler, /* EXTI Line8 interrupt */ + EXTI9_IRQHandler, /* EXTI Line9 interrupt */ + EXTI10_IRQHandler, /* EXTI Line10 interrupt */ + EXTI11_IRQHandler, /* EXTI Line11 interrupt */ + EXTI12_IRQHandler, /* EXTI Line12 interrupt */ + EXTI13_IRQHandler, /* EXTI Line13 interrupt */ + EXTI14_IRQHandler, /* EXTI Line14 interrupt */ + EXTI15_IRQHandler, /* EXTI Line15 interrupt */ + IWDG_IRQHandler, /* IWDG global interrupt */ + SAES_IRQHandler, /* Secure AES global interrupt */ + GPDMA1_Channel0_IRQHandler, /* GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQHandler, /* GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQHandler, /* GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQHandler, /* GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQHandler, /* GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQHandler, /* GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQHandler, /* GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQHandler, /* GPDMA1 Channel 7 global interrupt */ + ADC1_IRQHandler, /* ADC1 global interrupt */ + DAC1_IRQHandler, /* DAC1 global interrupt */ + FDCAN1_IT0_IRQHandler, /* FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQHandler, /* FDCAN1 interrupt 1 */ + TIM1_BRK_IRQHandler, /* TIM1 Break interrupt */ + TIM1_UP_IRQHandler, /* TIM1 Update interrupt */ + TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQHandler, /* TIM1 Capture Compare interrupt */ + TIM2_IRQHandler, /* TIM2 global interrupt */ + TIM3_IRQHandler, /* TIM3 global interrupt */ + TIM4_IRQHandler, /* TIM4 global interrupt */ + TIM5_IRQHandler, /* TIM5 global interrupt */ + TIM6_IRQHandler, /* TIM6 global interrupt */ + TIM7_IRQHandler, /* TIM7 global interrupt */ + TIM8_BRK_IRQHandler, /* TIM8 Break interrupt */ + TIM8_UP_IRQHandler, /* TIM8 Update interrupt */ + TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQHandler, /* TIM8 Capture Compare interrupt */ + I2C1_EV_IRQHandler, /* I2C1 Event interrupt */ + I2C1_ER_IRQHandler, /* I2C1 Error interrupt */ + I2C2_EV_IRQHandler, /* I2C2 Event interrupt */ + I2C2_ER_IRQHandler, /* I2C2 Error interrupt */ + SPI1_IRQHandler, /* SPI1 global interrupt */ + SPI2_IRQHandler, /* SPI2 global interrupt */ + USART1_IRQHandler, /* USART1 global interrupt */ + USART2_IRQHandler, /* USART2 global interrupt */ + USART3_IRQHandler, /* USART3 global interrupt */ + UART4_IRQHandler, /* UART4 global interrupt */ + UART5_IRQHandler, /* UART5 global interrupt */ + LPUART1_IRQHandler, /* LPUART1 global interrupt */ + LPTIM1_IRQHandler, /* LPTIM1 global interrupt */ + LPTIM2_IRQHandler, /* LPTIM2 global interrupt */ + TIM15_IRQHandler, /* TIM15 global interrupt */ + TIM16_IRQHandler, /* TIM16 global interrupt */ + TIM17_IRQHandler, /* TIM17 global interrupt */ + COMP_IRQHandler, /* COMP1 and COMP2 through EXTI Lines interrupt */ + OTG_FS_IRQHandler, /* USB OTG FS global interrupt */ + CRS_IRQHandler, /* CRS global interrupt */ + FMC_IRQHandler, /* FMC global interrupt */ + OCTOSPI1_IRQHandler, /* OctoSPI1 global interrupt */ + PWR_S3WU_IRQHandler, /* PWR wake up from Stop3 interrupt */ + SDMMC1_IRQHandler, /* SDMMC1 global interrupt */ + SDMMC2_IRQHandler, /* SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQHandler, /* GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQHandler, /* GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQHandler, /* GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQHandler, /* GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQHandler, /* GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQHandler, /* GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQHandler, /* GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQHandler, /* GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQHandler, /* I2C3 event interrupt */ + I2C3_ER_IRQHandler, /* I2C3 error interrupt */ + SAI1_IRQHandler, /* Serial Audio Interface 1 global interrupt */ + SAI2_IRQHandler, /* Serial Audio Interface 2 global interrupt */ + TSC_IRQHandler, /* Touch Sense Controller global interrupt */ + AES_IRQHandler, /* AES global interrupt */ + RNG_IRQHandler, /* RNG global interrupt */ + FPU_IRQHandler, /* FPU global interrupt */ + HASH_IRQHandler, /* HASH global interrupt */ + PKA_IRQHandler, /* PKA global interrupt */ + LPTIM3_IRQHandler, /* LPTIM3 global interrupt */ + SPI3_IRQHandler, /* SPI3 global interrupt */ + I2C4_ER_IRQHandler, /* I2C4 Error interrupt */ + I2C4_EV_IRQHandler, /* I2C4 Event interrupt */ + MDF1_FLT0_IRQHandler, /* MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQHandler, /* MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQHandler, /* MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQHandler, /* MDF1 Filter 3 global interrupt */ + UCPD1_IRQHandler, /* UCPD1 global interrupt */ + ICACHE_IRQHandler, /* Instruction cache global interrupt */ + OTFDEC1_IRQHandler, /* OTFDEC1 global interrupt */ + OTFDEC2_IRQHandler, /* OTFDEC2 global interrupt */ + LPTIM4_IRQHandler, /* LPTIM4 global interrupt */ + DCACHE1_IRQHandler, /* Data cache global interrupt */ + ADF1_IRQHandler, /* ADF interrupt */ + ADC4_IRQHandler, /* ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQHandler, /* LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQHandler, /* LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQHandler, /* LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQHandler, /* LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQHandler, /* DMA2D global interrupt */ + DCMI_PSSI_IRQHandler, /* DCMI/PSSI global interrupt */ + OCTOSPI2_IRQHandler, /* OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQHandler, /* MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQHandler, /* MDF1 Filter 5 global interrupt */ + CORDIC_IRQHandler, /* CORDIC global interrupt */ + FMAC_IRQHandler /* FMAC global interrupt */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld new file mode 100644 index 0000000..dbe3b05 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld @@ -0,0 +1,317 @@ +/****************************************************************************** + * @file stm32u585xx_flash_ns.ld + * @brief GNU Linker Script for STM32U585xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__ROM_BASE = 0x08100000; +__ROM_SIZE = 0x00100000; + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__RAM_BASE = 0x20040000; +__RAM_SIZE = 0x00080000; + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__NOINIT_SIZE = 0x00000500; + +/* +// <<< end of configuration section >>> + */ + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - 0x200 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + . = . + 0x100; /* RAM allowing privileged access only (for showing MemManage fault) */ + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* Uninitialized memory for Fault information (ARM_FaultInfo) */ + .noinit.fault 0x200B0000 (NOLOAD) : + { + *(.noinit.fault) + } > RAM + + /* This section contains data that is not initialised + * during load *or* application reset. + */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld.base@2.2.0 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld.base@2.2.0 new file mode 100644 index 0000000..02b8d5d --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.ld.base@2.2.0 @@ -0,0 +1,310 @@ +/****************************************************************************** + * @file stm32u585xx_flash_ns.ld + * @brief GNU Linker Script for STM32U585xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__ROM_BASE = 0x08100000; +__ROM_SIZE = 0x00100000; + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__RAM_BASE = 0x20040000; +__RAM_SIZE = 0x00080000; + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__NOINIT_SIZE = 0x00000800; + +/* +// <<< end of configuration section >>> + */ + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* This section contains data that is not initialised + * during load *or* application reset. + */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct new file mode 100644 index 0000000..036802a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct @@ -0,0 +1,118 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +/* command above MUST be in first line (no comment above!) */ + +/****************************************************************************** + * @file stm32u585xx_flash_ns.sct + * @brief GNU Linker Script for STM32U575xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __ROM_BASE 0x08100000 +#define __ROM_SIZE 0x00100000 + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __RAM_BASE 0x20040000 +#define __RAM_SIZE 0x00080000 + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000500 + +/* +// <<< end of configuration section >>> + */ + + +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE ) /* starts at end of RAM */ +#define __HEAP_BASE ( AlignExpr(+0, 8) ) /* starts after RW_RAM or RW_NOINIT section, 8 byte aligned */ + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE - 0x200 ) +#define __RW_NOINIT_BASE ( __RAM_BASE + __RW_SIZE ) /* starts after RW_RAM section */ + + +LR_APP __LR_BASE __LR_SIZE { /* load region for application */ + ER_APP __LR_BASE __LR_SIZE { /* execution region for application */ + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM_PRIV __RW_BASE EMPTY 0x100 { /* RAM allowing privileged access only (for showing MemManage fault) */ + } + + RW_RAM (__RW_BASE + 0x100) __RW_SIZE { /* RW, ZI data */ + .ANY (+RW +ZI) + } + + RW_NOINIT_FAULT 0x200B0000 UNINIT 0x100 { /* Uninitialized memory for Fault information (ARM_FaultInfo) */ + *(.bss.noinit.fault) + } + +#if __NOINIT_SIZE > 0 + RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { /* no init data */ + *(.bss.noinit) + } +#endif + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { /* empty region for heap */ + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { /* empty region for stack */ + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct.base@2.0.0 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct.base@2.0.0 new file mode 100644 index 0000000..677b185 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_ns.sct.base@2.0.0 @@ -0,0 +1,111 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +/* command above MUST be in first line (no comment above!) */ + +/****************************************************************************** + * @file stm32u585xx_flash_ns.sct + * @brief GNU Linker Script for STM32U575xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __ROM_BASE 0x08100000 +#define __ROM_SIZE 0x00100000 + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __RAM_BASE 0x20040000 +#define __RAM_SIZE 0x00080000 + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000000 + +/* +// <<< end of configuration section >>> + */ + + +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE ) /* starts at end of RAM */ +#define __HEAP_BASE ( AlignExpr(+0, 8) ) /* starts after RW_RAM or RW_NOINIT section, 8 byte aligned */ + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE ) +#define __RW_NOINIT_BASE ( __RAM_BASE + __RW_SIZE ) /* starts after RW_RAM section */ + + +LR_APP __LR_BASE __LR_SIZE { /* load region for application */ + ER_APP __LR_BASE __LR_SIZE { /* execution region for application */ + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { /* RW, ZI data */ + .ANY (+RW +ZI) + } + +#if __NOINIT_SIZE > 0 + RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { /* no init data */ + *(.bss.noinit) + } +#endif + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { /* empty region for heap */ + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { /* empty region for stack */ + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c new file mode 100644 index 0000000..262de2c --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx_ns.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in non-secure application when the system implements + * the TrustZone-M security. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at non-secure startup before + * branch to non-secure main program. + * This call is made inside the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main secure program. + * Later, when non-secure SystemInit() function is called, in "startup_stm32u5xx.s" + * file, the system clock may have been updated from reset value by the main + * secure program. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "stm32u5xx.h" + + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* Nothing done in non-secure */ + + /* Non-secure main application shall call SystemCoreClockUpdate() to update */ + /* the SystemCoreClock variable to insure non-secure application relies on */ + /* the initial clock reference set by secure application. */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note From the non-secure application, the SystemCoreClock value is + * retrieved from the secure domain via a Non-Secure Callable function + * since the RCC peripheral may be protected with security attributes + * that prevent to compute the SystemCoreClock variable from the RCC + * peripheral registers. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + /* Get the SystemCoreClock value from the secure domain */ + SystemCoreClock = SECURE_SystemCoreClockUpdate(); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c.base@1.2.0 b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c.base@1.2.0 new file mode 100644 index 0000000..262de2c --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/Device/STM32U585AIIx/system_stm32u5xx_ns.c.base@1.2.0 @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx_ns.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in non-secure application when the system implements + * the TrustZone-M security. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at non-secure startup before + * branch to non-secure main program. + * This call is made inside the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main secure program. + * Later, when non-secure SystemInit() function is called, in "startup_stm32u5xx.s" + * file, the system clock may have been updated from reset value by the main + * secure program. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "stm32u5xx.h" + + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* Nothing done in non-secure */ + + /* Non-secure main application shall call SystemCoreClockUpdate() to update */ + /* the SystemCoreClock variable to insure non-secure application relies on */ + /* the initial clock reference set by secure application. */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note From the non-secure application, the SystemCoreClock value is + * retrieved from the secure domain via a Non-Secure Callable function + * since the RCC peripheral may be protected with security attributes + * that prevent to compute the SystemCoreClock variable from the RCC + * peripheral registers. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + /* Get the SystemCoreClock value from the secure domain */ + SystemCoreClock = SECURE_SystemCoreClockUpdate(); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Examples/Fault/B-U585I-IOT02A/NonSecure/retarget_stdio.c b/Examples/Fault/B-U585I-IOT02A/NonSecure/retarget_stdio.c new file mode 100644 index 0000000..ff649bb --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/NonSecure/retarget_stdio.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: retarget_stdio.c + * Purpose: Retarget STDIO to USART1 + * + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#define HUARTx huart1 + +extern UART_HandleTypeDef HUARTx; + +extern int stderr_putchar (int ch); +extern int stdout_putchar (int ch); +extern int stdin_getchar (void); + +/** + Put a character to the stderr + + \param[in] ch Character to output + \return The character written, or -1 on error. +*/ +int stderr_putchar (int ch) { + + if (HAL_UART_Transmit(&HUARTx, (uint8_t *)&ch, 1U, 1000U) != HAL_OK) { + return -1; + } + + return ch; +} + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stdout_putchar (int ch) { + + if (HAL_UART_Transmit(&HUARTx, (uint8_t *)&ch, 1U, 1000U) != HAL_OK) { + return -1; + } + + return ch; +} + +/** + Get a character from the stdio + + \return The next character from the input, or -1 on error. +*/ +int stdin_getchar (void) { + uint8_t ch; + HAL_StatusTypeDef hal_stat; + + do { + hal_stat = HAL_UART_Receive(&HUARTx, &ch, 1U, 60000U); + } while (hal_stat == HAL_TIMEOUT); + + if (hal_stat != HAL_OK) { + return -1; + } + + return (int)ch; +} diff --git a/Examples/Fault/B-U585I-IOT02A/README.md b/Examples/Fault/B-U585I-IOT02A/README.md new file mode 100644 index 0000000..1ed1c23 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/README.md @@ -0,0 +1,130 @@ +# Fault example (Cortex-M33) {#flt_example_CM33_readme} + +## STMicroelectronics B-U585I-IOT02A board + +This project is a simple **Fault** component example running on **Arm Cortex-M33** microcontroller +on a STMicroelectronics [**B-U585I-IOT02A**](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) evaluation board. + +The application allows triggering of specific faults upon which the fault information is saved and system is reset. +When system restarts the fault information is output via the **Event Recorder** and via the **STDIO**. + +The fault information can also be inspected with **Component Viewer** in a debug session. + +## Prerequisites + +### Software: + - [**CMSIS-Toolbox v2.0.0**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) or newer + - [**Keil MDK v5.38**](https://www.keil.com/mdk5) or newer containing: + - Arm Compiler 6 (part of the MDK) + - [**STM32CubeMX v6.8.1**](https://www.st.com/en/development-tools/stm32cubemx.html) or newer with: + - STM32Cube MCU Package for STM32U5 Series v1.2.0 + - [**STM32CubeProgrammer**](https://www.st.com/en/development-tools/stm32cubeprog.html) utility + - [**Arm GNU Toolchain v12.2.MPACBTI-Rel1**](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) + (only necessary when building example with GCC) + +### CMSIS Packs: + - Required packs: + - ARM::CMSIS-View + - ARM::CMSIS-Compiler + - ARM::CMSIS + - Keil::STM32U5xx_DFP v2.1.0 + - Keil::B-U585I-IOT02A_BSP v1.0.0 + +### Hardware: + +This board has to be properly configured with **TrustZone** enabled. + +Please follow the steps below carefully: + +Configure the following **Option bytes** with **STM32CubeProgrammer** utility: + - **User Configuration**: + - `TZEN`: checked + - `DBANK`: checked + - **Boot Configuration**: + - `SECBOOTADD0`: Value = 0x1800 Address = 0x0c000000 + - **Secure Area 1**: + - `SECWM1_PSTRT`: Value = 0x0 Address = 0x08000000 + - `SECWM1_PEND`: Value = 0x7f Address = 0x080fe000 + - **Write Protection 1**: + - `WRP1A_PSTRT`: Value = 0x7f Address = 0x080fe000 + - `WRP1A_PEND`: Value = 0x0 Address = 0x08000000 + - **Secure Area 1**: + - `SECWM2_PSTRT`: Value = 0x7f Address = 0x08000000 + - `SECWM2_PEND`: Value = 0x0 Address = 0x08100000 + - **Write Protection 1**: + - `WRP2A_PSTRT`: Value = 0x7f Address = 0x081fe000 + - `WRP2A_PEND`: Value = 0x0 Address = 0x08100000 + +## Build and Run + +### Build and Run with uVision + +To try the example with uVision, do the following steps: + 1. Open the `Fault.uvmpw` in the uVision + 2. Build the `Project: Fault_S` project + 3. Build the `Project: Fault_NS` project + 4. Download the built application to the MCU's Flash + 5. Open the **Serial Terminal** application and connect to the **STMicroelectronics STLink Virtual COM Port (COMx)** (115200-8-N-1) + 6. Press **RESET** button on the board + 7. Follow the instructions in the **Serial Terminal** and observe the results + +> Note: In the debug session fault information can be inspected in the **Component View** and **Event Recorder** windows + +### Build with CMSIS-Toolbox + +Alternatively, this example can be built with [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox). + +To build the example with CMSIS-Toolbox do the following steps: + + 1. Use the `csolution` command to create `.cprj` project files (for **Arm Compiler 6** toolchain): + ``` + csolution convert -s Fault.csolution.yml + ``` + or, for **GCC** toolchain use the following command: + ``` + csolution convert -s Fault.csolution.yml -t GCC + ``` + 2. Use the `cbuild` command to create executable files for Secure and Non-secure applications: + ``` + cbuild ./Secure/Fault_S.Debug+HW.cprj + cbuild ./NonSecure/Fault_NS.Debug+HW.cprj + ``` +> Note: To run and debug executables built with CMSIS-Toolbox with uVision, it is necessary to adapt uVision settings + relating to output file, and also adapt Debug.ini and Flash.ini scripts accordingly + +## User Interface + +This example uses **Serial Terminal** as User Interface. + +The fault triggering is done by entering a number via **Serial Terminal** application (see possible values below). + + - 0: terminate the example + - 1: trigger the Non-Secure fault, Non-Secure data access Memory Management fault + - 2: trigger the Non-Secure fault, Non-Secure data access Bus fault + - 3: trigger the Non-Secure fault, Non-Secure undefined instruction Usage fault + - 4: trigger the Non-Secure fault, Non-Secure divide by 0 Usage fault + - 5: trigger the Secure fault, Non-Secure data access from Secure RAM memory + - 6: trigger the Secure fault, Non-Secure instruction execution from Secure Flash memory + - 7: trigger the Secure fault, Secure undefined instruction Usage fault + +## Example details + +Clock Settings: + - XTAL = MSIS = 4 MHz + - Core = **160 MHz** + +The example contains 2 applications: Secure and Non-Secure. + +**Secure application** (bare-metal, no RTOS): + - setups the system (clocks, power, security and privilege rights (GTZC), caching) according to the CubeMX configuration + - provides a function for triggering a fault on the Secure side + +**Non-Secure application** (uses RTX RTOS and Standard C Library): + - setups the peripherals used by the non-secure application (LEDs, button, UART1) according to the CubeMX configuration + - it runs 2 threads: + - 'AppThread' thread: Blink Green LED with 1 second interval + - 'FaultTriggerThread' thread: Trigger a fault according to input from the STDIO + +When a fault is triggered the fault handler saves the fault information with the **ARM_FaultSave** function. +When valid fault information exists it can be viewed with **Component Viewer** or with **ARM_FaultRecord** function +the fault information can be output to the **Event Recorder** or with the **ARM_FaultPrint** function it can be output to the STDIO. diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.cproject.yml b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.cproject.yml new file mode 100644 index 0000000..898bf77 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.cproject.yml @@ -0,0 +1,48 @@ +project: + + processor: + trustzone: secure + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler + - pack: ARM::CMSIS-View + + groups: + - group: Documentation + files: + - file: ../README.md + + - group: Interface + files: + - file: interface.c + - file: tz_context.c + + components: + - component: CMSIS:CORE + + - component: CMSIS-Compiler:I/O:STDERR&Breakpoint + - component: CMSIS-Compiler:I/O:STDOUT&Breakpoint + - component: CMSIS-Compiler:I/O:STDIN&Breakpoint + + - component: CMSIS-View:Fault:Storage + + - component: Device:STM32Cube Framework:STM32CubeMX + + - component: Device:STM32Cube HAL:Common + - component: Device:STM32Cube HAL:Cortex + - component: Device:STM32Cube HAL:DMA + - component: Device:STM32Cube HAL:Flash + - component: Device:STM32Cube HAL:GPIO + - component: Device:STM32Cube HAL:GTZC + - component: Device:STM32Cube HAL:ICACHE + - component: Device:STM32Cube HAL:PWR + - component: Device:STM32Cube HAL:RCC + - component: Device:STM32Cube HAL:UART + - component: Device:STM32Cube LL:Common + - component: Device:STM32Cube LL:GPIO + - component: Device:STM32Cube LL:PWR + - component: Device:STM32Cube LL:RCC + - component: Device:STM32Cube LL:UTILS + + - component: Device:Startup&Source C diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvguix b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvguix new file mode 100644 index 0000000..2f143ed --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvguix @@ -0,0 +1,3614 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1200 + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvoptx b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvoptx new file mode 100644 index 0000000..69df8e3 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + B-U585I-IOT02A + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + ..\Debug.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + EVENTREC_CNF + -l0 -a1 -s0 -fFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF007800000000FFFF000000000000000000000000000000000000000000000080044000000000FFFF0000000000000000000000000000000000000000000000800000 + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=769,868,1222,1200,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U002000123156501320323443 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BE12477) -L00(0) -TO131090 -TC160000000 -TT10000000 -TP21 -TDS800D -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FF1STM32U5xx_2M_0C00.FLM -FS1C000000 -FL1200000 -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800 -FS08000000 -FL0200000 -FF1STM32U5xx_2M_0C00 -FS1C000000 -FL1200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM)) + + + + + C:\ARM\PACK\ARM\CMSIS-View\1.0.1\Fault\ARM_Fault.scvd + ARM.CMSIS-View.1.0.1 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + C:\Lint\lint-nt.exe + + 0 + 0 + 59 + .\Lint\MISRA_C_2012_Config.lnt + MISRA_C_2012_Config + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Documentation + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\README.md + README.md + 0 + 0 + + + + + :STM32CubeMX_S:Common Sources + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\main.c + main.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Inc\stm32u5xx_it.h + stm32u5xx_it.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\stm32u5xx_it.c + stm32u5xx_it.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\secure_nsc.c + secure_nsc.c + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure_nsclib\secure_nsc.h + secure_nsc.h + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + ..\Board\B-U585I-IOT02A\STM32CubeMX\STM32CubeMX.ioc + STM32CubeMX.ioc + 0 + 0 + + + + + Interface + 0 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + .\tz_context.c + tz_context.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS-Compiler + 0 + 0 + 0 + 1 + + + + ::CMSIS-View + 1 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvprojx b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvprojx new file mode 100644 index 0000000..b288a2d --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.uvprojx @@ -0,0 +1,924 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + B-U585I-IOT02A + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 6190000::V6.19::ARMCLANG + 1 + + + STM32U585AIIx + STMicroelectronics + Keil.STM32U5xx_DFP.2.1.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00040000) IRAM2(0x20040000,0x00080000) IROM(0x08000000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC8000 -FN2 -FF0STM32U5xx_2M_0800 -FS08000000 -FL0200000 -FF1STM32U5xx_2M_0C00 -FS1C000000 -FL1200000 -FP0($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0800.FLM) -FP1($$Device:STM32U585AIIx$CMSIS\Flash\STM32U5xx_2M_0C00.FLM)) + 0 + $$Device:STM32U585AIIx$Drivers\CMSIS\Device\ST\STM32U5xx\Include\stm32u5xx.h + + + + + + + + + + $$Device:STM32U585AIIx$CMSIS\SVD\STM32U5xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Fault_S + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + ..\Flash.ini + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 1 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xc000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x40000 + + + 0 + 0x20040000 + 0x80000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + .\RTE\Device\STM32U585AIIx\stm32u585xx_flash_s.sct + + + + + + + + + + + Documentation + + + README.md + 5 + ..\README.md + + + + + :STM32CubeMX_S:Common Sources + + + main.c + 1 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\main.c + + + stm32u5xx_it.h + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Inc\stm32u5xx_it.h + + + stm32u5xx_it.c + 1 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\stm32u5xx_it.c + + + secure_nsc.c + 1 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure\Src\secure_nsc.c + + + secure_nsc.h + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\Secure_nsclib\secure_nsc.h + + + STM32CubeMX.ioc + 5 + ..\Board\B-U585I-IOT02A\STM32CubeMX\STM32CubeMX.ioc + + + + + Interface + + + interface.c + 1 + .\interface.c + + + tz_context.c + 1 + .\tz_context.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 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+ + + + + + + + + + + + + + + + + + + 4 + + + + + + + + RTE\Board_Support\STM32U585AIIx\b_u585i_iot02a_conf.h + + + + + + RTE\Device\STM32U585AIIx\partition_gen.h + + + + + + + + RTE\Device\STM32U585AIIx\partition_stm32u585xx.h + + + + + + + + RTE\Device\STM32U585AIIx\startup_stm32u585xx.c + + + + + + + + RTE\Device\STM32U585AIIx\startup_stm32u585xx.s + + + + + + RTE\Device\STM32U585AIIx\stm32u585xx_flash_s.sct + + + + + + + + RTE\Device\STM32U585AIIx\system_stm32u5xx_s.c + + + + + + + + + + + + + Fault_S + 1 + Fault_S + + + + + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h new file mode 100644 index 0000000..457e243 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h @@ -0,0 +1,444 @@ +/**************************************************************************//** + * @file partition_gen.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for STM32U585xx Device + * @version V1.1.0 + * @date 27.02.2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_GEN_H +#define PARTITION_GEN_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200CFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +#endif /* PARTITION_GEN_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h.base@1.1.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h.base@1.1.0 new file mode 100644 index 0000000..4697b9f --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_gen.h.base@1.1.0 @@ -0,0 +1,444 @@ +/**************************************************************************//** + * @file partition_gen.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for STM32U585xx Device + * @version V1.1.0 + * @date 27.02.2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_GEN_H +#define PARTITION_GEN_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +#endif /* PARTITION_GEN_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h new file mode 100644 index 0000000..3dee906 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file partition_stm32u585xx.h + * @author + * @brief CMSIS STM32U585xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2019 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32U585XX_H +#define PARTITION_STM32U585XX_H + +#include "partition_gen.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U585XX_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h.base@1.1.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h.base@1.1.0 new file mode 100644 index 0000000..3dee906 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/partition_stm32u585xx.h.base@1.1.0 @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file partition_stm32u585xx.h + * @author + * @brief CMSIS STM32U585xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2019 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32U585XX_H +#define PARTITION_STM32U585XX_H + +#include "partition_gen.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U585XX_H */ diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c new file mode 100644 index 0000000..8ad665a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c @@ -0,0 +1,394 @@ +/****************************************************************************** + * @file startup_stm32u585xx.c + * @brief CMSIS-Core Device Startup File for STM32U585xx Device + * @version V1.0.0 + * @date 23. February 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32u5xx.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void WWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PVD_PVM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TAMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RAMCFG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GTZC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPUART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM16_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM17_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTG_FS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CRS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWR_S3WU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PKA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UCPD1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCACHE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADF1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2D_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCMI_PSSI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CORDIC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMAC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + WWDG_IRQHandler, /* Window WatchDog */ + PVD_PVM_IRQHandler, /* PVD/PVM through EXTI Line detection interrupt */ + RTC_IRQHandler, /* RTC non-secure interrupt */ + RTC_S_IRQHandler, /* RTC secure interrupt */ + TAMP_IRQHandler, /* Tamper non-secure interrupt */ + RAMCFG_IRQHandler, /* RAMCFG global interrupt */ + FLASH_IRQHandler, /* FLASH non-secure global interrupt */ + FLASH_S_IRQHandler, /* FLASH secure global interrupt */ + GTZC_IRQHandler, /* Global TrustZone Controller interrupt */ + RCC_IRQHandler, /* RCC non-secure global interrupt */ + RCC_S_IRQHandler, /* RCC secure global interrupt */ + EXTI0_IRQHandler, /* EXTI Line0 interrupt */ + EXTI1_IRQHandler, /* EXTI Line1 interrupt */ + EXTI2_IRQHandler, /* EXTI Line2 interrupt */ + EXTI3_IRQHandler, /* EXTI Line3 interrupt */ + EXTI4_IRQHandler, /* EXTI Line4 interrupt */ + EXTI5_IRQHandler, /* EXTI Line5 interrupt */ + EXTI6_IRQHandler, /* EXTI Line6 interrupt */ + EXTI7_IRQHandler, /* EXTI Line7 interrupt */ + EXTI8_IRQHandler, /* EXTI Line8 interrupt */ + EXTI9_IRQHandler, /* EXTI Line9 interrupt */ + EXTI10_IRQHandler, /* EXTI Line10 interrupt */ + EXTI11_IRQHandler, /* EXTI Line11 interrupt */ + EXTI12_IRQHandler, /* EXTI Line12 interrupt */ + EXTI13_IRQHandler, /* EXTI Line13 interrupt */ + EXTI14_IRQHandler, /* EXTI Line14 interrupt */ + EXTI15_IRQHandler, /* EXTI Line15 interrupt */ + IWDG_IRQHandler, /* IWDG global interrupt */ + SAES_IRQHandler, /* Secure AES global interrupt */ + GPDMA1_Channel0_IRQHandler, /* GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQHandler, /* GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQHandler, /* GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQHandler, /* GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQHandler, /* GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQHandler, /* GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQHandler, /* GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQHandler, /* GPDMA1 Channel 7 global interrupt */ + ADC1_IRQHandler, /* ADC1 global interrupt */ + DAC1_IRQHandler, /* DAC1 global interrupt */ + FDCAN1_IT0_IRQHandler, /* FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQHandler, /* FDCAN1 interrupt 1 */ + TIM1_BRK_IRQHandler, /* TIM1 Break interrupt */ + TIM1_UP_IRQHandler, /* TIM1 Update interrupt */ + TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQHandler, /* TIM1 Capture Compare interrupt */ + TIM2_IRQHandler, /* TIM2 global interrupt */ + TIM3_IRQHandler, /* TIM3 global interrupt */ + TIM4_IRQHandler, /* TIM4 global interrupt */ + TIM5_IRQHandler, /* TIM5 global interrupt */ + TIM6_IRQHandler, /* TIM6 global interrupt */ + TIM7_IRQHandler, /* TIM7 global interrupt */ + TIM8_BRK_IRQHandler, /* TIM8 Break interrupt */ + TIM8_UP_IRQHandler, /* TIM8 Update interrupt */ + TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQHandler, /* TIM8 Capture Compare interrupt */ + I2C1_EV_IRQHandler, /* I2C1 Event interrupt */ + I2C1_ER_IRQHandler, /* I2C1 Error interrupt */ + I2C2_EV_IRQHandler, /* I2C2 Event interrupt */ + I2C2_ER_IRQHandler, /* I2C2 Error interrupt */ + SPI1_IRQHandler, /* SPI1 global interrupt */ + SPI2_IRQHandler, /* SPI2 global interrupt */ + USART1_IRQHandler, /* USART1 global interrupt */ + USART2_IRQHandler, /* USART2 global interrupt */ + USART3_IRQHandler, /* USART3 global interrupt */ + UART4_IRQHandler, /* UART4 global interrupt */ + UART5_IRQHandler, /* UART5 global interrupt */ + LPUART1_IRQHandler, /* LPUART1 global interrupt */ + LPTIM1_IRQHandler, /* LPTIM1 global interrupt */ + LPTIM2_IRQHandler, /* LPTIM2 global interrupt */ + TIM15_IRQHandler, /* TIM15 global interrupt */ + TIM16_IRQHandler, /* TIM16 global interrupt */ + TIM17_IRQHandler, /* TIM17 global interrupt */ + COMP_IRQHandler, /* COMP1 and COMP2 through EXTI Lines interrupt */ + OTG_FS_IRQHandler, /* USB OTG FS global interrupt */ + CRS_IRQHandler, /* CRS global interrupt */ + FMC_IRQHandler, /* FMC global interrupt */ + OCTOSPI1_IRQHandler, /* OctoSPI1 global interrupt */ + PWR_S3WU_IRQHandler, /* PWR wake up from Stop3 interrupt */ + SDMMC1_IRQHandler, /* SDMMC1 global interrupt */ + SDMMC2_IRQHandler, /* SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQHandler, /* GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQHandler, /* GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQHandler, /* GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQHandler, /* GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQHandler, /* GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQHandler, /* GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQHandler, /* GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQHandler, /* GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQHandler, /* I2C3 event interrupt */ + I2C3_ER_IRQHandler, /* I2C3 error interrupt */ + SAI1_IRQHandler, /* Serial Audio Interface 1 global interrupt */ + SAI2_IRQHandler, /* Serial Audio Interface 2 global interrupt */ + TSC_IRQHandler, /* Touch Sense Controller global interrupt */ + AES_IRQHandler, /* AES global interrupt */ + RNG_IRQHandler, /* RNG global interrupt */ + FPU_IRQHandler, /* FPU global interrupt */ + HASH_IRQHandler, /* HASH global interrupt */ + PKA_IRQHandler, /* PKA global interrupt */ + LPTIM3_IRQHandler, /* LPTIM3 global interrupt */ + SPI3_IRQHandler, /* SPI3 global interrupt */ + I2C4_ER_IRQHandler, /* I2C4 Error interrupt */ + I2C4_EV_IRQHandler, /* I2C4 Event interrupt */ + MDF1_FLT0_IRQHandler, /* MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQHandler, /* MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQHandler, /* MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQHandler, /* MDF1 Filter 3 global interrupt */ + UCPD1_IRQHandler, /* UCPD1 global interrupt */ + ICACHE_IRQHandler, /* Instruction cache global interrupt */ + OTFDEC1_IRQHandler, /* OTFDEC1 global interrupt */ + OTFDEC2_IRQHandler, /* OTFDEC2 global interrupt */ + LPTIM4_IRQHandler, /* LPTIM4 global interrupt */ + DCACHE1_IRQHandler, /* Data cache global interrupt */ + ADF1_IRQHandler, /* ADF interrupt */ + ADC4_IRQHandler, /* ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQHandler, /* LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQHandler, /* LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQHandler, /* LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQHandler, /* LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQHandler, /* DMA2D global interrupt */ + DCMI_PSSI_IRQHandler, /* DCMI/PSSI global interrupt */ + OCTOSPI2_IRQHandler, /* OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQHandler, /* MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQHandler, /* MDF1 Filter 5 global interrupt */ + CORDIC_IRQHandler, /* CORDIC global interrupt */ + FMAC_IRQHandler /* FMAC global interrupt */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 new file mode 100644 index 0000000..8ad665a --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/startup_stm32u585xx.c.base@1.0.0 @@ -0,0 +1,394 @@ +/****************************************************************************** + * @file startup_stm32u585xx.c + * @brief CMSIS-Core Device Startup File for STM32U585xx Device + * @version V1.0.0 + * @date 23. February 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32u5xx.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void WWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PVD_PVM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TAMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RAMCFG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLASH_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GTZC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RCC_S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void EXTI15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IWDG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM1_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_BRK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_UP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_TRG_COM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM8_CC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPUART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM16_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM17_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTG_FS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CRS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWR_S3WU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SDMMC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel8_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel9_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel10_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel11_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel12_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel13_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel14_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPDMA1_Channel15_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SAI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HASH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PKA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_ER_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_EV_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UCPD1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OTFDEC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPTIM4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCACHE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADF1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LPDMA1_Channel3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2D_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DCMI_PSSI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void OCTOSPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MDF1_FLT5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CORDIC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FMAC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + WWDG_IRQHandler, /* Window WatchDog */ + PVD_PVM_IRQHandler, /* PVD/PVM through EXTI Line detection interrupt */ + RTC_IRQHandler, /* RTC non-secure interrupt */ + RTC_S_IRQHandler, /* RTC secure interrupt */ + TAMP_IRQHandler, /* Tamper non-secure interrupt */ + RAMCFG_IRQHandler, /* RAMCFG global interrupt */ + FLASH_IRQHandler, /* FLASH non-secure global interrupt */ + FLASH_S_IRQHandler, /* FLASH secure global interrupt */ + GTZC_IRQHandler, /* Global TrustZone Controller interrupt */ + RCC_IRQHandler, /* RCC non-secure global interrupt */ + RCC_S_IRQHandler, /* RCC secure global interrupt */ + EXTI0_IRQHandler, /* EXTI Line0 interrupt */ + EXTI1_IRQHandler, /* EXTI Line1 interrupt */ + EXTI2_IRQHandler, /* EXTI Line2 interrupt */ + EXTI3_IRQHandler, /* EXTI Line3 interrupt */ + EXTI4_IRQHandler, /* EXTI Line4 interrupt */ + EXTI5_IRQHandler, /* EXTI Line5 interrupt */ + EXTI6_IRQHandler, /* EXTI Line6 interrupt */ + EXTI7_IRQHandler, /* EXTI Line7 interrupt */ + EXTI8_IRQHandler, /* EXTI Line8 interrupt */ + EXTI9_IRQHandler, /* EXTI Line9 interrupt */ + EXTI10_IRQHandler, /* EXTI Line10 interrupt */ + EXTI11_IRQHandler, /* EXTI Line11 interrupt */ + EXTI12_IRQHandler, /* EXTI Line12 interrupt */ + EXTI13_IRQHandler, /* EXTI Line13 interrupt */ + EXTI14_IRQHandler, /* EXTI Line14 interrupt */ + EXTI15_IRQHandler, /* EXTI Line15 interrupt */ + IWDG_IRQHandler, /* IWDG global interrupt */ + SAES_IRQHandler, /* Secure AES global interrupt */ + GPDMA1_Channel0_IRQHandler, /* GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQHandler, /* GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQHandler, /* GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQHandler, /* GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQHandler, /* GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQHandler, /* GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQHandler, /* GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQHandler, /* GPDMA1 Channel 7 global interrupt */ + ADC1_IRQHandler, /* ADC1 global interrupt */ + DAC1_IRQHandler, /* DAC1 global interrupt */ + FDCAN1_IT0_IRQHandler, /* FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQHandler, /* FDCAN1 interrupt 1 */ + TIM1_BRK_IRQHandler, /* TIM1 Break interrupt */ + TIM1_UP_IRQHandler, /* TIM1 Update interrupt */ + TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQHandler, /* TIM1 Capture Compare interrupt */ + TIM2_IRQHandler, /* TIM2 global interrupt */ + TIM3_IRQHandler, /* TIM3 global interrupt */ + TIM4_IRQHandler, /* TIM4 global interrupt */ + TIM5_IRQHandler, /* TIM5 global interrupt */ + TIM6_IRQHandler, /* TIM6 global interrupt */ + TIM7_IRQHandler, /* TIM7 global interrupt */ + TIM8_BRK_IRQHandler, /* TIM8 Break interrupt */ + TIM8_UP_IRQHandler, /* TIM8 Update interrupt */ + TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQHandler, /* TIM8 Capture Compare interrupt */ + I2C1_EV_IRQHandler, /* I2C1 Event interrupt */ + I2C1_ER_IRQHandler, /* I2C1 Error interrupt */ + I2C2_EV_IRQHandler, /* I2C2 Event interrupt */ + I2C2_ER_IRQHandler, /* I2C2 Error interrupt */ + SPI1_IRQHandler, /* SPI1 global interrupt */ + SPI2_IRQHandler, /* SPI2 global interrupt */ + USART1_IRQHandler, /* USART1 global interrupt */ + USART2_IRQHandler, /* USART2 global interrupt */ + USART3_IRQHandler, /* USART3 global interrupt */ + UART4_IRQHandler, /* UART4 global interrupt */ + UART5_IRQHandler, /* UART5 global interrupt */ + LPUART1_IRQHandler, /* LPUART1 global interrupt */ + LPTIM1_IRQHandler, /* LPTIM1 global interrupt */ + LPTIM2_IRQHandler, /* LPTIM2 global interrupt */ + TIM15_IRQHandler, /* TIM15 global interrupt */ + TIM16_IRQHandler, /* TIM16 global interrupt */ + TIM17_IRQHandler, /* TIM17 global interrupt */ + COMP_IRQHandler, /* COMP1 and COMP2 through EXTI Lines interrupt */ + OTG_FS_IRQHandler, /* USB OTG FS global interrupt */ + CRS_IRQHandler, /* CRS global interrupt */ + FMC_IRQHandler, /* FMC global interrupt */ + OCTOSPI1_IRQHandler, /* OctoSPI1 global interrupt */ + PWR_S3WU_IRQHandler, /* PWR wake up from Stop3 interrupt */ + SDMMC1_IRQHandler, /* SDMMC1 global interrupt */ + SDMMC2_IRQHandler, /* SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQHandler, /* GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQHandler, /* GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQHandler, /* GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQHandler, /* GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQHandler, /* GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQHandler, /* GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQHandler, /* GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQHandler, /* GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQHandler, /* I2C3 event interrupt */ + I2C3_ER_IRQHandler, /* I2C3 error interrupt */ + SAI1_IRQHandler, /* Serial Audio Interface 1 global interrupt */ + SAI2_IRQHandler, /* Serial Audio Interface 2 global interrupt */ + TSC_IRQHandler, /* Touch Sense Controller global interrupt */ + AES_IRQHandler, /* AES global interrupt */ + RNG_IRQHandler, /* RNG global interrupt */ + FPU_IRQHandler, /* FPU global interrupt */ + HASH_IRQHandler, /* HASH global interrupt */ + PKA_IRQHandler, /* PKA global interrupt */ + LPTIM3_IRQHandler, /* LPTIM3 global interrupt */ + SPI3_IRQHandler, /* SPI3 global interrupt */ + I2C4_ER_IRQHandler, /* I2C4 Error interrupt */ + I2C4_EV_IRQHandler, /* I2C4 Event interrupt */ + MDF1_FLT0_IRQHandler, /* MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQHandler, /* MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQHandler, /* MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQHandler, /* MDF1 Filter 3 global interrupt */ + UCPD1_IRQHandler, /* UCPD1 global interrupt */ + ICACHE_IRQHandler, /* Instruction cache global interrupt */ + OTFDEC1_IRQHandler, /* OTFDEC1 global interrupt */ + OTFDEC2_IRQHandler, /* OTFDEC2 global interrupt */ + LPTIM4_IRQHandler, /* LPTIM4 global interrupt */ + DCACHE1_IRQHandler, /* Data cache global interrupt */ + ADF1_IRQHandler, /* ADF interrupt */ + ADC4_IRQHandler, /* ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQHandler, /* LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQHandler, /* LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQHandler, /* LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQHandler, /* LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQHandler, /* DMA2D global interrupt */ + DCMI_PSSI_IRQHandler, /* DCMI/PSSI global interrupt */ + OCTOSPI2_IRQHandler, /* OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQHandler, /* MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQHandler, /* MDF1 Filter 5 global interrupt */ + CORDIC_IRQHandler, /* CORDIC global interrupt */ + FMAC_IRQHandler /* FMAC global interrupt */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld new file mode 100644 index 0000000..f86acd4 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld @@ -0,0 +1,350 @@ +/****************************************************************************** + * @file stm32u585xx_flash_s.ld + * @brief GNU Linker Script for STM32U585xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__ROM_BASE = 0x0C000000; +__ROM_SIZE = 0x00100000; + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__RAM_BASE = 0x30000000; +__RAM_SIZE = 0x00040000; + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__NOINIT_SIZE = 0x00000000; + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__CMSEVENEER_SIZE = 0x00002000; + +/* +// <<< end of configuration section >>> + */ + +/* ARMv8-M stack sealing: + * to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 8; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE + RAM_NS (rwx) : ORIGIN = 0x200B0000, LENGTH = 0x100 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. + */ + .gnu.sgstubs (ORIGIN(FLASH) + LENGTH(FLASH) - __CMSEVENEER_SIZE) : + { + . = ALIGN(32); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* This section contains data that is not initialised + * during load *or* application reset. + */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + * to use ARMv8-M stack sealing uncomment '.stackseal' section + */ + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Uninitialized memory for Fault information (ARM_FaultInfo) */ + .noinit.fault 0x200B0000 (NOLOAD) : + { + *(.noinit.fault) + } > RAM_NS +} diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld.base@2.2.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld.base@2.2.0 new file mode 100644 index 0000000..d030f62 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.ld.base@2.2.0 @@ -0,0 +1,343 @@ +/****************************************************************************** + * @file STM32U585xx_FLASH_s_c.ld + * @brief GNU Linker Script for STM32U585xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__ROM_BASE = 0x0C000000; +__ROM_SIZE = 0x00100000; + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__RAM_BASE = 0x30000000; +__RAM_SIZE = 0x00040000; + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__NOINIT_SIZE = 0x00000800; + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +__CMSEVENEER_SIZE = 0x00002000; + +/* +// <<< end of configuration section >>> + */ + +/* ARMv8-M stack sealing: + * to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 8; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. + */ + .gnu.sgstubs (ORIGIN(FLASH) + LENGTH(FLASH) - __CMSEVENEER_SIZE) : + { + . = ALIGN(32); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* This section contains data that is not initialised + * during load *or* application reset. + */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + * to use ARMv8-M stack sealing uncomment '.stackseal' section + */ + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct new file mode 100644 index 0000000..50a0f83 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct @@ -0,0 +1,136 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse +/* command above MUST be in first line (no comment above!) */ + +/****************************************************************************** + * @file stm32u585xx_flash_s.sct + * @brief GNU Linker Script for STM32U575xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __ROM_BASE 0x0C000000 +#define __ROM_SIZE 0x00100000 + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __RAM_BASE 0x30000000 +#define __RAM_SIZE 0x00040000 + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000000 + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __CMSEVENEER_SIZE 0x00002000 + +/* +// <<< end of configuration section >>> + */ + + +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE ) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE ( AlignExpr(+0, 8) ) /* starts after RW_RAM or RW_NOINIT section, 8 byte aligned */ + +#define __STACKSEAL_SIZE (8) + +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE - __STACKSEAL_SIZE ) +#define __RW_NOINIT_BASE ( __RAM_BASE + __RW_SIZE ) /* starts after RW_RAM section */ + + +LR_APP __LR_BASE __LR_SIZE { /* load region for application */ + ER_APP __LR_BASE __LR_SIZE { /* execution region for application */ + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { /* RW, ZI data */ + .ANY (+RW +ZI) + } + +#if __NOINIT_SIZE > 0 + RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { /* no init data */ + *(.bss.noinit) + } +#endif + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { /* empty region for heap */ + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { /* empty region for stack */ + } + + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { /* empty region for stack seal immediately after stack */ + } + + RW_NS_NOINIT_FAULT 0x200B0000 UNINIT 0x100 { /* Uninitialized memory for Fault information (ARM_FaultInfo) */ + *(.bss.noinit.fault) + } +} + +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { /* load/execution region for CMSE Veneers */ + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct.base@2.0.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct.base@2.0.0 new file mode 100644 index 0000000..09cc1ac --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/stm32u585xx_flash_s.sct.base@2.0.0 @@ -0,0 +1,132 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse +/* command above MUST be in first line (no comment above!) */ + +/****************************************************************************** + * @file stm32u585xx_flash_s.sct + * @brief GNU Linker Script for STM32U575xx Device + * @version V2.0.0 + * @date 10. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +// <<< Use Configuration Wizard in Context Menu >>> + */ + +/* +// Flash Configuration +// specify the base address and the size of the used Flash +// Flash Base Address <0x0-0xFFFFFFFF:8> +// Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __ROM_BASE 0x0C000000 +#define __ROM_SIZE 0x00100000 + +/* +// RAM Configuration +// specify the base address and the complete size of the used RAM +// RAM Base Address <0x0-0xFFFFFFFF:8> +// RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __RAM_BASE 0x30000000 +#define __RAM_SIZE 0x00040000 + +/* +// Stack / Heap Configuration +// specify the size used for the Stack, Heap sections +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + */ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000000 + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __CMSEVENEER_SIZE 0x00002000 + +/* +// <<< end of configuration section >>> + */ + + +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE ) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE ( AlignExpr(+0, 8) ) /* starts after RW_RAM or RW_NOINIT section, 8 byte aligned */ + +#define __STACKSEAL_SIZE (8 ) + +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE - __STACKSEAL_SIZE ) +#define __RW_NOINIT_BASE ( __RAM_BASE + __RW_SIZE ) /* starts after RW_RAM section */ + + +LR_APP __LR_BASE __LR_SIZE { /* load region for application */ + ER_APP __LR_BASE __LR_SIZE { /* execution region for application */ + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { /* RW, ZI data */ + .ANY (+RW +ZI) + } + +#if __NOINIT_SIZE > 0 + RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { /* no init data */ + *(.bss.noinit) + } +#endif + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { /* empty region for heap */ + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { /* empty region for stack */ + } + + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { /* empty region for stack seal immediately after stack */ + } +} + +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { /* load/execution region for CMSE Veneers */ + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c new file mode 100644 index 0000000..e17f8ce --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c @@ -0,0 +1,397 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in secure application when the system implements + * the TrustZone-M security. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 8 + *----------------------------------------------------------------------------- + * PLL1_P | 7 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL2_SRC | NA + *----------------------------------------------------------------------------- + * PLL2_M | NA + *----------------------------------------------------------------------------- + * PLL2_N | NA + *----------------------------------------------------------------------------- + * PLL2_P | NA + *----------------------------------------------------------------------------- + * PLL2_Q | NA + *----------------------------------------------------------------------------- + * PLL2_R | NA + *----------------------------------------------------------------------------- + * PLL3_SRC | NA + *----------------------------------------------------------------------------- + * PLL3_M | NA + *----------------------------------------------------------------------------- + * PLL3_N | NA + *----------------------------------------------------------------------------- + * PLL3_P | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "stm32u5xx.h" +#include "partition_stm32u5xx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + RCC->CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC->PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32u5xxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange; + float_t fracn1, pllvco; + + /* Get MSI Range frequency--------------------------------------------------*/ + if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x00: /* No clock sent to PLL*/ + pllvco = (float_t)0U; + break; + + case 0x02: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = ((float_t)msirange / (float_t)pllm); + break; + } + + pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U); + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); + SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr); + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value (HCLK) + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c.base@1.2.0 b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c.base@1.2.0 new file mode 100644 index 0000000..e02ffa3 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/RTE/Device/STM32U585AIIx/system_stm32u5xx_s.c.base@1.2.0 @@ -0,0 +1,399 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in secure application when the system implements + * the TrustZone-M security. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 8 + *----------------------------------------------------------------------------- + * PLL1_P | 7 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL2_SRC | NA + *----------------------------------------------------------------------------- + * PLL2_M | NA + *----------------------------------------------------------------------------- + * PLL2_N | NA + *----------------------------------------------------------------------------- + * PLL2_P | NA + *----------------------------------------------------------------------------- + * PLL2_Q | NA + *----------------------------------------------------------------------------- + * PLL2_R | NA + *----------------------------------------------------------------------------- + * PLL3_SRC | NA + *----------------------------------------------------------------------------- + * PLL3_M | NA + *----------------------------------------------------------------------------- + * PLL3_N | NA + *----------------------------------------------------------------------------- + * PLL3_P | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "stm32u5xx.h" +#include "partition_stm32u5xx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + RCC->CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC->PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32u5xxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange; + float_t fracn1, pllvco; + + /* Get MSI Range frequency--------------------------------------------------*/ + if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x00: /* No clock sent to PLL*/ + pllvco = (float_t)0U; + break; + + case 0x02: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = ((float_t)msirange / (float_t)pllm); + break; + } + + pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U); + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); + SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr); + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value (HCLK) + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/interface.c b/Examples/Fault/B-U585I-IOT02A/Secure/interface.c new file mode 100644 index 0000000..aab2915 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/interface.c @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Name: interface.c + * Purpose: Non-Secure to Secure function implementation + *----------------------------------------------------------------------------*/ + +#include +#include "interface.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "../NonSecure/ARM_FaultTrigger.h" + +/* Non-secure callable (entry) functions */ + +/* This function is used to trigger Secure fault */ +__attribute__((cmse_nonsecure_entry)) void Secure_TriggerFault (uint32_t fault_id) { + + switch (fault_id) { + case ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION: // Trigger Secure - UsageFault - undefined instruction + __ASM volatile ( + ".syntax unified\n" + ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 + ); + break; + } +} diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/interface.h b/Examples/Fault/B-U585I-IOT02A/Secure/interface.h new file mode 100644 index 0000000..2c632ad --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/interface.h @@ -0,0 +1,9 @@ +/*---------------------------------------------------------------------------- + * Name: interface.h + * Purpose: Non-Secure to Secure interface + *----------------------------------------------------------------------------*/ + +#include + +/* Non-secure callable functions */ +extern void Secure_TriggerFault (uint32_t fault_id); diff --git a/Examples/Fault/B-U585I-IOT02A/Secure/tz_context.c b/Examples/Fault/B-U585I-IOT02A/Secure/tz_context.c new file mode 100644 index 0000000..a195223 --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/Secure/tz_context.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 512U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + uint32_t control = 0U; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory+sizeof(ProcessStackMemory)); + + // Privileged Thread Mode using PSP +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + control = __get_CONTROL(); + control &= (CONTROL_PAC_EN_Msk | CONTROL_UPAC_EN_Msk | CONTROL_BTI_EN_Msk | CONTROL_UBTI_EN_Msk); +#endif + __set_CONTROL(control | 0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/Examples/Fault/B-U585I-IOT02A/cdefault.yml b/Examples/Fault/B-U585I-IOT02A/cdefault.yml new file mode 100644 index 0000000..8a63f4e --- /dev/null +++ b/Examples/Fault/B-U585I-IOT02A/cdefault.yml @@ -0,0 +1,24 @@ +default: + + compiler: AC6 + + misc: + - for-compiler: AC6 + C-CPP: + - -ffunction-sections + C: + - -std=gnu11 + ASM: + - -masm=auto + Link: + - --map + - --info summarysizes + + - for-compiler: GCC + C-CPP: + - -ffunction-sections + C: + - -std=gnu11 + Link: + - --specs=nano.specs + - -Wl,-Map=$elf()$.map diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.c b/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.c new file mode 100644 index 0000000..6c7205f --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARM_FaultTrigger.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +// ARM_FaultTrigger function --------------------------------------------------- + +/** + Trigger a fault. + \param[in] fault_id Fault ID of the fault to be triggered +*/ +void ARM_FaultTrigger (uint32_t fault_id) { + volatile uint32_t val; + void (*ptr_func) (void); + + switch (fault_id) { + case ARM_FAULT_ID_MEM_DATA: // Trigger Non-Secure MemManage fault - data access + val = *((uint32_t *)0x20000000); // Read from address not allowed by the MPU (non-privileged access not allowed) + break; + + case ARM_FAULT_ID_BUS_DATA_PRECISE: // Trigger BusFault - data access (precise) + val = *((uint32_t *)0x3FFFFFFC); // Read from invalid address + break; + + case ARM_FAULT_ID_BUS_DATA_IMPRECISE: // Trigger BusFault - data access (imprecise) + *((uint32_t *)0x3FFFFFFC) = 1U; // Write to invalid address + break; + + case ARM_FAULT_ID_BUS_INSTRUCTION: // Trigger BusFault - instruction execution + ptr_func = (void (*) (void))(0x1FFFFFFC); + ptr_func(); // Call function from invalid address + break; + + case ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION: // Trigger UsageFault - undefined instruction + __ASM volatile ( + ".syntax unified\n" + ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 + ); + break; + + case ARM_FAULT_ID_USG_DIV_0: // Trigger UsageFault - divide by 0 + val = 0U; + val = 123/val; + break; + + default: + break; + } +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.h b/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.h new file mode 100644 index 0000000..424bc2c --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/ARM_FaultTrigger.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +// Fault IDs for fault triggering +#define ARM_FAULT_ID_MEM_DATA (1U) +#define ARM_FAULT_ID_BUS_DATA_PRECISE (2U) +#define ARM_FAULT_ID_BUS_DATA_IMPRECISE (3U) +#define ARM_FAULT_ID_BUS_INSTRUCTION (4U) +#define ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION (5U) +#define ARM_FAULT_ID_USG_DIV_0 (6U) + +// ARM_FaultTrigger function --------------------------------------------------- + +/// Trigger a fault. +/// \param[in] fault_id Fault Id of the fault to be triggered +extern void ARM_FaultTrigger (uint32_t fault_id); diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.c b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.c new file mode 100644 index 0000000..b6d468b --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.c @@ -0,0 +1,118 @@ +/*---------------------------------------------------------------------------- + * Name: Fault.c + * Purpose: Fault example program + *----------------------------------------------------------------------------*/ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "cmsis_os2.h" + +#include "ARM_Fault.h" +#include "ARM_FaultTrigger.h" + +#include "EventRecorder.h" + +extern osThreadId_t tid_AppThread; +extern osThreadId_t tid_FaultTriggerThread; + +/* STDIO initialize function */ +extern int stdio_init (void); + +/* Global Thread IDs (for debug) */ +osThreadId_t tid_AppThread; +osThreadId_t tid_FaultTriggerThread; + +/*--------------------------------------------------------------------------- + * Application thread + *---------------------------------------------------------------------------*/ +static __NO_RETURN void AppThread (void *argument) { + volatile uint32_t counter = 0U; + + (void)argument; + + for (;;) { + counter++; + osDelay(100U); + } +} + +/*--------------------------------------------------------------------------- + * Fault trigger thread + *---------------------------------------------------------------------------*/ +static __NO_RETURN void FaultTriggerThread (void *argument) { + char ch; + + (void)argument; + + // Display user interface message + printf("\r\n--- Fault example ---\r\n\r\n"); + printf("To trigger a fault please input a corresponding number:\r\n"); + printf(" - 0: terminate the example\r\n"); + printf(" - 1: data access (precise) Memory Management fault\r\n"); + printf(" - 2: data access (precise) Bus fault\r\n"); + printf(" - 3: data access (imprecise) Bus fault\r\n"); + printf(" - 4: instruction execution Bus fault\r\n"); + printf(" - 5: undefined instruction Usage fault\r\n"); + printf(" - 6: divide by 0 Usage fault\r\n\r\n"); + printf("Input>"); + + for (;;) { + ch = (char)getchar(); // Read character from console (blocking) + if (ch == '0') { + putchar(0x04); // Shutdown the simulator + } else { + ARM_FaultTrigger((uint32_t)(ch - '0')); // Trigger a fault + } + } +} + +/*--------------------------------------------------------------------------- + * Application main function + *---------------------------------------------------------------------------*/ +int main (void) { + + SystemCoreClockUpdate(); // Update SystemCoreClock variable + + SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk | // Enable BusFault + SCB_SHCSR_USGFAULTENA_Msk; // Enable UsageFault + SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; // Enable divide by 0 trap + + /* Configure MPU + - region 0: ROM - 0x00000000 .. 0x1FFFFFFF (end is extended to be able to trigger Bus fault) + - region 1: RAM - 0x20000000 .. 0x3FFFFFFF (end is extended to be able to trigger Bus fault) + - region 2: RAM (privileged only) - 0x20000000 .. 0x200000FF + - region 3: Peripherals - 0x40000000 .. 0x4FFFFFFF + */ + ARM_MPU_Disable(); + + ARM_MPU_SetRegion(ARM_MPU_RBAR(0U, 0x00000000), ARM_MPU_RASR_EX(0U, ARM_MPU_AP_RO, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, 0U), 0x00U, ARM_MPU_REGION_SIZE_512MB)); + ARM_MPU_SetRegion(ARM_MPU_RBAR(1U, 0x20000000), ARM_MPU_RASR_EX(1U, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, 0U), 0x00U, ARM_MPU_REGION_SIZE_512MB)); + ARM_MPU_SetRegion(ARM_MPU_RBAR(2U, 0x20000000), ARM_MPU_RASR_EX(1U, ARM_MPU_AP_PRIV, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, 0U), 0x00U, ARM_MPU_REGION_SIZE_256B)); + ARM_MPU_SetRegion(ARM_MPU_RBAR(3U, 0x40000000), ARM_MPU_RASR_EX(1U, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_DEVICE(0U) , 0x00U, ARM_MPU_REGION_SIZE_256MB)); + + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); // Enable Privileged Default + + stdio_init(); // Initialize STDIO + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + printf("\r\n\r\n- System Restarted -\r\n\r\n"); + } + + EventRecorderInitialize(EventRecordAll, 1U); // Initialize and start Event Recorder + + if (ARM_FaultOccurred() != 0U) { // If fault information exists + ARM_FaultRecord(); // Output decoded fault information via Event Recorder + EventRecorderStop(); // Stop Event Recorder + } + + osKernelInitialize(); // Initialize CMSIS-RTOS2 + // Create threads + tid_AppThread = osThreadNew(AppThread, NULL, NULL); + tid_FaultTriggerThread = osThreadNew(FaultTriggerThread, NULL, NULL); + osKernelStart(); // Start thread execution + + for (;;); +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.cproject.yml b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.cproject.yml new file mode 100644 index 0000000..44fa310 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.cproject.yml @@ -0,0 +1,40 @@ +project: + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler + - pack: ARM::CMSIS-View + + define: + - RTE_Compiler_EventRecorder + - RTE_Compiler_EventRecorder_DAP + - RTE_Compiler_EventRecorder_Semihosting + + groups: + - group: Documentation + files: + - file: README.md + + - group: Source Files + files: + - file: Fault.c + - file: ARM_FaultTrigger.c + - file: retarget_stdio.c + + components: + - component: CMSIS:CORE + - component: CMSIS:RTOS2:Keil RTX5&Source + + - component: CMSIS-Compiler:I/O:STDERR&User + - component: CMSIS-Compiler:I/O:STDOUT&User + - component: CMSIS-Compiler:I/O:STDIN&User + + - component: CMSIS-View:Event Recorder&Semihosting + - component: CMSIS-View:Fault:Record + - component: CMSIS-View:Fault:Storage + + - component: Board Support&V2M-MPS2:Common + + - component: CMSIS Driver:USART + + - component: Device:Startup&C Startup diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.csolution.yml b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.csolution.yml new file mode 100644 index 0000000..f92e588 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/Fault.csolution.yml @@ -0,0 +1,19 @@ +solution: + + created-for: CMSIS-Toolbox@2.0.0 + cdefault: + + packs: + - pack: Keil::V2M-MPS2_CMx_BSP@1.8.0 + + target-types: + - type: VHT_MPS2_Cortex-M7 + device: ARM::CMSDK_CM7_SP_VHT + + build-types: + - type: Debug + debug: on + optimize: none + + projects: + - project: ./Fault.cproject.yml diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/README.md b/Examples/Fault/VHT_MPS2_Cortex-M7/README.md new file mode 100644 index 0000000..1d95ee6 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/README.md @@ -0,0 +1,106 @@ +# Fault example (Cortex-M7) {#flt_example_CM7_readme} + +This project is a simple **Fault** component example running on **Arm Cortex-M7** microcontroller +simulated by [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/simulation/html/Using.html) with the **VHT_MPS2_Cortex-M7** model simulator. + +The application allows triggering of specific faults upon which the fault information is saved and system is reset. +When system restarts the fault information is output via the **Event Recorder**. + +The fault information can also be inspected with **Component Viewer** in a debug session. + +> Note: This example runs on the **Arm Virtual Hardware** simulator and does not require any hardware. + +## Prerequisites + +### Software: + - [**CMSIS-Toolbox v2.0.0**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) or newer + - [**Keil MDK v5.38**](https://www.keil.com/mdk5) or newer containing: + - Arm Compiler 6 (part of the MDK) + - Arm Virtual Hardware (AVH) for MPS2 platform with Cortex-M7 (part of the MDK-Professional) + - [**eventlist v1.1.0**](https://github.com/ARM-software/CMSIS-View/releases/tag/tools%2Feventlist%2F1.1.0) or newer + - [**Arm GNU Toolchain v12.2.MPACBTI-Rel1**](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) + (only necessary when building example with GCC) + +### CMSIS Packs: + - Required packs: + - ARM::CMSIS-View + - ARM::CMSIS-Compiler + - ARM::CMSIS + - Keil::V2M-MPS2_CMx_BSP v1.8.0 + + Missing packs can be installed by executing the following `csolution` and `cpackget` commands: + ``` + csolution list packs -s Fault.csolution.yml -m >missing_packs_list.txt + cpackget add -f missing_packs_list.txt + ``` +## Build + +1. Use the `csolution` command to create `.cprj` project files (for **Arm Compiler 6** toolchain): + ``` + csolution convert -s Fault.csolution.yml + ``` + or, for **GCC** toolchain use the following command: + ``` + csolution convert -s Fault.csolution.yml -t GCC + ``` + +2. Use the `cbuild` command to create executable files: + ``` + cbuild Fault.Debug+VHT_MPS2_Cortex-M7.cprj + ``` +## Run + +### AVH Target + +Execute the following steps: + - run the AVH model (with example built with **Arm Compiler 6** toolchain) from the command line by executing the following command: + ``` + VHT_MPS2_Cortex-M7 -f vht_config.txt out/Fault/VHT_MPS2_Cortex-M7/Debug/Fault.axf + ``` + or, run the AVH model (with example built with **GCC** toolchain) from the command line by executing the following command: + ``` + VHT_MPS2_Cortex-M7 -f vht_config.txt out/Fault/VHT_MPS2_Cortex-M7/Debug/Fault.elf + ``` + > Note: The Arm Virtual Hardware executables have to be in the environment path, otherwise absolute path to the `VHT_MPS2_Cortex-M7.exe` (e.g. `c:\Keil\ARM\VHT\VHT_MPS2_Cortex-M7`) has to be provided instead of `VHT_MPS2_Cortex-M7`. + + The generated file `EventRecorder.log` contains the events that were generated during the example execution. + This file is the input for the `eventlist` utility which can be used for further analysis. + + - follow the instructions in the simulator console + +The fault triggering is done by entering a number via simulator console (see possible values below). + + - 0: terminate the example + - 1: trigger the data access (precise) Memory Management fault + - 2: trigger the data access (precise) Bus fault + - 3: trigger the data access (imprecise) Bus fault + - 4: trigger the instruction execution Bus fault + - 5: trigger the undefined instruction Usage fault + - 6: trigger the divide by 0 Usage fault + +### Running the example in the uVision + + - open `Fault.Debug+VHT_MPS2_Cortex-M7.cprj` with the **uVision** + - open **Options for Target** + - select **Debug** tab + - under **Use** select **Models Cortex-M Debugger** and click on **Settings** button end enter the following: + - Command: `$K\ARM\VHT\VHT_MPS2_Cortex-M7.exe` + - Target: `armcortexm7ct` + - Configuration File: `.\vht_config.txt` + - under **Initialization File:** enter the following: `.\debug.ini` + - start the **Debug Session** + - **Run** the code + - you can see the events recorded by opening **View** - **Analysis Windows** - **Event Recorder** + - you can see the state of the recorded fault by opening **View** - **Watch Windows** - **Fault** + +## Analysis + +To analyze the result `eventlist` utility is needed, copy the executable `eventlist` file to the same folder where `EventRecorder.log` is located. + +To process `EventRecorder.log` file with the `eventlist` utility in **Windows Command Prompt** (cmd.exe) execute the following command: + ``` + eventlist -I %CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.0/Fault/ARM_Fault.scvd -I %CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.0/EventRecorder/EventRecorder.scvd -I %CMSIS_PACK_ROOT%/ARM\CMSIS/5.9.0/CMSIS/RTOS2/RTX/RTX5.scvd EventRecorder.log + ``` + +> Note: If CMSIS-View v1.0.0 or CMSIS v5.9.0 packs are not installed, in the previous command replace corresponding path with the path of the latest installed packs + (for example replace "%CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.0/Fault/" with "%CMSIS_PACK_ROOT%/ARM/CMSIS-View/1.0.1/Fault/") \ No newline at end of file diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h new file mode 100644 index 0000000..f4709e0 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 2 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 new file mode 100644 index 0000000..9802f2a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..737078a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c.base@5.1.1 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c.base@5.1.1 new file mode 100644 index 0000000..737078a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c.base@5.1.1 @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..0f904a2 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 0 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 0 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 0 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 0 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 0 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 0 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 0 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 0 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 0 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 0 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 0 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h.base@5.5.2 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h.base@5.5.2 new file mode 100644 index 0000000..4d2f501 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.h.base@5.5.2 @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h new file mode 100644 index 0000000..7584efd --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 1 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..ca85e47 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct new file mode 100644 index 0000000..3412e16 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct @@ -0,0 +1,93 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- Uninitilized RAM Configuration ----------------------- +; Uninitialized RAM Configuration +; Uninitilized RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __NOINIT_SIZE 0x00001000 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - 0x100 - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE) +#define __RW_NOINIT_BASE (__RAM_BASE + __RW_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM_PRIV __RW_BASE EMPTY 0x100 { ; RAM only accessible by privileged code (MPU) + } + + RW_RAM (__RW_BASE + 0x100) __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __NOINIT_SIZE > 0 + RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { ; no init data + *(.bss.noinit*) + } +#endif + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..e1b77e5 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld new file mode 100644 index 0000000..f09c3fe --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/*--------------------- Uninitilized RAM Configuration ----------------------- +; Uninitialized RAM Configuration +; Uninitilized RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +__NOINIT_SIZE = 0x00001000; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - 0x100 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option --section-start or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + . = . + 0x100; /* RAM allowing privileged access only (for showing MemManage fault) */ + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* This section contains data that is not initialized + * during load *or* application reset. + */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + PROVIDE (__noinit_start = .); + *(.noinit*) + . = ALIGN(4); + PROVIDE (__noinit_end = .); + } > RAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..f4a9e24 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option --section-start or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c new file mode 100644 index 0000000..dcc8e1d --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c @@ -0,0 +1,429 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +#include "ARM_Fault.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Fault_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Fault_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Fault_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Fault_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Fault_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Fault Handler + *----------------------------------------------------------------------------*/ +__attribute__((naked)) void Fault_Handler (void) { + __ASM volatile ( + "b ARM_FaultSave\n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..82b8c8a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/cdefault.yml b/Examples/Fault/VHT_MPS2_Cortex-M7/cdefault.yml new file mode 100644 index 0000000..337aeb1 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/cdefault.yml @@ -0,0 +1,26 @@ +default: + + compiler: AC6 + + misc: + - for-compiler: AC6 + C-CPP: + - -ffunction-sections + C: + - -std=gnu11 + ASM: + - -masm=auto + Link: + - --entry=Reset_Handler + - --map + - --info summarysizes + + - for-compiler: GCC + C-CPP: + - -ffunction-sections + C: + - -std=gnu11 + Link: + - --entry=Reset_Handler + - --specs=nano.specs + - -Wl,-Map=$elf()$.map diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/debug.ini b/Examples/Fault/VHT_MPS2_Cortex-M7/debug.ini new file mode 100644 index 0000000..ee437f8 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/debug.ini @@ -0,0 +1 @@ +CORE_CLK=25000000 diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/retarget_stdio.c b/Examples/Fault/VHT_MPS2_Cortex-M7/retarget_stdio.c new file mode 100644 index 0000000..790b547 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/retarget_stdio.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: retarget_stdio.c + * Purpose: Retarget STDIO to USART0 + * + */ + +#include "Driver_USART.h" + +extern int stdio_init (void); +extern int stderr_putchar (int ch); +extern int stdout_putchar (int ch); +extern int stdin_getchar (void); + +#define USART_DRV_NUM 0 +#define USART_BAUDRATE 115200 + +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) + +extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); +#define ptrUSART (&USART_Driver_(USART_DRV_NUM)) + +/** + Initialize stdio + + \return 0 on success, or -1 on error. +*/ +int stdio_init (void) { + + if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1 | + ARM_USART_FLOW_CONTROL_NONE, + USART_BAUDRATE) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { + return -1; + } + + return 0; +} + +/** + Put a character to the stderr + + \param[in] ch Character to output + \return The character written, or -1 on error. +*/ +int stderr_putchar (int ch) { + uint8_t buf[1]; + + buf[0] = (uint8_t)ch; + + if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetTxCount() != 1U); + + return ch; +} + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stdout_putchar (int ch) { + uint8_t buf[1]; + + buf[0] = (uint8_t)ch; + + if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetTxCount() != 1U); + + return ch; +} + +/** + Get a character from the stdio + + \return The next character from the input, or -1 on error. +*/ +int stdin_getchar (void) { + uint8_t buf[1]; + + if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetRxCount() != 1U); + + return (int)buf[0]; +} diff --git a/Examples/Fault/VHT_MPS2_Cortex-M7/vht_config.txt b/Examples/Fault/VHT_MPS2_Cortex-M7/vht_config.txt new file mode 100644 index 0000000..f1ad090 --- /dev/null +++ b/Examples/Fault/VHT_MPS2_Cortex-M7/vht_config.txt @@ -0,0 +1,10 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ diff --git a/Examples/README.md b/Examples/README.md index ce3b9bf..1cb7c23 100644 --- a/Examples/README.md +++ b/Examples/README.md @@ -1,8 +1,23 @@ # Example Projects -These examples show you how to utilize Event Recorder in own application software. All example projects are based on an Arm Cortex-M processors, use the [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox) for project build, and run on [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/overview/html/index.html) processor simulation. +## Event Recorder + +This example shows you how to utilize Event Recorder in own application software. +This example project is based on an Arm Cortex-M processors and uses the [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/cmsis-toolbox) for project build, and runs on [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/overview/html/index.html) processor simulation. Example Project | Description :-----------------------------------------|:-------------------------------- -[**Event Statistic**](./EventStatistic) | Example that shows the usage of start/stop events for statistical code profiling with the Event Statistics window. \ No newline at end of file +[**Event Statistic**](./EventStatistic) | Example that shows the usage of start/stop events for statistical code profiling with the Event Statistics window. + + +## Fault component + +These examples show you how to utilize Fault component in own application software. + + +Example Project | Description +:----------------------------------------------------|:-------------------------------- +[**VHT_MPS2_Cortex-M7**](./Fault/VHT_MPS2_Cortex-M7) | Shows the usage of Fault component on an Cortex-M7. This example runs on [**Arm Virtual Hardware**](https://arm-software.github.io/AVH/main/overview/html/index.html) processor simulation. +[**B-U585I-IOT02A**](./Fault/B-U585I-IOT02A) | Shows the usage of Fault component on an Cortex-M33 with TrustZone. This example runs on [**STMicroelectronics B-U585I-IOT02A**](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) evaluation board. + diff --git a/Fault/ARM_Fault.scvd b/Fault/ARM_Fault.scvd new file mode 100644 index 0000000..41834c3 --- /dev/null +++ b/Fault/ARM_Fault.scvd @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + fault_info_valid = (ARM_FaultInfo.MagicNumber == 0x52746C46); + FaultRegsExist = fault_info_valid && (ARM_FaultInfo.Content & 1); + Armv8xM_Main = fault_info_valid && (ARM_FaultInfo.Content & 2) >> 1; + TZ_Enabled = fault_info_valid && (ARM_FaultInfo.Content & 4) >> 2; + TZ_SaveMode = fault_info_valid && (ARM_FaultInfo.Content & 8) >> 3; + TZ_FaultMode = fault_info_valid && (ARM_FaultInfo.Content & 16) >> 4; + StateContext = fault_info_valid && (ARM_FaultInfo.Content & 32) >> 5; + AdditionalContext = fault_info_valid && (ARM_FaultInfo.Content & 64) >> 6; + LimitRegs = fault_info_valid && (ARM_FaultInfo.Content & 128) >> 7; + FaultRegs = fault_info_valid && (ARM_FaultInfo.Content & 256) >> 8; + SecureFaultRegs = fault_info_valid && (ARM_FaultInfo.Content & 512) >> 9; + RAS_FaultReg = fault_info_valid && (ARM_FaultInfo.Content & 1024) >> 10; + + + + + + + + + + + + + + + + + + + + + + EXC_RETURN = (ARM_FaultInfo.EXC_RETURN); + xPSR_EXC_enum.val = (ARM_FaultInfo.xPSR & 0x000001FF); + EXC_xPSR_EXC_enum.val = (ARM_FaultInfo.EXC_xPSR & 0x000001FF); + TZ_SaveMode_enum.val = (TZ_SaveMode); + TZ_FaultMode_enum.val = (TZ_FaultMode); + CFSR = (FaultRegisters.CFSR); + UFSR = CFSR >> 16; + BFSR = (CFSR & 0xFF00) >> 8; + MMFSR = (CFSR & 0xFF); + HFSR = (FaultRegisters.HFSR); + DFSR = (FaultRegisters.DFSR); + SFSR = (FaultRegisters.SFSR); + RFSR = (FaultRegisters.RFSR); + RFSR_UET.val = (FaultRegisters.RFSR & 3); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Fault/Include/ARM_Fault.h b/Fault/Include/ARM_Fault.h new file mode 100644 index 0000000..52a0c8e --- /dev/null +++ b/Fault/Include/ARM_Fault.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARM_FAULT_H__ +#define ARM_FAULT_H__ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +// Check if Arm architecture is supported +#if ((!defined(__ARM_ARCH_6M__) || (__ARM_ARCH_6M__ == 0)) && \ + (!defined(__ARM_ARCH_7M__) || (__ARM_ARCH_7M__ == 0)) && \ + (!defined(__ARM_ARCH_7EM__) || (__ARM_ARCH_7EM__ == 0)) && \ + (!defined(__ARM_ARCH_8M_BASE__) || (__ARM_ARCH_8M_BASE__ == 0)) && \ + (!defined(__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8M_MAIN__ == 0)) && \ + (!defined(__ARM_ARCH_8_1M_MAIN__) || (__ARM_ARCH_8_1M_MAIN__ == 0)) ) +#error "Unknown or unsupported Arm Architecture!" +#endif + +// Determine if fault registers are available +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) ) +#define ARM_FAULT_FAULT_REGS_EXIST (1) +#else +#define ARM_FAULT_FAULT_REGS_EXIST (0) +#endif + +// Determine if architecture is Armv8/8.1-M +#if ((defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) ) +#define ARM_FAULT_ARCH_ARMV8x_M (1) +#else +#define ARM_FAULT_ARCH_ARMV8x_M (0) +#endif + +// Determine if architecture is Armv8-M Baseline +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) +#define ARM_FAULT_ARCH_ARMV8_M_BASE (1) +#else +#define ARM_FAULT_ARCH_ARMV8_M_BASE (0) +#endif + +// Determine if architecture is Armv8-M Mainline or Armv8.1 Mainline +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) ) +#define ARM_FAULT_ARCH_ARMV8x_M_MAIN (1) +#else +#define ARM_FAULT_ARCH_ARMV8x_M_MAIN (0) +#endif + +// Determine if architecture is Armv8.1-M Mainline +#if (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) +#define ARM_FAULT_ARCH_ARMV8_1M_MAIN (1) +#else +#define ARM_FAULT_ARCH_ARMV8_1M_MAIN (0) +#endif + +// Determine if the code is compiled with Cortex-M Security Extensions enabled +#if defined (__ARM_FEATURE_CMSE) +#define ARM_FAULT_TZ_ENABLED (1) +#else +#define ARM_FAULT_TZ_ENABLED (0) +#endif + +// Determine if the code is compiled for Secure World +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +#define ARM_FAULT_TZ_SECURE (1) +#else +#define ARM_FAULT_TZ_SECURE (0) +#endif + +// Fault component version +#define ARM_FAULT_VERSION "1.0.1" + +// Fault Information structure type version +#define ARM_FAULT_FAULT_INFO_VER_MAJOR (1U) // ARM_FaultInfo type Version.Major +#define ARM_FAULT_FAULT_INFO_VER_MINOR (0U) // ARM_FaultInfo type Version.Minor + +#ifdef __cplusplus +extern "C" { +#endif + +/// Fault information structure type definition +typedef struct { + uint32_t MagicNumber; //!< Magic number (ASCII "FltR") + uint32_t CRC32; //!< CRC32 of the structure content (excluding MagicNumber and CRC32 fields) + uint32_t Count; //!< Saved faults counter + + struct { // Version + uint8_t Minor; //!< Fault information structure version: Minor, see \ref ARM_FAULT_FAULT_INFO_VER_MINOR + uint8_t Major; //!< Fault information structure version: Major, see \ref ARM_FAULT_FAULT_INFO_VER_MAJOR + } Version; + + struct { // Content + // Compile-time information + uint16_t FaultRegsExist : 1; //!< Fault registers: 0 - absent; 1 - available + uint16_t Armv8xM_Main : 1; //!< Armv8/8.1-M Mainline information: 0 - absent; 1 - available + uint16_t TZ_Enabled : 1; //!< TrustZone (Cortex-M security extensions): 0 - not enabled; 1 - enabled + uint16_t TZ_SaveMode : 1; //!< Fault information was saved in: 0 - TrustZone-disabled or non-secure mode; 1 - secure mode + + // Runtime-time information + uint16_t TZ_FaultMode : 1; //!< Fault happened in: 0 - TrustZone-disabled or non-secure mode; 1 - secure mode + uint16_t StateContext : 1; //!< State Context: 0 - was not saved; 1 - was saved + uint16_t AdditionalContext : 1; //!< Additional State Context: 0 - was not saved; 1 - was saved + uint16_t LimitRegs : 1; //!< MSPLIM and PSPLIM: 0 - were not saved; 1 - were saved + uint16_t FaultRegs : 1; //!< Fault registers: 0 - were not saved; 1 - were saved + uint16_t SecureFaultRegs : 1; //!< Secure Fault registers: 0 - were not saved; 1 - were saved + uint16_t RAS_FaultReg : 1; //!< RAS Fault register: 0 - was not saved; 1 - was saved + + uint16_t Reserved : 5; //!< Reserved (0) + } Content; + + struct { // Registers + uint32_t R0; //!< R0 Register value + uint32_t R1; //!< R1 Register value + uint32_t R2; //!< R2 Register value + uint32_t R3; //!< R3 Register value + uint32_t R4; //!< R4 Register value + uint32_t R5; //!< R5 Register value + uint32_t R6; //!< R6 Register value + uint32_t R7; //!< R7 Register value + uint32_t R8; //!< R8 Register value + uint32_t R9; //!< R9 Register value + uint32_t R10; //!< R10 Register value + uint32_t R11; //!< R11 Register value + uint32_t R12; //!< R12 Register value + uint32_t LR; //!< Link Register (R14) value + uint32_t ReturnAddress; //!< Return address from exception + uint32_t xPSR; //!< Program Status Register value + uint32_t MSP; //!< Main Stack Pointer value + uint32_t PSP; //!< Process Stack Pointer value + uint32_t MSPLIM; //!< Main Stack Pointer Limit Register value (only for Armv8/8.1-M arch) + uint32_t PSPLIM; //!< Process Stack Pointer Limit Register value (only for Armv8/8.1-M arch) + } Registers; + + struct { // Exception State + uint32_t xPSR; //!< Program Status Register value, in exception handler + uint32_t EXC_RETURN; //!< Exception Return code (LR), in exception handler + } ExceptionState; + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + struct { // Fault Registers + uint32_t CFSR; //!< System Control Block - Configurable Fault Status Register value + uint32_t HFSR; //!< System Control Block - HardFault Status Register value + uint32_t DFSR; //!< System Control Block - Debug Fault Status Register value + uint32_t MMFAR; //!< System Control Block - MemManage Fault Address Register value + uint32_t BFAR; //!< System Control Block - BusFault Address Register value + uint32_t AFSR; //!< System Control Block - Auxiliary Fault Status Register value + + // Additional Armv8/8.1-M Mainline arch specific fault registers + uint32_t SFSR; //!< System Control Block - Secure Fault Status Register value + uint32_t SFAR; //!< System Control Block - Secure Fault Address Register value + + // Additional Armv8.1-M Mainline arch specific fault register + uint32_t RFSR; //!< System Control Block - RAS Fault Status Register value + } FaultRegisters; +#endif +} ARM_FaultInfo_t; + +// ARM Fault variables --------------------------------------------------------- + +//! Fault component version information +extern const char ARM_FaultVersion[]; + +//! Fault Information +extern ARM_FaultInfo_t ARM_FaultInfo; + +// ARM Fault Storage functions ------------------------------------------------- + +/// \brief Clear the saved fault information. +extern void ARM_FaultClear (void); + +/// \brief Check if the fault occurred and if the fault information was saved properly. +/// \return status (1 = fault occurred and valid fault information exists, +/// 0 = no fault information saved yet or fault information is invalid) +extern uint32_t ARM_FaultOccurred (void); + +/// \brief Save the fault information. +extern void ARM_FaultSave (void); + +/// \brief Callback function called after fault information was saved. +extern void ARM_FaultExit (void); + +// ARM Fault User Code template ------------------------ + +/// \brief Output decoded fault information via STDIO. +extern void ARM_FaultPrint (void); + +// ARM Fault Record function --------------------------------------------------- + +/// \brief Output decoded fault information via Event Recorder. +extern void ARM_FaultRecord (void); + +#ifdef __cplusplus +} +#endif + +#endif /* ARM_FAULT_H__ */ diff --git a/Fault/Source/ARM_FaultRecord.c b/Fault/Source/ARM_FaultRecord.c new file mode 100644 index 0000000..2f46655 --- /dev/null +++ b/Fault/Source/ARM_FaultRecord.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//lint -e46 "Suppress: field type should be _Bool, unsigned int or signed int [MISRA 2012 Rule 6.1, required]" +//lint -e750 "Suppress: local macro not referenced [MISRA 2012 Rule 2.5, advisory]" +//lint -e835 "Suppress: A zero has been given as left argument to operator '+'" +//lint -esym(9058, cmse_address_info) "Suppress: tag 'cmse_address_info' unused outside of typedefs [MISRA 2012 Rule 2.4, advisory]" + +#include "ARM_Fault.h" +#include "EventRecorder.h" + +// ARM Fault component number +#define EvtFault_No 0xEEU // Component number for ARM Fault + +// ARM Fault Event IDs +#define EvtFault_FaultInfo_Invalid EventID(EventLevelOp, EvtFault_No, 0x00U) +#define EvtFault_FaultInfo_NoFaultRegs EventID(EventLevelError, EvtFault_No, 0x01U) +#define EvtFault_HardFault_VECTTBL EventID(EventLevelError, EvtFault_No, 0x03U) +#define EvtFault_HardFault_FORCED EventID(EventLevelError, EvtFault_No, 0x05U) +#define EvtFault_HardFault_DEBUGEVT EventID(EventLevelError, EvtFault_No, 0x07U) +#define EvtFault_MemManage_IACCVIOL EventID(EventLevelError, EvtFault_No, 0x09U) +#define EvtFault_MemManage_DACCVIOL EventID(EventLevelError, EvtFault_No, 0x0DU) +#define EvtFault_MemManage_MUNSTKERR EventID(EventLevelError, EvtFault_No, 0x11U) +#define EvtFault_MemManage_MSTKERR EventID(EventLevelError, EvtFault_No, 0x15U) +#define EvtFault_MemManage_MLSPERR EventID(EventLevelError, EvtFault_No, 0x17U) +#define EvtFault_BusFault_IBUSERR EventID(EventLevelError, EvtFault_No, 0x1BU) +#define EvtFault_BusFault_PRECISERR EventID(EventLevelError, EvtFault_No, 0x1FU) +#define EvtFault_BusFault_IMPRECISERR EventID(EventLevelError, EvtFault_No, 0x23U) +#define EvtFault_BusFault_UNSTKERR EventID(EventLevelError, EvtFault_No, 0x27U) +#define EvtFault_BusFault_STKERR EventID(EventLevelError, EvtFault_No, 0x2BU) +#define EvtFault_BusFault_LSPERR EventID(EventLevelError, EvtFault_No, 0x2DU) +#define EvtFault_UsageFault_UNDEFINSTR EventID(EventLevelError, EvtFault_No, 0x31U) +#define EvtFault_UsageFault_INVSTATE EventID(EventLevelError, EvtFault_No, 0x33U) +#define EvtFault_UsageFault_INVPC EventID(EventLevelError, EvtFault_No, 0x35U) +#define EvtFault_UsageFault_NOCP EventID(EventLevelError, EvtFault_No, 0x37U) +#define EvtFault_UsageFault_STKOF EventID(EventLevelError, EvtFault_No, 0x39U) +#define EvtFault_UsageFault_UNALIGNED EventID(EventLevelError, EvtFault_No, 0x3AU) +#define EvtFault_UsageFault_DIVBYZERO EventID(EventLevelError, EvtFault_No, 0x3CU) +#define EvtFault_SecureFault_INVEP EventID(EventLevelError, EvtFault_No, 0x3EU) +#define EvtFault_SecureFault_INVIS EventID(EventLevelError, EvtFault_No, 0x42U) +#define EvtFault_SecureFault_INVER EventID(EventLevelError, EvtFault_No, 0x46U) +#define EvtFault_SecureFault_AUVIOL EventID(EventLevelError, EvtFault_No, 0x4AU) +#define EvtFault_SecureFault_INVTRAN EventID(EventLevelError, EvtFault_No, 0x4EU) +#define EvtFault_SecureFault_LSPERR EventID(EventLevelError, EvtFault_No, 0x52U) +#define EvtFault_SecureFault_LSERR EventID(EventLevelError, EvtFault_No, 0x56U) +#define EvtFault_RAS_Fault EventID(EventLevelError, EvtFault_No, 0x5AU) +#define EvtFault_TZ_Info EventID(EventLevelOp, EvtFault_No, 0x5CU) + +// Armv8/8.1-M Mainline architecture related defines +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) +#ifndef SAU_SFSR_LSERR_Msk +#define SAU_SFSR_LSERR_Msk (1UL << 7) // SAU SFSR: LSERR Mask +#endif +#ifndef SAU_SFSR_SFARVALID_Msk +#define SAU_SFSR_SFARVALID_Msk (1UL << 6) // SAU SFSR: SFARVALID Mask +#endif +#ifndef SAU_SFSR_LSPERR_Msk +#define SAU_SFSR_LSPERR_Msk (1UL << 5) // SAU SFSR: LSPERR Mask +#endif +#ifndef SAU_SFSR_INVTRAN_Msk +#define SAU_SFSR_INVTRAN_Msk (1UL << 4) // SAU SFSR: INVTRAN Mask +#endif +#ifndef SAU_SFSR_AUVIOL_Msk +#define SAU_SFSR_AUVIOL_Msk (1UL << 3) // SAU SFSR: AUVIOL Mask +#endif +#ifndef SAU_SFSR_INVER_Msk +#define SAU_SFSR_INVER_Msk (1UL << 2) // SAU SFSR: INVER Mask +#endif +#ifndef SAU_SFSR_INVIS_Msk +#define SAU_SFSR_INVIS_Msk (1UL << 1) // SAU SFSR: INVIS Mask +#endif +#ifndef SAU_SFSR_INVEP_Msk +#define SAU_SFSR_INVEP_Msk (1UL) // SAU SFSR: INVEP Mask +#endif +#endif + +// ARM_FaultRecord function ---------------------------------------------------- + +/** + Output decoded fault information via EventRecorder. + Should be called when system is running in normal operating mode with + EventRecorder fully functional. +*/ +void ARM_FaultRecord (void) { + int8_t fault_info_valid; + uint32_t return_address = 0U; + uint32_t evt_id_inc = 0U; + + /* Check if there is available valid fault information */ + fault_info_valid = (int8_t)ARM_FaultOccurred(); + + // Check if state context is valid + if (ARM_FaultInfo.Content.StateContext != 0U) { + return_address = ARM_FaultInfo.Registers.ReturnAddress; + } + + // Output: Message if fault info is invalid + if (fault_info_valid == 0) { + //lint -e845 "Suppress: The right argument to operator '|' is certain to be 0" + (void)EventRecord2(EvtFault_FaultInfo_Invalid, 0U, 0U); + } else { + // Fault information is valid + } + +#if (ARM_FAULT_TZ_ENABLED != 0) // If TrustZone is enabled + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.TZ_Enabled != 0U)) { + (void)EventRecord2(EvtFault_TZ_Info, ARM_FaultInfo.Content.TZ_FaultMode, ARM_FaultInfo.Content.TZ_SaveMode); + } +#endif + +#if (ARM_FAULT_FAULT_REGS_EXIST == 0) // If fault registers do not exist + /* Output: Message if fault registers do not exist */ + if (fault_info_valid != 0) { + if (ARM_FaultInfo.Content.StateContext == 0U) { + evt_id_inc = 0U; + } else { + evt_id_inc = 1U; + } + + (void)EventRecord2(EvtFault_FaultInfo_NoFaultRegs + evt_id_inc, return_address, 0U); + } +#endif + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) // If fault registers exist + /* Output: Decoded HardFault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.FaultRegs != 0U)) { + uint32_t scb_hfsr = ARM_FaultInfo.FaultRegisters.HFSR; + + if ((scb_hfsr & (SCB_HFSR_VECTTBL_Msk | + SCB_HFSR_FORCED_Msk | + SCB_HFSR_DEBUGEVT_Msk )) != 0U) { + + if (ARM_FaultInfo.Content.StateContext == 0U) { + evt_id_inc = 0U; + } else { + evt_id_inc = 1U; + } + + if ((scb_hfsr & SCB_HFSR_VECTTBL_Msk) != 0U) { + (void)EventRecord2(EvtFault_HardFault_VECTTBL + evt_id_inc, return_address, 0U); + } + if ((scb_hfsr & SCB_HFSR_FORCED_Msk) != 0U) { + (void)EventRecord2(EvtFault_HardFault_FORCED + evt_id_inc, return_address, 0U); + } + if ((scb_hfsr & SCB_HFSR_DEBUGEVT_Msk) != 0U) { + (void)EventRecord2(EvtFault_HardFault_DEBUGEVT + evt_id_inc, return_address, 0U); + } + } + } + + /* Output: Decoded MemManage fault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.FaultRegs != 0U)) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_mmfar = ARM_FaultInfo.FaultRegisters.MMFAR; + + if ((scb_cfsr & (SCB_CFSR_IACCVIOL_Msk | + SCB_CFSR_DACCVIOL_Msk | + SCB_CFSR_MUNSTKERR_Msk | +#ifdef SCB_CFSR_MLSPERR_Msk + SCB_CFSR_MLSPERR_Msk | +#endif + SCB_CFSR_MSTKERR_Msk )) != 0U) { + + evt_id_inc = 0U; + if (ARM_FaultInfo.Content.StateContext != 0U) { + evt_id_inc += 1U; + } + if ((scb_cfsr & SCB_CFSR_MMARVALID_Msk) != 0U) { + evt_id_inc += 2U; + } + + if ((scb_cfsr & SCB_CFSR_IACCVIOL_Msk) != 0U) { + (void)EventRecord2(EvtFault_MemManage_IACCVIOL + evt_id_inc, return_address, scb_mmfar); + } + if ((scb_cfsr & SCB_CFSR_DACCVIOL_Msk) != 0U) { + (void)EventRecord2(EvtFault_MemManage_DACCVIOL + evt_id_inc, return_address, scb_mmfar); + } + if ((scb_cfsr & SCB_CFSR_MUNSTKERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_MemManage_MUNSTKERR + evt_id_inc, return_address, scb_mmfar); + } + if ((scb_cfsr & SCB_CFSR_MSTKERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_MemManage_MSTKERR + evt_id_inc, return_address, scb_mmfar); + } +#ifdef SCB_CFSR_MLSPERR_Msk + if ((scb_cfsr & SCB_CFSR_MLSPERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_MemManage_MLSPERR + evt_id_inc, return_address, scb_mmfar); + } +#endif + } + } + + /* Output: Decoded BusFault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.FaultRegs != 0U)) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_bfar = ARM_FaultInfo.FaultRegisters.BFAR; + + if ((scb_cfsr & (SCB_CFSR_IBUSERR_Msk | + SCB_CFSR_PRECISERR_Msk | + SCB_CFSR_IMPRECISERR_Msk | + SCB_CFSR_UNSTKERR_Msk | +#ifdef SCB_CFSR_LSPERR_Msk + SCB_CFSR_LSPERR_Msk | +#endif + SCB_CFSR_STKERR_Msk )) != 0U) { + + evt_id_inc = 0U; + if (ARM_FaultInfo.Content.StateContext != 0U) { + evt_id_inc += 1U; + } + if ((scb_cfsr & SCB_CFSR_BFARVALID_Msk) != 0U) { + evt_id_inc += 2U; + } + + if ((scb_cfsr & SCB_CFSR_IBUSERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_IBUSERR + evt_id_inc, return_address, scb_bfar); + } + if ((scb_cfsr & SCB_CFSR_PRECISERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_PRECISERR + evt_id_inc, return_address, scb_bfar); + } + if ((scb_cfsr & SCB_CFSR_IMPRECISERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_IMPRECISERR + evt_id_inc, return_address, scb_bfar); + } + if ((scb_cfsr & SCB_CFSR_UNSTKERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_UNSTKERR + evt_id_inc, return_address, scb_bfar); + } + if ((scb_cfsr & SCB_CFSR_STKERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_STKERR + evt_id_inc, return_address, scb_bfar); + } +#ifdef SCB_CFSR_LSPERR_Msk + if ((scb_cfsr & SCB_CFSR_LSPERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_BusFault_LSPERR + evt_id_inc, return_address, scb_bfar); + } +#endif + } + } + + /* Output Decoded UsageFault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.FaultRegs != 0U)) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + + if ((scb_cfsr & (SCB_CFSR_UNDEFINSTR_Msk | + SCB_CFSR_INVSTATE_Msk | + SCB_CFSR_INVPC_Msk | + SCB_CFSR_NOCP_Msk | +#ifdef SCB_CFSR_STKOF_Msk + SCB_CFSR_STKOF_Msk | +#endif + SCB_CFSR_UNALIGNED_Msk | + SCB_CFSR_DIVBYZERO_Msk )) != 0U) { + + if (ARM_FaultInfo.Content.StateContext == 0U) { + evt_id_inc = 0U; + } else { + evt_id_inc = 1U; + } + + if ((scb_cfsr & SCB_CFSR_UNDEFINSTR_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_UNDEFINSTR + evt_id_inc, return_address, 0U); + } + if ((scb_cfsr & SCB_CFSR_INVSTATE_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_INVSTATE + evt_id_inc, return_address, 0U); + } + if ((scb_cfsr & SCB_CFSR_INVPC_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_INVPC + evt_id_inc, return_address, 0U); + } + if ((scb_cfsr & SCB_CFSR_NOCP_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_NOCP + evt_id_inc, return_address, 0U); + } +#ifdef SCB_CFSR_STKOF_Msk + if ((scb_cfsr & SCB_CFSR_STKOF_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_STKOF + evt_id_inc, return_address, 0U); + } +#endif + if ((scb_cfsr & SCB_CFSR_UNALIGNED_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_UNALIGNED + evt_id_inc, return_address, 0U); + } + if ((scb_cfsr & SCB_CFSR_DIVBYZERO_Msk) != 0U) { + (void)EventRecord2(EvtFault_UsageFault_DIVBYZERO + evt_id_inc, return_address, 0U); + } + } + } + +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) + /* Output: Decoded SecureFault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.SecureFaultRegs != 0U)) { + uint32_t scb_sfsr = ARM_FaultInfo.FaultRegisters.SFSR; + uint32_t scb_sfar = ARM_FaultInfo.FaultRegisters.SFAR; + + if ((scb_sfsr & (SAU_SFSR_INVEP_Msk | + SAU_SFSR_INVIS_Msk | + SAU_SFSR_INVER_Msk | + SAU_SFSR_AUVIOL_Msk | + SAU_SFSR_INVTRAN_Msk | + SAU_SFSR_LSPERR_Msk | + SAU_SFSR_LSERR_Msk )) != 0U) { + + evt_id_inc = 0U; + if (ARM_FaultInfo.Content.StateContext != 0U) { + evt_id_inc += 1U; + } + if ((scb_sfsr & SAU_SFSR_SFARVALID_Msk) != 0U) { + evt_id_inc += 2U; + } + + if ((scb_sfsr & SAU_SFSR_INVEP_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_INVEP + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_INVIS_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_INVIS + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_INVER_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_INVER + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_AUVIOL_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_AUVIOL + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_INVTRAN_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_INVTRAN + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_LSPERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_LSPERR + evt_id_inc, return_address, scb_sfar); + } + if ((scb_sfsr & SAU_SFSR_LSERR_Msk) != 0U) { + (void)EventRecord2(EvtFault_SecureFault_LSERR + evt_id_inc, return_address, scb_sfar); + } + } + } +#endif + +#if (ARM_FAULT_ARCH_ARMV8_1M_MAIN != 0) + /* Output: RAS Fault information */ + if ((fault_info_valid != 0) && (ARM_FaultInfo.Content.RAS_FaultReg != 0U)) { + uint32_t scb_rfsr = ARM_FaultInfo.FaultRegisters.RFSR; + + if ((scb_rfsr & SCB_RFSR_V_Msk) != 0U) { + + evt_id_inc = 0U; + if (ARM_FaultInfo.Content.StateContext != 0U) { + evt_id_inc += 1U; + } + + (void)EventRecord2(EvtFault_RAS_Fault + evt_id_inc, return_address, scb_rfsr); + } + } +#endif +#endif +} diff --git a/Fault/Source/ARM_FaultStorage.c b/Fault/Source/ARM_FaultStorage.c new file mode 100644 index 0000000..57378ec --- /dev/null +++ b/Fault/Source/ARM_FaultStorage.c @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//lint -e46 "Suppress: field type should be _Bool, unsigned int or signed int [MISRA 2012 Rule 6.1, required]" +//lint -e451 "Suppress: repeatedly included but does not have a standard include guard [MISRA 2012 Directive 4.10, required]" +//lint -e537 "Suppress: Repeated include file 'stddef.h'" +//lint -esym(9058, cmse_address_info) "Suppress: tag 'cmse_address_info' unused outside of typedefs [MISRA 2012 Rule 2.4, advisory]" + +#include "ARM_Fault.h" + +#include +#include + +// Compiler-specific defines +#if !defined(__NAKED) + //lint -esym(9071, __NAKED) "Suppress: defined macro is reserved to the compiler" + #define __NAKED __attribute__((naked)) +#endif +#if !defined(__WEAK) + //lint -esym(9071, __WEAK) "Suppress: defined macro is reserved to the compiler" + #define __WEAK __attribute__((weak)) +#endif +#if !defined(__NO_INIT) + //lint -esym(9071, __NO_INIT) "Suppress: defined macro is reserved to the compiler" + #if defined (__CC_ARM) /* ARM Compiler 4/5 */ + #define __NO_INIT __attribute__ ((section (".bss.noinit.fault"), zero_init)) + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ + #define __NO_INIT __attribute__ ((section (".bss.noinit.fault"))) + #elif defined (__GNUC__) /* GNU Compiler */ + #define __NO_INIT __attribute__ ((section (".noinit.fault"))) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __NO_INIT __attribute__ ((section (".noinit.fault"))) + #else + #warning "No compiler specific solution for __NO_INIT. __NO_INIT is ignored." + #define __NO_INIT + #endif +#endif + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) +// Define CFSR mask for detecting state context stacking failure +#ifndef SCB_CFSR_Stack_Err_Msk +#ifdef SCB_CFSR_STKOF_Msk +#define SCB_CFSR_Stack_Err_Msk (SCB_CFSR_STKERR_Msk | SCB_CFSR_MSTKERR_Msk | SCB_CFSR_STKOF_Msk) +#else +#define SCB_CFSR_Stack_Err_Msk (SCB_CFSR_STKERR_Msk | SCB_CFSR_MSTKERR_Msk) +#endif +#endif +#endif + +// Fault information definitions +#define ARM_FAULT_MAGIC_NUMBER (0x52746C46U) // ARM Fault Magic number (ASCII "FltR") +#define ARM_FAULT_CRC32_INIT_VAL (0xFFFFFFFFU) // ARM Fault CRC-32 initial value +#define ARM_FAULT_CRC32_POLYNOM (0x04C11DB7U) // ARM Fault CRC-32 polynom + +// Fault component version information +const char ARM_FaultVersion[] __USED = ARM_FAULT_VERSION; + +// Fault information +ARM_FaultInfo_t ARM_FaultInfo __USED __NO_INIT; + +// Local function prototype +static uint32_t CalcCRC32 ( uint32_t init_val, + const uint8_t *data_ptr, + uint32_t data_len, + uint32_t polynom); + +// ARM Fault Storage functions ------------------------------------------------- + +/** + Clear the saved fault information. +*/ +void ARM_FaultClear (void) { + memset(&ARM_FaultInfo, 0, sizeof(ARM_FaultInfo)); +} + +/** + Check if the fault occurred and if the fault information was saved properly. + \return status (1 = fault occurred and valid fault information exists, + 0 = no fault information saved yet or fault information is invalid) +*/ +uint32_t ARM_FaultOccurred (void) { + uint32_t fault_info_valid = 1U; + + // Check if magic number is valid + if (ARM_FaultInfo.MagicNumber != ARM_FAULT_MAGIC_NUMBER) { + fault_info_valid = 0U; + } + + // Check if CRC of the ARM_FaultInfo structure is valid + if (fault_info_valid != 0U) { + if (ARM_FaultInfo.CRC32 != CalcCRC32(ARM_FAULT_CRC32_INIT_VAL, + (const uint8_t *)&ARM_FaultInfo.Count, + (sizeof(ARM_FaultInfo) - (sizeof(ARM_FaultInfo.MagicNumber) + sizeof(ARM_FaultInfo.CRC32))), + ARM_FAULT_CRC32_POLYNOM)) { + fault_info_valid = 0U; + } + } + + return fault_info_valid; +} + +/** + Save the fault information. + Must be called from fault handler with preserved Link Register value and unchanged + Stack Pointer, typically by branching to this function. +*/ +__NAKED void ARM_FaultSave (void) { + //lint -efunc(10, ARM_FaultSave) "Suppress: expecting ';'" + //lint -efunc(522, ARM_FaultSave) "Suppress: Warning 522: Highest operation, a 'constant', lacks side-effects [MISRA 2012 Rule 2.2, required]" + + /* This function contains 3 ASM blocks because of the GCC limitation that the 'asm' supports up to 30 operands. + Also there is ARM Compiler 6 warning if string literal exceeds maximum length 4095 that ISO C99 compilers are required to support. */ + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n" +#endif + + /* --- Handle ARM_FaultInfo.Count value --- */ + /* If MagicNumber is valid then read the Count value, otherwise clear it */ + "ldr r0, =%c[MagicNumber_addr]\n" // Load MagicNumber address + "ldr r0, [r0]\n" // Load MagicNumber value + "ldr r1, =%c[MagicNumber_val]\n" // Load MagicNumber valid value + "movs r3, #0\n" // R3 = 0 + "cmp r0, r1\n" // Compare MagicNumber from memory to valid value + "bne count_done\n" // If MagicNumber is different than valid value, reset Count value to 0 + // Otherwise + "ldr r2, =%c[Count_addr]\n" // Load Count address + "ldr r3, [r2]\n" // Load Count value + "count_done:\n" + + /* --- Clear ARM_FaultInfo structure --- */ + "movs r0, #0\n" // R0 = 0 + "ldr r1, =%c[ARM_FaultInfo_addr]\n" // R1 = &ARM_FaultInfo + "movs r2, %[ARM_FaultInfo_size]\n" // R2 = sizeof(ARM_FaultInfo)/4 + "b clr_done\n" + "clr_loop:\n" + "stm r1!, {r0}\n" + "subs r2, r2, #1\n" + "clr_done:\n" + "bne clr_loop\n" + + /* --- Increment and store new ARM_FaultInfo.Count value --- */ + "ldr r2, =%c[Count_addr]\n" // Load Count address + "adds r3, r3, #1\n" // Increment Count value + "stm r2!, {r3}\n" // Store new Count value + + /* --- Store ARM_FaultInfo.Version --- */ + // R2 = &ARM_FaultInfo.Version + "ldr r0, =%c[Version_val]\n" // Load Version constant + "strh r0, [r2]\n" // Store Version value + + /* --- Store ARM_FaultInfo.Content compile-time information --- */ + "adds r2, #2\n" // R2 = &ARM_FaultInfo.Content + "ldr r0, =%c[Content_val]\n" // Load Content compile-time constant + "strh r0, [r2]\n" // Store Content value + + /* --- Store current values of registers R4 .. R11 into ARM_FaultInfo --- */ + /* After R4 .. R11 are stored they can be used in the code since they will be restored at the end of this function */ + "ldr r2, =%c[R4_addr]\n" // R2 = &ARM_FaultInfo.Registers.R4 + "stm r2!, {r4-r7}\n" // Store R4 .. R7 + "mov r4, r8\n" // R4 = R8 + "mov r5, r9\n" // R5 = R9 + "mov r6, r10\n" // R6 = R10 + "mov r7, r11\n" // R7 = R11 + "stm r2!, {r4-r7}\n" // Store R8 .. R11 + + /* Use R4 from here on as a pointer to ARM_FaultInfo */ + "ldr r4, =%c[ARM_FaultInfo_addr]\n" // R4 = &ARM_FaultInfo + + /* --- Determine stack used, and for TrustZone devices Secure or Non-Secure registers used --- */ + + /* Determine the beginning of the state context or the additional state context + (for device with TruztZone) that was stacked upon exception entry and put that + address into R6 register. + For device with TrustZone, also determine if state context was pushed from + Non-Secure World but the exception handling is happening in the Secure World + and if so, mark it by setting bit [0] of the R7 register to value 1, thus indicating + usage of Non-Secure aliases. + + after this section: + R6 == start of state context or additional state context if that was pushed also + R7 bit [0]: == 0 - no access to Non-Secure aliases or device without TrustZone + == 1 - access to Non-Secure aliases + + Determination is done by analyzing EXC_RETURN (Link Register): + EXC_RETURN: + - bit [6] (S): only on device with TrustZone + == 0 - Non-Secure stack was used + == 1 - Secure stack was used + - bit [5] (DCRS): only on device with TrustZone + == 0 - additional state context was also stacked + == 1 - only basic state context was stacked + - bit [2] (SPSEL): == 0 - Main Stack Pointer (MSP) was used for stacking on exception entry + == 1 - Process Stack Pointer (PSP) was used for stacking on exception entry */ + "movs r7, #0\n" // R7 = 0 + + "mov r0, lr\n" // R0 = LR (EXC_RETURN) + "lsrs r0, r0, #3\n" // Shift bit [2] (SPSEL) into Carry flag + "bcc msp_used\n" // If bit [2] (SPSEL) == 0, MSP or MSP_NS was used + // If bit [2] (SPSEL) == 1, PSP or PSP_NS was used + "psp_used:\n" +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "mov r0, lr\n" // R0 = LR (EXC_RETURN) + "lsrs r0, r0, #7\n" // Shift bit [6] (S) into Carry flag + "bcs load_psp\n" // If bit [6] (S) == 1, jump to load PSP + "load_psp_ns:\n" // else if bit [6] (S) == 0, load PSP_NS + "mrs r6, psp_ns\n" // R6 = PSP_NS + "movs r7, #1\n" // R7 = 1 + "b sp_loaded\n" // PSP_NS loaded to R6, exit section + "load_psp:\n" +#endif + "mrs r6, psp\n" // R6 = PSP + "b sp_loaded\n" // PSP loaded to R6, exit section + + "msp_used:\n" +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "mov r0, lr\n" // R0 = LR (EXC_RETURN) + "lsrs r0, r0, #7\n" // Shift bit [6] (S) into Carry flag + "bcs load_msp\n" // If bit [6] (S) == 1, jump to load MSP + "load_msp_ns:\n" // else if bit [6] (S) == 0, load MSP_NS + "mrs r6, msp_ns\n" // R6 = MSP_NS + "movs r7, #1\n" // R7 = 1 + "b sp_loaded\n" // MSP_NS loaded to R6, exit section + "load_msp:\n" +#endif + "mrs r6, msp\n" // R6 = MSP + "b sp_loaded\n" // MSP loaded to R6, exit section + + "sp_loaded:\n" // Stack Pointer is loaded to R6 + + /* Set ARM_FaultInfo.Content.TZ_FaultMode to 1 if the fault happened in the Secure World --- */ +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "lsrs r0, r7, #1\n" // Shift bit [0] of R7 into Carry flag + "bcs tz_fault_mode_end\n" // If bit [0] of R7 == 1, do not set TZ_FaultMode bit + "set_tz_fault_mode:\n" // else if bit [0] of R7 == 0, set TZ_FaultMode bit + + /* Set ARM_FaultInfo.Content.TZ_FaultMode to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "movs r1, %[TZ_FaultMode_bit]\n" // Load TZ_FaultMode bit value + "orrs r0, r1\n" // OR TZ_FaultMode bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back + + "tz_fault_mode_end:\n" +#endif + + /* --- Determine stack validity --- */ + + /* Determine if stack is valid. + If stack pointer value is 4-byte aligned and if no stacking fault has occurred. + If stack information is not valid then mark it by setting bit [1] of the R7 to value 1. + Note: for Armv6-M and Armv8-M Baseline CFSR register is not available, so stack is + considered valid although it might not always be so. */ + "movs r0, #3\n" + "ands r0, r6\n" // Mask low 2 bits of stack pointer (they must be 0 for 4-byte aligned address) + "beq check_cfsr\n" // If stack pointer is 4-byte aligned, branch to check CFSR register flags + "stack_pointer_is_zero:\n" // else if stack pointer is not 4-byte aligned, stack information is invalid + "adds r7, #2\n" // R7 |= (1 << 1) + "b stack_check_end\n" // Exit stack checking + "check_cfsr:\n" +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) // If fault registers exist +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "lsrs r0, r7, #1\n" // Shift bit [0] of R7 into Carry flag + "bcc load_cfsr_addr\n" // If bit [0] of R7 == 0, jump to load CFSR register address + "load_cfsr_ns_addr:\n" // else if bit [0] of R7 == 1, load CFSR_NS register address + "ldr r2, =%c[CFSR_NS_addr]\n" // R2 = CFSR_NS address + "b load_cfsr_val\n" + "load_cfsr_addr:\n" +#endif + "ldr r2, =%c[CFSR_addr]\n" // R2 = CFSR address + "load_cfsr_val:\n" + "ldr r0, [r2]\n" // R0 = CFSR (or CFSR_NS) register value + "ldr r1, =%c[CFSR_err_msk]\n" // R1 = SCB_CFSR_Stack_Err_Msk + "tst r0, r1\n" // Test if CFSR value has any of the stacking error bits set + "it ne\n" // If any of the stacking error bits is set + "orrne r7, #2\n" // Then R7 |= (1 << 1) +#endif + "stack_check_end:\n" + + /* --- Store stacked context into ARM_FaultInfo (R0 .. R3, R12 .. xPSR; R4 .. R11 only if additional state context was stacked) --- */ + + /* Check if state context (also additional state context if it exists (on TrustZone only)) is valid and + if it is then copy it into ARM_FaultInfo */ + "lsrs r0, r7, #2\n" // Shift bit [1] of R7 into Carry flag + "bcs state_context_end\n" // If stack is not valid (bit [1] == 1), skip copying information from stack + +#if (ARM_FAULT_ARCH_ARMV8x_M != 0) // If arch is Armv8/8.1-M + /* If additional state context was stacked upon exception entry, copy R4 .. R11 into ARM_FaultInfo */ + /* Content of additional state context on stack is: + Integrity signature, Reserved, R4, R5, R6, R7, R8, R9, R10, R11 */ + "mov r0, lr\n" // R0 = LR (EXC_RETURN) + "lsrs r0, r0, #6\n" // Shift bit [5] (DCRS) into Carry flag + "bcs additional_context_end\n" // If bit [5] (DCRS) == 1, skip additional state context + // else if bit [5] (DCRS) == 0, copy additional state context + "adds r6, #8\n" // Skip Integrity signature and Reserved as they will not be stored + "ldr r5, =%c[R4_addr]\n" // Load R4 address + "ldm r6!, {r0-r3}\n" // Load stacked R4 .. R7 + "stm r5!, {r0-r3}\n" // Store R4 .. R7 + "ldm r6!, {r0-r3}\n" // Load stacked R8 .. R11 + "stm r5!, {r0-r3}\n" // Store R8 .. R11 + + /* Set ARM_FaultInfo.Content.AdditionalContext to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "movs r1, %[AdditionalContext_bit]\n" // Load AdditionalContext bit value + "orrs r0, r1\n" // OR AdditionalContext bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back + + "additional_context_end:\n" +#endif + + /* Copy state context stacked upon exception entry into ARM_FaultInfo */ + /* Content of state context (Basic Stack Frame) on stack is: + R0, R1, R2, R3, R12, LR (R14), ReturnAddress, xPSR */ + "ldr r5, =%c[R0_addr]\n" // Load R0 address + "ldm r6!, {r0-r3}\n" // Load stacked R0 .. R3 + "stm r5!, {r0-r3}\n" // Store R0 .. R3 + "ldr r5, =%c[R12_addr]\n" // Load R12 address + "ldm r6!, {r0-r3}\n" // Load stacked R12 .. xPSR + "stm r5!, {r0-r3}\n" // Store R12 .. xPSR + + /* Set ARM_FaultInfo.Content.StateContext to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "movs r1, %[StateContext_bit]\n" // Load StateContext bit value + "orrs r0, r1\n" // OR StateContext bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back + + "state_context_end:\n" + + /* --- Store MSP and PSP into ARM_FaultInfo --- */ +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "lsrs r0, r7, #1\n" // Shift bit [0] of R7 into Carry flag + "bcc load_sps\n" // If bit [0] of R7 == 0, jump to load MSP and PSP + "load_sps_ns:\n" // else if bit [0] of R7 == 1, load MSP_NS and PSP_NS + "mrs r0, msp_ns\n" // R0 = current MSP_NS + "mrs r1, psp_ns\n" // R1 = current PSP_NS + "b store_regs\n" +#endif + "load_sps:\n" + "mrs r0, msp\n" // R0 = current MSP + "mrs r1, psp\n" // R1 = current PSP + "store_regs:\n" + "ldr r5, =%c[MSP_addr]\n" // Load MSP address + "stm r5!, {r0-r1}\n" // Store MSP and PSP + + /* --- Store MSPLIM and PSPLIM (if they are available) into ARM_FaultInfo --- */ + /* Armv8-M Baseline does not have MSPLIM_NS and PSPLIM_NS */ +#if (ARM_FAULT_ARCH_ARMV8x_M != 0) // If arch is Armv8/8.1-M +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "lsrs r0, r7, #1\n" // Shift bit [0] of R7 into Carry flag + "bcc load_splims\n" // If bit [0] of R7 == 0, jump to load MSPLIM and PSPLIM +#if (ARM_FAULT_ARCH_ARMV8_M_BASE != 0) // If arch is Armv8-M Baseline + "b splims_end\n" // MSPLIM_NS and PSPLIM_NS do not exist, skip storing them +#else // Else if arch is Armv8/8.1-M Mainline + "load_splims_ns:\n" // else if bit [0] of R7 == 1, load MSPLIM_NS and PSPLIM_NS + "mrs r0, msplim_ns\n" // R0 = current MSPLIM_NS + "mrs r1, psplim_ns\n" // R1 = current PSPLIM_NS + "b store_splims\n" +#endif +#endif + "load_splims:\n" + "mrs r0, msplim\n" // R0 = current MSPLIM + "mrs r1, psplim\n" // R1 = current PSPLIM + "store_splims:\n" + "stm r5!, {r0, r1}\n" // Store MSPLIM (or MSPLIM_NS) and PSPLIM (or PSPLIM_NS) + + /* Set ARM_FaultInfo.Content.LimitRegs to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "movs r1, %[LimitRegs_bit]\n" // Load LimitRegs bit value + "orrs r0, r1\n" // OR LimitRegs bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back + + "splims_end:\n" +#endif + + /* --- Store ExceptionState xPSR and EXC_RETURN into ARM_FaultInfo --- */ + "ldr r5, =%c[ExceptionState_addr]\n" // Load ExceptionState address + "mrs r0, xpsr\n" // R0 = current xPSR + "mov r1, lr\n" // R1 = current LR (exception return code) + "stm r5!, {r0, r1}\n" // Store xPSR and EXC_RETURN + + /* Inline assembly template operands */ + : /* no outputs */ + : /* inputs */ + [ARM_FaultInfo_addr] "i" (&ARM_FaultInfo) + , [ARM_FaultInfo_size] "i" (sizeof(ARM_FaultInfo)/4) + , [MagicNumber_addr] "i" (&ARM_FaultInfo.MagicNumber) + , [MagicNumber_val] "i" (ARM_FAULT_MAGIC_NUMBER) + , [Count_addr] "i" (&ARM_FaultInfo.Count) + , [Version_addr] "i" (&ARM_FaultInfo.Version) + , [Version_val] "i" (ARM_FAULT_FAULT_INFO_VER_MINOR + | (ARM_FAULT_FAULT_INFO_VER_MAJOR << 8)) + , [Content_ofs] "i" (offsetof(ARM_FaultInfo_t, Content)) + , [Content_val] "i" ((ARM_FAULT_FAULT_REGS_EXIST ) + | (ARM_FAULT_ARCH_ARMV8x_M_MAIN << 1) + | (ARM_FAULT_TZ_ENABLED << 2) + | (ARM_FAULT_TZ_SECURE << 3)) + , [TZ_FaultMode_bit] "i" (1U << 4) + , [StateContext_bit] "i" (1U << 5) + , [AdditionalContext_bit] "i" (1U << 6) + , [LimitRegs_bit] "i" (1U << 7) + , [R0_addr] "i" (&ARM_FaultInfo.Registers.R0) + , [R4_addr] "i" (&ARM_FaultInfo.Registers.R4) + , [R12_addr] "i" (&ARM_FaultInfo.Registers.R12) + , [MSP_addr] "i" (&ARM_FaultInfo.Registers.MSP) + , [ExceptionState_addr] "i" (&ARM_FaultInfo.ExceptionState) +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + , [CFSR_err_msk] "i" (SCB_CFSR_Stack_Err_Msk) + , [CFSR_addr] "i" (SCB_BASE + offsetof(SCB_Type, CFSR)) +#if (ARM_FAULT_TZ_SECURE != 0) + , [CFSR_NS_addr] "i" (SCB_BASE_NS + offsetof(SCB_Type, CFSR)) +#endif +#endif + : /* clobber list */ + "r0", "r1", "r2", "r3", "cc", "memory"); + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) // If fault registers exist + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n" +#endif + + /* --- Store Fault Registers (if they are available) into ARM_FaultInfo --- */ +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "lsrs r0, r7, #1\n" // Shift bit [0] of R7 into Carry flag + "bcc load_scb_addr\n" // If bit [0] of R7 == 0, jump to load SCB BASE address + "load_scb_ns_addr:\n" // else if bit [0] of R7 == 1, load SCB_NS BASE address + "ldr r6, =%c[SCB_NS_base_addr]\n" // Load SCB_NS BASE address + "b load_fault_regs\n" + "load_scb_addr:\n" +#endif + "ldr r6, =%c[SCB_base_addr]\n" // Load SCB BASE address + "load_fault_regs:\n" + "ldr r5, =%c[FaultRegisters_addr]\n" // Load FaultRegisters start address in ARM_FaultInfo + "ldr r0, [r6, %[CFSR_ofs]]\n" // R0 = SCB_CFSR + "ldr r1, [r6, %[HFSR_ofs]]\n" // R1 = SCB_HFSR + "ldr r2, [r6, %[DFSR_ofs]]\n" // R2 = SCB_DFSR + "ldr r3, [r6, %[MMFAR_ofs]]\n" // R3 = SCB_MMFAR + "stm r5!, {r0-r3}\n" // Store CFSR, HFSR, DFSR and MMFAR + "ldr r0, [r6, %[BFAR_ofs]]\n" // R0 = SCB_BFSR + "ldr r1, [r6, %[AFSR_ofs]]\n" // R1 = SCB_AFSR + "stm r5!, {r0, r1}\n" // Store BFSR and AFSR + + /* Set ARM_FaultInfo.Content.FaultRegs to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "orrs r0, %[FaultRegs_bit]\n" // OR FaultRegs bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back + + /* --- Armv8.1-M Mainline RAS Fault Status Register (RFSR) --- */ +#if (ARM_FAULT_ARCH_ARMV8_1M_MAIN != 0) // If arch is Armv8.1-M Mainline + "ldr r5, =%c[RFSR_reg_addr]\n" // Load address of RFSR register in ARM_FaultInfo + "ldr r0, [r6, %[RFSR_ofs]]\n" // R0 = SCB_RFSR + "str r0, [r5]\n" // Store RFSR + + /* Set ARM_FaultInfo.Content.RAS_FaultReg to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "orrs r0, %[RAS_FaultReg_bit]\n" // OR RAS_FaultReg bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back +#endif + + /* --- Armv8/8.1-M Mainline Fault Registers --- */ + /* Store values of Armv8/8.1-M Fault Registers (Mainline only) if code is running in Secure World into ARM_FaultInfo */ +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) // If arch is Armv8-M Mainline +#if (ARM_FAULT_TZ_SECURE != 0) // If code was compiled for and is running in Secure World + "ldr r5, =%c[SFSR_reg_addr]\n" // Load address of SFSR register in ARM_FaultInfo + "ldr r6, =%c[SCB_base_addr]\n" // Load SCB BASE address + "ldr r0, [r6, %[SFSR_ofs]]\n" // R0 = SFSR + "ldr r1, [r6, %[SFAR_ofs]]\n" // R1 = SFAR + "stm r5!, {r0, r1}\n" // Store SFSR and SFAR + + /* Set ARM_FaultInfo.Content.SecureFaultRegs to 1 --- */ + "ldrh r0, [r4, %[Content_ofs]]\n" // Load Content value + "orrs r0, %[SecureFaultRegs_bit]\n" // OR SecureFaultRegs bit with Content + "strh r0, [r4, %[Content_ofs]]\n" // Store updated Content value back +#endif +#endif + + /* Inline assembly template operands */ + : /* no outputs */ + : /* inputs */ + [Content_ofs] "i" (offsetof(ARM_FaultInfo_t, Content)) + , [FaultRegs_bit] "i" (1U << 8) + , [SecureFaultRegs_bit] "i" (1U << 9) + , [RAS_FaultReg_bit] "i" (1U << 10) +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + , [FaultRegisters_addr] "i" (&ARM_FaultInfo.FaultRegisters) + , [SCB_base_addr] "i" (SCB_BASE) + , [CFSR_ofs] "i" (offsetof(SCB_Type, CFSR )) + , [HFSR_ofs] "i" (offsetof(SCB_Type, HFSR )) + , [DFSR_ofs] "i" (offsetof(SCB_Type, DFSR )) + , [MMFAR_ofs] "i" (offsetof(SCB_Type, MMFAR)) + , [BFAR_ofs] "i" (offsetof(SCB_Type, BFAR )) + , [AFSR_ofs] "i" (offsetof(SCB_Type, AFSR )) +#if (ARM_FAULT_TZ_SECURE != 0) + , [SCB_NS_base_addr] "i" (SCB_BASE_NS) +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) + , [SFSR_reg_addr] "i" (&ARM_FaultInfo.FaultRegisters.SFSR) + , [SFSR_ofs] "i" (offsetof(SCB_Type, SFSR )) + , [SFAR_ofs] "i" (offsetof(SCB_Type, SFAR )) +#endif +#endif +#if (ARM_FAULT_ARCH_ARMV8_1M_MAIN != 0) + , [RFSR_reg_addr] "i" (&ARM_FaultInfo.FaultRegisters.RFSR) + , [RFSR_ofs] "i" (offsetof(SCB_Type, RFSR )) +#endif +#endif + : /* clobber list */ + "r0", "r1", "r2", "r3", "cc", "memory"); +#endif + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n" +#endif + + /* --- Calculate and store CRC-32 value into ARM_FaultInfo.CRC32 --- */ + /* Calculate CRC-32 on ARM_FaultInfo structure (excluding MagicNumber and CRC32 fields) and + store it into ARM_FaultInfo.CRC32 */ + "ldr r0, =%c[crc_init_val]\n" // R0 = init_val parameter + "ldr r1, =%c[crc_data_ptr]\n" // R1 = data_ptr parameter + "ldr r2, =%c[crc_data_len]\n" // R2 = data_len parameter + "ldr r3, =%c[crc_polynom]\n" // R3 = polynom parameter + + /* Calculate CRC-32 with result provided in R0 register */ + "b crc_check\n" + "crc_wloop:\n" + "ldrb r5, [r1,#0]\n" + "lsls r5, r5, #24\n" + "eors r0, r0, r5\n" + "movs r4, #8\n" + "crc_floop:\n" + "lsls r0, r0, #1\n" + "bcc crc_next\n" + "eors r0, r0, r3\n" + "crc_next:\n" + "subs r4, r4, #1\n" + "bne crc_floop\n" + "adds r1, r1, #1\n" + "subs r2, r2, #1\n" + "crc_check:\n" + "cmp r2, #0\n" + "bne crc_wloop\n" + + /* Use R4 from here on as pointer to ARM_FaultInfo */ + "ldr r4, =%c[ARM_FaultInfo_addr]\n" // R4 = &ARM_FaultInfo + + "str r0, [r4,%[CRC32_ofs]]\n" // Store CRC32 value + + /* --- Store ARM_FaultInfo.magic_number --- */ + "ldr r0, =%c[MagicNumber_val]\n" // Load MagicNumber constant + "str r0, [r4, %[MagicNumber_ofs]]\n" // Store CRC32 value + + "dsb\n" // Ensure content of ARM_FaultInfo is up-to-date + + /* Restore registers R4 .. R7 */ + "ldr r0, =%c[R4_addr]\n" + "ldm r0!, {r4-r7}\n" + + /* If additional state information is available then clear the R4 .. R7 */ +#if (ARM_FAULT_ARCH_ARMV8x_M != 0) // If arch is Armv8/8.1-M + "ldr r0, =%c[Content_addr]\n" // Load Content address + "ldrh r0, [r0]\n" // Load Content value + "movs r1, %[AdditionalContext_bit]\n" // Load AdditionalContext bit + "ands r0, r1\n" // AND Content with AdditionalContext bit to determine if additional state context was saved + "beq restore_regs_done\n" // If additional state context was not saved, do not clear R4 .. R7 and exit section + "movs r4, #0\n" // Else if additional state context was saved, clear R4 .. R7 + "movs r5, #0\n" + "movs r6, #0\n" + "movs r7, #0\n" +#endif + "restore_regs_done:\n" + + /* Jump to ARM_FaultExit function */ + "ldr r0, =ARM_FaultExit\n" + "mov pc, r0\n" + + /* Inline assembly template operands */ + : /* no outputs */ + : /* inputs */ + [ARM_FaultInfo_addr] "i" (&ARM_FaultInfo) + , [MagicNumber_ofs] "i" (offsetof(ARM_FaultInfo_t, MagicNumber)) + , [MagicNumber_val] "i" (ARM_FAULT_MAGIC_NUMBER) + , [CRC32_ofs] "i" (offsetof(ARM_FaultInfo_t, CRC32)) + , [Content_addr] "i" (&ARM_FaultInfo.Content) + , [AdditionalContext_bit] "i" (1U << 6) + , [R4_addr] "i" (&ARM_FaultInfo.Registers.R4) + , [crc_init_val] "i" (ARM_FAULT_CRC32_INIT_VAL) + , [crc_data_ptr] "i" (&ARM_FaultInfo.Count) + , [crc_data_len] "i" (sizeof(ARM_FaultInfo) - (sizeof(ARM_FaultInfo.MagicNumber) + sizeof(ARM_FaultInfo.CRC32))) + , [crc_polynom] "i" (ARM_FAULT_CRC32_POLYNOM) + : /* clobber list */ + "r0", "r1", "r2", "r3", "cc", "memory"); +} + +/** + Callback function called after fault information was saved. + Used to provide a specific reaction to fault after it was saved. + The default implementation will RESET the system. + User can override this function to provide desired reaction. + It is preferred that user implemented function would not use stack + since it that could cause another fault. +*/ +__WEAK __NAKED void ARM_FaultExit (void) { + //lint -efunc(10, ARM_FaultExit) "Suppress: expecting ';'" + //lint -efunc(522, ARM_FaultExit) "Suppress: Warning 522: Highest operation, a 'constant', lacks side-effects [MISRA 2012 Rule 2.2, required]" + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n" +#endif + + "dsb\n" + "ldr r0, =%c[aircr_addr]\n" + "ldr r1, =%c[aircr_val]\n" +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + "ldr r2, =%c[aircr_msk]\n" + "ldr r3, [r0]\n" + "ands r3, r2\n" + "orrs r1, r3\n" +#endif + "str r1, [r0]\n" + "dsb\n" + "b .\n" + + : /* no outputs */ + : /* inputs */ + [aircr_addr] "i" (SCB_BASE + offsetof(SCB_Type, AIRCR)) + , [aircr_val] "i" ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk) +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + , [aircr_msk] "i" (SCB_AIRCR_PRIGROUP_Msk) +#endif + : /* clobber list */ + "r0", "r1", "r2", "r3", "cc", "memory"); +} + + +// Helper function + +/** + Calculate CRC-32 on data block in memory + \param[in] init_val initial CRC value + \param[in] data_ptr pointer to data + \param[in] data_len data length (in bytes) + \param[in] polynom CRC polynom + \return CRC-32 value (32-bit) +*/ +static uint32_t CalcCRC32 ( uint32_t init_val, + const uint8_t *data_ptr, + uint32_t data_len, + uint32_t polynom) { + uint32_t crc32, i; + + crc32 = init_val; + while (data_len != 0U) { + crc32 ^= ((uint32_t)*data_ptr) << 24; + for (i = 8U; i != 0U; i--) { + if ((crc32 & 0x80000000U) != 0U) { + crc32 <<= 1; + crc32 ^= polynom; + } else { + crc32 <<= 1; + } + } + data_ptr++; + data_len--; + } + + return crc32; +} diff --git a/Fault/Template/ARM_FaultPrint.c b/Fault/Template/ARM_FaultPrint.c new file mode 100644 index 0000000..845451e --- /dev/null +++ b/Fault/Template/ARM_FaultPrint.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARM_Fault.h" + +#include + +// General defines +#ifndef EXC_RETURN_SPSEL +#define EXC_RETURN_SPSEL (1UL << 2) +#endif + +// Armv8/8.1-M Mainline architecture related defines +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) +#ifndef SAU_SFSR_LSERR_Msk +#define SAU_SFSR_LSERR_Msk (1UL << 7) // SAU SFSR: LSERR Mask +#endif +#ifndef SAU_SFSR_SFARVALID_Msk +#define SAU_SFSR_SFARVALID_Msk (1UL << 6) // SAU SFSR: SFARVALID Mask +#endif +#ifndef SAU_SFSR_LSPERR_Msk +#define SAU_SFSR_LSPERR_Msk (1UL << 5) // SAU SFSR: LSPERR Mask +#endif +#ifndef SAU_SFSR_INVTRAN_Msk +#define SAU_SFSR_INVTRAN_Msk (1UL << 4) // SAU SFSR: INVTRAN Mask +#endif +#ifndef SAU_SFSR_AUVIOL_Msk +#define SAU_SFSR_AUVIOL_Msk (1UL << 3) // SAU SFSR: AUVIOL Mask +#endif +#ifndef SAU_SFSR_INVER_Msk +#define SAU_SFSR_INVER_Msk (1UL << 2) // SAU SFSR: INVER Mask +#endif +#ifndef SAU_SFSR_INVIS_Msk +#define SAU_SFSR_INVIS_Msk (1UL << 1) // SAU SFSR: INVIS Mask +#endif +#ifndef SAU_SFSR_INVEP_Msk +#define SAU_SFSR_INVEP_Msk (1UL) // SAU SFSR: INVEP Mask +#endif +#endif + +// ARM_FaultPrint function ----------------------------------------------------- + +/** + Output decoded fault information via STDIO. + Should be called when system is running in normal operating mode with + standard input/output fully functional. +*/ +void ARM_FaultPrint (void) { + int8_t fault_info_valid; + + /* Check if there is available valid fault information */ + fault_info_valid = (int8_t)ARM_FaultOccurred(); + + // Output: Header and version information + printf("\n --- Fault (v%s) ---\n\n", (const char *)ARM_FaultVersion); + + // Output: Message if fault info is invalid + if (fault_info_valid == 0) { + printf("\n No fault saved yet or fault information is invalid!\n\n"); + return; + } + + // Output: Fault count + printf(" Fault count: %u\n\n", (unsigned int)ARM_FaultInfo.Count); + + // Output: Exception which saved the fault information + printf(" Exception Handler: "); + + if (ARM_FaultInfo.Content.TZ_Enabled != 0U) { + if (ARM_FaultInfo.Content.TZ_SaveMode != 0U) { + printf("Secure - "); + } else { + printf("Non-Secure - "); + } + } + + switch (ARM_FaultInfo.ExceptionState.xPSR & IPSR_ISR_Msk) { + case 3: + printf("HardFault"); + break; + case 4: + printf("MemManage fault"); + break; + case 5: + printf("BusFault"); + break; + case 6: + printf("UsageFault"); + break; + case 7: + printf("SecureFault"); + break; + default: + printf("unknown, exception number = %u", (unsigned int)(ARM_FaultInfo.ExceptionState.xPSR & IPSR_ISR_Msk)); + break; + } + printf("\n"); + +#if (ARM_FAULT_ARCH_ARMV8x_M != 0) + // Output: state in which the fault occurred + if (ARM_FaultInfo.Content.TZ_Enabled != 0U) { + printf(" State: "); + + if (ARM_FaultInfo.Content.TZ_FaultMode != 0U) { + printf("Secure"); + } else { + printf("Non-Secure"); + } + printf("\n"); + } +#endif + + // Output: Mode in which the fault occurred + printf(" Mode: "); + + if ((ARM_FaultInfo.ExceptionState.EXC_RETURN & EXC_RETURN_SPSEL) == 0U) { + printf("Handler"); + } else { + printf("Thread"); + } + printf("\n"); + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) // If fault registers exist + /* Output: Decoded HardFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_hfsr = ARM_FaultInfo.FaultRegisters.HFSR; + + if ((scb_hfsr & (SCB_HFSR_VECTTBL_Msk | + SCB_HFSR_FORCED_Msk | + SCB_HFSR_DEBUGEVT_Msk )) != 0U) { + + printf(" Fault: HardFault - "); + + if ((scb_hfsr & SCB_HFSR_VECTTBL_Msk) != 0U) { + printf("Bus error on vector read"); + } + if ((scb_hfsr & SCB_HFSR_FORCED_Msk) != 0U) { + printf("Escalated fault (original fault was disabled or it caused another lower priority fault)"); + } + if ((scb_hfsr & SCB_HFSR_DEBUGEVT_Msk) != 0U) { + printf("Breakpoint hit with Debug Monitor disabled"); + } + printf("\n"); + } + } + + /* Output: Decoded MemManage fault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_mmfar = ARM_FaultInfo.FaultRegisters.MMFAR; + + if ((scb_cfsr & (SCB_CFSR_IACCVIOL_Msk | + SCB_CFSR_DACCVIOL_Msk | + SCB_CFSR_MUNSTKERR_Msk | +#ifdef SCB_CFSR_MLSPERR_Msk + SCB_CFSR_MLSPERR_Msk | +#endif + SCB_CFSR_MSTKERR_Msk )) != 0U) { + + printf(" Fault: MemManage - "); + + if ((scb_cfsr & SCB_CFSR_IACCVIOL_Msk) != 0U) { + printf("Instruction execution failure due to MPU violation or fault"); + } + if ((scb_cfsr & SCB_CFSR_DACCVIOL_Msk) != 0U) { + printf("Data access failure due to MPU violation or fault"); + } + if ((scb_cfsr & SCB_CFSR_MUNSTKERR_Msk) != 0U) { + printf("Exception exit unstacking failure due to MPU access violation"); + } + if ((scb_cfsr & SCB_CFSR_MSTKERR_Msk) != 0U) { + printf("Exception entry stacking failure due to MPU access violation"); + } +#ifdef SCB_CFSR_MLSPERR_Msk + if ((scb_cfsr & SCB_CFSR_MLSPERR_Msk) != 0U) { + printf("Floating-point lazy stacking failure due to MPU access violation"); + } +#endif + if ((scb_cfsr & SCB_CFSR_MMARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_mmfar); + } + printf("\n"); + } + } + + /* Output: Decoded BusFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + uint32_t scb_bfar = ARM_FaultInfo.FaultRegisters.BFAR; + + if ((scb_cfsr & (SCB_CFSR_IBUSERR_Msk | + SCB_CFSR_PRECISERR_Msk | + SCB_CFSR_IMPRECISERR_Msk | + SCB_CFSR_UNSTKERR_Msk | +#ifdef SCB_CFSR_LSPERR_Msk + SCB_CFSR_LSPERR_Msk | +#endif + SCB_CFSR_STKERR_Msk )) != 0U) { + + printf(" Fault: BusFault - "); + + if ((scb_cfsr & SCB_CFSR_IBUSERR_Msk) != 0U) { + printf("Instruction prefetch failure due to bus fault"); + } + if ((scb_cfsr & SCB_CFSR_PRECISERR_Msk) != 0U) { + printf("Data access failure due to bus fault (precise)"); + } + if ((scb_cfsr & SCB_CFSR_IMPRECISERR_Msk) != 0U) { + printf("Data access failure due to bus fault (imprecise)"); + } + if ((scb_cfsr & SCB_CFSR_UNSTKERR_Msk) != 0U) { + printf("Exception exit unstacking failure due to bus fault"); + } + if ((scb_cfsr & SCB_CFSR_STKERR_Msk) != 0U) { + printf("Exception entry stacking failure due to bus fault"); + } +#ifdef SCB_CFSR_LSPERR_Msk + if ((scb_cfsr & SCB_CFSR_LSPERR_Msk) != 0U) { + printf("Floating-point lazy stacking failure due to bus fault"); + } +#endif + if ((scb_cfsr & SCB_CFSR_BFARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_bfar); + } + printf("\n"); + } + } + + /* Output Decoded UsageFault information */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + uint32_t scb_cfsr = ARM_FaultInfo.FaultRegisters.CFSR; + + if ((scb_cfsr & (SCB_CFSR_UNDEFINSTR_Msk | + SCB_CFSR_INVSTATE_Msk | + SCB_CFSR_INVPC_Msk | + SCB_CFSR_NOCP_Msk | +#ifdef SCB_CFSR_STKOF_Msk + SCB_CFSR_STKOF_Msk | +#endif + SCB_CFSR_UNALIGNED_Msk | + SCB_CFSR_DIVBYZERO_Msk )) != 0U) { + + printf(" Fault: UsageFault - "); + + if ((scb_cfsr & SCB_CFSR_UNDEFINSTR_Msk) != 0U) { + printf("Execution of undefined instruction"); + } + if ((scb_cfsr & SCB_CFSR_INVSTATE_Msk) != 0U) { + printf("Execution of Thumb instruction with Thumb mode turned off"); + } + if ((scb_cfsr & SCB_CFSR_INVPC_Msk) != 0U) { + printf("Invalid exception return value"); + } + if ((scb_cfsr & SCB_CFSR_NOCP_Msk) != 0U) { + printf("Coprocessor instruction with coprocessor disabled or non-existent"); + } +#ifdef SCB_CFSR_STKOF_Msk + if ((scb_cfsr & SCB_CFSR_STKOF_Msk) != 0U) { + printf("Stack overflow"); + } +#endif + if ((scb_cfsr & SCB_CFSR_UNALIGNED_Msk) != 0U) { + printf("Unaligned load/store"); + } + if ((scb_cfsr & SCB_CFSR_DIVBYZERO_Msk) != 0U) { + printf("Divide by 0"); + } + printf("\n"); + } + } + +#if (ARM_FAULT_ARCH_ARMV8x_M_MAIN != 0) + /* Output: Decoded SecureFault information */ + if (ARM_FaultInfo.Content.SecureFaultRegs != 0U) { + uint32_t scb_sfsr = ARM_FaultInfo.FaultRegisters.SFSR; + uint32_t scb_sfar = ARM_FaultInfo.FaultRegisters.SFAR; + + if ((scb_sfsr & (SAU_SFSR_INVEP_Msk | + SAU_SFSR_INVIS_Msk | + SAU_SFSR_INVER_Msk | + SAU_SFSR_AUVIOL_Msk | + SAU_SFSR_INVTRAN_Msk | + SAU_SFSR_LSPERR_Msk | + SAU_SFSR_LSERR_Msk )) != 0U) { + + printf(" Fault: SecureFault - "); + + if ((scb_sfsr & SAU_SFSR_INVEP_Msk) != 0U) { + printf("Invalid entry point due to invalid attempt to enter Secure state"); + } + if ((scb_sfsr & SAU_SFSR_INVIS_Msk) != 0U) { + printf("Invalid integrity signature in exception stack frame found on unstacking"); + } + if ((scb_sfsr & SAU_SFSR_INVER_Msk) != 0U) { + printf("Invalid exception return due to mismatch on EXC_RETURN.DCRS or EXC_RETURN.ES"); + } + if ((scb_sfsr & SAU_SFSR_AUVIOL_Msk) != 0U) { + printf("Attribution unit violation due to Non-secure access to Secure address space"); + } + if ((scb_sfsr & SAU_SFSR_INVTRAN_Msk) != 0U) { + printf("Invalid transaction caused by domain crossing branch not flagged as such"); + } + if ((scb_sfsr & SAU_SFSR_LSPERR_Msk) != 0U) { + printf("Lazy stacking preservation failure due to SAU or IDAU violation"); + } + if ((scb_sfsr & SAU_SFSR_LSERR_Msk) != 0U) { + printf("Lazy stacking activation or deactivation failure"); + } + if ((scb_sfsr & SAU_SFSR_SFARVALID_Msk) != 0U) { + printf(", fault address 0x%08X", (unsigned int)scb_sfar); + } + printf("\n"); + } + } +#endif +#endif + + /* Output: Program Counter */ + /* Output here is named PC (Program Counter) since in most situations stacked Return Address will be + the address of the instruction which caused the fault, there are some exceptions (asynchronous faults) + but these are for the sake of simplicity not taken into account here */ + printf(" Program Counter: "); + + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf("0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.ReturnAddress); + } else { + printf("unknown (was not stacked)\n"); + } + + /* Output: Registers */ + /* Registers R4 .. R11 values might be either: stacked (if additional state context (TrustZone only) + was stacked) or values as they were when fault handler started execution */ + printf("\n Registers:\n"); + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf(" - R0: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R0); + printf(" - R1: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R1); + printf(" - R2: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R2); + printf(" - R3: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R3); + } else { + printf(" - R0 .. R3: unknown (were not stacked)\n"); + } + + /* Output: R4 .. R11 */ + printf(" - R4: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R4); + printf(" - R5: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R5); + printf(" - R6: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R6); + printf(" - R7: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R7); + printf(" - R8: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R8); + printf(" - R9: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R9); + printf(" - R10: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R10); + printf(" - R11: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R11); + + if (ARM_FaultInfo.Content.StateContext != 0U) { + printf(" - R12: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.R12); + printf(" - LR: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.LR); + printf(" - Return Address: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.ReturnAddress); + printf(" - xPSR: 0x%08X\n\n", (unsigned int)ARM_FaultInfo.Registers.xPSR); + } else { + printf(" - R12: unknown (was not stacked)\n"); + printf(" - LR: unknown (was not stacked)\n"); + printf(" - Return Address: unknown (was not stacked)\n"); + printf(" - xPSR: unknown (was not stacked)\n"); + } + + printf(" - MSP: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.MSP); + if (ARM_FaultInfo.Content.LimitRegs != 0U) { + printf(" - MSPLIM: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.MSPLIM); + } + printf(" - PSP: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.PSP); + if (ARM_FaultInfo.Content.LimitRegs != 0U) { + printf(" - PSPLIM: 0x%08X\n", (unsigned int)ARM_FaultInfo.Registers.PSPLIM); + } + + /* Output: Exception State */ + printf("\n Exception State:\n"); + printf(" - xPSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.ExceptionState.xPSR); + printf(" - Exception Return: 0x%08X\n", (unsigned int)ARM_FaultInfo.ExceptionState.EXC_RETURN); + printf("\n"); + +#if (ARM_FAULT_FAULT_REGS_EXIST != 0) + /* Output: Fault Registers (if they exist) */ + if (ARM_FaultInfo.Content.FaultRegs != 0U) { + printf(" Fault Registers:\n"); + + printf(" - CFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.CFSR); + printf(" - HFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.HFSR); + printf(" - DFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.DFSR); + printf(" - MMFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.MMFAR); + printf(" - BFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.BFAR); + printf(" - AFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.AFSR); + + if (ARM_FaultInfo.Content.SecureFaultRegs != 0U) { + printf(" - SFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.SFSR); + printf(" - SFAR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.SFAR); + } + +#if (ARM_FAULT_ARCH_ARMV8_1M_MAIN != 0) + if (ARM_FaultInfo.Content.RAS_FaultReg != 0U) { + printf(" - RFSR: 0x%08X\n", (unsigned int)ARM_FaultInfo.FaultRegisters.RFSR); + } +#endif + + printf("\n"); + } +#else + /* Output: Message if fault registers do not exist */ + printf(" Fault Registers do not exist!\n\n"); +#endif +} diff --git a/LICENSE.md b/LICENSE.md deleted file mode 100644 index f771df9..0000000 --- a/LICENSE.md +++ /dev/null @@ -1,31 +0,0 @@ -# License Terms - -Copyright 2022 Arm Limited. All rights reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -## Note - -Individual files contain the following tag instead of the full license text. - -SPDX-License-Identifier: Apache-2.0 - -This enables machine processing of license information based on the SPDX License Identifiers that are here available: http://spdx.org/licenses/ - -## External Dependencies - -The components listed below are not redistributed with the project but are used internally for building, development, or testing purposes. - -| Component | Version | License | Origin | Usage | -| --------- | ------- | ------- | ------ | ----- | -|goversioninfo||[MIT](https://opensource.org/licenses/MIT)|https://github.com/josephspurrier/goversioninfo| Used in [eventlist](./tools/eventlist) to generate MS Windows version info | diff --git a/README.md b/README.md index 957007f..2c6f989 100644 --- a/README.md +++ b/README.md @@ -1,22 +1,24 @@ # CMSIS-View -The [**Keil MDK Event Recorder**](https://www2.keil.com/mdk5/debug) is now available as open source component along with tooling. +The [**Keil MDK Event Recorder**](https://developer.arm.com/documentation/101407/latest/Debugging/Debug-Windows-and-Dialogs/Event-Recorder) is now available as open source component along with tooling. This repository contains the source code of: - - [**ARM::CMSIS-View**](https://arm-software.github.io/CMSIS-View/main/index.html) software pack that provides the event recorder software component. - - [**EventList**](./tools/eventlist) command line utility that allows to dump the events on command line. - - [**Example Projects**](./Examples) that show the usage of the Event Recorder. + +- [**ARM::CMSIS-View**](https://arm-software.github.io/CMSIS-View/main/index.html) software pack that provides the Event Recorder and Fault software components. +- [**EventList**](./tools/eventlist) command line utility that allows to dump the events on command line. +- [**Example Projects**](./Examples) that show the usage of the Event Recorder and Fault components. ## Repository toplevel structure -``` +```txt 📦 ┣ 📂 .github GitHub Action workflow and configuration ┣ 📂 Documentation Target directory for generated documentation ┣ 📂 Doxygen Source directory for documentation ┣ 📂 EventRecorder Source code of EventRecorder software component - ┣ 📂 Examples Usage examples of the EventRecorder component - ┣ 📂 tools EventList command line tool source code - ┗ 📂 Scripts Helper scripts + ┣ 📂 Examples Usage examples + ┣ 📂 Fault Source code of Fault software component + ┣ 📂 Schema Schema files + ┗ 📂 tools EventList command line tool source code ``` ## Generating Software Pack @@ -27,26 +29,28 @@ Some helper scripts are provided to generate the release artifacts from this rep Generating the HTML-formatted documentation from its Doxygen-based source is done via -```bash +```sh CMSIS-View $ ./Doxygen/gen_doc.sh -``` +``` Prerequisites for this script to succeed are: - - Doxygen 1.9.2 + +- Doxygen 1.9.2 ### CMSIS-Pack Bundle The CMSIS-Pack bundle can be generated with -```bash +```sh CMSIS-View $ ./gen_pack.sh -``` +``` Prerequisites for this script to succeed are: - - Generated documentation (see above) - - 7z - - packchk - - xmllint (optional) + +- Generated documentation (see above) +- 7z/GNU Zip +- packchk (e.g., via CMSIS-Toolbox) +- xmllint (optional) ### Version and Changelog Inference @@ -54,51 +58,81 @@ The version and changelog embedded into the documentation and pack are inferred local Git history. In order to get the full changelog one needs to have a full clone (not a shallow one) including all release tags. -One can check the inferred version by calling the helper script: - -```bash -CMSIS-View $ ./Scripts/git_describe.sh -Git version: '1.2.4-dev5+g6a00f35' -1.2.4-dev5+g6a00f35 -^ ^ ^ ^ ^ -| | | | ┗ Commit SHA of the commit used for generation -| | | ┗ Number of commits added since latest tag -| | ┗ Patch version from the latest tag incremented by one -| ┗ Minor version as in the latest tag -┗ Major version as in the latest tag -``` - -The full changelog can be inspected by calling the helper script: - -```bash -CMSIS-View $ ./Scripts/gen_changelog.sh [-h] [-f ] -Generating changelog ... -Git version: '1.2.4-dev5+g6a00f35' -1.2.3 (2022-07-28) -- EventRecorder - - Change 1 - - Change 2 -- EventList - - Change 1 - - Change 2 -1.1.1 (2022-03-31) -Added clock frequency to internal Event Recorder Initialization message -1.1.0 (2022-02-25) -Added Event Recorder logging via Semihosting -1.0.0 (2021-01-28) -Add EventRecorder component +The version numbers and change logs are taken from the available annotated tags. + +### Release Pack + +A release is simply done via the GitHub Web UI. The newly created tag needs to have +the pattern `pack/` where `` shall be the SemVer `..` +version string for the release. The release description is used as the change log +message for the release. + +When using an auto-generated tag (via Web UI) the release description is used as the +annotation message for the generated tag. Alternatively, one can prepare the release +tag in the local clone and add the annotation message independently from creating the +release. + +Once the release is published via the GitHub Web UI the release workflow generates the +documentation and the pack (see above) and attaches the resulting pack archive as an +additional asset to the release. + +## EventList Utility + +The command line utility to decode EventRecorder log files written in Go. + +### Compile and Test + +To build and EventList run `make.sh` script. + +```sh +CMSIS-View/tools/eventlist $ ./make.sh build +GOOS=windows GOARCH=amd64 go build -v -ldflags '-X "..."' -o ./eventlist.exe ./cmd/eventlist + +build finished successfully! + +CMSIS-View/tools/eventlist $ ./make.sh test +go test ./... +? eventlist/cmd/make [no test files] +ok eventlist/cmd/eventlist 7.584s +ok eventlist/pkg/elf 6.802s +ok eventlist/pkg/eval 7.458s +ok eventlist/pkg/event 7.471s +ok eventlist/pkg/output 7.645s +ok eventlist/pkg/xml/scvd 6.808s ``` -The version numbers are taken from the available tags. The shown release dates and -changelogs are one of: +One can run cross-builds for other than the own host platform by specifying `-arch ` +and/or `-os ` on the `make.sh` command line, see `--help` for details. + +### Release + +A release for EventList utility is done independently from the CMSIS-View pack via +the GitHub Web UI. The release tag must match the pattern `tools/eventlist/` +where `` is a SemVer string. + +The GitHub Action release workflow is triggered once a release is published. The +workflow builds release bundles for all supported target platforms and attaches +them as assets to the release. + +## License Terms + +CMSIS-View is licensed under [Apache License 2.0](LICENSE). + +### Note + +Individual files contain the following tag instead of the full license text. + +SPDX-License-Identifier: Apache-2.0 -1. For annotated tags the tagger date and the associated message is used. -2. For simple tags the committer date and message of the pointed-to commit is used. +This enables machine processing of license information based on the SPDX License Identifiers that are here available: http://spdx.org/licenses/ +### External Dependencies -## License +The components listed below are not redistributed with the project but are used internally for building, development, or testing purposes. -CMSIS-View is licensed under Apache 2.0. +| Component | Version | License | Origin | Usage | +| --------- | ------- | ------- | ------ | ----- | +|goversioninfo|n/a|[MIT](https://opensource.org/licenses/MIT)|https://github.com/josephspurrier/goversioninfo| Used in [eventlist](./tools/eventlist) to generate MS Windows version info | ## Contributions and Pull Requests diff --git a/Schema/Component_Viewer.xsd b/Schema/Component_Viewer.xsd new file mode 100644 index 0000000..b1dd4f7 --- /dev/null +++ b/Schema/Component_Viewer.xsd @@ -0,0 +1,407 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Scripts/check_links.sh b/Scripts/check_links.sh deleted file mode 100755 index 355639c..0000000 --- a/Scripts/check_links.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash - -usage() { - echo "" - echo "Usage: $(basename $0) " - echo " Index.html file to start link scanning at." - echo " Directory with doxygen source files." - echo "" -} - -if [ ! -f "$1" ]; then - if [ -z "$1" ]; then - echo "No index file provided!" >&2 - else - echo "Index file not found: '$1'" >&2 - fi - usage - exit 1 -fi - -if [ ! -d "$2" ]; then - if [ -z "$2" ]; then - echo "No source directory provided!" >&2 - else - echo "Source dir not found: '$2'" >&2 - fi - usage - exit 1 -fi - -linkchecker -F csv --timeout 3 --check-extern $1 - -OFS=$IFS -IFS=$'\n' - -for line in $(grep -E '^[^#]' linkchecker-out.csv | tail -n +2); do - link=$(echo $line | cut -d';' -f 1) - msg=$(echo $line | cut -d';' -f 4) - origin=$(grep -Ern "href=['\"]${link}['\"]" $2) - for o in $origin; do - ofile=$(echo $o | cut -d':' -f 1) - oline=$(echo $o | cut -d':' -f 2) - match=$(echo $o | cut -d':' -f 3-) - rest="${match#*$link}" - ocolumn=$((${#match} - ${#rest} - ${#link})) - echo "$(readlink -f -n $ofile):${oline}:${ocolumn};${link};${msg};URL '${link}' results to '${msg}'" >&2 - done -done - -IFS=$OFS - -exit 0 diff --git a/gen_pack.sh b/gen_pack.sh index 132f1cf..db61c96 100755 --- a/gen_pack.sh +++ b/gen_pack.sh @@ -7,7 +7,7 @@ set -o pipefail # Set version of gen pack library -REQUIRED_GEN_PACK_LIB="0.6.0" +REQUIRED_GEN_PACK_LIB="0.7.0" # Set default command line arguments DEFAULT_ARGS=(-c "pack/") @@ -22,6 +22,8 @@ PACK_BUILD=./build PACK_DIRS=" Documentation EventRecorder + Examples + Fault " # Specify file names to be added to pack base directory @@ -40,7 +42,10 @@ PACK_PATCH_FILES="" PACKCHK_ARGS=() # Specify additional dependencies for packchk -PACKCHK_DEPS="" +PACKCHK_DEPS=" + ARM.V2M_MPS3_SSE_300_BSP.pdsc + Keil.B-U585I-IOT02A_BSP.pdsc +" # Optional: restrict fallback modes for changelog generation # Default: full diff --git a/tools/eventlist/README.md b/tools/eventlist/README.md index 9a2ca5e..4401fd1 100644 --- a/tools/eventlist/README.md +++ b/tools/eventlist/README.md @@ -9,13 +9,14 @@ Usage: eventlist [-I ]... [-o ] [-a ] [-b] Flags: - -a elf/axf file name - -b --begin show statistic at beginning - -h --help show short help - -I include SCVD file name - -o output file name - -s --statistic show statistic only - -V --version show version info + -a elf/axf file name + -b --begin show statistic at beginning + -f output format, default: txt + -h --help show short help + -I include SCVD file name + -o output file name + -s --statistic show statistic only + -V --version show version info ``` ## Building the tool locally @@ -35,18 +36,20 @@ Note that some of the required tools are platform dependent: - Platform specific command line terminal - **Windows:** - [GIT Bash](https://gitforwindows.org/) - ``` + + ```txt ☑️ Note: Make sure 'git' and 'bash' paths are listed under the PATH environment variable and set the git bash priority higher in the path. ``` + - **Linux/MacOS:** - GNU Bash (minimum recommended version **5.0.17**) ## Clone repository Clone GitHub repository to create a local copy on your computer to make -it easier to develop and test. Cloning of repository can be done by following +it easier to develop and test. Cloning of the repository can be done by following the below git command: ```bash @@ -55,27 +58,56 @@ git clone git@github.com:ARM-software/CMSIS-View.git ## Build components -The commands below demonstrate how to build and create executable: +The steps below demonstrate how to build and create an executable: + +- Go to eventlist directory + - cd \<**root**\>/tools/eventlist +- Run the command to build an executable under `build` directory + - `./make.sh build` : Build and generate executable for host OS & architecture in current directory. + - `./make.sh build -arch -os -outdir ` : Build and generate executable for provided configs.\ + for e.g. - - Go to eventlist directory - > cd \<**root**\>/tools/eventlist - - Create and switch to build directory ```bash - mkdir build - cd build + ./make.sh build -arch amd64 -os darwin -outdir "Path/to/output/dir" ``` - - Run go command to build an executable - > go build ./.. ## Run Tests -One can directly run the tests from command line. - - Go to eventlist directory +One can directly run the tests from the command line. + +- Go to eventlist directory + - cd \<**root**\>/tools/eventlist +- Clean existing cache test results + - go clean -cache +- Run command + - `./make.sh test` : Run all tests. + - `./make.sh test ` : Run test related to the specified package.\ + for e.g. + + ```bash + ./make.sh test eventlist/pkg/event + ``` + +## Code coverage + +Users can get coverage and generate code coverage report in HTML format + +- Go to eventlist directory > cd \<**root**\>/tools/eventlist - - Clean existing cache test results - > go clean -cache - - Run the executable - > go test ./... +- Run command + - `./make.sh coverage` : Run tests and show coverage info.\ + - `./make.sh coverage -html ` : Run tests with coverage info and generate specified HTML coverage report.\ + + for e.g. + + ```bash + ./make.sh coverage -html cov/coverage.html + ``` + +```txt +☑️ Note: + for more usable commands, Use `./make.sh -h`. +``` ## License diff --git a/tools/eventlist/main.go b/tools/eventlist/cmd/eventlist/main.go similarity index 87% rename from tools/eventlist/main.go rename to tools/eventlist/cmd/eventlist/main.go index 1924f80..75307a0 100644 --- a/tools/eventlist/main.go +++ b/tools/eventlist/cmd/eventlist/main.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -18,12 +18,10 @@ package main -//go:generate goversioninfo -gofile=versioninfo.go -arm=true - import ( - "eventlist/elf" - "eventlist/output" - "eventlist/xml/scvd" + "eventlist/pkg/elf" + "eventlist/pkg/output" + "eventlist/pkg/xml/scvd" "flag" "fmt" "os" @@ -31,6 +29,7 @@ import ( ) var Progname string +var versionInfo string type includes []string @@ -93,7 +92,6 @@ func main() { } commFlag := flag.CommandLine - fmt.Println(os.Args) // --- this is only for unit tests of main() testRun := flag.Lookup("test.run") @@ -117,12 +115,16 @@ func main() { infoOpt(commFlag, "o", "", "") infoOpt(commFlag, "s", "statistic", "") infoOpt(commFlag, "V", "version", "") + infoOpt(commFlag, "f", "format", "") + infoOpt(commFlag, "l", "level", "") usage = true } // parse command line commFlag.Var(&paths, "I", "include SCVD file name") outputFile := commFlag.String("o", "", "output file name") elfFile := commFlag.String("a", "", "elf/axf file name") + formatType := commFlag.String("f", "", "format type: txt, json, xml") + level := commFlag.String("l", "", "level: Error|API|Op|Detail") var statBegin bool commFlag.BoolVar(&statBegin, "b", false, "show statistic at beginning") commFlag.BoolVar(&statBegin, "begin", false, "show statistic at beginning") @@ -139,13 +141,7 @@ func main() { } if showVersion { - version := versionInfo.StringFileInfo.ProductVersion - i := strings.LastIndex(version, ".") - if i > 0 { - version = version[:i] - } - fmt.Printf("%s: Version %s\n", Progname, version) - fmt.Printf("%s\n", versionInfo.StringFileInfo.LegalCopyright) + fmt.Printf("%s %s\n", Progname, versionInfo) return } @@ -177,7 +173,7 @@ func main() { return } - if err := output.Print(outputFile, &eventFile[0], evdefs, typedefs, statBegin, showStatistic); err != nil { + if err := output.Print(outputFile, formatType, level, &eventFile[0], evdefs, typedefs, statBegin, showStatistic); err != nil { fmt.Print(Progname + ": ") fmt.Println(err) } diff --git a/tools/eventlist/main_test.go b/tools/eventlist/cmd/eventlist/main_test.go similarity index 77% rename from tools/eventlist/main_test.go rename to tools/eventlist/cmd/eventlist/main_test.go index 952d528..59eec4d 100644 --- a/tools/eventlist/main_test.go +++ b/tools/eventlist/cmd/eventlist/main_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -131,8 +131,7 @@ func Test_main(t *testing.T) { //nolint:golint,paralleltest outFile := "out.out" lines1 := - "\\[.*\\]\\n" + - " Detailed event list\\n" + + " Detailed event list\\n" + " -------------------\\n" + "\\n" + "Index Time \\(s\\) Component Event Property Value\\n" + @@ -147,15 +146,14 @@ func Test_main(t *testing.T) { //nolint:golint,paralleltest "----- ----- ----- --- --- ------- ----- ----\\n" lines2 := - "\\[.*\\]\\n" + - " Start/Stop event statistic\\n" + + " Start/Stop event statistic\\n" + " --------------------------\\n" + "\\n" + "Event count total min max average first last\\n" + "----- ----- ----- --- --- ------- ----- ----\\n" help := - "\\[.*\\]\\nUsage: [^ ]+ \\[-I \\]\\.\\.\\. \\[-o \\] \\[-a \\] \\[-b\\] \\n" + + "Usage: [^ ]+ \\[-I \\]\\.\\.\\. \\[-o \\] \\[-a \\] \\[-b\\] \\n" + "\\t-a \\telf/axf file name\\n" + "\\t-b --begin\\tshow statistic at beginning\\n" + "\\t-h --help\\tshow short help\\n" + @@ -164,28 +162,29 @@ func Test_main(t *testing.T) { //nolint:golint,paralleltest "\\t-s --statistic\\tshow statistic only\\n" + "\\t-V --version\\tshow version info\\n" + versionInfo = "1.2.3 (C) 2022 Arm Ltd. and Contributors" tests := []struct { name string args []string want string removefile string }{ - {"-a", []string{"-a", "testdata/nix", "xxx"}, ".*: open testdata/nix: (no such file or directory|The system cannot find the file specified.)\\n", ""}, - {"-s stdout", []string{"-s", "testdata/test10.binary"}, lines2, ""}, - {"-s", []string{"-s", "-o", outFile, "testdata/test10.binary"}, "\\[.*\\]\\n", outFile}, - {"-statistic", []string{"-statistic", "-o", outFile, "testdata/test10.binary"}, "\\[.*\\]\\n", outFile}, + {"-a", []string{"-a", "../../testdata/nix", "xxx"}, ".*: open ../../testdata/nix: (no such file or directory|The system cannot find the file specified.)\\n", ""}, + {"-s stdout", []string{"-s", "../../testdata/test10.binary"}, lines2, ""}, + {"-s", []string{"-s", "-o", outFile, "../../testdata/test10.binary"}, "", outFile}, + {"-statistic", []string{"-statistic", "-o", outFile, "../../testdata/test10.binary"}, "", outFile}, {"-help", []string{"-help"}, help, ""}, - {"stdout", []string{"testdata/test10.binary"}, lines1, ""}, - {"-o -begin", []string{"-begin", "-o", outFile, "testdata/test10.binary"}, "\\[.*\\]\\n", outFile}, - {"-o -b", []string{"-b", "-o", outFile, "testdata/test10.binary"}, "\\[.*\\]\\n", outFile}, - {"-o", []string{"-o", outFile, "testdata/test10.binary"}, "\\[.*\\]\\n", outFile}, - {"-o", []string{"-o", outFile, "testdata/nix"}, ".*: cannot open event file\\n", outFile}, - {"-V", []string{"-V"}, ".*: Version [0-9]+\\.[0-9]+\\.[0-9]+\\nCopyright \\(C\\) [0-9]+ ARM Limited or its Affiliates\\. All rights reserved\\.\\n", ""}, - {"-version", []string{"-version"}, ".*: Version [0-9]+\\.[0-9]+\\.[0-9]+\\nCopyright \\(C\\) [0-9]+ ARM Limited or its Affiliates\\. All rights reserved\\.\\n", ""}, + {"stdout", []string{"../../testdata/test10.binary"}, lines1, ""}, + {"-o -begin", []string{"-begin", "-o", outFile, "../../testdata/test10.binary"}, "", outFile}, + {"-o -b", []string{"-b", "-o", outFile, "../../testdata/test10.binary"}, "", outFile}, + {"-o", []string{"-o", outFile, "../../testdata/test10.binary"}, "", outFile}, + {"-o", []string{"-o", outFile, "../../testdata/nix"}, ".*: cannot open event file\\n", outFile}, + {"-V", []string{"-V"}, ".* [0-9]+\\.[0-9]+\\.[0-9]+ \\(C\\) [0-9]+ Arm Ltd. and Contributors\\n", ""}, + {"-version", []string{"-version"}, ".* [0-9]+\\.[0-9]+\\.[0-9]+ \\(C\\) [0-9]+ Arm Ltd. and Contributors\\n", ""}, {"err", []string{"xxx", "yyy"}, ".*: only one binary input file allowed\n", ""}, {"missing", nil, ".*: missing input file\n", ""}, // -I must be the last test - {"-I", []string{"-I", "testdata/nix", "xxx"}, ".*: open testdata/nix: (no such file or directory|The system cannot find the file specified.)\\n", ""}, + {"-I", []string{"-I", "../../testdata/nix", "xxx"}, ".*: open ../../testdata/nix: (no such file or directory|The system cannot find the file specified.)\\n", ""}, } savedArgs := os.Args for _, tt := range tests { //nolint:golint,paralleltest diff --git a/tools/eventlist/cmd/make/make.go b/tools/eventlist/cmd/make/make.go new file mode 100644 index 0000000..b2c15a4 --- /dev/null +++ b/tools/eventlist/cmd/make/make.go @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package main + +import ( + "bytes" + "errors" + "flag" + "fmt" + "os" + "os/exec" + "path" + "runtime" + "strconv" + "strings" + + "github.com/josephspurrier/goversioninfo" +) + +const program = "eventlist" +const mainPath = "./cmd/" + program +const resourceFileName = "resource.syso" +const unknownVersion = "0.0.0.0" +const unknownYear = "2023" + +var legalCopyright = "Arm Ltd. and Contributors" + +// Errors +var ErrGitTag = errors.New("git tag error") +var ErrVersion = errors.New("version error") +var ErrCommand = errors.New("command error") + +func reportError(err error, msg string) error { + return fmt.Errorf("%w: %s", err, msg) +} + +type Options struct { + targetOs string + targetArch string + outDir string + covReport string +} + +type runner struct { + options Options + args []string +} + +func (r runner) run(command string) { + switch { + case command == "build": + versionInfo, err := createResourceInfoFile(r.options.targetArch) + if err != nil { + fmt.Println(err.Error()) + return + } + info := versionInfo.StringFileInfo.FileVersion + " " + versionInfo.StringFileInfo.LegalCopyright + if err = r.build(r.options, info); err != nil { + fmt.Println(err.Error()) + } + case command == "test": + if err := r.test(); err != nil { + fmt.Println(err.Error()) + return + } + case command == "coverage": + if r.options.covReport == "" { + if err := r.coverage(); err != nil { + fmt.Println(err.Error()) + return + } + } else { + if err := r.coverageReport(r.options.covReport); err != nil { + fmt.Println(err.Error()) + return + } + } + case command == "lint": + r.lint() + case command == "format": + r.format() + } +} + +func (r runner) executeCommand(command string) (err error) { + var stdout, stderr bytes.Buffer + fmt.Println(command) + cmd := exec.Command("bash", "-c", command) + cmd.Stdout = &stdout + cmd.Stderr = &stderr + err = cmd.Run() + stdoutStr := stdout.String() + stderrStr := stderr.String() + if stdoutStr != "" { + fmt.Println(stdoutStr) + } + if stderrStr != "" { + fmt.Println(stderrStr) + } + return err +} + +func (r runner) build(options Options, versionInfo string) (err error) { + var extn string + + if options.targetOs == "windows" { + extn = ".exe" + } + cmd := "GOOS=" + options.targetOs + " GOARCH=" + options.targetArch + + " go build -v -ldflags '-X \"main.versionInfo=" + versionInfo + + "\"' -o " + options.outDir + "/" + program + extn + " " + mainPath + + if err = r.executeCommand(cmd); err == nil { + fmt.Println("build finished successfully!") + } + return err +} + +func (r runner) test() (err error) { + args := "./..." + if len(r.args) != 0 { + args = strings.Join(r.args[:], " ") + } + return r.executeCommand("go test " + args) +} + +func (r runner) coverage() (err error) { + args := "./..." + if len(r.args) != 0 { + args = strings.Join(r.args[:], " ") + } + return r.executeCommand("go test -cover " + args) +} + +func (r runner) coverageReport(covReport string) (err error) { + covDir := path.Dir(covReport) + if covReport == covDir { + return reportError(ErrCommand, "invalid file path '"+covReport+"'") + } + + if _, err = os.Stat(covDir); os.IsNotExist(err) { + if err = os.Mkdir(covDir, os.ModePerm); err != nil { + return + } + } + err = r.executeCommand("go test ./... -coverprofile " + covDir + "/cover.out") + if err != nil { + return + } + err = r.executeCommand("go tool cover -html=" + covDir + "/cover.out -o " + covReport) + if err == nil { + fmt.Println("info: HTML coverage output written to " + covReport) + } + return +} + +func (r runner) lint() { + _ = r.executeCommand("golangci-lint run --config=./.golangci.yaml") +} + +func (r runner) format() { + _ = r.executeCommand("gofmt -s -w .") +} + +func fetchVersionInfoFromGit() (version version, err error) { + out, err := exec.Command("git", "describe", "--tags", "--match", "tools/eventlist/*").Output() + if len(out) == 0 && err != nil { + fmt.Println("warning: no release tag found, setting version to default \"" + unknownVersion + "\"") + return newVersion(unknownVersion) + } + if err != nil { + return + } + tag := strings.TrimSpace(string(out)) + if tag == "" { + return version, reportError(ErrGitTag, "no git release tag found") + } + tokens := strings.Split(tag, "/") + if len(tokens) != 3 { + return version, reportError(ErrGitTag, "invalid release tag") + } + return newVersion(tokens[2]) +} + +func fetchChangeYearFromGit() (year string) { + out, err := exec.Command("git", "log", "-n", "1", "--format=%ad", "--date=format:%Y").Output() + if len(out) == 0 || err != nil { + fmt.Println("warning: no change log found, setting year to default \"" + unknownYear + "\"") + return unknownYear + } + return strings.TrimSpace(string(out)) +} + +func createResourceInfoFile(arch string) (version goversioninfo.VersionInfo, err error) { + gitVersion, err := fetchVersionInfoFromGit() + if err != nil { + return + } + gitYear := fetchChangeYearFromGit() + + verInfo := goversioninfo.VersionInfo{} + + verInfo.FixedFileInfo.FileVersion = goversioninfo.FileVersion{ + Major: gitVersion.major, + Minor: gitVersion.minor, + Patch: gitVersion.patch, + Build: gitVersion.numCommit, + } + + verInfo.FixedFileInfo.ProductVersion = verInfo.FixedFileInfo.FileVersion + verInfo.StringFileInfo = goversioninfo.StringFileInfo{ + FileDescription: program, + InternalName: program, + ProductName: program, + OriginalFilename: program + ".exe", + FileVersion: gitVersion.String(), + ProductVersion: gitVersion.String(), + LegalCopyright: "Copyright (c) 2022-" + gitYear + " " + legalCopyright, + } + verInfo.VarFileInfo.Translation = goversioninfo.Translation{ + LangID: 1033, + CharsetID: 1200, + } + + // Fill the structures with config data + verInfo.Build() + // Write the data to a buffer + verInfo.Walk() + + return verInfo, verInfo.WriteSyso(mainPath+"/"+resourceFileName, arch) +} + +func isCommandValid(command string) (result bool) { + for _, cmd := range []string{ + "build", "coverage", "coverage-report", + "format", "help", "lint", "test", + } { + if cmd == command { + return true + } + } + fmt.Println(reportError(ErrCommand, "invalid command").Error()) + return false +} + +type version struct { + major, minor, patch int + numCommit int + shaCommit string +} + +func (v version) String() string { + if v.Empty() { + return unknownVersion + } + if v.shaCommit == "" && v.numCommit == 0 { + return fmt.Sprintf("%d.%d.%d.%d", v.major, v.minor, v.patch, v.numCommit) + } + return fmt.Sprintf("%d.%d.%d-dev%d+%s", v.major, v.minor, v.patch, v.numCommit, v.shaCommit) +} + +func (v version) Empty() bool { + if v.major == 0 && v.minor == 0 && v.patch == 0 && v.shaCommit == "" && v.numCommit == 0 { + return true + } + return false +} + +func newVersion(verStr string) (ver version, err error) { + if verStr == "" || verStr == unknownVersion { + return + } + + versionStr := strings.TrimSpace(verStr) + tokens := strings.Split(versionStr, "-") + numTokens := len(tokens) + + if !(numTokens == 1 || numTokens == 3) { + return ver, reportError(ErrVersion, "invalid version string") + } + verParts := strings.Split(tokens[0], ".") + if len(verParts) != 3 { + return ver, reportError(ErrVersion, "invalid version string") + } + + // Major + ver.major, err = strconv.Atoi(verParts[0]) + if err != nil { + return version{}, err + } + // Minor + ver.minor, err = strconv.Atoi(verParts[1]) + if err != nil { + return version{}, err + } + // Patch + ver.patch, err = strconv.Atoi(verParts[2]) + if err != nil { + return version{}, err + } + + if numTokens == 3 { + // Number of commits + ver.numCommit, err = strconv.Atoi(tokens[1]) + if err != nil { + return version{}, err + } + // SHA of commit + ver.shaCommit = tokens[2] + } + return ver, nil +} + +func main() { + if len(os.Args) < 2 { + fmt.Println(reportError(ErrCommand, "invalid command").Error()) + os.Exit(1) + } + + command := os.Args[1] + if !isCommandValid(command) { + os.Exit(1) + } + + commFlag := flag.CommandLine + targetOs := commFlag.String("os", runtime.GOOS, "Target Operating System") + targetArch := commFlag.String("arch", runtime.GOARCH, "Target architecture") + outDir := commFlag.String("outdir", ".", "Output directory") + covReport := commFlag.String("html", "", "Coverage report") + _ = commFlag.Parse(os.Args[2:]) + arguments := commFlag.Args() + + runner := runner{ + options: Options{ + targetOs: *targetOs, + targetArch: *targetArch, + outDir: *outDir, + covReport: *covReport, + }, + args: arguments, + } + runner.run(command) +} diff --git a/tools/eventlist/go.mod b/tools/eventlist/go.mod index 550fda5..4e48d20 100644 --- a/tools/eventlist/go.mod +++ b/tools/eventlist/go.mod @@ -1,6 +1,6 @@ module eventlist -go 1.17 +go 1.20 require ( github.com/akavel/rsrc v0.10.2 // indirect diff --git a/tools/eventlist/make.sh b/tools/eventlist/make.sh new file mode 100755 index 0000000..6b02bf5 --- /dev/null +++ b/tools/eventlist/make.sh @@ -0,0 +1,54 @@ +#!/bin/bash + +# ------------------------------------------------------- +# Copyright (c) 2023 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# ------------------------------------------------------- + +# usage +usage() { + echo "" + echo "Usage:" + echo " make.sh [OPTIONS...]" + echo "" + echo "commands:" + echo " build : Build executable" + echo " coverage : Run tests with coverage info" + echo " format : Align indentation and format code" + echo " lint : Run linter" + echo " test : Run all tests" + echo "" + echo "build options:" + echo " -arch arg : Optional target architecture for e.g amd64 etc [default: host arch]" + echo " -os arg : Optional target operating system for e.g windows, linux, darwin etc [default: host OS]" + echo " -outdir arg : Optional output directory for executable generation [default: current directory]" + echo "" + echo "coverage options:" + echo " -html arg : Coverage file path" +} + +if [ $# -eq 0 ] +then + usage + exit 0 +fi + +for cmdline in "$@" +do + if [[ "${cmdline}" == "help" || "${cmdline}" == "-h" || "${cmdline}" == "--help" ]]; then + usage + exit 0 + fi + arg="${cmdline}" + args+=("${arg}") +done + +go run cmd/make/make.go "${args[@]}" + +RESULT=$? +if [ $RESULT -ne 0 ]; then + usage + exit 1 +fi +exit 0 \ No newline at end of file diff --git a/tools/eventlist/elf/elf.go b/tools/eventlist/pkg/elf/elf.go similarity index 100% rename from tools/eventlist/elf/elf.go rename to tools/eventlist/pkg/elf/elf.go diff --git a/tools/eventlist/elf/elf_test.go b/tools/eventlist/pkg/elf/elf_test.go similarity index 95% rename from tools/eventlist/elf/elf_test.go rename to tools/eventlist/pkg/elf/elf_test.go index 4e23965..3aac16a 100644 --- a/tools/eventlist/elf/elf_test.go +++ b/tools/eventlist/pkg/elf/elf_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -24,9 +24,9 @@ import ( ) func Test_sections_Readelf(t *testing.T) { //nolint:golint,paralleltest - fileTest := "../testdata/elftest.elf" - fileNix := "../testdata/nix.elf" - fileSym := "../testdata/elfsym.elf" + fileTest := "../../testdata/elftest.elf" + fileNix := "../../testdata/nix.elf" + fileSym := "../../testdata/elfsym.elf" type args struct { name *string diff --git a/tools/eventlist/eval/eval.go b/tools/eventlist/pkg/eval/eval.go similarity index 100% rename from tools/eventlist/eval/eval.go rename to tools/eventlist/pkg/eval/eval.go diff --git a/tools/eventlist/eval/eval_test.go b/tools/eventlist/pkg/eval/eval_test.go similarity index 100% rename from tools/eventlist/eval/eval_test.go rename to tools/eventlist/pkg/eval/eval_test.go diff --git a/tools/eventlist/eval/expression.go b/tools/eventlist/pkg/eval/expression.go similarity index 100% rename from tools/eventlist/eval/expression.go rename to tools/eventlist/pkg/eval/expression.go diff --git a/tools/eventlist/eval/expression_test.go b/tools/eventlist/pkg/eval/expression_test.go similarity index 100% rename from tools/eventlist/eval/expression_test.go rename to tools/eventlist/pkg/eval/expression_test.go diff --git a/tools/eventlist/eval/value.go b/tools/eventlist/pkg/eval/value.go similarity index 99% rename from tools/eventlist/eval/value.go rename to tools/eventlist/pkg/eval/value.go index 76c5cc1..8a0b049 100644 --- a/tools/eventlist/eval/value.go +++ b/tools/eventlist/pkg/eval/value.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -18,7 +18,7 @@ package eval -import "eventlist/elf" +import "eventlist/pkg/elf" type Value struct { t Token diff --git a/tools/eventlist/eval/value_test.go b/tools/eventlist/pkg/eval/value_test.go similarity index 99% rename from tools/eventlist/eval/value_test.go rename to tools/eventlist/pkg/eval/value_test.go index e0a20d6..53592fc 100644 --- a/tools/eventlist/eval/value_test.go +++ b/tools/eventlist/pkg/eval/value_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ package eval import ( - "eventlist/elf" + "eventlist/pkg/elf" "reflect" "testing" ) diff --git a/tools/eventlist/eval/variable.go b/tools/eventlist/pkg/eval/variable.go similarity index 100% rename from tools/eventlist/eval/variable.go rename to tools/eventlist/pkg/eval/variable.go diff --git a/tools/eventlist/eval/variable_test.go b/tools/eventlist/pkg/eval/variable_test.go similarity index 100% rename from tools/eventlist/eval/variable_test.go rename to tools/eventlist/pkg/eval/variable_test.go diff --git a/tools/eventlist/event/event.go b/tools/eventlist/pkg/event/event.go similarity index 95% rename from tools/eventlist/event/event.go rename to tools/eventlist/pkg/event/event.go index 8765519..c8a9919 100644 --- a/tools/eventlist/event/event.go +++ b/tools/eventlist/pkg/event/event.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,9 +22,9 @@ import ( "bufio" "encoding/binary" "errors" - "eventlist/elf" - "eventlist/eval" - "eventlist/xml/scvd" + "eventlist/pkg/elf" + "eventlist/pkg/eval" + "eventlist/pkg/xml/scvd" "fmt" "io" "os" @@ -146,11 +146,11 @@ func (e *Data) calculateExpression(value string, i *int) (string, error) { case 't': // text out = elf.Sections.GetString(val.GetUInt()) case 'x': // hexadecimal - out = fmt.Sprintf("%02x", val.GetUInt()) + out = fmt.Sprintf("0x%02x", val.GetUInt()) case 'F': // File out = elf.Sections.GetString(val.GetUInt()) if len(out) == 0 { - out = fmt.Sprintf("%08x", val.GetUInt()) + out = fmt.Sprintf("0x%08x", val.GetUInt()) } case 'C': // address with file return "", eval.ErrSyntax @@ -163,7 +163,7 @@ func (e *Data) calculateExpression(value string, i *int) (string, error) { case 'N': // string address out = elf.Sections.GetString(val.GetUInt()) if len(out) == 0 { - out = fmt.Sprintf("%08x", val.GetUInt()) + out = fmt.Sprintf("0x%08x", val.GetUInt()) } case 'M': // MAC address out = fmt.Sprintf("%02x-%02x-%02x-%02x-%02x-%02x", val.GetUInt()>>40&0xFF, val.GetUInt()>>32&0xFF, @@ -338,17 +338,29 @@ func (e *Data) Read(in *bufio.Reader) error { if err != nil { return err } + if len(data) < 12 { + return eval.ErrEof + } e.Time = convert64(data[:8]) e.Info.getInfoFromBytes(data[8:12]) e.Typ = typ switch typ { case 1: // EventrecordData + if len(data) < 12+int(e.Info.length) { + return eval.ErrEof + } e.Data = new([]uint8) *e.Data = data[12 : 12+int(e.Info.length)] case 2: // Eventrecord2 + if len(data) < 20 { + return eval.ErrEof + } e.Value1 = int32(convert32(data[12:16])) e.Value2 = int32(convert32(data[16:20])) case 3: // Eventrecord4 + if len(data) < 28 { + return eval.ErrEof + } e.Value1 = int32(convert32(data[12:16])) e.Value2 = int32(convert32(data[16:20])) e.Value3 = int32(convert32(data[20:24])) diff --git a/tools/eventlist/event/event_test.go b/tools/eventlist/pkg/event/event_test.go similarity index 93% rename from tools/eventlist/event/event_test.go rename to tools/eventlist/pkg/event/event_test.go index f97656d..493bf91 100644 --- a/tools/eventlist/event/event_test.go +++ b/tools/eventlist/pkg/event/event_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -21,9 +21,9 @@ package event import ( "bufio" "errors" - "eventlist/elf" - "eventlist/eval" - "eventlist/xml/scvd" + "eventlist/pkg/elf" + "eventlist/pkg/eval" + "eventlist/pkg/xml/scvd" "reflect" "testing" ) @@ -169,7 +169,7 @@ func TestInfo_SplitID(t *testing.T) { func TestEventData_calculateExpression(t *testing.T) { //nolint:golint,paralleltest var i int - fileTest := "../testdata/elftest.elf" + fileTest := "../../testdata/elftest.elf" type fields struct { Time uint64 @@ -200,14 +200,14 @@ func TestEventData_calculateExpression(t *testing.T) { //nolint:golint,parallelt {"expr d", ed1, args{"d[val2]", &i}, "-24", 7, false}, {"expr u", ed1, args{"u[val1]", &i}, "257", 7, false}, {"expr t", ed1, args{"t[val4]", &i}, "def", 7, false}, - {"expr x", ed1, args{"x[val1]", &i}, "101", 7, false}, + {"expr x", ed1, args{"x[val1]", &i}, "0x101", 7, false}, {"expr F", ed1, args{"F[val4]", &i}, "def", 7, false}, - {"expr F", ed1, args{"F[val1]", &i}, "00000101", 7, false}, + {"expr F", ed1, args{"F[val1]", &i}, "0x00000101", 7, false}, {"expr C", ed1, args{"C[val2]", &i}, "", 7, true}, {"expr I", ed1, args{"I[val3]", &i}, "37.72.10.117", 7, false}, {"expr J", ed1, args{"J[val3]", &i}, "0:0:2548:a75:", 7, false}, {"expr N", ed1, args{"N[val4]", &i}, "def", 7, false}, - {"expr N", ed1, args{"N[val1]", &i}, "00000101", 7, false}, + {"expr N", ed1, args{"N[val1]", &i}, "0x00000101", 7, false}, {"expr M", ed1, args{"M[val3]", &i}, "00-00-25-48-0a-75", 7, false}, {"expr S", ed1, args{"S[val3]", &i}, "25480a75", 7, false}, {"expr ?", ed1, args{"?[val3]", &i}, "?", 7, false}, @@ -358,7 +358,7 @@ func TestEventData_EvalLine(t *testing.T) { wantErr bool }{ {"EvalLine ev1", ed1, args{ev1, tds}, "x%257y4711z", false}, - {"EvalLine ev2", ed1, args{ev2, tds}, "x257y1267z", false}, + {"EvalLine ev2", ed1, args{ev2, tds}, "x257y0x1267z", false}, {"EvalLine ev3", ed1, args{ev3, tds}, "x37.72.10.117y0:0:2548:a75:z", false}, {"EvalLine ev4", ed1, args{ev4, tds}, "x00-00-25-48-0a-75y25480a75z", false}, {"EvalLine evE1", ed1, args{evE1, tds}, "xenumy", false}, @@ -517,13 +517,17 @@ func Test_convert64(t *testing.T) { func TestEventData_Read(t *testing.T) { t.Parallel() - var s0 = "../testdata/test0.binary" - var s1 = "../testdata/test1.binary" - var s2 = "../testdata/test2.binary" - var sNix = "../testdata/xxxx" - var s3 = "../testdata/test3.binary" - var s4 = "../testdata/test4.binary" - var s5 = "../testdata/test5.binary" + var s0 = "../../testdata/test0.binary" + var s1 = "../../testdata/test1.binary" + var s2 = "../../testdata/test2.binary" + var sNix = "../../testdata/xxxx" + var s3 = "../../testdata/test3.binary" + var s4 = "../../testdata/test4.binary" + var s5 = "../../testdata/test5.binary" + var s8 = "../../testdata/test8.binary" + var s9 = "../../testdata/test9.binary" + var s12 = "../../testdata/test12.binary" + var s13 = "../../testdata/test13.binary" var b0 = []uint8("hello wo") @@ -553,6 +557,10 @@ func TestEventData_Read(t *testing.T) { {"read fail0", fields{}, args{}, &s0, false, Data{}, true, false}, {"read fail1", fields{}, args{}, &s1, false, Data{}, false, true}, {"read fail2", fields{}, args{}, &s2, false, Data{}, false, true}, + {"read fail3", fields{}, args{}, &s8, false, Data{}, true, false}, + {"read fail4", fields{}, args{}, &s9, false, Data{Typ: 1, Time: 1410, Info: Info{0xfe00, 8, false}}, true, false}, + {"read fail5", fields{}, args{}, &s12, false, Data{Typ: 2, Time: 31, Info: Info{0xff00, 0, false}}, true, false}, + {"read fail6", fields{}, args{}, &s13, false, Data{Typ: 3, Time: 306, Info: Info{0xf000, 0, true}}, true, false}, {"read failOpen", fields{}, args{}, &sNix, true, Data{}, true, false}, {"read ok1", fields{}, args{}, &s3, false, Data{Typ: 1, Data: &b0, Time: 1410, Info: Info{0xfe00, 8, false}}, false, false}, {"read ok2", fields{}, args{}, &s4, false, Data{Typ: 2, Value1: 1, Value2: 2, Time: 31, Info: Info{0xff00, 0, false}}, false, false}, diff --git a/tools/eventlist/output/output.go b/tools/eventlist/pkg/output/output.go similarity index 59% rename from tools/eventlist/output/output.go rename to tools/eventlist/pkg/output/output.go index b85ab5f..6744886 100644 --- a/tools/eventlist/output/output.go +++ b/tools/eventlist/pkg/output/output.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -20,10 +20,13 @@ package output import ( "bufio" + "bytes" + "encoding/json" + "encoding/xml" "errors" - "eventlist/eval" - "eventlist/event" - "eventlist/xml/scvd" + "eventlist/pkg/eval" + "eventlist/pkg/event" + "eventlist/pkg/xml/scvd" "fmt" "math" "os" @@ -32,6 +35,8 @@ import ( var errNoEvents = errors.New("cannot open event file") var TimeFactor *float64 +var FormatType = "txt" +var Level = "" func TimeInSecs(time uint64) float64 { if TimeFactor == nil { @@ -62,6 +67,43 @@ type eventStatistic struct { textMaxE string } +type EventRecord struct { + Index int `json:"index" xml:"index"` + Time float64 `json:"time" xml:"time"` + Component string `json:"component" xml:"component"` + EventProperty string `json:"eventProperty" xml:"eventProperty"` + Value string `json:"value" xml:"value"` +} + +type EventRecordStatistic struct { + Event string `json:"event" xml:"event"` + Count int `json:"count" xml:"count"` + AddCount string `json:"addCount" xml:"addCount"` + Start string `json:"start" xml:"start"` + MinStopTime float64 `json:"minStopTime" xml:"minStopTime"` + MaxStopTime float64 `json:"maxStopTime" xml:"maxStopTime"` + Total string `json:"total" xml:"total"` + Min string `json:"min" xml:"min"` + Max string `json:"max" xml:"max"` + First string `json:"first" xml:"first"` + Last string `json:"last" xml:"last"` + Avg string `json:"avg" xml:"avg"` + MinTime float64 `json:"minTime" xml:"minTime"` + MaxTime float64 `json:"maxTime" xml:"maxTime"` + FirstTime string `json:"firstTime" xml:"firstTime"` + LastTime string `json:"lastTime" xml:"lastTime"` + TextB string `json:"textB" xml:"textB"` + TextMinB string `json:"textMinB" xml:"textMinB"` + TextMinE string `json:"textMinE" xml:"textMinE"` + TextMaxB string `json:"textMaxB" xml:"textMaxB"` + TextMaxE string `json:"textMaxE" xml:"textMaxE"` +} + +type EventsTable struct { + Events []EventRecord `json:"events" xml:"events"` + Statistics []EventRecordStatistic `json:"statistics" xml:"statistics"` +} + func (es *eventStatistic) init() { es.evFirst = false es.evStart = false @@ -279,60 +321,88 @@ func (o *Output) buildStatistic(in *bufio.Reader, evdefs map[uint16]scvd.Event, return eventCount } -func (o *Output) printStatistic(out *bufio.Writer, eventCount int) error { +func conditionalWrite(out *bufio.Writer, format string, a ...any) (err error) { + if FormatType == "txt" { + _, err = fmt.Fprintf(out, format, a...) + return err + } + return nil +} + +func (o *Output) printStatistic(out *bufio.Writer, eventCount int, eventTable *EventsTable) error { var err error if out != nil && eventCount > 0 { - if _, err = out.WriteString(" Start/Stop event statistic\n"); err != nil { + if err = conditionalWrite(out, " Start/Stop event statistic\n"); err != nil { return err } - if _, err = out.WriteString(" --------------------------\n\n"); err != nil { + if err = conditionalWrite(out, " --------------------------\n\n"); err != nil { return err } - if _, err = out.WriteString("Event count total min max average first last\n"); err != nil { + if err = conditionalWrite(out, "Event count total min max average first last\n"); err != nil { return err } - if _, err = out.WriteString("----- ----- ----- --- --- ------- ----- ----\n"); err != nil { + if err = conditionalWrite(out, "----- ----- ----- --- --- ------- ----- ----\n"); err != nil { return err } for i := uint16(0); i < uint16(len(o.evProps)); i++ { for j := uint16(0); j < uint16(len(o.evProps[i].values)); j++ { if o.evProps[i].values[j].evFirst { - _, err = fmt.Fprintf(out, "%c(%d)", byte(i+'A'), j) + eventStat := EventRecordStatistic{ + Event: fmt.Sprintf("%c(%d)", byte(i+'A'), j), + AddCount: o.evProps[i].getAddCount(j), + Count: o.evProps[i].getCount(j), + Total: o.evProps[i].getTot(j), + Min: o.evProps[i].getMin(j), + Max: o.evProps[i].getMax(j), + Avg: o.evProps[i].getAvg(j), + First: o.evProps[i].getFirst(j), + Last: o.evProps[i].getLast(j), + MinTime: o.evProps[i].values[j].minTime, + TextMinB: o.evProps[i].values[j].textMinB, + TextMinE: o.evProps[i].values[j].textMinE, + MinStopTime: o.evProps[i].values[j].minTime + o.evProps[i].values[j].min, + MaxStopTime: o.evProps[i].values[j].maxTime + o.evProps[i].values[j].max, + MaxTime: o.evProps[i].values[j].maxTime, + TextMaxB: o.evProps[i].values[j].textMaxB, + TextMaxE: o.evProps[i].values[j].textMaxE, + } + err = conditionalWrite(out, eventStat.Event) if err == nil && j < 10 { - err = out.WriteByte(' ') + err = conditionalWrite(out, " ") } if err != nil { return err } - _, err = fmt.Fprintf(out, " %5d%s %s %s %s %s %s %s\n", - o.evProps[i].getCount(j), - o.evProps[i].getAddCount(j), - o.evProps[i].getTot(j), - o.evProps[i].getMin(j), - o.evProps[i].getMax(j), - o.evProps[i].getAvg(j), - o.evProps[i].getFirst(j), - o.evProps[i].getLast(j)) + err = conditionalWrite(out, " %5d%s %s %s %s %s %s %s\n", + eventStat.Count, + eventStat.AddCount, + eventStat.Total, + eventStat.Min, + eventStat.Max, + eventStat.Avg, + eventStat.First, + eventStat.Last) if err != nil { return err } - _, err = fmt.Fprintf(out, " Min: Start: %.8f %s Stop: %.8f %s\n", - o.evProps[i].values[j].minTime, - o.evProps[i].values[j].textMinB, - o.evProps[i].values[j].minTime+o.evProps[i].values[j].min, - o.evProps[i].values[j].textMinE) + err = conditionalWrite(out, " Min: Start: %.8f %s Stop: %.8f %s\n", + eventStat.MinTime, + eventStat.TextMinB, + eventStat.MinStopTime, + eventStat.TextMinE) if err != nil { return err } - _, err = fmt.Fprintf(out, " Max: Start: %.8f %s Stop: %.8f %s\n\n", - o.evProps[i].values[j].maxTime, - o.evProps[i].values[j].textMaxB, - o.evProps[i].values[j].maxTime+o.evProps[i].values[j].max, - o.evProps[i].values[j].textMaxE) + err = conditionalWrite(out, " Max: Start: %.8f %s Stop: %.8f %s\n\n", + eventStat.MaxTime, + eventStat.TextMaxB, + eventStat.MaxStopTime, + eventStat.TextMaxE) if err != nil { return err } + eventTable.Statistics = append(eventTable.Statistics, eventStat) } } } @@ -376,7 +446,7 @@ func escapeGen(s string) string { } func (o *Output) printEvents(out *bufio.Writer, in *bufio.Reader, evdefs map[uint16]scvd.Event, - typedefs map[string]map[string]map[int16]string) error { + typedefs map[string]map[string]map[int16]string, eventTable *EventsTable) error { if out == nil || in == nil { return nil } @@ -416,36 +486,52 @@ func (o *Output) printEvents(out *bufio.Writer, in *bufio.Reader, evdefs map[uin *TimeFactor = 1.0 / float64(ev.Value1) } } + eventRecord := EventRecord{ + Index: no, + Time: beforeClockEvent + TimeInSecs(ev.Time-lastClockEvent), + } var rep string if evdef, ok := evdefs[ev.Info.ID]; ok { - if ev.Info.ID == 0xFE00 && ev.Data != nil { // special case stdout - s := escapeGen(string(*ev.Data)) - _, err = fmt.Fprintf(out, "%5d %.8f %*s %*s \"%s\"\n", - no, beforeClockEvent+TimeInSecs(ev.Time-lastClockEvent), - -o.componentSize, evdef.Brief, -o.propertySize, evdef.Property, s) - } else { - rep, err = ev.EvalLine(evdef, typedefs) - if err == nil { - _, err = fmt.Fprintf(out, "%5d %.8f %*s %*s %s\n", - no, beforeClockEvent+TimeInSecs(ev.Time-lastClockEvent), - -o.componentSize, evdef.Brief, -o.propertySize, evdef.Property, rep) + // Filter events by level + if Level == "" || evdef.Level == Level { + eventRecord.Component = evdef.Brief + eventRecord.EventProperty = evdef.Property + if ev.Info.ID == 0xFE00 && ev.Data != nil { // special case stdout + s := escapeGen(string(*ev.Data)) + eventRecord.Value = s + err = conditionalWrite(out, "%5d %.8f %*s %*s \"%s\"\n", + eventRecord.Index, eventRecord.Time, -o.componentSize, + eventRecord.Component, -o.propertySize, eventRecord.EventProperty, eventRecord.Value) + } else { + rep, err = ev.EvalLine(evdef, typedefs) + if err == nil { + eventRecord.Value = rep + err = conditionalWrite(out, "%5d %.8f %*s %*s %s\n", + eventRecord.Index, eventRecord.Time, -o.componentSize, + eventRecord.Component, -o.propertySize, eventRecord.EventProperty, eventRecord.Value) + } } } } else { + eventRecord.Component = fmt.Sprintf("0x%02X%*s", uint8(ev.Info.ID>>8), 0, "") + eventRecord.EventProperty = fmt.Sprintf("0x%04X%*s", ev.Info.ID, 0, "") if ev.Info.ID == 0xFE00 && ev.Data != nil { // special case stdout s := escapeGen(string(*ev.Data)) - _, err = fmt.Fprintf(out, "%5d %.8f 0x%02X%*s 0x%04X%*s \"%s\"\n", - no, beforeClockEvent+TimeInSecs(ev.Time-lastClockEvent), + eventRecord.Value = s + err = conditionalWrite(out, "%5d %.8f 0x%02X%*s 0x%04X%*s \"%s\"\n", + eventRecord.Index, eventRecord.Time, uint8(ev.Info.ID>>8), -(o.componentSize - 4), "", - ev.Info.ID, -(o.propertySize - 6), "", s) + ev.Info.ID, -(o.propertySize - 6), "", eventRecord.Value) } else { rep = ev.GetValuesAsString() - _, err = fmt.Fprintf(out, "%5d %.8f 0x%02X%*s 0x%04X%*s %s\n", - no, beforeClockEvent+TimeInSecs(ev.Time-lastClockEvent), + eventRecord.Value = rep + err = conditionalWrite(out, "%5d %.8f 0x%02X%*s 0x%04X%*s %s\n", + eventRecord.Index, eventRecord.Time, uint8(ev.Info.ID>>8), -(o.componentSize - 4), "", - ev.Info.ID, -(o.propertySize - 6), "", rep) + ev.Info.ID, -(o.propertySize - 6), "", eventRecord.Value) } } + eventTable.Events = append(eventTable.Events, eventRecord) if err != nil { break } @@ -456,24 +542,24 @@ func (o *Output) printEvents(out *bufio.Writer, in *bufio.Reader, evdefs map[uin func (o *Output) printHeader(out *bufio.Writer) error { var err error - if _, err = out.WriteString(" Detailed event list\n"); err != nil { + if err = conditionalWrite(out, " Detailed event list\n"); err != nil { return err } - if _, err = out.WriteString(" -------------------\n\n"); err != nil { + if err = conditionalWrite(out, " -------------------\n\n"); err != nil { return err } - _, err = fmt.Fprintf(out, "%5s %-10s %*s %*s %s\n", o.columns[0], o.columns[1], + err = conditionalWrite(out, "%5s %-10s %*s %*s %s\n", o.columns[0], o.columns[1], -o.componentSize, o.columns[2], -o.propertySize, o.columns[3], o.columns[4]) if err != nil { return err } - _, err = fmt.Fprintf(out, "----- -------- %*s %*s -----\n", + err = conditionalWrite(out, "----- -------- %*s %*s -----\n", -o.componentSize, "---------", -o.propertySize, "--------------") return err } func (o *Output) print(out *bufio.Writer, eventFile *string, evdefs map[uint16]scvd.Event, - typedefs map[string]map[string]map[int16]string, statBegin bool, showStatistic bool) error { + typedefs map[string]map[string]map[int16]string, statBegin bool, showStatistic bool, eventsTable *EventsTable) error { var b event.Binary var err error var eventCount int @@ -492,9 +578,9 @@ func (o *Output) print(out *bufio.Writer, eventFile *string, evdefs map[uint16]s } if err == nil && statBegin { - err = o.printStatistic(out, eventCount) + err = o.printStatistic(out, eventCount, eventsTable) if err == nil && !showStatistic { - _, err = out.WriteString("\n") + err = conditionalWrite(out, "\n") } } @@ -503,7 +589,7 @@ func (o *Output) print(out *bufio.Writer, eventFile *string, evdefs map[uint16]s if err == nil { in = b.Open(eventFile) if in != nil { - err = o.printEvents(out, in, evdefs, typedefs) + err = o.printEvents(out, in, evdefs, typedefs, eventsTable) if err != nil { _ = b.Close() } else { @@ -517,31 +603,43 @@ func (o *Output) print(out *bufio.Writer, eventFile *string, evdefs map[uint16]s if err == nil && !statBegin { if !showStatistic { - _, err = out.WriteString("\n") + err = conditionalWrite(out, "\n") } if err == nil { - err = o.printStatistic(out, eventCount) + err = o.printStatistic(out, eventCount, eventsTable) } } - if err == nil { err = out.Flush() } return err } -func Print(filename *string, eventFile *string, evdefs map[uint16]scvd.Event, +func Print(filename *string, formatType *string, level *string, eventFile *string, evdefs map[uint16]scvd.Event, typedefs map[string]map[string]map[int16]string, statBegin bool, showStatistic bool) error { var file *os.File var err error var o Output + eventsTable := EventsTable{ + Events: []EventRecord{}, + Statistics: []EventRecordStatistic{}, + } + if TimeFactor == nil { TimeFactor = new(float64) } if *TimeFactor == 0.0 { *TimeFactor = 4e-8 } + if formatType != nil { + if *formatType == "xml" || *formatType == "json" { + FormatType = *formatType + } + } + if level != nil && *level != "" { + Level = *level + } if filename != nil && len(*filename) != 0 { if file, err = os.Create(*filename); err != nil { @@ -553,9 +651,29 @@ func Print(filename *string, eventFile *string, evdefs map[uint16]scvd.Event, } out := bufio.NewWriter(file) - err = o.print(out, eventFile, evdefs, typedefs, statBegin, showStatistic) + err = o.print(out, eventFile, evdefs, typedefs, statBegin, showStatistic, &eventsTable) if err == nil { - err = out.Flush() + if FormatType == "json" { + output, err := json.Marshal(eventsTable) + if err == nil { + buf := bytes.NewBuffer(output) + _, err = fmt.Fprint(out, buf) + if err == nil { + out.Flush() + } + } + } else if FormatType == "xml" { + output, err := xml.Marshal(eventsTable) + if err == nil { + buf := bytes.NewBuffer(output) + _, err = fmt.Fprint(out, buf) + if err == nil { + out.Flush() + } + } + } else { + err = out.Flush() + } } else { _ = out.Flush() } diff --git a/tools/eventlist/output/output_test.go b/tools/eventlist/pkg/output/output_test.go similarity index 84% rename from tools/eventlist/output/output_test.go rename to tools/eventlist/pkg/output/output_test.go index 5288a92..4884764 100644 --- a/tools/eventlist/output/output_test.go +++ b/tools/eventlist/pkg/output/output_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,8 +22,8 @@ import ( "bufio" "bytes" "errors" - "eventlist/event" - "eventlist/xml/scvd" + "eventlist/pkg/event" + "eventlist/pkg/xml/scvd" "fmt" "io" "math" @@ -609,11 +609,11 @@ func TestOutput_buildStatistic(t *testing.T) { //nolint:golint,paralleltest tds := make(map[string]map[string]map[int16]string) - var s1 = "../testdata/test1.binary" - var s3 = "../testdata/test3.binary" - var s4 = "../testdata/test4.binary" - var s6 = "../testdata/test6.binary" - var s7 = "../testdata/test7.binary" + var s1 = "../../testdata/test1.binary" + var s3 = "../../testdata/test3.binary" + var s4 = "../../testdata/test4.binary" + var s6 = "../../testdata/test6.binary" + var s7 = "../../testdata/test7.binary" type fields struct { evProps [4]eventProperty @@ -701,6 +701,10 @@ func TestOutput_printStatistic(t *testing.T) { //nolint:golint,paralleltest {"header", fields{props0, 15, 20}, args{nil, 1}, header, false}, {"line1", fields{props1, 15, 20}, args{nil, 1}, header + line1, false}, } + eventsTable := EventsTable{ + Events: []EventRecord{}, + Statistics: []EventRecordStatistic{}, + } for _, tt := range tests { //nolint:golint,paralleltest t.Run(tt.name, func(t *testing.T) { tt.args.out = bufio.NewWriter(&b) @@ -709,7 +713,7 @@ func TestOutput_printStatistic(t *testing.T) { //nolint:golint,paralleltest componentSize: tt.fields.componentSize, propertySize: tt.fields.propertySize, } - if err := o.printStatistic(tt.args.out, tt.args.eventCount); (err != nil) != tt.wantErr { + if err := o.printStatistic(tt.args.out, tt.args.eventCount, &eventsTable); (err != nil) != tt.wantErr { t.Errorf("Output.printStatistic() error = %v, wantErr %v", err, tt.wantErr) } tt.args.out.Flush() @@ -766,11 +770,11 @@ func TestOutput_printEvents(t *testing.T) { //nolint:golint,paralleltest eds[0xFE00] = scvd.Event{Brief: "briefbriefbrief", Property: "propertypropertyproperty", Value: "value"} eds[0xFF03] = scvd.Event{Brief: "briefbriefbrief", Property: "propertypropertyproperty", Value: "value"} - var s0 = "../testdata/test0.binary" - var s1 = "../testdata/test1.binary" - var s10 = "../testdata/test10.binary" - var s11 = "../testdata/test11.binary" - var sNix = "../testdata/xxxx" + var s0 = "../../testdata/test0.binary" + var s1 = "../../testdata/test1.binary" + var s10 = "../../testdata/test10.binary" + var s11 = "../../testdata/test11.binary" + var sNix = "../../testdata/xxxx" line1 := " 0 0.00000124 0xFF 0xFF03 val1=0x00000004, val2=0x00000002\n" + " 1 0.00000124 0xFE 0xFE00 \"hello wo\"\n" @@ -806,6 +810,10 @@ func TestOutput_printEvents(t *testing.T) { //nolint:golint,paralleltest {"read3", fields{}, args{}, &s11, line3, false}, {"readNix", fields{}, args{}, &sNix, "", false}, } + eventsTable := EventsTable{ + Events: []EventRecord{}, + Statistics: []EventRecordStatistic{}, + } for _, tt := range tests { //nolint:golint,paralleltest t.Run(tt.name, func(t *testing.T) { tt.args.out = bufio.NewWriter(&b) @@ -819,7 +827,7 @@ func TestOutput_printEvents(t *testing.T) { //nolint:golint,paralleltest componentSize: tt.fields.componentSize, propertySize: tt.fields.propertySize, } - if err := o.printEvents(tt.args.out, tt.args.in, tt.args.evdefs, tt.args.typedefs); (err != nil) != tt.wantErr { + if err := o.printEvents(tt.args.out, tt.args.in, tt.args.evdefs, tt.args.typedefs, &eventsTable); (err != nil) != tt.wantErr { t.Errorf("Output.printEvents() %s error = %v, wantErr %v", tt.name, err, tt.wantErr) } tt.args.out.Flush() @@ -900,9 +908,9 @@ func TestOutput_printHeader(t *testing.T) { //nolint:golint,paralleltest func TestOutput_print(t *testing.T) { //nolint:golint,paralleltest var b bytes.Buffer - // var e0 = "../testdata/test.xml" - var s10 = "../testdata/test10.binary" - var s11 = "../testdata/nix.binary" + // var e0 = "../../testdata/test.xml" + var s10 = "../../testdata/test10.binary" + var s11 = "../../testdata/nix.binary" line1 := " Detailed event list\n" + " -------------------\n\n" + @@ -952,6 +960,10 @@ func TestOutput_print(t *testing.T) { //nolint:golint,paralleltest {"statEnd", fields{}, args{eventFile: &s10}, line1, false}, {"statBegin", fields{}, args{eventFile: &s10, statBegin: true}, line2, false}, } + eventsTable := EventsTable{ + Events: []EventRecord{}, + Statistics: []EventRecordStatistic{}, + } for _, tt := range tests { //nolint:golint,paralleltest t.Run(tt.name, func(t *testing.T) { tt.args.out = bufio.NewWriter(&b) @@ -963,7 +975,7 @@ func TestOutput_print(t *testing.T) { //nolint:golint,paralleltest componentSize: tt.fields.componentSize, propertySize: tt.fields.propertySize, } - if err := o.print(tt.args.out, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic); (err != nil) != tt.wantErr { + if err := o.print(tt.args.out, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic, &eventsTable); (err != nil) != tt.wantErr { t.Errorf("Output.print() error = %v, wantErr %v", err, tt.wantErr) } tt.args.out.Flush() @@ -981,7 +993,7 @@ func TestOutput_print(t *testing.T) { //nolint:golint,paralleltest func TestPrint(t *testing.T) { //nolint:golint,paralleltest o1 := "testOutput.out" - var s10 = "../testdata/test10.binary" + var s10 = "../../testdata/test10.binary" lines1 := [...]string{ " Detailed event list\n", @@ -1006,6 +1018,8 @@ func TestPrint(t *testing.T) { //nolint:golint,paralleltest statBegin bool showStatistic bool } + formatType := "txt" + level := "" tests := []struct { name string args args @@ -1017,7 +1031,7 @@ func TestPrint(t *testing.T) { //nolint:golint,paralleltest t.Run(tt.name, func(t *testing.T) { TimeFactor = nil defer os.Remove(*tt.args.filename) - if err := Print(tt.args.filename, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic); (err != nil) != tt.wantErr { + if err := Print(tt.args.filename, &formatType, &level, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic); (err != nil) != tt.wantErr { t.Errorf("Print() error = %v, wantErr %v", err, tt.wantErr) } file, err := os.Open(*tt.args.filename) @@ -1051,3 +1065,125 @@ func TestPrint(t *testing.T) { //nolint:golint,paralleltest }) } } + +func TestPrintJSON(t *testing.T) { //nolint:golint,paralleltest + o1 := "testOutput.json" + + var s10 = "../../testdata/test10.binary" + + lines1 := [...]string{ + "{\"events\":[{\"index\":0,\"time\":7.75,\"component\":\"0xFF\",\"eventProperty\":\"0xFF03\",\"value\":\"val1=0x00000004, val2=0x00000002\"},{\"index\":1,\"time\":7.75,\"component\":\"0xFE\",\"eventProperty\":\"0xFE00\",\"value\":\"hello wo\"}],\"statistics\":[]}", + } + + type args struct { + filename *string + eventFile *string + evdefs map[uint16]scvd.Event + typedefs map[string]map[string]map[int16]string + statBegin bool + showStatistic bool + } + formatType := "json" + level := "" + tests := []struct { + name string + args args + wantErr bool + }{ + {"test1", args{filename: &o1, eventFile: &s10}, false}, + } + for _, tt := range tests { //nolint:golint,paralleltest + t.Run(tt.name, func(t *testing.T) { + TimeFactor = nil + defer os.Remove(*tt.args.filename) + if err := Print(tt.args.filename, &formatType, &level, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic); (err != nil) != tt.wantErr { + t.Errorf("Print() error = %v, wantErr %v", err, tt.wantErr) + } + file, err := os.Open(*tt.args.filename) + if err != nil { + t.Errorf("Print() error = %v, output file not created", err) + } + if file != nil { + in := bufio.NewReader(file) + var l string + end := false + for _, l = range lines1 { + line, _ := in.ReadString('\n') + if line != l { + t.Errorf("Print() %s = %v, want %v", tt.name, line, l) + } + } + line, err := in.ReadString('\n') + if errors.Is(err, io.EOF) { + end = true + } else { + t.Errorf("Print() %s = %v, want EOF", tt.name, line) + } + if !end { + t.Errorf("Print() %s = EOF, want %v", tt.name, l) + } + } + }) + } +} + +func TestPrintXML(t *testing.T) { //nolint:golint,paralleltest + o1 := "testOutput.xml" + + var s10 = "../../testdata/test10.binary" + + lines1 := [...]string{ + "00xFF0xFF03val1=0x00000004, val2=0x0000000210xFE0xFE00hello wo", + } + + type args struct { + filename *string + eventFile *string + evdefs map[uint16]scvd.Event + typedefs map[string]map[string]map[int16]string + statBegin bool + showStatistic bool + } + formatType := "xml" + level := "" + tests := []struct { + name string + args args + wantErr bool + }{ + {"test", args{filename: &o1, eventFile: &s10}, false}, + } + for _, tt := range tests { //nolint:golint,paralleltest + t.Run(tt.name, func(t *testing.T) { + TimeFactor = nil + defer os.Remove(*tt.args.filename) + if err := Print(tt.args.filename, &formatType, &level, tt.args.eventFile, tt.args.evdefs, tt.args.typedefs, tt.args.statBegin, tt.args.showStatistic); (err != nil) != tt.wantErr { + t.Errorf("Print() error = %v, wantErr %v", err, tt.wantErr) + } + file, err := os.Open(*tt.args.filename) + if err != nil { + t.Errorf("Print() error = %v, output file not created", err) + } + if file != nil { + in := bufio.NewReader(file) + var l string + end := false + for _, l = range lines1 { + line, _ := in.ReadString('\n') + if line != l { + t.Errorf("Print() %s = %v, want %v", tt.name, line, l) + } + } + line, err := in.ReadString('\n') + if errors.Is(err, io.EOF) { + end = true + } else { + t.Errorf("Print() %s = %v, want EOF", tt.name, line) + } + if !end { + t.Errorf("Print() %s = EOF, want %v", tt.name, l) + } + } + }) + } +} diff --git a/tools/eventlist/xml/scvd/scvd.go b/tools/eventlist/pkg/xml/scvd/scvd.go similarity index 98% rename from tools/eventlist/xml/scvd/scvd.go rename to tools/eventlist/pkg/xml/scvd/scvd.go index 2097cb6..1e4ca1d 100644 --- a/tools/eventlist/xml/scvd/scvd.go +++ b/tools/eventlist/pkg/xml/scvd/scvd.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -21,7 +21,7 @@ package scvd import ( "encoding/xml" "errors" - "eventlist/eval" + "eventlist/pkg/eval" "os" "strconv" "strings" diff --git a/tools/eventlist/xml/scvd/scvd_test.go b/tools/eventlist/pkg/xml/scvd/scvd_test.go similarity index 90% rename from tools/eventlist/xml/scvd/scvd_test.go rename to tools/eventlist/pkg/xml/scvd/scvd_test.go index 2300e4f..cfc3472 100644 --- a/tools/eventlist/xml/scvd/scvd_test.go +++ b/tools/eventlist/pkg/xml/scvd/scvd_test.go @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -24,8 +24,8 @@ import ( ) func TestComponentViewer_getFromFile(t *testing.T) { - var name = "../../testdata/test.xml" - var wrongName = "../../testdata/xxxxx" + var name = "../../../testdata/test.xml" + var wrongName = "../../../testdata/xxxxx" type fields struct { Component Component @@ -120,11 +120,11 @@ func TestID_getIdValue(t *testing.T) { } func Test_getOne(t *testing.T) { - var name = "../../testdata/test.xml" - var wrongName = "../../testdata/xxxxx" - var nameErr1 = "../../testdata/test_err1.xml" - var nameErr2 = "../../testdata/test_err2.xml" - var nameErr3 = "../../testdata/test_err3.xml" + var name = "../../../testdata/test.xml" + var wrongName = "../../../testdata/xxxxx" + var nameErr1 = "../../../testdata/test_err1.xml" + var nameErr2 = "../../../testdata/test_err2.xml" + var nameErr3 = "../../../testdata/test_err3.xml" var evs = make(map[uint16]Event) var tds = make(map[string]map[string]map[int16]string) @@ -166,8 +166,8 @@ func Test_getOne(t *testing.T) { } func TestGet(t *testing.T) { - var files = []string{"../../testdata/test.xml"} - var files1 = []string{"../../testdata/xxxxx"} + var files = []string{"../../../testdata/test.xml"} + var files1 = []string{"../../../testdata/xxxxx"} var evs = make(map[uint16]Event) var tds = make(map[string]map[string]map[int16]string) diff --git a/tools/eventlist/testdata/test12.binary b/tools/eventlist/testdata/test12.binary new file mode 100644 index 0000000..0942090 Binary files /dev/null and b/tools/eventlist/testdata/test12.binary differ diff --git a/tools/eventlist/testdata/test13.binary b/tools/eventlist/testdata/test13.binary new file mode 100644 index 0000000..9415cb1 Binary files /dev/null and b/tools/eventlist/testdata/test13.binary differ diff --git a/tools/eventlist/testdata/test8.binary b/tools/eventlist/testdata/test8.binary new file mode 100644 index 0000000..01a773b Binary files /dev/null and b/tools/eventlist/testdata/test8.binary differ diff --git a/tools/eventlist/testdata/test9.binary b/tools/eventlist/testdata/test9.binary new file mode 100644 index 0000000..574bc74 Binary files /dev/null and b/tools/eventlist/testdata/test9.binary differ diff --git a/tools/eventlist/versioninfo.go b/tools/eventlist/versioninfo.go deleted file mode 100644 index feeb815..0000000 --- a/tools/eventlist/versioninfo.go +++ /dev/null @@ -1,56 +0,0 @@ -// Auto-generated file by goversioninfo. Do not edit. -package main - -import ( - "encoding/json" - - "github.com/josephspurrier/goversioninfo" -) - -func unmarshalGoVersionInfo(b []byte) goversioninfo.VersionInfo { - vi := goversioninfo.VersionInfo{} - json.Unmarshal(b, &vi) - return vi -} - -var versionInfo = unmarshalGoVersionInfo([]byte(`{ - "FixedFileInfo":{ - "FileVersion": { - "Major": 1, - "Minor": 0, - "Patch": 10, - "Build": 0 - }, - "ProductVersion": { - "Major": 1, - "Minor": 0, - "Patch": 10, - "Build": 0 - }, - "FileFlagsMask": "3f", - "FileFlags": "", - "FileOS": "040004", - "FileType": "01", - "FileSubType": "00" - }, - "StringFileInfo":{ - "Comments": "", - "CompanyName": "ARM Limited", - "FileDescription": "", - "FileVersion": "1.0.10.0", - "InternalName": "eventlist", - "LegalCopyright": "Copyright (C) 2022 ARM Limited or its Affiliates. All rights reserved.", - "LegalTrademarks": "", - "OriginalFilename": "eventlist", - "PrivateBuild": "", - "ProductName": "eventlist", - "ProductVersion": "1.0.10.0", - "SpecialBuild": "" - }, - "VarFileInfo":{ - "Translation": { - "LangID": 1033, - "CharsetID": 1200 - } - } -}`)) diff --git a/tools/eventlist/versioninfo.json b/tools/eventlist/versioninfo.json deleted file mode 100644 index 9542326..0000000 --- a/tools/eventlist/versioninfo.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "FixedFileInfo": { - "FileVersion": { - "Major": 1, - "Minor": 0, - "Patch": 10, - "Build": 0 - }, - "ProductVersion": { - "Major": 1, - "Minor": 0, - "Patch": 10, - "Build": 0 - }, - "FileFlagsMask": "3f", - "FileFlags ": "00", - "FileOS": "040004", - "FileType": "01", - "FileSubType": "00" - }, - "StringFileInfo": { - "Comments": "", - "CompanyName": "ARM Limited", - "FileDescription": "", - "FileVersion": "1.0.10.0", - "InternalName": "eventlist", - "LegalCopyright": "Copyright (C) 2022 ARM Limited or its Affiliates. All rights reserved.", - "LegalTrademarks": "", - "OriginalFilename": "eventlist", - "PrivateBuild": "", - "ProductName": "eventlist", - "ProductVersion": "1.0.10.0", - "SpecialBuild": "" - }, - "VarFileInfo": { - "Translation": { - "LangID": "0409", - "CharsetID": "04B0" - } - }, - "IconPath": "", - "ManifestPath": "" -}