diff --git a/test/data/include-define/project/asm.s b/test/data/include-define/project/asm.s new file mode 100644 index 00000000..583fb37e --- /dev/null +++ b/test/data/include-define/project/asm.s @@ -0,0 +1,21 @@ + + .syntax unified + .arch armv7-m + + .include "target.s" + .include "group.s" + .include "file.s" + + .ifndef TARGET_ASM_DEF + .error "TARGET_ASM_DEF is not defined!" + .endif + + .ifndef GROUP_ASM_DEF + .error "GROUP_ASM_DEF is not defined!" + .endif + + .ifndef FILE_ASM_DEF + .error "FILE_ASM_DEF is not defined!" + .endif + + .end diff --git a/test/data/include-define/project/file/file.s b/test/data/include-define/project/file/file.s new file mode 100644 index 00000000..4ce4571f --- /dev/null +++ b/test/data/include-define/project/file/file.s @@ -0,0 +1 @@ + .set FILE_ASM_DEF,1 diff --git a/test/data/include-define/project/group/group.s b/test/data/include-define/project/group/group.s new file mode 100644 index 00000000..13baea2a --- /dev/null +++ b/test/data/include-define/project/group/group.s @@ -0,0 +1 @@ + .set GROUP_ASM_DEF,1 diff --git a/test/data/include-define/project/inc3/inc.h b/test/data/include-define/project/inc3/inc.h index 2a9b5898..92dae9c7 100644 --- a/test/data/include-define/project/inc3/inc.h +++ b/test/data/include-define/project/inc3/inc.h @@ -1 +1 @@ -#define INC3 1 +#define INC3 1 diff --git a/test/data/include-define/project/project.AC6+ARMCM0.cbuild.yml b/test/data/include-define/project/project.AC6+ARMCM0.cbuild.yml new file mode 100644 index 00000000..22a44064 --- /dev/null +++ b/test/data/include-define/project/project.AC6+ARMCM0.cbuild.yml @@ -0,0 +1,181 @@ +build: + generated-by: csolution version 2.4.0-devint1 + solution: ../solution.csolution.yml + project: project.cproject.yml + context: project.AC6+ARMCM0 + compiler: AC6 + device: ARMCM0 + device-pack: ARM::Cortex_DFP@1.0.0 + processor: + fpu: off + core: Cortex-M0 + packs: + - pack: ARM::CMSIS@6.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0 + - pack: ARM::Cortex_DFP@1.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0 + misc: + ASM: + - -masm=auto + C: + - -std=gnu11 + - -Wno-macro-redefined + - -Wno-pragma-pack + - -Wno-parentheses-equality + - -Wno-license-management + CPP: + - -Wno-macro-redefined + - -Wno-pragma-pack + - -Wno-parentheses-equality + - -Wno-license-management + Link: + - --entry=Reset_Handler + - --map + - --info summarysizes + - --summary_stderr + - --diag_suppress=L6314W + define: + - ARMCM0 + - _RTE_ + define-asm: + - ARMCM0 + - _RTE_ + add-path-asm: + - target + - RTE/_AC6_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + add-path: + - RTE/_AC6_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + output-dirs: + intdir: ../tmp/project/ARMCM0/AC6 + outdir: ../out/project/ARMCM0/AC6 + rtedir: RTE + output: + - type: elf + file: project.axf + components: + - component: ARM::CMSIS:CORE@6.0.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@6.0.0 + selected-by: ARM::CMSIS:CORE + undefine: + - DEF1 + del-path: + - inc1 + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + category: include + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include/tz_context.h + category: header + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/main_s.c + category: sourceC + attr: template + version: 1.1.1 + select: Secure mode 'main' module for ARMv8-M + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/tz_context.c + category: sourceC + attr: template + version: 1.1.1 + select: RTOS Context Management (TrustZone for ARMv8-M) + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Documentation/html/Core/index.html + category: doc + version: 6.0.0 + - component: ARM::Device:Startup&C Startup@2.2.0 + condition: ARMCM0 CMSIS + from-pack: ARM::Cortex_DFP@1.0.0 + selected-by: ARM::Device:Startup&C Startup + define: + - DEF2: 1 + add-path: + - inc2 + add-path-asm: + - component + files: + - file: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include/ARMCM0.h + category: header + version: 2.2.0 + - file: RTE/Device/ARMCM0/ARMCM0_ac6.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/ARMCM0/startup_ARMCM0.c + category: sourceC + attr: config + version: 2.0.3 + - file: RTE/Device/ARMCM0/system_ARMCM0.c + category: sourceC + attr: config + version: 1.0.0 + linker: + script: RTE/Device/ARMCM0/ARMCM0_ac6.sct + groups: + - group: Source1 + define: + - DEF1: 1 + add-path: + - inc1 + add-path-asm: + - group + files: + - file: asm.s + category: sourceAsm + add-path-asm: + - file + - file: source1.c + category: sourceC + - file: source3.c + category: sourceC + define: + - DEF3 + undefine: + - DEF1 + add-path: + - inc3 + del-path: + - inc1 + groups: + - group: Source2 + define: + - DEF2: 1 + undefine: + - DEF1 + add-path: + - inc2 + del-path: + - inc1 + files: + - file: source2.c + category: sourceC + - group: Main + files: + - file: main.c + category: sourceC + define: + - DEF2 + add-path: + - inc2 + - group: Headers + files: + - file: inc1/inc.h + category: header + constructed-files: + - file: RTE/_AC6_ARMCM0/RTE_Components.h + category: header + licenses: + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/LICENSE + packs: + - pack: ARM::CMSIS@6.0.0 + components: + - component: ARM::CMSIS:CORE@6.0.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/LICENSE + packs: + - pack: ARM::Cortex_DFP@1.0.0 + components: + - component: ARM::Device:Startup&C Startup@2.2.0 diff --git a/test/data/include-define/project/project.CLANG+ARMCM0.cbuild.yml b/test/data/include-define/project/project.CLANG+ARMCM0.cbuild.yml new file mode 100644 index 00000000..fc9ce1e4 --- /dev/null +++ b/test/data/include-define/project/project.CLANG+ARMCM0.cbuild.yml @@ -0,0 +1,173 @@ +build: + generated-by: csolution version 2.4.0-devint1 + solution: ../solution.csolution.yml + project: project.cproject.yml + context: project.CLANG+ARMCM0 + compiler: CLANG + device: ARMCM0 + device-pack: ARM::Cortex_DFP@1.0.0 + processor: + fpu: off + core: Cortex-M0 + packs: + - pack: ARM::CMSIS@6.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0 + - pack: ARM::Cortex_DFP@1.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0 + misc: + C: + - -std=gnu11 + - -fomit-frame-pointer + - -ffunction-sections + - -fdata-sections + CPP: + - -fomit-frame-pointer + - -ffunction-sections + - -fdata-sections + Link: + - -lcrt0-semihost + - -lsemihost + - -Wl,-Map=../out/project/ARMCM0/CLANG/project.elf.map + - -Wl,--gc-sections + define: + - ARMCM0 + - _RTE_ + define-asm: + - ARMCM0 + - _RTE_ + add-path-asm: + - target + - RTE/_CLANG_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + add-path: + - RTE/_CLANG_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + output-dirs: + intdir: ../tmp/project/ARMCM0/CLANG + outdir: ../out/project/ARMCM0/CLANG + rtedir: RTE + output: + - type: elf + file: project.elf + components: + - component: ARM::CMSIS:CORE@6.0.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@6.0.0 + selected-by: ARM::CMSIS:CORE + undefine: + - DEF1 + del-path: + - inc1 + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + category: include + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include/tz_context.h + category: header + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/main_s.c + category: sourceC + attr: template + version: 1.1.1 + select: Secure mode 'main' module for ARMv8-M + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/tz_context.c + category: sourceC + attr: template + version: 1.1.1 + select: RTOS Context Management (TrustZone for ARMv8-M) + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Documentation/html/Core/index.html + category: doc + version: 6.0.0 + - component: ARM::Device:Startup&C Startup@2.2.0 + condition: ARMCM0 CMSIS + from-pack: ARM::Cortex_DFP@1.0.0 + selected-by: ARM::Device:Startup&C Startup + define: + - DEF2: 1 + add-path: + - inc2 + add-path-asm: + - component + files: + - file: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include/ARMCM0.h + category: header + version: 2.2.0 + - file: RTE/Device/ARMCM0/startup_ARMCM0.c + category: sourceC + attr: config + version: 2.0.3 + - file: RTE/Device/ARMCM0/system_ARMCM0.c + category: sourceC + attr: config + version: 1.0.0 + linker: + script: RTE/Device/ARMCM0/clang_linker_script.ld.src + regions: RTE/Device/ARMCM0/regions_ARMCM0.h + groups: + - group: Source1 + define: + - DEF1: 1 + add-path: + - inc1 + add-path-asm: + - group + files: + - file: asm.s + category: sourceAsm + add-path-asm: + - file + - file: source1.c + category: sourceC + - file: source3.c + category: sourceC + define: + - DEF3 + undefine: + - DEF1 + add-path: + - inc3 + del-path: + - inc1 + groups: + - group: Source2 + define: + - DEF2: 1 + undefine: + - DEF1 + add-path: + - inc2 + del-path: + - inc1 + files: + - file: source2.c + category: sourceC + - group: Main + files: + - file: main.c + category: sourceC + define: + - DEF2 + add-path: + - inc2 + - group: Headers + files: + - file: inc1/inc.h + category: header + constructed-files: + - file: RTE/_CLANG_ARMCM0/RTE_Components.h + category: header + licenses: + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/LICENSE + packs: + - pack: ARM::CMSIS@6.0.0 + components: + - component: ARM::CMSIS:CORE@6.0.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/LICENSE + packs: + - pack: ARM::Cortex_DFP@1.0.0 + components: + - component: ARM::Device:Startup&C Startup@2.2.0 diff --git a/test/data/include-define/project/project.GCC+ARMCM0.cbuild.yml b/test/data/include-define/project/project.GCC+ARMCM0.cbuild.yml new file mode 100644 index 00000000..c5b51a78 --- /dev/null +++ b/test/data/include-define/project/project.GCC+ARMCM0.cbuild.yml @@ -0,0 +1,178 @@ +build: + generated-by: csolution version 0.0.0+g447ad5d7 + solution: ../solution.csolution.yml + project: project.cproject.yml + context: project.GCC+ARMCM0 + compiler: GCC + device: ARMCM0 + device-pack: ARM::Cortex_DFP@1.0.0 + processor: + fpu: off + core: Cortex-M0 + packs: + - pack: ARM::CMSIS@6.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0 + - pack: ARM::Cortex_DFP@1.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0 + misc: + C: + - -std=gnu11 + - -masm-syntax-unified + - -fomit-frame-pointer + - -ffunction-sections + - -fdata-sections + CPP: + - -masm-syntax-unified + - -fomit-frame-pointer + - -ffunction-sections + - -fdata-sections + Link: + - --specs=nano.specs + - --specs=rdimon.specs + - -Wl,-Map=../out/project/ARMCM0/GCC/project.elf.map + - -Wl,--gc-sections + define: + - ARMCM0 + - _RTE_ + define-asm: + - ARMCM0 + - _RTE_ + add-path-asm: + - target + - RTE/_GCC_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + add-path: + - RTE/_GCC_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + output-dirs: + intdir: ../tmp/project/ARMCM0/GCC + outdir: ../out/project/ARMCM0/GCC + rtedir: RTE + output: + - type: elf + file: project.elf + components: + - component: ARM::CMSIS:CORE@6.0.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@6.0.0 + selected-by: ARM::CMSIS:CORE + undefine: + - DEF1 + del-path: + - inc1 + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + category: include + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include/tz_context.h + category: header + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/main_s.c + category: sourceC + attr: template + version: 1.1.1 + select: Secure mode 'main' module for ARMv8-M + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/tz_context.c + category: sourceC + attr: template + version: 1.1.1 + select: RTOS Context Management (TrustZone for ARMv8-M) + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Documentation/html/Core/index.html + category: doc + version: 6.0.0 + - component: ARM::Device:Startup&C Startup@2.2.0 + condition: ARMCM0 CMSIS + from-pack: ARM::Cortex_DFP@1.0.0 + selected-by: ARM::Device:Startup&C Startup + define: + - DEF2: 1 + add-path: + - inc2 + add-path-asm: + - component + files: + - file: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include/ARMCM0.h + category: header + version: 2.2.0 + - file: RTE/Device/ARMCM0/ARMCM0_gcc.ld + category: linkerScript + attr: config + version: 2.2.0 + - file: RTE/Device/ARMCM0/startup_ARMCM0.c + category: sourceC + attr: config + version: 2.0.3 + - file: RTE/Device/ARMCM0/system_ARMCM0.c + category: sourceC + attr: config + version: 1.0.0 + linker: + script: RTE/Device/ARMCM0/ARMCM0_gcc.ld + groups: + - group: Source1 + define: + - DEF1: 1 + add-path: + - inc1 + add-path-asm: + - group + files: + - file: asm.s + category: sourceAsm + add-path-asm: + - file + - file: source1.c + category: sourceC + - file: source3.c + category: sourceC + define: + - DEF3 + undefine: + - DEF1 + add-path: + - inc3 + del-path: + - inc1 + groups: + - group: Source2 + define: + - DEF2: 1 + undefine: + - DEF1 + add-path: + - inc2 + del-path: + - inc1 + files: + - file: source2.c + category: sourceC + - group: Main + files: + - file: main.c + category: sourceC + define: + - DEF2 + add-path: + - inc2 + - group: Headers + files: + - file: inc1/inc.h + category: header + constructed-files: + - file: RTE/_GCC_ARMCM0/RTE_Components.h + category: header + licenses: + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/LICENSE + packs: + - pack: ARM::CMSIS@6.0.0 + components: + - component: ARM::CMSIS:CORE@6.0.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/LICENSE + packs: + - pack: ARM::Cortex_DFP@1.0.0 + components: + - component: ARM::Device:Startup&C Startup@2.2.0 diff --git a/test/data/include-define/project/project.IAR+ARMCM0.cbuild.yml b/test/data/include-define/project/project.IAR+ARMCM0.cbuild.yml new file mode 100644 index 00000000..d38ea54b --- /dev/null +++ b/test/data/include-define/project/project.IAR+ARMCM0.cbuild.yml @@ -0,0 +1,162 @@ +build: + generated-by: csolution version 2.4.0-devint1 + solution: ../solution.csolution.yml + project: project.cproject.yml + context: project.IAR+ARMCM0 + compiler: IAR + device: ARMCM0 + device-pack: ARM::Cortex_DFP@1.0.0 + processor: + fpu: off + core: Cortex-M0 + packs: + - pack: ARM::CMSIS@6.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0 + - pack: ARM::Cortex_DFP@1.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0 + misc: + C: + - --dlib_config DLib_Config_Full.h + CPP: + - --dlib_config DLib_Config_Full.h + Link: + - --semihosting + - --map=../out/project/ARMCM0/IAR/project.out.map + define: + - ARMCM0 + - _RTE_ + define-asm: + - ARMCM0 + - _RTE_ + add-path-asm: + - target + - RTE/_IAR_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + add-path: + - RTE/_IAR_ARMCM0 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include + output-dirs: + intdir: ../tmp/project/ARMCM0/IAR + outdir: ../out/project/ARMCM0/IAR + rtedir: RTE + output: + - type: elf + file: project.out + components: + - component: ARM::CMSIS:CORE@6.0.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@6.0.0 + selected-by: ARM::CMSIS:CORE + undefine: + - DEF1 + del-path: + - inc1 + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + category: include + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include/tz_context.h + category: header + version: 6.0.0 + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/main_s.c + category: sourceC + attr: template + version: 1.1.1 + select: Secure mode 'main' module for ARMv8-M + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Template/ARMv8-M/tz_context.c + category: sourceC + attr: template + version: 1.1.1 + select: RTOS Context Management (TrustZone for ARMv8-M) + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Documentation/html/Core/index.html + category: doc + version: 6.0.0 + - component: ARM::Device:Startup&C Startup@2.2.0 + condition: ARMCM0 CMSIS + from-pack: ARM::Cortex_DFP@1.0.0 + selected-by: ARM::Device:Startup&C Startup + define: + - DEF2: 1 + add-path: + - inc2 + add-path-asm: + - component + files: + - file: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM0/Include/ARMCM0.h + category: header + version: 2.2.0 + - file: RTE/Device/ARMCM0/startup_ARMCM0.c + category: sourceC + attr: config + version: 2.0.3 + - file: RTE/Device/ARMCM0/system_ARMCM0.c + category: sourceC + attr: config + version: 1.0.0 + linker: + script: RTE/Device/ARMCM0/iar_linker_script.icf.src + regions: RTE/Device/ARMCM0/regions_ARMCM0.h + groups: + - group: Source1 + define: + - DEF1: 1 + add-path: + - inc1 + add-path-asm: + - group + files: + - file: source1.c + category: sourceC + - file: source3.c + category: sourceC + define: + - DEF3 + undefine: + - DEF1 + add-path: + - inc3 + del-path: + - inc1 + groups: + - group: Source2 + define: + - DEF2: 1 + undefine: + - DEF1 + add-path: + - inc2 + del-path: + - inc1 + files: + - file: source2.c + category: sourceC + - group: Main + files: + - file: main.c + category: sourceC + define: + - DEF2 + add-path: + - inc2 + - group: Headers + files: + - file: inc1/inc.h + category: header + constructed-files: + - file: RTE/_IAR_ARMCM0/RTE_Components.h + category: header + licenses: + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/LICENSE + packs: + - pack: ARM::CMSIS@6.0.0 + components: + - component: ARM::CMSIS:CORE@6.0.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/LICENSE + packs: + - pack: ARM::Cortex_DFP@1.0.0 + components: + - component: ARM::Device:Startup&C Startup@2.2.0 diff --git a/test/data/include-define/project/project.cproject.yml b/test/data/include-define/project/project.cproject.yml index c6f1826b..1d6f2168 100644 --- a/test/data/include-define/project/project.cproject.yml +++ b/test/data/include-define/project/project.cproject.yml @@ -9,13 +9,30 @@ project: - component: ARM::Device:Startup&C Startup add-path: - ./inc2 + add-path-asm: + - ./component define: - DEF2: 1 groups: - group: Source1 + add-path-asm: + - ./group files: + - file: asm.s + for-context: [.AC6, .GCC, .CLANG] + add-path-asm: + - ./file - file: source1.c + - file: source3.c + add-path: + - ./inc3 + define: + - DEF3 + del-path: + - ./inc1 + undefine: + - DEF1 add-path: - ./inc1 define: @@ -40,11 +57,7 @@ project: - ./inc2 define: - DEF2 - del-path: - - ./not-supported - undefine: - - not-supported - group: Headers files: - - file: ./inc3/inc.h + - file: ./inc1/inc.h diff --git a/test/data/include-define/project/source3.c b/test/data/include-define/project/source3.c new file mode 100644 index 00000000..9b12bff7 --- /dev/null +++ b/test/data/include-define/project/source3.c @@ -0,0 +1,29 @@ +#include "inc.h" + +#ifdef INC1 +#error "INC1 is defined" +#endif + +#ifdef INC2 +#error "INC2 is defined" +#endif + +#ifndef INC3 +#error "INC3 is not defined" +#endif + +#ifdef DEF1 +#error "DEF1 is defined" +#endif + +#ifdef DEF2 +#error "DEF2 is defined" +#endif + +#ifndef DEF3 +#error "DEF3 is not defined" +#endif + +int source3(void) { + return 0; +} diff --git a/test/data/include-define/project/target/target.s b/test/data/include-define/project/target/target.s new file mode 100644 index 00000000..98f8938a --- /dev/null +++ b/test/data/include-define/project/target/target.s @@ -0,0 +1 @@ + .set TARGET_ASM_DEF,1 diff --git a/test/data/include-define/solution.csolution.yml b/test/data/include-define/solution.csolution.yml index 748369db..5e946b58 100644 --- a/test/data/include-define/solution.csolution.yml +++ b/test/data/include-define/solution.csolution.yml @@ -8,6 +8,8 @@ solution: target-types: - type: ARMCM0 device: ARMCM0 + add-path-asm: + - ./project/target build-types: - type: AC6 @@ -15,7 +17,7 @@ solution: - type: GCC compiler: GCC - + # - type: IAR # compiler: IAR diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct new file mode 100644 index 00000000..5300b01c --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct @@ -0,0 +1,80 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct.base@1.0.0 b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct.base@1.0.0 new file mode 100644 index 00000000..5300b01c --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_ac6.sct.base@1.0.0 @@ -0,0 +1,80 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld new file mode 100644 index 00000000..93ed813c --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld @@ -0,0 +1,263 @@ +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 AT > FLASH +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld.base@2.2.0 b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld.base@2.2.0 new file mode 100644 index 00000000..93ed813c --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/ARMCM0_gcc.ld.base@2.2.0 @@ -0,0 +1,263 @@ +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 AT > FLASH +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/clang_linker_script.ld.src b/test/data/language-scope/project/RTE/Device/ARMCM0/clang_linker_script.ld.src new file mode 100644 index 00000000..db077496 --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/clang_linker_script.ld.src @@ -0,0 +1,374 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :text + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM0 AT>ROM0 :text + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :text +#endif + + .toc : { + *(.toc .toc.*) + } >ROM0 AT>ROM0 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM0 AT>ROM0 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM0 AT>ROM0 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM0 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM0 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/regions_ARMCM0.h b/test/data/language-scope/project/RTE/Device/ARMCM0/regions_ARMCM0.h new file mode 100644 index 00000000..c40d7aa7 --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/regions_ARMCM0.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM0_H +#define REGIONS_ARMCM0_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM::Cortex_DFP@1.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00040000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 +// + + +#endif /* REGIONS_ARMCM0_H */ diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c b/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 00000000..fb321109 --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0) + #include "ARMCM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 b/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 new file mode 100644 index 00000000..fb321109 --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0) + #include "ARMCM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c b/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 00000000..bf724aed --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V1.0.0 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c.base@1.0.0 b/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c.base@1.0.0 new file mode 100644 index 00000000..bf724aed --- /dev/null +++ b/test/data/language-scope/project/RTE/Device/ARMCM0/system_ARMCM0.c.base@1.0.0 @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V1.0.0 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/test/data/language-scope/project/RTE/_AC6_ARMCM0/RTE_Components.h b/test/data/language-scope/project/RTE/_AC6_ARMCM0/RTE_Components.h new file mode 100644 index 00000000..51a07537 --- /dev/null +++ b/test/data/language-scope/project/RTE/_AC6_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'project.AC6+ARMCM0' + * Target: 'AC6+ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/test/data/language-scope/project/RTE/_CLANG_ARMCM0/RTE_Components.h b/test/data/language-scope/project/RTE/_CLANG_ARMCM0/RTE_Components.h new file mode 100644 index 00000000..5dee6a87 --- /dev/null +++ b/test/data/language-scope/project/RTE/_CLANG_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'project.CLANG+ARMCM0' + * Target: 'CLANG+ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/test/data/language-scope/project/RTE/_GCC_ARMCM0/RTE_Components.h b/test/data/language-scope/project/RTE/_GCC_ARMCM0/RTE_Components.h new file mode 100644 index 00000000..66e15907 --- /dev/null +++ b/test/data/language-scope/project/RTE/_GCC_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'project.GCC+ARMCM0' + * Target: 'GCC+ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/test/data/language-scope/solution.csolution.yml b/test/data/language-scope/solution.csolution.yml index 172fc3c2..611a2223 100644 --- a/test/data/language-scope/solution.csolution.yml +++ b/test/data/language-scope/solution.csolution.yml @@ -23,7 +23,7 @@ solution: - -lc # - type: IAR - # compiler: IAR + # compiler: IAR - type: CLANG compiler: CLANG diff --git a/test/local_example_tests.robot b/test/local_example_tests.robot index 7e2f6ac5..f450d74d 100644 --- a/test/local_example_tests.robot +++ b/test/local_example_tests.robot @@ -29,34 +29,34 @@ ${Hello} Hello # Validate build-asm Example - ${TEST_DATA_DIR}${/}${build-asm}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${build-asm}${/}solution.csolution.yml ${Fail} ${Pass} Validate build-c Example - ${TEST_DATA_DIR}${/}${build-c}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${build-c}${/}solution.csolution.yml ${Pass} ${Pass} Validate build-cpp Example - ${TEST_DATA_DIR}${/}${build-cpp}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${build-cpp}${/}solution.csolution.yml ${Pass} ${Pass} Validate include-define Example - ${TEST_DATA_DIR}${/}${include-define}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${include-define}${/}solution.csolution.yml ${Pass} ${Pass} Validate language-scope Example - ${TEST_DATA_DIR}${/}${language-scope}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${language-scope}${/}solution.csolution.yml ${Fail} ${Pass} Validate linker-pre-processing Example - ${TEST_DATA_DIR}${/}${linker-pre-processing}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${linker-pre-processing}${/}solution.csolution.yml ${Pass} ${Pass} Validate pre-include Example - ${TEST_DATA_DIR}${/}${pre-include}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${pre-include}${/}solution.csolution.yml ${Pass} ${Pass} Validate whitespace Example - ${TEST_DATA_DIR}${/}${whitespace}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${whitespace}${/}solution.csolution.yml ${Pass} ${Pass} Validate trustzone Example - ${TEST_DATA_DIR}${/}${trustzone}${/}solution.csolution.yml ${Pass} + ${TEST_DATA_DIR}${/}${trustzone}${/}solution.csolution.yml ${Pass} ${Pass} *** Keywords *** Build Local CSolution Example - [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} - ${result}= Build CSolution Example ${input_file} ${expect} ${args} + [Arguments] ${input_file} ${cbuildgen_expect} ${cbuild2cmake_expect} ${args}=@{EMPTY} + ${result}= Build CSolution Example ${input_file} ${cbuildgen_expect} ${cbuild2cmake_expect} ${args} Should Be True ${result} diff --git a/test/pack_example_tests.robot b/test/pack_example_tests.robot index 5abd50ba..e55347de 100644 --- a/test/pack_example_tests.robot +++ b/test/pack_example_tests.robot @@ -2,6 +2,7 @@ Documentation Tests to build pack csolution examples Suite Setup Global Setup Suite Teardown Global Teardown +Test Teardown Global Teardown Library BuiltIn Library Collections Library DataDriver @@ -36,13 +37,15 @@ Test packs examples END Run Csolution Project - [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} + [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} ${contexts}= Get Contexts From Project ${input_file} ${expect} ${args} ${filcontexts}= Convert And Filter Contexts ${contexts} - @{args_ex} Create List @{args} @{filcontexts} + @{args_ex} Create List @{args} @{filcontexts} - ${res_cbuildgen}= Run Keyword And Ignore Error Build Example With cbuildgen ${input_file} ${expect} ${args_ex} - ${res_cbuild2cmake}= Run Keyword And Ignore Error Build Example with cbuild2cmake ${input_file} ${expect} ${args_ex} + ${res_cbuildgen}= Run Keyword And Ignore Error + ... Build Example With cbuildgen ${input_file} ${expect} ${args_ex} + ${res_cbuild2cmake}= Run Keyword And Ignore Error + ... Build Example with cbuild2cmake ${input_file} ${expect} ${args_ex} # Check the result of the first run ${success}= Set Variable ${res_cbuildgen[0]} diff --git a/test/remote_example_tests.robot b/test/remote_example_tests.robot index 8483dc8c..237da142 100644 --- a/test/remote_example_tests.robot +++ b/test/remote_example_tests.robot @@ -27,5 +27,5 @@ Test github examples Build Remote CSolution Example [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} - ${result}= Build CSolution Example ${input_file} ${expect} ${args} + ${result}= Build CSolution Example ${input_file} ${expect} ${expect} ${args} Should Be True ${result} diff --git a/test/resources/exec.resource b/test/resources/exec.resource index 8ab93d41..d8e19154 100644 --- a/test/resources/exec.resource +++ b/test/resources/exec.resource @@ -58,13 +58,14 @@ Install Pack [Arguments] ${pack_id} ${pack_root_dir} ${ret_code}= Run Program cpackget add ${pack_id} ... -R ${pack_root_dir} - ... --agree-embedded-license --force-reinstall + ... --agree-embedded-license --force-reinstall --no-dependencies RETURN ${ret_code} Get Contexts From Project [Documentation] Get list of contexts from the csolution project [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} ${parent_path}= Get Parent Directory Path ${input_file} + ${result} Run Process csolution list contexts ${input_File} ... -q shell=True stdout=${CURDIR}/stdout.txt ${ret_code}= Set Variable If ${result.rc} == ${0} ${result.rc} ${1} @@ -72,23 +73,27 @@ Get Contexts From Project RETURN ${result.stdout} Build CSolution Example - [Arguments] ${input_file} ${expect} ${args}=@{EMPTY} - ${res_cbuildgen}= Run Keyword And Ignore Error Build Example With cbuild2cmake ${input_file} ${expect} ${args} - ${res_cbuild2cmake}= Run Keyword And Ignore Error Build Example With cbuildgen ${input_file} ${expect} ${args} + [Arguments] ${input_file} ${cbuildgen_expect} ${cbuild2cmake_expect} ${args}=@{EMPTY} + Build Example With cbuild2cmake ${input_file} ${cbuild2cmake_expect} ${args} + Build Example With cbuildgen ${input_file} ${cbuildgen_expect} ${args} + + ${res_cbuild2cmake}= Run Keyword And Ignore Error Build Example With cbuild2cmake ${input_file} ${cbuild2cmake_expect} ${args} + ${res_cbuildgen}= Run Keyword And Ignore Error Build Example With cbuildgen ${input_file} ${cbuildgen_expect} ${args} + + # # Check the result of the first run + # ${success}= Set Variable ${res_cbuildgen[0]} + # ${message}= Set Variable ${res_cbuildgen[1]} + # Run Keyword If '${success}' == 'PASS' Log cbuildgen ran successfully + # ... ELSE Log cbuildgen failed with message: ${message} - # Check the result of the first run - ${success}= Set Variable ${res_cbuildgen[0]} - ${message}= Set Variable ${res_cbuildgen[1]} - Run Keyword If '${success}' == 'PASS' Log cbuildgen ran successfully - ... ELSE Log cbuildgen failed with message: ${message} + # # Check the result of the second run + # ${success}= Set Variable ${res_cbuild2cmake[0]} + # ${message}= Set Variable ${res_cbuild2cmake[1]} + # Run Keyword If '${success}' == 'PASS' Log cbuild2cmake ran successfully + # ... ELSE Log cbuild2cmake failed with message: ${message} - # Check the result of the second run - ${success}= Set Variable ${res_cbuild2cmake[0]} - ${message}= Set Variable ${res_cbuild2cmake[1]} - Run Keyword If '${success}' == 'PASS' Log cbuild2cmake ran successfully - ... ELSE Log cbuild2cmake failed with message: ${message} + # Should Be Equal ${res_cbuildgen[0]} ${res_cbuild2cmake[0]} build status doesn't match - Should Be Equal ${res_cbuildgen[0]} ${res_cbuild2cmake[0]} build status doesn't match ${parent_path}= Get Parent Directory Path ${input_file} ${result}= Run Keyword And Return ... Compare Elf Information ${input_file} diff --git a/test/resources/utils.resource b/test/resources/utils.resource index f74c29b9..2b2b1eed 100644 --- a/test/resources/utils.resource +++ b/test/resources/utils.resource @@ -19,6 +19,8 @@ Global Setup ${src_dir}= Join Paths ${parent_dir} ${Data} ${dest_dir}= Get Test Data Directory Set Global Variable ${TEST_DATA_DIR} ${dest_dir} + # Remove previous test data + Run Keyword And Ignore Error Remove Directory with Content ${TEST_DATA_DIR} # Copy test data under build tree Copy Directory ${src_dir} ${dest_dir} # Generate test_env.md file under output directory