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lines changed- .github/workflows/Documentation.yml+3-3
- .github/workflows/Processor.yml+1-1
- CHANGELOG.md+5
- README.md+2-1
- docs/Makefile+1-1
- docs/attrs.adoc+1-1
- docs/datasheet/cpu.adoc+86-33
- docs/datasheet/soc.adoc+13-3
- docs/datasheet/soc_imem.adoc+1-1
- docs/datasheet/soc_sysinfo.adoc+1-1
- docs/datasheet/soc_trng.adoc+23-32
- docs/datasheet/soc_twd.adoc+167
- docs/datasheet/soc_twi.adoc+9-4
- docs/datasheet/software_bootloader.adoc+8-1
- docs/figures/neorv32_processor.png
- docs/figures/twd_sequences.png
- docs/sources/twd_sequences.json+34
- docs/userguide/customizing_the_bootloader.adoc+1-1
- rtl/core/neorv32_bootloader_image.vhd+442-481
- rtl/core/neorv32_cpu_cp_muldiv.vhd+1-1
- rtl/core/neorv32_fifo.vhd+3-3
- rtl/core/neorv32_package.vhd+20-2
- rtl/core/neorv32_sysinfo.vhd+2-1
- rtl/core/neorv32_top.vhd+77-36
- rtl/core/neorv32_trng.vhd+35-53
- rtl/core/neorv32_twd.vhd+441
- rtl/core/neorv32_twi.vhd+5-5
- rtl/core/neorv32_xbus.vhd+1-1
- rtl/file_list_soc.f+1
- rtl/system_integration/neorv32_vivado_ip.tcl+8-1
- rtl/system_integration/neorv32_vivado_ip.vhd+19-1
- sim/ghdl.run.sh+1-1
- sim/neorv32_tb.vhd+108-64
- sim/sim_uart_rx.vhd+7-7
- sim/xbus_gateway.vhd+15-10
- sim/xbus_memory.vhd+65-18
- sw/bootloader/bootloader.c-8
- sw/bootloader/makefile+4-4
- sw/example/demo_trng/main.c+4-4
- sw/example/game_of_life/main.c+1-1
- sw/example/processor_check/main.c+34-15
- sw/lib/include/neorv32.h+7-6
- sw/lib/include/neorv32_sysinfo.h+1-1
- sw/lib/include/neorv32_trng.h+15-13
- sw/lib/include/neorv32_twd.h+92
- sw/lib/include/neorv32_twi.h+4-4
- sw/lib/source/neorv32_rte.c+1
- sw/lib/source/neorv32_trng.c+5-13
- sw/lib/source/neorv32_twd.c+244
- sw/svd/neorv32.svd+152-23
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