accessing MCLK/SCK on ECP5 (OrangeCrab)

[biosbob]

i'm starting to target a 25K OrangeCrab board, and ran into an issue when trying to bind the neorv32_top.xip_sck_o signal to a physical pin on the board.... with iCEBreaker, for instance, this binding is established in my constraints.pcf file....

trying something similar in my constraints.lpf file:

LOCATE COMP "OC_FLASH_SCK" SITE "U16";
IOBUF PORT "OC_FLASH_SCK" IO_TYPE=LVCMOS33;

indeed, the schematic for OrangeCrab shows U16 as the appropriate pin; the Lattice spreadsheets for this package confirm U16 as well

when i run synthesis using yosys, however, PNR fails as follows:

Info: pin 'OC_FLASH_SDO$tr_io' constrained to Bel 'X11/Y50/PIOA'.
Info: pin 'OC_FLASH_SDI$tr_io' constrained to Bel 'X13/Y50/PIOB'.
ERROR: IO pin 'OC_FLASH_SCK$tr_io' constrained to pin 'U16', which does not exist for package 'CSFBGA285'.
ERROR: Packing design failed.

looking online, there are suggestions that i use the USRMCLK primitive available through nextpnr/ecp5.... in general, my question is HOW do i actually use these primitives in my design????

the OrangeCrab example in neorv32_setups/osflow unfortunately doesn't use xip, so there is no need to bind a SPI clock; in fact, the (overspecified) OrangeCrab.lpf file does not even include a binding for this signal -- though the other SPI signal are included....

[GideonZ]

library ECP5U;
use ECP5U.components.all;

...

    u1: USRMCLK
    port map (
        USRMCLKI => flash_sck_o,
        USRMCLKTS => flash_sck_t  -- this cannot be a constant!
    );

[biosbob]

that's pretty simple.... but the latest version of ECP5. components only defines the EHXPLL component; adding a definition of USRMCLK was straightforward....

when i was fiddling around with the OrangeCrab_BoardTop_Minimal design the other day, i was able to increase the clock speed to 72MHz using the PLL; my design is a little more complex, and i was only able to get the clock to 40MHz....

question: can i simply use the 48MHz OSC on the board itself and skip the PLL altogether??? when i synthesize this design, all of the timing constraints are now passing....

[GideonZ]

Hi Biosbob,

I am using the ECP5U.components from the latest Diamond 3.12, so I think the USRMCLK should be there, since there is no extra component declaration in my architecture body.

I don't know the OrangeCrab board, nor its configuration, so I can't answer you what you need. But in general, whether a clock passes through a PLL or not, it doesn't really matter, as long as the timing constraints that describe the clock are correct, and the timing analyzer passes, you are good. Usually...

In my design I have a 100 MHz clock and a 50 MHz clock that need to be edge aligned, passing data in both directions over this boundary without a FIFO. In this case, it is good to have a bit of extra margin; the tools are not particularly good at estimating the clock skew in these scenarios. I even calibrate the clock phase of the PLL outputs in software before 'trusting' this clock transfer. Both clock outputs come from the same PLL and should have edge aligned outputs, but since the loading of the clock nets differs greatly, and the PLL has only one feedback to compensate for this, the edges are off. But hey, I don't think you are doing crazy stuff like that.

[biosbob]

for my use-case, i need a relatively small number of logic elements.... as i may have suggested above, i basically hit 95% on my iCEBreaker board and am now looking at something with more capacity.... i recently played with a CMOD-A7 -- though i find the vivado tools large and slow.... using yosys, i'm actually able to build larger designs faster for the ecp5 versus ice40!!! why, because i'm using ~20% of the logic elements, hence PNR completes much quicker....

assuming i can continue using yosys, what would you recommend for a "faster" FPGA dev board.... though my need for logic elements is quite modest (i'll easily fit in <25K), i would like to run my design in the 100MHz - 200MHz range.... i was able to hit 120MHz using CMOD-A7 -- but iterating on an evolving RTL design is very painful with vivado....

thoughts???

[stnolting]

Indeed, Vivado has become a real monster - but of course it also provides a lot of features including an unconstrained simulator.

If you want to switch to Intel (the IDE feels to be little bit smaller and way faster - at least for my old school FPGA boards) you might want to have a visit at Terasic. They provide pretty nice FPGA boards from all price segments: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=13&List=Simple

If you like to stick with Lattice the iCE40HX FPGAs might be of interest. The largest one has about 2x the LUT capacity of the ice40ultraplus - but with limited internal memory. Here is a (really cheap!) board I would recommend: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware