ASK_modulator.vt

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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "04/20/2024 06:47:33"
                                                                                
// Verilog Test Bench template for design : ASK_modulator
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ps
module ASK_modulator_tb();
reg button0;
reg button1;
reg button2;
reg button3;
reg switch_button;
reg clk;
reg rst;
// wires                                               
wire clk_dac;
wire [7:0]  data_out;

                        
ASK_modulator i1 (
	.button2(button2),
	.button3(button3),
	.switch_button(switch_button),
	.button0(button0),
	.button1(button1),
	.clk(clk),
	.clk_dac(clk_dac),
	.data_out(data_out),
	.rst(rst)
);
initial                                                
begin   		
clk<=0;  
rst<=1;
button0<=1;     
button1<=1;                                        
                      
#200 rst <= 0; // start 4ASK
#100 rst <= 1;

#100 button0 <= 0;
#100 button0 <= 1;

#100 button1 <= 0;
#100 button1 <= 1;

// input 01 to 4ASK

#100 switch_button <= 0;
#100 switch_button <= 1;


#100 button2 <= 0;// input 0
#100 button2 <= 1;


#100 button3 <= 0;// 1
#100 button3 <= 1;


#100000

// input 11 to ASK

#100 button3 <= 0;// input 1
#100 button3 <= 1;


#100 button3 <= 0;// 1
#100 button3 <= 1;


#1000
                                                                                                  
$display("Running testbench");                       
end                                                    
always #10 clk <= ~clk;                                                 
               
                                                    
endmodule