Crate arm_boards
source ·Expand description
Configuration and definitions for specific boards on aarch64 systems.
+Crate arm_boards
source ·Expand description
Configuration and definitions for specific boards on aarch64 systems.
| Board Name | Num CPUs | Interrupt Controller | Secondary CPU Startup Method |
|---|---|---|---|
| qemu_virt | 4 | GICv3 | PSCI |
Function device_manager::early_init
source · pub fn early_init(
+early_init in device_manager - Rust Function device_manager::early_init
source · pub fn early_init(
rsdp_address: Option<PhysicalAddress>,
kernel_mmi: &mut MemoryManagementInfo
) -> Result<(), &'static str>
Expand description
Performs early-stage initialization for simple devices needed during early boot.
diff --git a/doc/device_manager/fn.init.html b/doc/device_manager/fn.init.html
index 8659b5d2ba..c0b100196e 100644
--- a/doc/device_manager/fn.init.html
+++ b/doc/device_manager/fn.init.html
@@ -1,4 +1,4 @@
-init in device_manager - Rust Function device_manager::init
source · pub fn init(
+init in device_manager - Rust Function device_manager::init
source · pub fn init(
key_producer: Queue<Event>,
mouse_producer: Queue<Event>
) -> Result<(), &'static str>
Expand description
Initializes all other devices not initialized during early_init().
diff --git a/doc/device_manager/index.html b/doc/device_manager/index.html
index 8a72c8333e..36c1cc358e 100644
--- a/doc/device_manager/index.html
+++ b/doc/device_manager/index.html
@@ -1,2 +1,2 @@
device_manager - Rust Crate device_manager
source · Functions
- Performs early-stage initialization for simple devices needed during early boot.
- Initializes all other devices not initialized during
early_init().
All Items Crate device_manager
source · Functions
- Performs early-stage initialization for simple devices needed during early boot.
- Initializes all other devices not initialized during
early_init().
FilterProtocol in ixgbe - Rust Enum ixgbe::FilterProtocol
source · pub enum FilterProtocol {
+FilterProtocol in ixgbe - Rust Enum ixgbe::FilterProtocol
source · pub enum FilterProtocol {
Tcp = 0,
Udp = 1,
Sctp = 2,
diff --git a/doc/ixgbe/enum.LinkSpeedMbps.html b/doc/ixgbe/enum.LinkSpeedMbps.html
index c5f8a161d8..944c742867 100644
--- a/doc/ixgbe/enum.LinkSpeedMbps.html
+++ b/doc/ixgbe/enum.LinkSpeedMbps.html
@@ -1,12 +1,12 @@
-LinkSpeedMbps in ixgbe - Rust Enum ixgbe::LinkSpeedMbps
source · pub enum LinkSpeedMbps {
+LinkSpeedMbps in ixgbe - Rust Enum ixgbe::LinkSpeedMbps
source · pub enum LinkSpeedMbps {
LS100 = 100,
LS1000 = 1_000,
LS10000 = 10_000,
LSUnknown = 0,
}
Expand description
Possible link speeds of the 82599 NIC
-Variants§
Trait Implementations§
source§impl PartialEq<LinkSpeedMbps> for LinkSpeedMbps
source§fn eq(&self, other: &LinkSpeedMbps) -> bool
This method tests for self and other values to be equal, and is used
+Variants§
Trait Implementations§
source§impl PartialEq<LinkSpeedMbps> for LinkSpeedMbps
source§fn eq(&self, other: &LinkSpeedMbps) -> bool
This method tests for self and other values to be equal, and is used
by ==.source§impl StructuralPartialEq for LinkSpeedMbps
Auto Trait Implementations§
§impl RefUnwindSafe for LinkSpeedMbps
§impl Send for LinkSpeedMbps
§impl Sync for LinkSpeedMbps
§impl Unpin for LinkSpeedMbps
§impl UnwindSafe for LinkSpeedMbps
Blanket Implementations§
source§impl StructuralPartialEq for LinkSpeedMbps
Auto Trait Implementations§
§impl RefUnwindSafe for LinkSpeedMbps
§impl Send for LinkSpeedMbps
§impl Sync for LinkSpeedMbps
§impl Unpin for LinkSpeedMbps
§impl UnwindSafe for LinkSpeedMbps
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/ixgbe/enum.RxBufferSizeKiB.html b/doc/ixgbe/enum.RxBufferSizeKiB.html
index 0e745c8241..938dccecf1 100644
--- a/doc/ixgbe/enum.RxBufferSizeKiB.html
+++ b/doc/ixgbe/enum.RxBufferSizeKiB.html
@@ -1,4 +1,4 @@
-RxBufferSizeKiB in ixgbe - Rust Enum ixgbe::RxBufferSizeKiB
source · pub enum RxBufferSizeKiB {
+RxBufferSizeKiB in ixgbe - Rust Enum ixgbe::RxBufferSizeKiB
source · pub enum RxBufferSizeKiB {
Show 16 variants
Buffer1KiB = 1,
Buffer2KiB = 2,
Buffer3KiB = 3,
@@ -16,7 +16,7 @@
Buffer15KiB = 15,
Buffer16KiB = 16,
}
Expand description
The set of receive buffer sizes that are accepted by the 82599 device.
-Variants§
§Buffer1KiB = 1
§Buffer2KiB = 2
§Buffer3KiB = 3
§Buffer4KiB = 4
§Buffer5KiB = 5
§Buffer6KiB = 6
§Buffer7KiB = 7
§Buffer8KiB = 8
§Buffer9KiB = 9
§Buffer10KiB = 10
§Buffer11KiB = 11
§Buffer12KiB = 12
§Buffer13KiB = 13
§Buffer14KiB = 14
§Buffer15KiB = 15
§Buffer16KiB = 16
Trait Implementations§
source§impl Clone for RxBufferSizeKiB
source§fn clone(&self) -> RxBufferSizeKiB
Returns a copy of the value. Read more1.0.0 · source§fn clone_from(&mut self, source: &Self)
Performs copy-assignment from source. Read moresource§impl Copy for RxBufferSizeKiB
Auto Trait Implementations§
§impl RefUnwindSafe for RxBufferSizeKiB
§impl Send for RxBufferSizeKiB
§impl Sync for RxBufferSizeKiB
§impl Unpin for RxBufferSizeKiB
§impl UnwindSafe for RxBufferSizeKiB
Blanket Implementations§
Variants§
§Buffer1KiB = 1
§Buffer2KiB = 2
§Buffer3KiB = 3
§Buffer4KiB = 4
§Buffer5KiB = 5
§Buffer6KiB = 6
§Buffer7KiB = 7
§Buffer8KiB = 8
§Buffer9KiB = 9
§Buffer10KiB = 10
§Buffer11KiB = 11
§Buffer12KiB = 12
§Buffer13KiB = 13
§Buffer14KiB = 14
§Buffer15KiB = 15
§Buffer16KiB = 16
Trait Implementations§
source§impl Clone for RxBufferSizeKiB
source§fn clone(&self) -> RxBufferSizeKiB
Returns a copy of the value. Read more1.0.0 · source§fn clone_from(&mut self, source: &Self)
Performs copy-assignment from source. Read moresource§impl Copy for RxBufferSizeKiB
Auto Trait Implementations§
§impl RefUnwindSafe for RxBufferSizeKiB
§impl Send for RxBufferSizeKiB
§impl Sync for RxBufferSizeKiB
§impl Unpin for RxBufferSizeKiB
§impl UnwindSafe for RxBufferSizeKiB
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/ixgbe/fn.rx_poll_mq.html b/doc/ixgbe/fn.rx_poll_mq.html
index b1782d7879..18a4ed39ca 100644
--- a/doc/ixgbe/fn.rx_poll_mq.html
+++ b/doc/ixgbe/fn.rx_poll_mq.html
@@ -1,4 +1,4 @@
-rx_poll_mq in ixgbe - Rust Function ixgbe::rx_poll_mq
source · pub fn rx_poll_mq(
+rx_poll_mq in ixgbe - Rust Function ixgbe::rx_poll_mq
source · pub fn rx_poll_mq(
qid: usize,
nic_id: PciLocation
) -> Result<ReceivedFrame, &'static str>
Expand description
A helper function to poll the nic receive queues (only for testing purposes).
diff --git a/doc/ixgbe/fn.tx_send_mq.html b/doc/ixgbe/fn.tx_send_mq.html
index 36f5b18c28..17f0a8847b 100644
--- a/doc/ixgbe/fn.tx_send_mq.html
+++ b/doc/ixgbe/fn.tx_send_mq.html
@@ -1,4 +1,4 @@
-tx_send_mq in ixgbe - Rust Function ixgbe::tx_send_mq
source · pub fn tx_send_mq(
+tx_send_mq in ixgbe - Rust Function ixgbe::tx_send_mq
source · pub fn tx_send_mq(
qid: usize,
nic_id: PciLocation,
packet: Option<TransmitBuffer>
diff --git a/doc/ixgbe/index.html b/doc/ixgbe/index.html
index 98f53d6571..de6e21c2a6 100644
--- a/doc/ixgbe/index.html
+++ b/doc/ixgbe/index.html
@@ -1,5 +1,5 @@
ixgbe - Rust Expand description
Expand description
An ixgbe driver for a 82599 10GbE Network Interface Card.
Currently we support basic send and receive, Receive Side Scaling (RSS), 5-tuple filters, and MSI interrupts.
We also support language-level virtualization of the NIC so that applications can directly access their assigned transmit and receive queues.
When using virtualization, we disable RSS since we use 5-tuple filters to ensure packets are routed to the correct queues.
diff --git a/doc/ixgbe/struct.IxgbeNic.html b/doc/ixgbe/struct.IxgbeNic.html
index b5e50fe67d..b717c58c19 100644
--- a/doc/ixgbe/struct.IxgbeNic.html
+++ b/doc/ixgbe/struct.IxgbeNic.html
@@ -1,5 +1,5 @@
IxgbeNic in ixgbe - Rust pub struct IxgbeNic { /* private fields */ }
Expand description
A struct representing an ixgbe network interface card.
-Implementations§
Implementations§
sourcepub fn spoof_mac(&mut self, spoofed_mac_addr: [u8; 6])
sourcepub fn link_status(&self) -> (u32, u32)
Returns value of (links, links2) registers
-sourcepub fn link_speed(&self) -> LinkSpeedMbps
Returns link speed in Mb/s
-sourcepub fn get_stats(&self) -> (u32, u64, u32, u64)
Returns the Rx and Tx statistics in the form: (Good Rx packets, Good Rx bytes, Good Tx packets, Good Tx bytes).
+
sourcepub fn spoof_mac(&mut self, spoofed_mac_addr: [u8; 6])
sourcepub fn link_status(&self) -> (u32, u32)
Returns value of (links, links2) registers
+sourcepub fn link_speed(&self) -> LinkSpeedMbps
Returns link speed in Mb/s
+sourcepub fn get_stats(&self) -> (u32, u64, u32, u64)
Returns the Rx and Tx statistics in the form: (Good Rx packets, Good Rx bytes, Good Tx packets, Good Tx bytes).
A good packet is one that is >= 64 bytes including ethernet header and CRC
-sourcepub fn enable_rss(
+
sourcepub fn enable_rss(
regs2: &mut IntelIxgbeRegisters2,
regs3: &mut IntelIxgbeRegisters3
) -> Result<(), &'static str>
Enable multiple receive queues with RSS.
Part of queue initialization is done in the rx_init function.
-sourcepub fn set_5_tuple_filter(
+
sourcepub fn set_5_tuple_filter(
&mut self,
source_ip: Option<[u8; 4]>,
dest_ip: Option<[u8; 4]>,
diff --git a/doc/ixgbe/virtual_function/fn.create_virtual_nic.html b/doc/ixgbe/virtual_function/fn.create_virtual_nic.html
index d98e4d6230..948ab14a62 100644
--- a/doc/ixgbe/virtual_function/fn.create_virtual_nic.html
+++ b/doc/ixgbe/virtual_function/fn.create_virtual_nic.html
@@ -3,7 +3,7 @@
ip_addresses: Vec<[u8; 4]>,
default_rx_queue: usize,
default_tx_queue: usize
-) -> Result<VirtualNic<IxgbeRxQueueRegisters, AdvancedRxDescriptor, IxgbeTxQueueRegisters, AdvancedTxDescriptor>, &'static str>Expand description
Create a virtual NIC from the ixgbe device.
+) -> Result<VirtualNic<IxgbeRxQueueRegisters, AdvancedRxDescriptor, IxgbeTxQueueRegisters, AdvancedTxDescriptor>, &'static str>Expand description
Create a virtual NIC from the ixgbe device.
Arguments
nic_id: the ixgbe NIC we will take receive and transmit queue from.List of all items in this crate List of all items in this crate InterruptPin in pci - Rust Enum pci::InterruptPin
source · pub enum InterruptPin {
+InterruptPin in pci - Rust Enum pci::InterruptPin
source · pub enum InterruptPin {
A,
B,
C,
diff --git a/doc/pci/enum.PciCapability.html b/doc/pci/enum.PciCapability.html
index 9c074d9184..5cd66c8a59 100644
--- a/doc/pci/enum.PciCapability.html
+++ b/doc/pci/enum.PciCapability.html
@@ -1,4 +1,4 @@
-PciCapability in pci - Rust Enum pci::PciCapability
source · #[repr(u8)]pub enum PciCapability {
+PciCapability in pci - Rust Enum pci::PciCapability
source · #[repr(u8)]pub enum PciCapability {
Msi = 5,
Msix = 17,
}
Variants§
Auto Trait Implementations§
§impl RefUnwindSafe for PciCapability
§impl Send for PciCapability
§impl Sync for PciCapability
§impl Unpin for PciCapability
§impl UnwindSafe for PciCapability
Blanket Implementations§
source§impl<T> Any for Twhere
diff --git a/doc/pci/enum.PciConfigSpaceAccessMechanism.html b/doc/pci/enum.PciConfigSpaceAccessMechanism.html
index b5492b2d17..78cc7eab23 100644
--- a/doc/pci/enum.PciConfigSpaceAccessMechanism.html
+++ b/doc/pci/enum.PciConfigSpaceAccessMechanism.html
@@ -1,4 +1,4 @@
-PciConfigSpaceAccessMechanism in pci - Rust pub enum PciConfigSpaceAccessMechanism {
+PciConfigSpaceAccessMechanism in pci - Rust pub enum PciConfigSpaceAccessMechanism {
MemoryMapped = 0,
IoPort = 1,
}
Expand description
Lists the 2 possible PCI configuration space access mechanisms
diff --git a/doc/pci/fn.get_pci_buses.html b/doc/pci/fn.get_pci_buses.html
index 319b2dfbc9..12d7a2825c 100644
--- a/doc/pci/fn.get_pci_buses.html
+++ b/doc/pci/fn.get_pci_buses.html
@@ -1,3 +1,3 @@
-
get_pci_buses in pci - Rust Function pci::get_pci_buses
source · pub fn get_pci_buses() -> Result<&'static Vec<PciBus>, &'static str>
Expand description
Returns a list of all PCI buses in this system.
+
get_pci_buses in pci - Rust get_pci_device_bsf in pci - Rust Function pci::get_pci_device_bsf
source · pub fn get_pci_device_bsf(
+get_pci_device_bsf in pci - Rust Function pci::get_pci_device_bsf
source · pub fn get_pci_device_bsf(
bus: u8,
slot: u8,
func: u8
diff --git a/doc/pci/fn.init.html b/doc/pci/fn.init.html
new file mode 100644
index 0000000000..a437cad0ad
--- /dev/null
+++ b/doc/pci/fn.init.html
@@ -0,0 +1,2 @@
+init in pci - Rust pci_device_iter in pci - Rust Function pci::pci_device_iter
source · pub fn pci_device_iter(
+pci_device_iter in pci - Rust Function pci::pci_device_iter
source · pub fn pci_device_iter(
) -> Result<impl Iterator<Item = &'static PciDevice>, &'static str>
Expand description
Returns an iterator that iterates over all PciDevices, in no particular guaranteed order.
If the PCI bus hasn’t been initialized, this initializes the PCI bus & scans it to enumerates devices.
pci - Rust Expand description
Expand description
PCI Configuration Space Access
Note: while pci currently uses port-io on x86 and mmio on aarch64,
x86 may also support memory-based PCI configuration in the future;
port-io is the legacy way to access the config space.
+For context on the various interrupt mechanisms (MSI/MSI-X/INTx):
+
+- this StackExchange reply
+- PCI Express Base Specification, Revision 2, Chapter 6.1 - Interrupt & PME Support
+
Structs
- A single Message Signaled Interrupt entry.
- A memory-mapped array of
MsixVectorEntry - A PCI bus, which contains a list of PCI devices on that bus.
- Contains information common to every type of PCI Device,
and offers functions for reading/writing to the PCI configuration space.
- The bus, slot, and function number of a given PCI device.
This offers methods for reading and writing the PCI config space.
Enums
- Lists the 2 possible PCI configuration space access mechanisms
that can be found from the LSB of the devices’s BAR0
Functions
- Returns a list of all PCI buses in this system.
If the PCI bus hasn’t been initialized, this initializes the PCI bus & scans it to enumerates devices.
- Returns a reference to the
PciDevice with the given bus, slot, func identifier.
-If the PCI bus hasn’t been initialized, this initializes the PCI bus & scans it to enumerates devices. - Returns an iterator that iterates over all
PciDevices, in no particular guaranteed order.
+If the PCI bus hasn’t been initialized, this initializes the PCI bus & scans it to enumerates devices. - Initializes the PCI interrupt handler
- Returns an iterator that iterates over all
PciDevices, in no particular guaranteed order.
If the PCI bus hasn’t been initialized, this initializes the PCI bus & scans it to enumerates devices.
MsixVectorEntry in pci - Rust Struct pci::MsixVectorEntry
source · #[repr(C)]pub struct MsixVectorEntry { /* private fields */ }
Expand description
A single Message Signaled Interrupt entry.
+MsixVectorEntry in pci - Rust Struct pci::MsixVectorEntry
source · #[repr(C)]pub struct MsixVectorEntry { /* private fields */ }
Expand description
A single Message Signaled Interrupt entry.
This entry contains the interrupt’s IRQ vector number
and the CPU to which the interrupt will be delivered.
-Implementations§
source§impl MsixVectorEntry
sourcepub fn init(&mut self, cpu_id: CpuId, int_num: InterruptNumber)
Sets interrupt destination & number for this entry and makes sure the
+
Implementations§
Trait Implementations§
source§impl FromBytes for MsixVectorEntry
Auto Trait Implementations§
§impl RefUnwindSafe for MsixVectorEntry
§impl Send for MsixVectorEntry
§impl Sync for MsixVectorEntry
§impl Unpin for MsixVectorEntry
§impl UnwindSafe for MsixVectorEntry
Blanket Implementations§
Trait Implementations§
source§impl FromBytes for MsixVectorEntry
Auto Trait Implementations§
§impl RefUnwindSafe for MsixVectorEntry
§impl Send for MsixVectorEntry
§impl Sync for MsixVectorEntry
§impl Unpin for MsixVectorEntry
§impl UnwindSafe for MsixVectorEntry
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/pci/struct.MsixVectorTable.html b/doc/pci/struct.MsixVectorTable.html
index 140665daf5..7d695a3d6b 100644
--- a/doc/pci/struct.MsixVectorTable.html
+++ b/doc/pci/struct.MsixVectorTable.html
@@ -1,5 +1,5 @@
-MsixVectorTable in pci - Rust Struct pci::MsixVectorTable
source · pub struct MsixVectorTable { /* private fields */ }
Expand description
A memory-mapped array of MsixVectorEntry
-Implementations§
source§impl MsixVectorTable
sourcepub fn new(entries: BorrowedSliceMappedPages<MsixVectorEntry, Mutable>) -> Self
Methods from Deref<Target = [MsixVectorEntry]>§
sourcepub fn flatten(&self) -> &[T]
🔬This is a nightly-only experimental API. (slice_flatten)
Takes a &[[T; N]], and flattens it to a &[T].
+MsixVectorTable in pci - Rust Struct pci::MsixVectorTable
source · pub struct MsixVectorTable { /* private fields */ }
Expand description
A memory-mapped array of MsixVectorEntry
+Implementations§
source§impl MsixVectorTable
sourcepub fn new(entries: BorrowedSliceMappedPages<MsixVectorEntry, Mutable>) -> Self
Methods from Deref<Target = [MsixVectorEntry]>§
sourcepub fn flatten(&self) -> &[T]
🔬This is a nightly-only experimental API. (slice_flatten)
Takes a &[[T; N]], and flattens it to a &[T].
Panics
This panics if the length of the resulting slice would overflow a usize.
This is only possible when flattening a slice of arrays of zero-sized
@@ -2367,7 +2367,7 @@
Examples
ASCII letters ‘A’ to ‘Z’ are mapped to ‘a’ to ‘z’,
but non-ASCII letters are unchanged.
To lowercase the value in-place, use make_ascii_lowercase.
-Trait Implementations§
source§impl Deref for MsixVectorTable
Auto Trait Implementations§
§impl RefUnwindSafe for MsixVectorTable
§impl Send for MsixVectorTable
§impl Sync for MsixVectorTable
§impl Unpin for MsixVectorTable
§impl UnwindSafe for MsixVectorTable
Blanket Implementations§
Trait Implementations§
source§impl Deref for MsixVectorTable
Auto Trait Implementations§
§impl RefUnwindSafe for MsixVectorTable
§impl Send for MsixVectorTable
§impl Sync for MsixVectorTable
§impl Unpin for MsixVectorTable
§impl UnwindSafe for MsixVectorTable
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/pci/struct.PciBus.html b/doc/pci/struct.PciBus.html
index df6d77ec7e..edf830e321 100644
--- a/doc/pci/struct.PciBus.html
+++ b/doc/pci/struct.PciBus.html
@@ -1,10 +1,10 @@
-PciBus in pci - Rust pub struct PciBus {
+PciBus in pci - Rust pub struct PciBus {
pub bus_number: u8,
pub devices: Vec<PciDevice>,
}
Expand description
A PCI bus, which contains a list of PCI devices on that bus.
Fields§
§bus_number: u8The number identifier of this PCI bus.
§devices: Vec<PciDevice>The list of devices attached to this PCI bus.
-Trait Implementations§
Auto Trait Implementations§
§impl RefUnwindSafe for PciBus
§impl Send for PciBus
§impl Sync for PciBus
§impl Unpin for PciBus
§impl UnwindSafe for PciBus
Blanket Implementations§
Trait Implementations§
Auto Trait Implementations§
§impl !RefUnwindSafe for PciBus
§impl Send for PciBus
§impl Sync for PciBus
§impl Unpin for PciBus
§impl UnwindSafe for PciBus
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/pci/struct.PciDevice.html b/doc/pci/struct.PciDevice.html
index 0a5a37da35..823a44dc94 100644
--- a/doc/pci/struct.PciDevice.html
+++ b/doc/pci/struct.PciDevice.html
@@ -1,5 +1,6 @@
-PciDevice in pci - Rust pub struct PciDevice {Show 16 fields
+PciDevice in pci - Rust pub struct PciDevice {Show 17 fields
pub location: PciLocation,
+ pub interrupt_waker: Mutex<Option<Waker>>,
pub class: u8,
pub subclass: u8,
pub prog_if: u8,
@@ -20,11 +21,12 @@
For more, see this partial table
of class, subclass, and prog_if codes,
Fields§
§location: PciLocationthe bus, slot, and function number that locates this PCI device in the bus tree.
+§interrupt_waker: Mutex<Option<Waker>>The handling task for legacy PCI interrupts
§class: u8The class code, used to determine device type.
§subclass: u8The subclass code, used to determine device type.
§prog_if: u8The programming interface of this PCI device, also used to determine device type.
§bars: [u32; 6]The six Base Address Registers (BARs)
-§vendor_id: u16§device_id: u16§command: u16§status: u16§revision_id: u8§cache_line_size: u8§latency_timer: u8§header_type: u8§bist: u8§int_pin: u8§int_line: u8Implementations§
source§impl PciDevice
sourcepub fn determine_mem_base(
+
§vendor_id: u16§device_id: u16§command: u16§status: u16§revision_id: u8§cache_line_size: u8§latency_timer: u8§header_type: u8§bist: u8§int_pin: u8§int_line: u8Implementations§
source§impl PciDevice
sourcepub fn determine_mem_base(
&self,
bar_index: usize
) -> Result<PhysicalAddress, &'static str>
Returns the base address of the memory region specified by the given BAR
@@ -40,14 +42,14 @@
Argument
TODO: currently we assume the BAR represents a memory space (memory mapped I/O)
rather than I/O space like Port I/O. Obviously, this is not always the case.
Instead, we should return an enum specifying which kind of memory space the calculated base address is.
-sourcepub fn determine_mem_size(&self, bar_index: usize) -> u32
Returns the size in bytes of the memory region specified by the given BAR
+
sourcepub fn determine_mem_size(&self, bar_index: usize) -> u32
Returns the size in bytes of the memory region specified by the given BAR
(Base Address Register) for this PCI device.
Argument
bar_index must be between 0 and 5 inclusively, as each PCI device
can only have 6 BARs at the most.
-sourcepub fn pci_enable_msi(
+
sourcepub fn pci_enable_msix(&self) -> Result<(), &'static str>
Enable MSI-X interrupts for a PCI device.
+
sourcepub fn pci_enable_msix(&self) -> Result<(), &'static str>
Enable MSI-X interrupts for a PCI device.
Only the enable bit is set and the remaining initialization steps of
setting the interrupt number and core id should be completed in the device driver.
-sourcepub fn pci_mem_map_msix(
+
sourcepub fn pci_mem_map_msix(
&self,
max_vectors: usize
) -> Result<MsixVectorTable, &'static str>
Returns the memory mapped msix vector table
@@ -73,7 +75,7 @@ Panics
- returns
Err("Device not MSI-X capable") if the device doesn’t have the MSI-X capability
- returns
Err("Invalid BAR content") if the Base Address Register contains an invalid address
-sourcepub fn pci_map_bar_mem(
+
sourcepub fn pci_map_bar_mem(
&self,
bar_index: usize
) -> Result<MappedPages, &'static str>
Maps device memory specified by a Base Address Register.
@@ -81,13 +83,17 @@ Arguments
bar_index: index of the Base Address Register to use
-sourcepub fn pci_get_interrupt_info(
+
sourcepub fn pci_get_interrupt_info(
&self
) -> Result<(Option<u8>, Option<InterruptPin>), &'static str>
Reads and returns this PCI device’s interrupt line and interrupt pin registers.
Returns an error if this PCI device’s interrupt pin value is invalid (greater than 4).
-Methods from Deref<Target = PciLocation>§
sourcepub fn bus(&self) -> u8
sourcepub fn slot(&self) -> u8
sourcepub fn function(&self) -> u8
sourcepub fn pci_set_command_bus_master_bit(&self)
Sets the PCI device’s bit 3 in the command portion, which is apparently needed to activate DMA (??)
-sourcepub fn pci_set_interrupt_disable_bit(&self)
Sets the PCI device’s command bit 10 to disable legacy interrupts
-Trait Implementations§
Auto Trait Implementations§
§impl RefUnwindSafe for PciDevice
§impl Send for PciDevice
§impl Sync for PciDevice
§impl Unpin for PciDevice
§impl UnwindSafe for PciDevice
Blanket Implementations§
sourcepub fn pci_enable_interrupts(&self, enable: bool)
Enables/Disables legacy (INTx) interrupts for this device
+sourcepub fn pci_get_interrupt_status(&self, check_enabled: bool) -> bool
Reads and returns this PCI device’s interrupt status flag.
+sourcepub fn set_interrupt_waker(&'static self, waker: Waker) -> Option<Waker>
Sets a task waker to be used when this device triggers an interrupt
+Returns the previous interrupt waker for this device, if there was one.
+
Methods from Deref<Target = PciLocation>§
sourcepub fn bus(&self) -> u8
sourcepub fn slot(&self) -> u8
sourcepub fn function(&self) -> u8
sourcepub fn pci_set_command_bus_master_bit(&self)
Sets the PCI device’s bit 3 in the command portion, which is apparently needed to activate DMA (??)
+sourcepub fn pci_set_interrupt_disable_bit(&self, bit: bool)
Sets the PCI device’s command bit 10 to disable legacy interrupts
+Trait Implementations§
Auto Trait Implementations§
§impl !RefUnwindSafe for PciDevice
§impl Send for PciDevice
§impl Sync for PciDevice
§impl Unpin for PciDevice
§impl UnwindSafe for PciDevice
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read moresource§impl<T> From<T> for T
source§fn from(t: T) -> T
Returns the argument unchanged.
diff --git a/doc/pci/struct.PciLocation.html b/doc/pci/struct.PciLocation.html
index 0eb5f5a355..066a42e5d3 100644
--- a/doc/pci/struct.PciLocation.html
+++ b/doc/pci/struct.PciLocation.html
@@ -1,12 +1,12 @@
-PciLocation in pci - Rust Struct pci::PciLocation
source · pub struct PciLocation { /* private fields */ }
Expand description
The bus, slot, and function number of a given PCI device.
+
PciLocation in pci - Rust Struct pci::PciLocation
source · pub struct PciLocation { /* private fields */ }
Expand description
The bus, slot, and function number of a given PCI device.
This offers methods for reading and writing the PCI config space.
-Implementations§
source§impl PciLocation
sourcepub fn bus(&self) -> u8
sourcepub fn slot(&self) -> u8
sourcepub fn function(&self) -> u8
sourcepub fn pci_set_command_bus_master_bit(&self)
Sets the PCI device’s bit 3 in the command portion, which is apparently needed to activate DMA (??)
-sourcepub fn pci_set_interrupt_disable_bit(&self)
Sets the PCI device’s command bit 10 to disable legacy interrupts
-Trait Implementations§
source§impl Clone for PciLocation
source§fn clone(&self) -> PciLocation
Returns a copy of the value. Read more1.0.0 · source§fn clone_from(&mut self, source: &Self)
Performs copy-assignment from source. Read moresource§impl Debug for PciLocation
source§impl Display for PciLocation
source§impl Hash for PciLocation
Implementations§
source§impl PciLocation
sourcepub fn bus(&self) -> u8
sourcepub fn slot(&self) -> u8
sourcepub fn function(&self) -> u8
sourcepub fn pci_set_command_bus_master_bit(&self)
Sets the PCI device’s bit 3 in the command portion, which is apparently needed to activate DMA (??)
+sourcepub fn pci_set_interrupt_disable_bit(&self, bit: bool)
Sets the PCI device’s command bit 10 to disable legacy interrupts
+Trait Implementations§
source§impl Clone for PciLocation
source§fn clone(&self) -> PciLocation
Returns a copy of the value. Read more1.0.0 · source§fn clone_from(&mut self, source: &Self)
Performs copy-assignment from source. Read moresource§impl Debug for PciLocation
source§impl Display for PciLocation
source§impl Hash for PciLocation
source§impl PartialEq<PciLocation> for PciLocation
source§fn eq(&self, other: &PciLocation) -> bool
source§impl PartialEq<PciLocation> for PciLocation
source§fn eq(&self, other: &PciLocation) -> bool
This method tests for self and other values to be equal, and is used
by ==.source§impl Copy for PciLocation
source§impl Eq for PciLocation
source§impl StructuralEq for PciLocation
source§impl StructuralPartialEq for PciLocation
Auto Trait Implementations§
§impl RefUnwindSafe for PciLocation
§impl Send for PciLocation
§impl Sync for PciLocation
§impl Unpin for PciLocation
§impl UnwindSafe for PciLocation
Blanket Implementations§
source§impl Copy for PciLocation
source§impl Eq for PciLocation
source§impl StructuralEq for PciLocation
source§impl StructuralPartialEq for PciLocation
Auto Trait Implementations§
§impl RefUnwindSafe for PciLocation
§impl Send for PciLocation
§impl Sync for PciLocation
§impl Unpin for PciLocation
§impl UnwindSafe for PciLocation
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more§impl<T> CallHasher for Twhere
diff --git a/doc/search-index.js b/doc/search-index.js
index c5428343da..339bbc55a1 100644
--- a/doc/search-index.js
+++ b/doc/search-index.js
@@ -111,7 +111,7 @@ var searchIndex = JSON.parse('{\
"panic_entry":{"doc":"Provides the default entry points and lang items for …","t":"","n":[],"q":[],"d":[],"i":[],"f":[],"c":[],"p":[],"b":[]},\
"panic_wrapper":{"doc":"Provides types and simple routines for handling panics. …","t":"F","n":["panic_wrapper"],"q":[[0,"panic_wrapper"],[1,"core::panic::panic_info"],[2,"core::result"]],"d":["Performs the standard panic handling routine, which …"],"i":[0],"f":[[1,[[4,[2,3]]]]],"c":[],"p":[[3,"PanicInfo",1],[15,"tuple"],[15,"str"],[4,"Result",2]],"b":[]},\
"path":{"doc":"File system paths.","t":"EDNNNDDNLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL","n":["Component","Components","CurDir","Normal","ParentDir","Path","PathBuf","RootDir","as_mut","as_mut","as_path","as_ref","as_ref","as_ref","as_ref","as_ref","as_ref","borrow","borrow","borrow","borrow","borrow","borrow_mut","borrow_mut","borrow_mut","borrow_mut","clone","clone","clone","clone_into","clone_into","clone_into","cmp","cmp","components","default","deref","deref_mut","eq","eq","eq","eq","extension","file_name","file_stem","fmt","fmt","fmt","fmt","fmt","fmt","from","from","from","from","from","from_iter","get","get_absolute","get_dir","get_file","into","into","into","into_iter","is_absolute","join","new","new","next","next_back","parent","partial_cmp","partial_cmp","partial_cmp","pop","push","relative","to_owned","to_owned","to_owned","to_owned","to_string","to_string","try_from","try_from","try_from","try_into","try_into","try_into","type_id","type_id","type_id","type_id"],"q":[[0,"path"],[94,"core::cmp"],[95,"core::option"],[96,"core::fmt"],[97,"core::fmt"],[98,"core::convert"],[99,"alloc::string"],[100,"core::iter::traits::collect"],[101,"fs_node"],[102,"fs_node"],[103,"core::any"]],"d":["","An iterator over the components of a path.","","","","A slice of a path.","An owned, mutable path.","","","","Extracts a slice corresponding to the portion of the path …","","","","","","","","","","","","","","","","","","","","","","","","Produces an iterator over the Components of the path.","","","","","","","","Extracts the extension (without the leading dot) of …","Returns the final component of the Path, if there is one.","Extracts the stem (non-extension) portion of self.file_name…","","","","","","","Returns the argument unchanged.","Returns the argument unchanged.","","Returns the argument unchanged.","","","Returns the file or directory at the given path.","Returns the file or directory at the given absolute path.","Returns the directory at the given path.","Returns the file at the given path.","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","","Returns true if the path starts with the root.","Creates an owned PathBuf with path adjoined to self.","Wraps a string slice as a path slice.","Allocates an empty PathBuf.","","","Returns the path without its final component, if there is …","","","","Truncates self to self.parent.","Extends self with path.","Construct a relative path from a provided base directory …","","","","","","","","","","","","","","","",""],"i":[0,0,4,4,4,0,0,4,1,1,3,4,4,1,1,5,5,3,4,1,5,5,3,4,1,5,3,4,5,3,4,5,1,5,1,5,5,5,3,4,1,5,1,1,1,3,4,1,1,5,5,3,4,5,5,5,5,1,1,1,1,3,4,5,3,1,1,1,5,3,3,1,3,1,5,5,5,1,3,4,1,5,1,5,3,4,5,3,4,5,3,4,1,5],"f":[0,0,0,0,0,0,0,0,[1,1],[1,2],[3,1],[4,2],[4,1],[1,2],[1,1],[5,1],[5,2],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[5,1],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[3,3],[4,4],[5,5],[[-1,-2],6,[],[]],[[-1,-2],6,[],[]],[[-1,-2],6,[],[]],[[1,1],7],[[5,5],7],[1,3],[[],5],[5],[5],[[3,3],8],[[4,4],8],[[1,1],8],[[5,5],8],[1,[[9,[2]]]],[1,[[9,[2]]]],[1,[[9,[2]]]],[[3,10],11],[[4,10],11],[[1,10],11],[[1,10],11],[[5,10],11],[[5,10],11],[-1,-1,[]],[-1,-1,[]],[-1,5,[12,[13,[2]]]],[-1,-1,[]],[14,5],[-1,5,15],[[1,16],[[9,[17]]]],[1,[[9,[17]]]],[[1,16],[[9,[16]]]],[[1,16],[[9,[18]]]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[1,8],[[1,-1],5,[[13,[1]]]],[-1,1,[[13,[2]],12]],[[],5],[3,9],[3,9],[1,[[9,[1]]]],[[3,3],[[9,[7]]]],[[1,1],[[9,[7]]]],[[5,5],[[9,[7]]]],[5,8],[[5,-1],6,[[13,[1]]]],[[1,-1],[[9,[5]]],[[13,[1]]]],[-1,-2,[],[]],[-1,-2,[],[]],[1],[-1,-2,[],[]],[-1,14,[]],[-1,14,[]],[-1,[[19,[-2]]],[],[]],[-1,[[19,[-2]]],[],[]],[-1,[[19,[-2]]],[],[]],[-1,[[19,[-2]]],[],[]],[-1,[[19,[-2]]],[],[]],[-1,[[19,[-2]]],[],[]],[-1,20,[]],[-1,20,[]],[-1,20,[]],[-1,20,[]]],"c":[],"p":[[3,"Path",0],[15,"str"],[3,"Components",0],[4,"Component",0],[3,"PathBuf",0],[15,"tuple"],[4,"Ordering",94],[15,"bool"],[4,"Option",95],[3,"Formatter",96],[6,"Result",96],[8,"Sized",97],[8,"AsRef",98],[3,"String",99],[8,"IntoIterator",100],[6,"DirRef",101],[4,"FileOrDir",101],[6,"FileRef",101],[4,"Result",102],[3,"TypeId",103]],"b":[[8,"impl-AsMut%3CPath%3E-for-Path"],[9,"impl-AsMut%3Cstr%3E-for-Path"],[11,"impl-AsRef%3Cstr%3E-for-Component%3C\'a%3E"],[12,"impl-AsRef%3CPath%3E-for-Component%3C\'a%3E"],[13,"impl-AsRef%3Cstr%3E-for-Path"],[14,"impl-AsRef%3CPath%3E-for-Path"],[15,"impl-AsRef%3CPath%3E-for-PathBuf"],[16,"impl-AsRef%3Cstr%3E-for-PathBuf"],[47,"impl-Debug-for-Path"],[48,"impl-Display-for-Path"],[49,"impl-Debug-for-PathBuf"],[50,"impl-Display-for-PathBuf"],[53,"impl-From%3C%26T%3E-for-PathBuf"],[55,"impl-From%3CString%3E-for-PathBuf"]]},\
-"pci":{"doc":"PCI Configuration Space Access","t":"NNNNENNNNDDDEEDDMMLLLLLLLLLLLLLLLLLMMMLLMLLLLLLMMLLLLLLLLLLLLLLLFFLMLMMLLLLLLLLMMLFLLLLLLLMMLMMLLLLLLLLLLLLLLLLLLLLLLLLLLM","n":["A","B","C","D","InterruptPin","IoPort","MemoryMapped","Msi","Msix","MsixVectorEntry","MsixVectorTable","PciBus","PciCapability","PciConfigSpaceAccessMechanism","PciDevice","PciLocation","bars","bist","borrow","borrow","borrow","borrow","borrow","borrow","borrow","borrow","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","bus","bus_number","cache_line_size","class","clone","clone_into","command","deref","deref","deref_mut","deref_mut","determine_mem_base","determine_mem_size","device_id","devices","eq","fmt","fmt","fmt","fmt","from","from","from","from","from","from","from","from","function","get_hash","get_pci_buses","get_pci_device_bsf","hash","header_type","init","int_line","int_pin","into","into","into","into","into","into","into","into","latency_timer","location","new","pci_device_iter","pci_enable_msi","pci_enable_msix","pci_get_interrupt_info","pci_map_bar_mem","pci_mem_map_msix","pci_set_command_bus_master_bit","pci_set_interrupt_disable_bit","prog_if","revision_id","slot","status","subclass","to_owned","to_string","try_from","try_from","try_from","try_from","try_from","try_from","try_from","try_from","try_into","try_into","try_into","try_into","try_into","try_into","try_into","try_into","type_id","type_id","type_id","type_id","type_id","type_id","type_id","type_id","vendor_id"],"q":[[0,"pci"],[122,"memory_structs"],[123,"core::result"],[124,"core::fmt"],[125,"core::fmt"],[126,"core::marker"],[127,"core::hash"],[128,"core::option"],[129,"core::hash"],[130,"interrupts::arch"],[131,"memory::paging::mapper"],[132,"memory::paging::mapper"],[133,"memory::paging::mapper"],[134,"core::any"]],"d":["","","","","","","","","","A single Message Signaled Interrupt entry.","A memory-mapped array of MsixVectorEntry","A PCI bus, which contains a list of PCI devices on that …","","Lists the 2 possible PCI configuration space access …","Contains information common to every type of PCI Device, …","The bus, slot, and function number of a given PCI device. …","The six Base Address Registers (BARs)","","","","","","","","","","","","","","","","","","","The number identifier of this PCI bus.","","The class code, used to determine device type.","","","","","","","","Returns the base address of the memory region specified by …","Returns the size in bytes of the memory region specified …","","The list of devices attached to this PCI bus.","","","","","","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","","","Returns a list of all PCI buses in this system. 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+"pci":{"doc":"PCI Configuration Space Access","t":"NNNNENNNNDDDEEDDMMLLLLLLLLLLLLLLLLLMMMLLMLLLLLLMMLLLLLLLLLLLLLLLFFLMFLMMMLLLLLLLLMMLFLLLLLLLLLMMLLMMLLLLLLLLLLLLLLLLLLLLLLLLLLM","n":["A","B","C","D","InterruptPin","IoPort","MemoryMapped","Msi","Msix","MsixVectorEntry","MsixVectorTable","PciBus","PciCapability","PciConfigSpaceAccessMechanism","PciDevice","PciLocation","bars","bist","borrow","borrow","borrow","borrow","borrow","borrow","borrow","borrow","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","bus","bus_number","cache_line_size","class","clone","clone_into","command","deref","deref","deref_mut","deref_mut","determine_mem_base","determine_mem_size","device_id","devices","eq","fmt","fmt","fmt","fmt","from","from","from","from","from","from","from","from","function","get_hash","get_pci_buses","get_pci_device_bsf","hash","header_type","init","init","int_line","int_pin","interrupt_waker","into","into","into","into","into","into","into","into","latency_timer","location","new","pci_device_iter","pci_enable_interrupts","pci_enable_msi","pci_enable_msix","pci_get_interrupt_info","pci_get_interrupt_status","pci_map_bar_mem","pci_mem_map_msix","pci_set_command_bus_master_bit","pci_set_interrupt_disable_bit","prog_if","revision_id","set_interrupt_waker","slot","status","subclass","to_owned","to_string","try_from","try_from","try_from","try_from","try_from","try_from","try_from","try_from","try_into","try_into","try_into","try_into","try_into","try_into","try_into","try_into","type_id","type_id","type_id","type_id","type_id","type_id","type_id","type_id","vendor_id"],"q":[[0,"pci"],[127,"memory_structs"],[128,"core::result"],[129,"core::fmt"],[130,"core::fmt"],[131,"core::marker"],[132,"core::hash"],[133,"core::option"],[134,"core::hash"],[135,"interrupts::arch"],[136,"memory::paging::mapper"],[137,"memory::paging::mapper"],[138,"memory::paging::mapper"],[139,"alloc::string"],[140,"core::any"]],"d":["","","","","","","","","","A single Message Signaled Interrupt entry.","A memory-mapped array of MsixVectorEntry","A PCI bus, which contains a list of PCI devices on that …","","Lists the 2 possible PCI configuration space access …","Contains information common to every type of PCI Device, …","The bus, slot, and function number of a given PCI device. …","The six Base Address Registers (BARs)","","","","","","","","","","","","","","","","","","","The number identifier of this PCI bus.","","The class code, used to determine device type.","","","","","","","","Returns the base address of the memory region specified by …","Returns the size in bytes of the memory region specified …","","The list of devices attached to this PCI bus.","","","","","","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","","","Returns a list of all PCI buses in this system. If the PCI …","Returns a reference to the PciDevice with the given bus, …","","","Initializes the PCI interrupt handler","Sets interrupt destination & number for this entry and …","","","The handling task for legacy PCI interrupts","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","","the bus, slot, and function number that locates this PCI …","","Returns an iterator that iterates over all PciDevices, in …","Enables/Disables legacy (INTx) interrupts for this device","Enable MSI interrupts for a PCI device. We assume the …","Enable MSI-X interrupts for a PCI device. Only the enable …","Reads and returns this PCI device’s interrupt line and …","Reads and returns this PCI device’s interrupt status …","Maps device memory specified by a Base Address Register.","Returns the memory mapped msix vector table","Sets the PCI device’s bit 3 in the command portion, …","Sets the PCI device’s command bit 10 to disable legacy …","The programming interface of this PCI device, also used to …","","Sets a task waker to be used when this device triggers an …","","","The subclass code, used to determine device type.","","","","","","","","","","","","","","","","","","","","","","","","","","",""],"i":[29,29,29,29,0,34,34,35,35,0,0,0,0,0,0,0,5,5,35,29,34,4,12,1,5,23,35,29,34,4,12,1,5,23,1,12,5,5,1,1,5,4,5,4,5,5,5,5,12,1,12,1,1,5,35,29,34,4,12,1,5,23,1,1,0,0,1,5,0,23,5,5,5,35,29,34,4,12,1,5,23,5,5,4,0,5,5,5,5,5,5,5,1,1,5,5,5,1,5,5,1,1,35,29,34,4,12,1,5,23,35,29,34,4,12,1,5,23,35,29,34,4,12,1,5,23,5],"f":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[1,2],0,0,0,[1,1],[[-1,-2],3,[],[]],0,[4],[5,1],[4],[5,1],[[5,6],[[9,[7,8]]]],[[5,6],10],0,0,[[1,1],11],[[12,13],14],[[1,13],[[9,[3,15]]]],[[1,13],[[9,[3,15]]]],[[5,13],14],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[1,2],[[-1,-2],16,[17,18],19],[[],[[9,[[20,[12]],8]]]],[[2,2,2],[[9,[[21,[5]],8]]]],[[1,-1],3,22],0,[[],[[9,[3,8]]]],[[23,24,25],3],0,0,0,[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],0,0,[[[27,[23,26]]],4],[[],[[9,[[0,[28]],8]]]],[[5,11],3],[[5,2,2],[[9,[3,8]]]],[5,[[9,[3,8]]]],[5,[[9,[[3,[[21,[2]],[21,[29]]]],8]]]],[[5,11],11],[[5,6],[[9,[30,8]]]],[[5,6],[[9,[4,8]]]],[1,3],[[1,11],3],0,0,[[5,31],[[21,[31]]]],[1,2],0,0,[-1,-2,[],[]],[-1,32,[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,[[9,[-2]]],[],[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],[-1,33,[]],0],"c":[],"p":[[3,"PciLocation",0],[15,"u8"],[15,"tuple"],[3,"MsixVectorTable",0],[3,"PciDevice",0],[15,"usize"],[3,"PhysicalAddress",127],[15,"str"],[4,"Result",128],[15,"u32"],[15,"bool"],[3,"PciBus",0],[3,"Formatter",129],[6,"Result",129],[3,"Error",129],[15,"u64"],[8,"Hash",130],[8,"Sized",131],[8,"BuildHasher",130],[3,"Vec",132],[4,"Option",133],[8,"Hasher",130],[3,"MsixVectorEntry",0],[3,"CpuId",134],[6,"InterruptNumber",135],[3,"Mutable",136],[3,"BorrowedSliceMappedPages",136],[8,"Iterator",137],[4,"InterruptPin",0],[3,"MappedPages",136],[3,"Waker",138],[3,"String",139],[3,"TypeId",140],[4,"PciConfigSpaceAccessMechanism",0],[4,"PciCapability",0]],"b":[[51,"impl-Display-for-PciLocation"],[52,"impl-Debug-for-PciLocation"]]},\
"percent_encoding":{"doc":"URLs use special chacters to indicate the parts of the …","t":"DIDDDDDDLLLLLLLLLLLLLLLLLLLLLLLLLLLLKLLLLLLLOLLLLLLLLLLLLLLLLLLLLLLLLLLLFFFLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLF","n":["DEFAULT_ENCODE_SET","EncodeSet","PATH_SEGMENT_ENCODE_SET","PercentDecode","PercentEncode","QUERY_ENCODE_SET","SIMPLE_ENCODE_SET","USERINFO_ENCODE_SET","borrow","borrow","borrow","borrow","borrow","borrow","borrow","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","borrow_mut","clone","clone","clone","clone","clone","clone","clone","clone_into","clone_into","clone_into","clone_into","clone_into","clone_into","clone_into","contains","contains","contains","contains","contains","contains","decode_utf8","decode_utf8_lossy","define_encode_set","fmt","fmt","fmt","fmt","fmt","fmt","fmt","fmt","from","from","from","from","from","from","from","if_any","into","into","into","into","into","into","into","into_iter","into_iter","next","next","percent_decode","percent_encode","percent_encode_byte","size_hint","size_hint","to_owned","to_owned","to_owned","to_owned","to_owned","to_owned","to_owned","to_string","try_from","try_from","try_from","try_from","try_from","try_from","try_from","try_into","try_into","try_into","try_into","try_into","try_into","try_into","type_id","type_id","type_id","type_id","type_id","type_id","type_id","utf8_percent_encode"],"q":[[0,"percent_encoding"],[107,"core::clone"],[108,"alloc::borrow"],[109,"core::str::error"],[110,"core::result"],[111,"core::fmt"],[112,"core::fmt"],[113,"core::option"],[114,"alloc::string"],[115,"core::any"]],"d":["This encode set is used for path components.","Represents a set of characters / bytes that should be …","This encode set is used for on ‘/’-separated path …","The return type of percent_decode().","The return type of percent_encode() and …","This encode set is used in the URL parser for query …","This encode set is used for the path of cannot-be-a-base …","This encode set is used for username and password.","","","","","","","","","","","","","","","","","","","","","","","","","","","","","Called with UTF-8 bytes rather than code points. Should …","","","","","","Decode the result of percent-decoding as UTF-8.","Decode the result of percent-decoding as UTF-8, lossily.","Define a new struct that implements the EncodeSet trait, …","","","","","","","","","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","Returns the argument unchanged.","If the percent-decoding is different from the input, …","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","Calls U::from(self).","","","","","Percent-decode the given bytes.","Percent-encode the given bytes with the given encode set.","Return the percent-encoding of the given bytes.","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","Percent-encode the UTF-8 encoding of the given string."],"i":[0,0,0,0,0,0,0,0,1,2,3,4,5,6,9,1,2,3,4,5,6,9,1,2,3,4,5,6,9,1,2,3,4,5,6,9,8,1,2,3,4,5,9,9,0,1,2,3,4,5,6,6,9,1,2,3,4,5,6,9,9,1,2,3,4,5,6,9,6,9,6,9,0,0,0,6,9,1,2,3,4,5,6,9,6,1,2,3,4,5,6,9,1,2,3,4,5,6,9,1,2,3,4,5,6,9,0],"f":[0,0,0,0,0,0,0,0,[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[1,1],[2,2],[3,3],[4,4],[5,5],[[[6,[-1]]],[[6,[-1]]],[7,8]],[9,9],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,-2],10,[],[]],[[-1,11],12,[]],[[1,11],12],[[2,11],12],[[3,11],12],[[4,11],12],[[5,11],12],[9,[[16,[[14,[13]],15]]]],[9,[[14,[13]]]],0,[[1,17],18],[[2,17],18],[[3,17],18],[[4,17],18],[[5,17],18],[[[6,[-1]],17],18,[19,8]],[[[6,[-1]],17],18,8],[[9,17],18],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[-1,-1,[]],[9,[[21,[[20,[11]]]]]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[[[6,[-1]]],[[21,[13]]],8],[9,[[21,[11]]]],[[[22,[11]]],9],[[[22,[11]],-1],[[6,[-1]]],8],[11,13],[[[6,[-1]]],[[10,[23,[21,[23]]]]],8],[9,[[10,[23,[21,[23]]]]]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,24,[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,[[16,[-2]]],[],[]],[-1,25,[]],[-1,25,[]],[-1,25,[]],[-1,25,[]],[-1,25,[]],[-1,25,[]],[-1,25,[]],[[13,-1],[[6,[-1]]],8]],"c":[],"p":[[3,"SIMPLE_ENCODE_SET",0],[3,"QUERY_ENCODE_SET",0],[3,"DEFAULT_ENCODE_SET",0],[3,"PATH_SEGMENT_ENCODE_SET",0],[3,"USERINFO_ENCODE_SET",0],[3,"PercentEncode",0],[8,"Clone",107],[8,"EncodeSet",0],[3,"PercentDecode",0],[15,"tuple"],[15,"u8"],[15,"bool"],[15,"str"],[4,"Cow",108],[3,"Utf8Error",109],[4,"Result",110],[3,"Formatter",111],[6,"Result",111],[8,"Debug",111],[3,"Vec",112],[4,"Option",113],[15,"slice"],[15,"usize"],[3,"String",114],[3,"TypeId",115]],"b":[[50,"impl-Debug-for-PercentEncode%3C\'a,+E%3E"],[51,"impl-Display-for-PercentEncode%3C\'a,+E%3E"]]},\
"physical_nic":{"doc":"Defines a trait PhysicalNic that must be implemented by …","t":"IKK","n":["PhysicalNic","return_rx_queues","return_tx_queues"],"q":[[0,"physical_nic"],[3,"nic_queues"],[4,"alloc::vec"],[5,"nic_queues"]],"d":["This trait must be implemented by any NIC driver that …","Returns the RxQueues owned by a virtual NIC back to the …","Returns the TxQueues owned by a virtual NIC back to the …"],"i":[0,5,5],"f":[0,[[-1,[2,[[1,[-2,-3]]]]],3,[],[],[]],[[-1,[2,[[4,[-2,-3]]]]],3,[],[],[]]],"c":[],"p":[[3,"RxQueue",3],[3,"Vec",4],[15,"tuple"],[3,"TxQueue",3],[8,"PhysicalNic",0]],"b":[]},\
"pic":{"doc":"Support for the x86 PIC (8259 Programmable Interrupt …","t":"DRDRLLLLLLLLLLLLMMLLMMLLLLLL","n":["ChainedPics","IRQ_BASE_OFFSET","IrqStatusRegisters","PIC_SPURIOUS_INTERRUPT_IRQ","borrow","borrow","borrow_mut","borrow_mut","fmt","fmt","from","from","init","into","into","mask_irqs","master_irr","master_isr","notify_end_of_interrupt","read_isr_irr","slave_irr","slave_isr","try_from","try_from","try_into","try_into","type_id","type_id"],"q":[[0,"pic"],[28,"core::fmt"],[29,"core::fmt"],[30,"core::any"]],"d":["A pair of chained PIC chips, which represents the standard …","The offset added to the first IRQ: 0x20.","The set of status registers for both PIC chips.","The IRQ number reserved for spurious PIC interrupts (as …","","","","","","","Returns the argument unchanged.","Returns the argument unchanged.","Create a new interface for the standard PIC1 and PIC2 …","Calls U::from(self).","Calls U::from(self).","Each mask is a bitwise mask for each IRQ line, with the …","","","Figure out which (if any) PICs in our chain need to know …","Reads the ISR and IRR registers of both the master and …","","","","","","","",""],"i":[0,0,0,0,1,5,1,5,1,1,1,5,5,1,5,5,1,1,5,5,1,1,1,5,1,5,1,5],"f":[0,0,0,0,[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[-1,-2,[],[]],[[1,2],3],[[1,2],3],[-1,-1,[]],[-1,-1,[]],[[4,4],5],[-1,-2,[],[]],[-1,-2,[],[]],[[5,4,4],6],0,0,[[5,4],6],[5,1],0,0,[-1,[[7,[-2]]],[],[]],[-1,[[7,[-2]]],[],[]],[-1,[[7,[-2]]],[],[]],[-1,[[7,[-2]]],[],[]],[-1,8,[]],[-1,8,[]]],"c":[],"p":[[3,"IrqStatusRegisters",0],[3,"Formatter",28],[6,"Result",28],[15,"u8"],[3,"ChainedPics",0],[15,"tuple"],[4,"Result",29],[3,"TypeId",30]],"b":[[8,"impl-Display-for-IrqStatusRegisters"],[9,"impl-Debug-for-IrqStatusRegisters"]]},\
diff --git a/doc/src/arm_boards/lib.rs.html b/doc/src/arm_boards/lib.rs.html
index 4d7d720762..6196ab7757 100644
--- a/doc/src/arm_boards/lib.rs.html
+++ b/doc/src/arm_boards/lib.rs.html
@@ -72,6 +72,9 @@
72
73
74
+75
+76
+77
//! Configuration and definitions for specific boards on aarch64 systems.
//!
//! | Board Name | Num CPUs | Interrupt Controller | Secondary CPU Startup Method |
@@ -129,6 +132,9 @@
// aarch64 manuals define the default timer IRQ number to be 30.
pub cpu_local_timer_ppi: u8,
+ /// The IRQ numbers reserved for legacy PCI interrupts: INTA, INTB, INTC and INTD.
+ pub pci_intx: [u8; 4],
+
pub pci_ecam: PciEcamConfig,
}
diff --git a/doc/src/device_manager/lib.rs.html b/doc/src/device_manager/lib.rs.html
index 84d80530b9..ae2c9aefe4 100644
--- a/doc/src/device_manager/lib.rs.html
+++ b/doc/src/device_manager/lib.rs.html
@@ -286,16 +286,25 @@
286
287
288
+289
+290
+291
+292
+293
+294
+295
+296
+297
+298
#![no_std]
#![cfg_attr(target_arch = "x86_64", feature(trait_alias))]
extern crate alloc;
-use log::{info, debug};
+use log::*;
#[cfg(target_arch = "x86_64")]
use {
- log::{error, warn},
mpmc::Queue,
event_types::Event,
memory::MemoryManagementInfo,
@@ -369,15 +378,16 @@
mouse::init(ps2_controller.mouse_ref(), mouse_producer)?;
}
+ pci::init()?;
+
// Initialize/scan the PCI bus to discover PCI devices
for dev in pci::pci_device_iter()? {
debug!("Found PCI device: {:X?}", dev);
}
- // No NIC support on aarch64 at the moment
- #[cfg(target_arch = "x86_64")] {
-
// store all the initialized ixgbe NICs here to be added to the network interface list
+ // No NIC support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")]
let mut ixgbe_devs = Vec::new();
// Iterate over all PCI devices and initialize the drivers for the devices we support.
@@ -389,6 +399,8 @@
}
// If this is a storage device, initialize it as such.
+ // No storage device support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")]
match storage_manager::init_device(dev) {
// Successfully initialized this storage device.
Ok(Some(_storage_controller)) => continue,
@@ -405,6 +417,8 @@
// If this is a network device, initialize it as such.
// Look for networking controllers, specifically ethernet cards
+ // No NIC support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")]
if dev.class == 0x02 && dev.subclass == 0x00 {
if dev.vendor_id == e1000::INTEL_VEND && dev.device_id == e1000::E1000_DEV {
info!("e1000 PCI device found at: {:?}", dev.location);
@@ -455,18 +469,25 @@
}
// Once all the NICs have been initialized, we can store them and add them to the list of network interfaces.
- let ixgbe_nics = ixgbe::IXGBE_NICS.call_once(|| ixgbe_devs);
- for ixgbe_nic_ref in ixgbe_nics.iter() {
- net::register_device(ixgbe_nic_ref);
+ // No NIC support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")] {
+ let ixgbe_nics = ixgbe::IXGBE_NICS.call_once(|| ixgbe_devs);
+ for ixgbe_nic_ref in ixgbe_nics.iter() {
+ net::register_device(ixgbe_nic_ref);
+ }
}
// Convenience notification for developers to inform them of no networking devices
+ // No NIC support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")]
if net::get_default_interface().is_none() {
warn!("Note: no network devices found on this system.");
}
// Discover filesystems from each storage device on the storage controllers initialized above
// and mount each filesystem to the root directory by default.
+ // No storage device support on aarch64 at the moment
+ #[cfg(target_arch = "x86_64")]
if false {
for storage_device in storage_manager::storage_devices() {
let disk = fatfs_adapter::FatFsAdapter::new(
@@ -501,7 +522,6 @@
}
}
}
- }
Ok(())
}
diff --git a/doc/src/ixgbe/lib.rs.html b/doc/src/ixgbe/lib.rs.html
index 944886b9ba..b5d7efaf0a 100644
--- a/doc/src/ixgbe/lib.rs.html
+++ b/doc/src/ixgbe/lib.rs.html
@@ -1273,6 +1273,8 @@
1273
1274
1275
+1276
+1277
//! An ixgbe driver for a 82599 10GbE Network Interface Card.
//!
//! Currently we support basic send and receive, Receive Side Scaling (RSS), 5-tuple filters, and MSI interrupts.
@@ -1619,8 +1621,10 @@
// enable msi-x interrupts if required and return the assigned interrupt numbers
let interrupt_num =
if let Some(interrupt_handlers) = interrupts {
- ixgbe_pci_dev.pci_enable_msix()?;
- ixgbe_pci_dev.pci_set_interrupt_disable_bit();
+ // no need to disable legacy interrupts, it was done during device initialization.
+ // ixgbe_pci_dev.pci_set_interrupt_disable_bit(true);
+
+ ixgbe_pci_dev.pci_enable_msix()?;
Self::enable_msix_interrupts(&mut mapped_registers1, &mut rx_queues, &mut vector_table, &interrupt_handlers)?
}
else {
diff --git a/doc/src/pci/lib.rs.html b/doc/src/pci/lib.rs.html
index e0997a0bee..0b4d7f01ae 100644
--- a/doc/src/pci/lib.rs.html
+++ b/doc/src/pci/lib.rs.html
@@ -924,11 +924,95 @@
924
925
926
+927
+928
+929
+930
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+932
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//! PCI Configuration Space Access
//!
//! Note: while pci currently uses port-io on x86 and mmio on aarch64,
//! x86 may also support memory-based PCI configuration in the future;
//! port-io is the legacy way to access the config space.
+//!
+//! For context on the various interrupt mechanisms (MSI/MSI-X/INTx):
+//! - [this StackExchange reply](https://electronics.stackexchange.com/a/343218)
+//! - PCI Express Base Specification, Revision 2, Chapter 6.1 - Interrupt & PME Support
#![no_std]
#![allow(dead_code)]
@@ -936,7 +1020,7 @@
extern crate alloc;
use log::*;
-use core::{fmt, ops::{Deref, DerefMut}, mem::size_of};
+use core::{fmt, ops::{Deref, DerefMut}, mem::size_of, task::Waker};
use alloc::vec::Vec;
use spin::{Once, Mutex};
use memory::{PhysicalAddress, BorrowedSliceMappedPages, Mutable, MappedPages, map_frame_range, MMIO_FLAGS};
@@ -950,7 +1034,10 @@
use port_io::Port;
#[cfg(target_arch = "aarch64")]
-use arm_boards::BOARD_CONFIG;
+use {
+ arm_boards::BOARD_CONFIG,
+ interrupts::{EoiBehaviour, interrupt_handler, init_pci_interrupts},
+};
#[derive(Debug, Copy, Clone)]
/// The span of bytes within a 4-byte chunk that a PCI register occupies.
@@ -1047,6 +1134,8 @@
pci_register!(PCI_MIN_GRANT, 0x3E, 1);
pci_register!(PCI_MAX_LATENCY, 0x3F, 1);
+const PCI_COMMAND_INT_DISABLED: u16 = 1 << 10;
+
#[repr(u8)]
pub enum PciCapability {
Msi = 0x05,
@@ -1133,6 +1222,37 @@
Ok(get_pci_buses()?.iter().flat_map(|b| b.devices.iter()))
}
+static INTX_DEVICES: Mutex<Vec<&'static PciDevice>> = Mutex::new(Vec::new());
+
+// Architecture-independent PCI interrupt handler
+// Currently aarch64-only, because legacy interrupts aren't supported on x86 yet.
+#[cfg(target_arch = "aarch64")]
+interrupt_handler!(pci_int_handler, None, _stack_frame, {
+ let devices = INTX_DEVICES.lock();
+
+ for device in &*devices {
+ if device.pci_get_interrupt_status(true) {
+ device.pci_enable_interrupts(false);
+ log::info!("Device {} triggered an interrupt", device.location);
+
+ let reader = device.interrupt_waker.lock();
+ match &*reader {
+ Some(waker) => waker.wake_by_ref(),
+ None => log::error!("Device doesn't have an interrupt waker!"),
+ }
+ }
+ }
+
+ EoiBehaviour::HandlerDidNotSendEoi
+});
+
+/// Initializes the PCI interrupt handler
+pub fn init() -> Result<(), &'static str> {
+ #[cfg(target_arch = "aarch64")]
+ init_pci_interrupts([pci_int_handler; 4])?;
+
+ Ok(())
+}
/// A PCI bus, which contains a list of PCI devices on that bus.
#[derive(Debug)]
@@ -1212,8 +1332,12 @@
int_pin: location.pci_read_8(PCI_INTERRUPT_PIN),
int_line: location.pci_read_8(PCI_INTERRUPT_LINE),
location,
+ interrupt_waker: Mutex::new(None),
};
+ // disable legacy interrupts initially
+ device.pci_enable_interrupts(false);
+
device_list.push(device);
}
}
@@ -1432,18 +1556,21 @@
}
/// Sets the PCI device's command bit 10 to disable legacy interrupts
- pub fn pci_set_interrupt_disable_bit(&self) {
+ pub fn pci_set_interrupt_disable_bit(&self, bit: bool) {
let command = self.pci_read_16(PCI_COMMAND);
- trace!("pci_set_interrupt_disable_bit: PciDevice: {}, read value: {:#x}", self, command);
+ // trace!("pci_set_interrupt_disable_bit: PciDevice: {}, read value: {:#x}", self, command);
- const INTERRUPT_DISABLE: u16 = 1 << 10;
- self.pci_write_16(PCI_COMMAND, command | INTERRUPT_DISABLE);
+ let new_value = match bit {
+ true => command | PCI_COMMAND_INT_DISABLED,
+ false => command & !PCI_COMMAND_INT_DISABLED,
+ };
+ self.pci_write_16(PCI_COMMAND, new_value);
- trace!("pci_set_interrupt_disable_bit: PciDevice: {} read value AFTER WRITE CMD: {:#x}",
- self,
- self.pci_read_16(PCI_COMMAND),
- );
- }
+ /*trace!("pci_set_interrupt_disable_bit: PciDevice: {} read value AFTER WRITE CMD: {:#x}",
+ self,
+ self.pci_read_16(PCI_COMMAND),
+ );*/
+ }
/// Explores the PCI config space and returns address of requested capability, if present.
/// PCI capabilities are stored as a linked list in the PCI config space,
@@ -1515,6 +1642,9 @@
/// the bus, slot, and function number that locates this PCI device in the bus tree.
pub location: PciLocation,
+ /// The handling task for legacy PCI interrupts
+ pub interrupt_waker: Mutex<Option<Waker>>,
+
/// The class code, used to determine device type.
pub class: u8,
/// The subclass code, used to determine device type.
@@ -1755,6 +1885,36 @@
Ok((int_line, int_pin))
}
+
+ /// Enables/Disables legacy (INTx) interrupts for this device
+ pub fn pci_enable_interrupts(&self, enable: bool) {
+ self.pci_set_interrupt_disable_bit(!enable);
+ }
+
+ /// Reads and returns this PCI device's interrupt status flag.
+ pub fn pci_get_interrupt_status(&self, check_enabled: bool) -> bool {
+ const PCI_STATUS_INT: u16 = 1 << 3;
+
+ let interrupt_enabled = || (self.pci_read_16(PCI_COMMAND) & PCI_COMMAND_INT_DISABLED) == 0;
+ let pending_interrupt = || (self.pci_read_16(PCI_STATUS) & PCI_STATUS_INT ) != 0;
+
+ ((!check_enabled) || interrupt_enabled()) && pending_interrupt()
+ }
+
+ /// Sets a task waker to be used when this device triggers an interrupt
+ ///
+ /// Returns the previous interrupt waker for this device, if there was one.
+ pub fn set_interrupt_waker(&'static self, waker: Waker) -> Option<Waker> {
+ let mut handle = self.interrupt_waker.lock();
+ let prev_value = handle.replace(waker);
+
+ if prev_value.is_none() {
+ let mut intx_devices = INTX_DEVICES.lock();
+ intx_devices.push(self)
+ }
+
+ prev_value
+ }
}
impl Deref for PciDevice {