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plf_dram.c
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/*
* C code entry: dram_init_main();
*/
#include <types.h>
#include <common.h>
#include <config.h>
#include <dram_param.h>
// #define DRAM_INIT_DEBUG 0 // defined in Makefile: please use "make debug"
#ifdef CSIM_ASIC
#define ASIC_CSIM
#elif defined(CSIM_FPGA)
#define SDRAM_FPGA
#else
#error Please define => simulation type
#endif
struct sp_registers {
unsigned int sp_register[1024][32];
};
static volatile struct sp_registers *sp_reg_ptr = (volatile struct sp_registers *)(RF_GRP(0, 0));
#define SP_REG(GROUP, OFFSET) (sp_reg_ptr->sp_register[GROUP][OFFSET])
struct umctl2_regs {
unsigned int umctl2_reg[1024]; /* change the size here, (area >> 2) */
};
static volatile struct umctl2_regs *umctl2_reg_ptr = (volatile struct umctl2_regs *)(UMCTL2_REG_Base);
#define UMCTL2_REG(OFFSET) (umctl2_reg_ptr->umctl2_reg[OFFSET >> 2])
#define TEST_LEN_0 (4 << 10)
#ifdef SDRAM0_SIZE_256Mb
#define TEST_LEN_ALL (32 << 20)
#elif defined(SDRAM0_SIZE_512Mb)
#define TEST_LEN_ALL (64 << 20)
#elif defined(SDRAM0_SIZE_1Gb)
#define TEST_LEN_ALL (128 << 20)
#elif defined(SDRAM0_SIZE_2Gb)
#define TEST_LEN_ALL (256 << 20)
#elif defined(SDRAM0_SIZE_4Gb)
#define TEST_LEN_ALL (512 << 20)
#elif defined(SDRAM0_SIZE_8Gb)
#define TEST_LEN_ALL (1024 << 20)
#else
#error Please assign TEST_LEN_ALL
#endif
#define SDRAM0_SIZE TEST_LEN_ALL
#define SDRAM1_SIZE SDRAM0_SIZE
#ifdef PLATFORM_PENTAGRAM
static const unsigned int dram_base_addr[] = {0, SDRAM0_SIZE};
#else
static const unsigned int dram_base_addr[] = {0x20000000, SDRAM0_SIZE};
#endif
//static const unsigned int dram_size[] = {SDRAM0_SIZE, SDRAM1_SIZE};
#define DRAM_0_SDC_REG_BASE 33
#define DRAM_0_PHY_REG_BASE 50
#define DRAM_1_SDC_REG_BASE 0 /* N/A */
#define DRAM_1_PHY_REG_BASE 0 /* N/A */
#define SCAN_TRIM_LEN 5
static unsigned int rgst_value = 0;
static unsigned int aphy_select_value = 0;
static unsigned int ckobd_training_flag = 0;
static unsigned int ckobd_re_training_number = 0;
static unsigned int data_byte_0_RDQSG_left_total_tap = 0;
static unsigned int data_byte_0_RDQSG_right_total_tap = 0;
static unsigned int data_byte_1_RDQSG_left_total_tap = 0;
static unsigned int data_byte_1_RDQSG_right_total_tap = 0;
static unsigned int gAC, gACK, gCK;
#ifdef CONFIG_DRAM_SIZE_USE_OTP
static unsigned int DRAM_SIZE_FLAG;
#define DRAM_SIZE_512Mb 0x0
#define DRAM_SIZE_1Gb 0x1
#define DRAM_SIZE_2Gb 0x2
#define DRAM_SIZE_4Gb 0x3
#endif
#if (defined(DRAMSCAN) || defined(SISCOPE))
static unsigned int scan_val_190;
#endif
u32 mp;
#ifdef PLATFORM_PENTAGRAM
#define CHIP_WARM_RESET
#endif
#define SDRAM_WATCHDOG
#ifdef SDRAM_WATCHDOG
#define WATCHDOG_CMD_CNT_WR_UNLOCK 0xAB00
#define WATCHDOG_CMD_CNT_WR_LOCK 0xAB01
#define WATCHDOG_CMD_CNT_WR_MAX 0xDEAF
#define WATCHDOG_CMD_PAUSE 0x3877
#define WATCHDOG_CMD_RESUME 0x4A4B
#define WATCHDOG_CMD_INTR_CLR 0x7482
#endif
void get_sdc_phy_addr(unsigned int dram_id, unsigned int *sdc, unsigned int *phy)
{
const unsigned int dram_sdc_reg_addr[] = {DRAM_0_SDC_REG_BASE, DRAM_1_SDC_REG_BASE};
const unsigned int dram_phy_reg_addr[] = {DRAM_0_PHY_REG_BASE, DRAM_1_PHY_REG_BASE};
if (dram_id < (sizeof(dram_sdc_reg_addr) / sizeof(dram_sdc_reg_addr[0]))) {
*sdc = dram_sdc_reg_addr[dram_id];
*phy = dram_phy_reg_addr[dram_id];
} else {
prn_string("Err: get_sdc_phy_addr, invalid dram_id\n");
while (1);
}
}
void wait_loop(unsigned int wait_counter)
{
unsigned int i;
for (i = 0; i < wait_counter; i++) {
__asm__("nop");
}
}
// ***********************************************************************
// * FUNC : DPCU_DT_RESULT_DUMP
// * PARAM : dram_id
// * PURPOSE : Dump DPCU Training information
// ***********************************************************************
void DPCU_DT_RESULT_DUMP(unsigned int dram_id)
{
unsigned int SDC_BASE_GRP = 0;
unsigned int PHY_BASE_GRP = 0;
unsigned int temp_a = 0;
unsigned int temp_b = 0;
unsigned int temp_c = 0;
unsigned int only_dump_PSD = 0;
unsigned int RDQS_IPRD_TAP_NO = 0;
if (dram_id == 0) {
prn_string("DPCU_DT_INFO : ----- DUMP DRAM-0 delay line status -----\n\n");
} else {
prn_string("DPCU_DT_INFO : ----- DUMP DRAM-1 delay line status -----\n\n");
}
// -------------------------------------------------------
// 0. DDR_PHY RGST GRP selection
// -------------------------------------------------------
get_sdc_phy_addr(dram_id, &SDC_BASE_GRP, &PHY_BASE_GRP);
// DUMP SSCPLL Speed
prn_string("DPCU_DT_INFO : \t********** DRAM SPEED **********\n");
temp_a = (SP_REG(PHY_BASE_GRP, 12) >> 0) & 0x3F;
prn_string(" SSCPLL Setting =");
prn_byte(temp_a);
// DUMP CK0BD
prn_string("DPCU_DT_INFO : \t********** DDRPHY Setting **********\n");
temp_a = (SP_REG(PHY_BASE_GRP, 17) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP, 17) >> 8) & 0x3F;
temp_c = (SP_REG(PHY_BASE_GRP, 17) >> 0) & 0x3F;
prn_string(" ACK0BD=");
prn_decimal(temp_a);
prn_string(" AC0BD=");
prn_decimal(temp_b);
prn_string(" CK0BD=");
prn_decimal(temp_c);
prn_string(" \n\n");
// DUMP INIT & Training flag
temp_a = SP_REG(PHY_BASE_GRP, 2) & 0x03;
temp_b = temp_a & 0x01;
temp_c = (temp_a >> 1) & 0x01;
prn_string("DPCU_DT_INFO : \t********** DUMP APHY INIT flag **********\n");
prn_string(" Init done flag =");
prn_decimal(temp_b);
prn_string("(0 : means don't init, 1 : means init done) \n");
prn_string(" Init error flag =");
prn_decimal(temp_c);
prn_string("(0 : means init pass, 1 : means init error) \n\n");
// initial error
if (temp_c == 1) {
prn_string("DPCU_DT_INFO : \t********** DUMP APHY INIT error information **********\n");
temp_a = (SP_REG(PHY_BASE_GRP, 2) >> 8) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP, 2) >> 9) & 0x01;
prn_string("\tCTCAL_ERR flag =");
prn_decimal(temp_a);
prn_string("\tSSCPLL_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP, 2) >> 10) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP, 2) >> 11) & 0x01;
prn_string("\tDDL_ERR flag =");
prn_decimal(temp_a);
prn_string("\tPZQ_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
}
temp_a = SP_REG(PHY_BASE_GRP + 1, 0) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 1, 0) >> 8) & 0x3F;
prn_string("DPCU_DT_INFO : \t********** DUMP Training flag **********\n");
prn_string(" Training done flag = ");
prn_decimal(temp_a);
prn_string("(0:don't train, 1 : means training done) \n");
prn_string(" Training error flag =");
prn_byte(temp_b);
prn_string("(0:train pass, other : means training error) \n\n");
// training error
if (temp_b != 0) {
prn_string("DPCU_DT_INFO : \t********** DUMP APHY DX0 training error information **********\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 2) >> 8) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 2, 2) >> 9) & 0x01;
prn_string("\tWL_ERR flag =");
prn_decimal(temp_a);
prn_string("\tRG_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 2) >> 10) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 2, 2) >> 11) & 0x01;
prn_string("\tRDE_ERR flag =");
prn_decimal(temp_a);
prn_string("\tREYE_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 2) >> 12) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 2, 2) >> 13) & 0x01;
prn_string("\tWDE_ERR flag =");
prn_decimal(temp_a);
prn_string("\tWEYE_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 2) >> 16) & 0x0F;
temp_b = (SP_REG(PHY_BASE_GRP + 2, 2) >> 20) & 0x0F;
prn_string("\tWL_ERR infor =");
prn_byte(temp_a);
prn_string("\tRG_ERR infor =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 2) >> 24) & 0x0F;
temp_b = (SP_REG(PHY_BASE_GRP + 2, 2) >> 28) & 0x0F;
prn_string("\tREYE_ERR infor =");
prn_byte(temp_a);
prn_string("\tWEYE_ERR infor =");
prn_byte(temp_b);
prn_string("\n");
prn_string("DPCU_DT_INFO : \t********** DUMP APHY DX1 training error information **********\n");
temp_a = (SP_REG(PHY_BASE_GRP + 3, 2) >> 8) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 2) >> 9) & 0x01;
prn_string("\tWL_ERR flag =");
prn_decimal(temp_a);
prn_string("\tRG_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 3, 2) >> 10) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 2) >> 11) & 0x01;
prn_string("\tRDE_ERR flag =");
prn_decimal(temp_a);
prn_string("\tREYE_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 3, 2) >> 12) & 0x01;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 2) >> 13) & 0x01;
prn_string("\tWDE_ERR flag =");
prn_decimal(temp_a);
prn_string("\tWEYE_ERR flag =");
prn_decimal(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 3, 2) >> 16) & 0x0F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 2) >> 20) & 0x0F;
prn_string("\tWL_ERR infor =");
prn_byte(temp_a);
prn_string("\tRG_ERR infor =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 3, 2) >> 24) & 0x0F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 2) >> 28) & 0x0F;
prn_string("\tREYE_ERR infor =");
prn_byte(temp_a);
prn_string("\tWEYE_ERR infor =");
prn_byte(temp_b);
prn_string("\n");
}
// DUMP IPRD register
prn_string("DPCU_DT_INFO : \t********** DUMP initial DDR period **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 3) >> 0) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 3) >> 0) & 0xFF;
prn_string("\tDX0 : WL_IPRD =");
prn_byte(temp_a);
prn_string("\tDX1 : WL_IPRD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 3) >> 8) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 3) >> 8) & 0xFF;
prn_string("\tDX0 : RG_IPRD =");
prn_byte(temp_a);
prn_string("\tDX1 : RG_IPRD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 3) >> 16) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 3) >> 16) & 0xFF;
prn_string("\tDX0 : RDQS_IPRD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQS_IPRD =");
prn_byte(temp_b);
prn_string("\n");
if (temp_a > temp_b) {
RDQS_IPRD_TAP_NO = temp_b;
} else {
RDQS_IPRD_TAP_NO = temp_a;
}
temp_a = (SP_REG(PHY_BASE_GRP + 2, 3) >> 24) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 3) >> 24) & 0xFF;
prn_string("\tDX0 : WDQS_IPRD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQS_IPRD =");
prn_byte(temp_b);
prn_string("\n\n");
// DUMP PSD register
prn_string("DPCU_DT_INFO : \t********** DUMP Training PSD status **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 4) >> 0) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 4) >> 0) & 0xFF;
prn_string("\tDX0 : WL_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : WL_PSD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 4) >> 8) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 4) >> 8) & 0xFF;
prn_string("\tDX0 : WL_SEL =");
prn_byte(temp_a);
prn_string("\tDX1 : WL_SEL =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 6) >> 0) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 6) >> 0) & 0xFF;
prn_string("\tDX0 : REYE_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : REYE_PSD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 7) >> 0) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 7) >> 0) & 0xFF;
prn_string("\tDX0 : WEYE_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : WEYE_PSD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 14) >> 0) & 0x1F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 14) >> 0) & 0x1F;
prn_string("\tDX0 : RG_RSL =");
prn_byte(temp_a);
prn_string("\tDX1 : RG_RSL =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 14) >> 8) & 0x03;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 14) >> 8) & 0x03;
prn_string("\tDX0 : RG_PHA =");
prn_byte(temp_a);
prn_string("\tDX1 : RG_PHA =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 14) >> 16) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 14) >> 16) & 0xFF;
prn_string("\tDX0 : RG_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : RG_PSD =");
prn_byte(temp_b);
prn_string("\n\n");
prn_string("DPCU_DT_INFO : \t********** DUMP RG L-side & R-side status **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 0) & 0x1F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 0) & 0x1F;
prn_string("\tDX0 : L_SIDE_RSL =");
prn_byte(temp_a);
prn_string("\tDX1 : L_SIDE_RSL =");
prn_byte(temp_b);
prn_string("\n");
data_byte_0_RDQSG_left_total_tap = temp_a * RDQS_IPRD_TAP_NO;
data_byte_1_RDQSG_left_total_tap = temp_b * RDQS_IPRD_TAP_NO;
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 5) & 0x03;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 5) & 0x03;
prn_string("\tDX0 : L_SIDE_PHA =");
prn_byte(temp_a);
prn_string("\tDX1 : L_SIDE_PHA =");
prn_byte(temp_b);
prn_string("\n");
data_byte_0_RDQSG_left_total_tap = (temp_a * RDQS_IPRD_TAP_NO / 2) + data_byte_0_RDQSG_left_total_tap;
data_byte_1_RDQSG_left_total_tap = (temp_b * RDQS_IPRD_TAP_NO / 2) + data_byte_1_RDQSG_left_total_tap;
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 8) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 8) & 0xFF;
prn_string("\tDX0 : L_SIDE_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : L_SIDE_PSD =");
prn_byte(temp_b);
prn_string("\n");
data_byte_0_RDQSG_left_total_tap = temp_a + data_byte_0_RDQSG_left_total_tap;
data_byte_1_RDQSG_left_total_tap = temp_b + data_byte_1_RDQSG_left_total_tap;
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 16) & 0x1F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 16) & 0x1F;
prn_string("\tDX0 : R_SIDE_RSL =");
prn_byte(temp_a);
prn_string("\tDX1 : R_SIDE_RSL =");
prn_byte(temp_b);
prn_string("\n");
data_byte_0_RDQSG_right_total_tap = temp_a * RDQS_IPRD_TAP_NO;
data_byte_1_RDQSG_right_total_tap = temp_b * RDQS_IPRD_TAP_NO;
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 21) & 0x03;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 21) & 0x03;
prn_string("\tDX0 : R_SIDE_PHA =");
prn_byte(temp_a);
prn_string("\tDX1 : R_SIDE_PHA =");
prn_byte(temp_b);
prn_string("\n");
data_byte_0_RDQSG_right_total_tap = (temp_a * RDQS_IPRD_TAP_NO / 2) + data_byte_0_RDQSG_right_total_tap;
data_byte_1_RDQSG_right_total_tap = (temp_b * RDQS_IPRD_TAP_NO / 2) + data_byte_1_RDQSG_right_total_tap;
temp_a = (SP_REG(PHY_BASE_GRP + 2, 15) >> 24) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 15) >> 24) & 0xFF;
prn_string("\tDX0 : R_SIDE_PSD =");
prn_byte(temp_a);
prn_string("\tDX1 : R_SIDE_PSD =");
prn_byte(temp_b);
prn_string("\n\n");
data_byte_0_RDQSG_right_total_tap = temp_a + data_byte_0_RDQSG_right_total_tap;
data_byte_1_RDQSG_right_total_tap = temp_b + data_byte_1_RDQSG_right_total_tap;
prn_string("DPCU_DT_INFO : \t********** DUMP R/W EYE status **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 16) >> 0) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 16) >> 0) & 0xFF;
prn_string("\tDX0 : REYE_MIN =");
prn_byte(temp_a);
prn_string("\tDX1 : REYE_MIN =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 16) >> 8) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 16) >> 8) & 0xFF;
prn_string("\tDX0 : REYE_MAX =");
prn_byte(temp_a);
prn_string("\tDX1 : REYE_MAX =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 16) >> 16) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 16) >> 16) & 0xFF;
prn_string("\tDX0 : WEYE_MIN =");
prn_byte(temp_a);
prn_string("\tDX1 : WEYE_MIN =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 16) >> 24) & 0xFF;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 16) >> 24) & 0xFF;
prn_string("\tDX0 : WEYE_MAX =");
prn_byte(temp_a);
prn_string("\tDX1 : WEYE_MAX =");
prn_byte(temp_b);
prn_string("\n\n");
if (!only_dump_PSD) {
prn_string("DPCU_DT_INFO : \t********** DUMP REYE BDD status **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 11) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 11) >> 0) & 0x3F;
prn_string("\tDX0 : RDQS_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQS_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 12) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 12) >> 0) & 0x3F;
prn_string("\tDX0 : RDQ0_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ0_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 12) >> 8) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 12) >> 8) & 0x3F;
prn_string("\tDX0 : RDQ1_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ1_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 12) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 12) >> 16) & 0x3F;
prn_string("\tDX0 : RDQ2_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ2_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 12) >> 24) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 12) >> 24) & 0x3F;
prn_string("\tDX0 : RDQ3_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ3_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 13) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 13) >> 0) & 0x3F;
prn_string("\tDX0 : RDQ4_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ4_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 13) >> 8) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 13) >> 8) & 0x3F;
prn_string("\tDX0 : RDQ5_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ5_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 13) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 13) >> 16) & 0x3F;
prn_string("\tDX0 : RDQ6_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ6_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 13) >> 24) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 13) >> 24) & 0x3F;
prn_string("\tDX0 : RDQ7_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : RDQ7_BDD =");
prn_byte(temp_b);
prn_string("\n\n");
prn_string("DPCU_DT_INFO : \t********** DUMP WEYE BDD status **********\n");
prn_string("\t[DATx8-0]\t\t[DATx8-1]\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 8) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 8) >> 0) & 0x3F;
prn_string("\tDX0 : WDM_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDM_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 8) >> 8) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 8) >> 8) & 0x3F;
prn_string("\tDX0 : WDQS_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQS_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 8) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 8) >> 16) & 0x3F;
prn_string("\tDX0 : WDQS_OE_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQS_OE_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 8) >> 24) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 8) >> 24) & 0x3F;
prn_string("\tDX0 : WDQ_OE_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ_OE_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 9) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 9) >> 0) & 0x3F;
prn_string("\tDX0 : WDQ0_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ0_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 9) >> 8) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 9) >> 8) & 0x3F;
prn_string("\tDX0 : WDQ1_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ1_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 9) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 9) >> 16) & 0x3F;
prn_string("\tDX0 : WDQ2_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ2_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 9) >> 24) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 9) >> 24) & 0x3F;
prn_string("\tDX0 : WDQ3_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ3_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 10) >> 0) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 10) >> 0) & 0x3F;
prn_string("\tDX0 : WDQ4_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ4_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 10) >> 8) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 10) >> 8) & 0x3F;
prn_string("\tDX0 : WDQ5_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ5_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 10) >> 16) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 10) >> 16) & 0x3F;
prn_string("\tDX0 : WDQ6_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ6_BDD =");
prn_byte(temp_b);
prn_string("\n");
temp_a = (SP_REG(PHY_BASE_GRP + 2, 10) >> 24) & 0x3F;
temp_b = (SP_REG(PHY_BASE_GRP + 3, 10) >> 24) & 0x3F;
prn_string("\tDX0 : WDQ7_BDD =");
prn_byte(temp_a);
prn_string("\tDX1 : WDQ7_BDD =");
prn_byte(temp_b);
prn_string("\n\n");
}
prn_string("\t-----------------------------------------------------\n\n");
// finish
prn_string("DPCU_INFO : ----- DPCU dump done -----\n\n");
} // end function => DPCU_DT_RESULT_DUMP
void assert_sdc_phy_reset(void)
{
#ifdef PLATFORM_PENTAGRAM
SP_REG(0, 21) = RF_MASK_V_SET(1 << 14); // SDCTRL0
SP_REG(0, 22) = RF_MASK_V_SET(1 << 0); // PHY
#elif defined(PLATFORM_I143)
SP_REG(0, 21) = RF_MASK_V_SET(1 << 10); // UMCTL2
SP_REG(0, 21) = RF_MASK_V_SET(1 << 14); // SDCTRL0
SP_REG(0, 22) = RF_MASK_V_SET(1 << 0); // PHY
#endif
}
void release_sdc_phy_reset(void)
{
#ifdef PLATFORM_PENTAGRAM
SP_REG(0, 21) = RF_MASK_V_CLR(1 << 14); // SDCTRL0
SP_REG(0, 22) = RF_MASK_V_CLR(1 << 0); // PHY
#elif defined(PLATFORM_I143)
SP_REG(0, 21) = RF_MASK_V_CLR(1 << 10); // UMCTL2
SP_REG(0, 21) = RF_MASK_V_CLR(1 << 14); // SDCTRL0
SP_REG(0, 22) = RF_MASK_V_CLR(1 << 0); // PHY
#endif
}
// ***********************************************************************
// * FUNC : do_system_reset_flow
// * PARAM : dram_id
// * PURPOSE : do SDC & PHY reset flow
// ***********************************************************************
void do_system_reset_flow(unsigned int dram_id)
{
assert_sdc_phy_reset();
wait_loop(1000);
release_sdc_phy_reset();
}
void dram_fill_zero(unsigned int test_size, unsigned int dram_id)
{
int idx;
volatile unsigned int *ram = (volatile unsigned int *)ADDRESS_CONVERT(dram_base_addr[dram_id]);
for (idx = 0; idx < (test_size / sizeof(unsigned int)); idx++) {
ram[idx] = 0;
}
}
int memory_rw_check(unsigned int value, unsigned int answer, int debug)
{
int ret = 0;
if (value != answer) {
if (debug) {
prn_string("\tvalue: ");
prn_dword0(value);
prn_string(", expected: ");
prn_dword0(answer);
prn_string("\n");
}
ret = -1;
}
return ret;
}
const unsigned int pattern[] = {0xAAAAAAAA, 0x55555555, 0xAAAA5555, 0x5555AAAA, 0xAA57AA57, 0xFFDDFFDD, 0x55D755D7};
int memory_rw_test_cases(int test_case, unsigned int start_addr, unsigned int test_size, int debug)
{
int ret = 0;
unsigned int i;
unsigned int test_size_word = test_size >> 2;
const int num_pattern = sizeof(pattern) / sizeof(pattern[0]);
// volatile unsigned int *ram = (volatile unsigned int *)(dram_base_addr[0]);
volatile unsigned int *ram = (volatile unsigned int *)ADDRESS_CONVERT(start_addr);
// TODO: Use CBDMA.
//dram_fill_zero(test_size, 0);
// debug = 1;
if (debug) {
prn_string("\t memory_rw_test(");
}
switch (test_case) {
case 0:
if (debug) {
prn_string("seq)");
}
for (i = 0; i < test_size_word; i++) {
ram[i] = i;
}
break;
default:
if (debug) {
prn_string("patterns)");
}
for (i = 0; i < test_size_word; i++) {
ram[i] = pattern[i % num_pattern];
}
break;
}
for (i = 0; i < test_size_word; i++) {
switch (test_case) {
case 0:
ret = memory_rw_check(ram[i], i, debug);
break;
default:
ret = memory_rw_check(ram[i], pattern[i % num_pattern], debug);
break;
}
if (ret < 0) {
if (debug) {
prn_string(" fails\n");
}
ret = -1;
break;
}
}
if (ret == 0) {
if (debug) {
prn_string(" pass\n");
}
}
return ret;
}
#define MEMORY_RW_FLAG_DBG (1 << 0)
#define MEMORY_RW_FLAG_LOOP (1 << 1)
#define MEMORY_RW_FLAG_EXIT (1 << 2)
int memory_rw_test(unsigned int start_addr, unsigned int test_len, int flag)
{
int ret;
int is_dbg = flag & MEMORY_RW_FLAG_DBG;
int exit = flag & MEMORY_RW_FLAG_EXIT;
int test_case = 0;
do {
do {
ret = memory_rw_test_cases(test_case, start_addr, test_len, is_dbg);
if ((ret < 0) && exit) {
return ret;
}
test_case++;
test_case %= 2;
} while (test_case != 0);
} while (flag & MEMORY_RW_FLAG_LOOP);
return 0;
}
// ***********************************************************************
// * FUNC : SDCTRL_TRIMMER_TEST
// * PARAM : dram_id
// * PURPOSE : trigger SDC.trimmer 4 modes to do random DRAM access test
// ***********************************************************************
int SDCTRL_TRIMMER_TEST(unsigned int dram_id, unsigned int start_addr, unsigned int TEST_DATA_LENGTH)
{
// H/W trimmer has beem removed.
// Just run memory test.
return ((memory_rw_test(start_addr, TEST_DATA_LENGTH, MEMORY_RW_FLAG_EXIT) < 0) ? 0 : 1);
}
// ***********************************************************************
// * FUNC : DPCU_CMD_ISSUE_SW_CMD
// * PARAM : CMD, RANK,BANK,ADDR, DATA_MASK, DATA, TRIGGER
// * PURPOSE : using CMD ISSUE issue
// ***********************************************************************
void DPCU_CMD_ISSUE_SW_CMD(unsigned int dram_id, unsigned int CMD, unsigned int RANK, unsigned int BANK, unsigned int ADDR,
unsigned int SW_WRDATA_MASK, unsigned int SW_WRDATA1_HIGH, unsigned int SW_WRDATA1_LOW,
unsigned int SW_WRDATA0_HIGH, unsigned int SW_WRDATA0_LOW, unsigned int CMD_TRIGGER)
{
unsigned int temp;
unsigned int SDC_BASE_GRP = 0,
PHY_BASE_GRP = 0;
get_sdc_phy_addr(dram_id, &SDC_BASE_GRP, &PHY_BASE_GRP);
temp = SP_REG(PHY_BASE_GRP + 1, 27) & 0xF0000000;
// fill cmd, RANK, BANK, ADDR infor
SP_REG(PHY_BASE_GRP + 1, 27) = temp | (CMD << 24) | (RANK << 20) | (BANK << 16) | (ADDR);
// fill WRdata mask
SP_REG(PHY_BASE_GRP + 2, 21) = SW_WRDATA_MASK & 0xFF;
SP_REG(PHY_BASE_GRP + 3, 21) = (SW_WRDATA_MASK >> 8) & 0xFF;
// fill WRDATA
SP_REG(PHY_BASE_GRP + 2, 22) = SW_WRDATA0_LOW;
SP_REG(PHY_BASE_GRP + 2, 23) = SW_WRDATA0_HIGH;
SP_REG(PHY_BASE_GRP + 3, 22) = SW_WRDATA1_LOW;
SP_REG(PHY_BASE_GRP + 3, 23) = SW_WRDATA1_HIGH;
// Commit the cmd setting to DPCU CMD CUE
temp = SP_REG(PHY_BASE_GRP + 1, 10);
wait_loop(10);
SP_REG(PHY_BASE_GRP + 1, 10) = temp | (1 << 8); // commit
wait_loop(10);
// Trigger CMD if need
temp = SP_REG(PHY_BASE_GRP + 1, 10);
wait_loop(10);
SP_REG(PHY_BASE_GRP + 1, 10) = temp | (CMD_TRIGGER << 9); // Trigger
} // End DPCU_CMD_ISSUE_SW_CMD
// ***********************************************************************
// * FUNC : dram_booting_flow
// * PARAM : dram_id
// * PURPOSE : to do the following sequences
// * : (1). DDR_APHY initial sequence (CTCAL->SSCPLL->PZQ)
// ***********************************************************************
int dram_booting_flow(unsigned int dram_id)
{
unsigned int SDC_BASE_GRP = 0,
PHY_BASE_GRP = 0;
unsigned int wait_flag = 0; // min
unsigned int aphy_select1_value = 0;
unsigned int aphy_select2_value = 0;
prn_string(">>> enter dram_booting_flow for DRAM");
prn_decimal(dram_id);
prn_string("\n");
// -------------------------------------------------------
// 0. SDCTRL / DDR_PHY RGST GRP selection
// -------------------------------------------------------
get_sdc_phy_addr(dram_id, &SDC_BASE_GRP, &PHY_BASE_GRP);
#ifdef PLATFORM_PENTAGRAM
// CBUS-MBUS Bridge setting
#ifdef CONFIG_DRAM_SIZE_USE_OTP
DRAM_SIZE_FLAG = ((SP_REG(350,7) >> 16) & 0x3);
if (DRAM_SIZE_FLAG == DRAM_SIZE_512Mb) {
SP_REG(5, 6) = (0x000f << 16) | (0 << 2) | (0 << 0);
} else if (DRAM_SIZE_FLAG == DRAM_SIZE_1Gb) {
SP_REG(5, 6) = (0x000f << 16) | (0 << 2) | (0 << 0);
} else if (DRAM_SIZE_FLAG == DRAM_SIZE_4Gb) {
SP_REG(5, 6) = (0x000f << 16) | (2 << 2) | (2 << 0);
} else {
DRAM_SIZE_FLAG = 0xFF;
SP_REG(5, 6) = (0x000f << 16) | (MO_SDRAM_B_SIZE << 2) | (MO_SDRAM_A_SIZE << 0);
}
#else
SP_REG(5, 6) = (0x000f << 16) | (MO_SDRAM_B_SIZE << 2) | (MO_SDRAM_A_SIZE << 0);
#endif
#elif defined(PLATFORM_I143)
SP_REG(5, 6) = (0x000f << 16) | (MO_SDRAM_B_SIZE << 2) | (MO_SDRAM_A_SIZE << 0);
#endif
// -------------------------------------------------------
// 1. DPCU_APHY_INIT setting => a001
// -------------------------------------------------------
#ifdef SDRAM_FPGA
// There are no APHY circuit in FPGA platform, so bypass this flow
#else
do_system_reset_flow(dram_id);
dbg_stamp(0xA000);
SP_REG(PHY_BASE_GRP + 0, 0) = DPCU_GLB_CFG0 | DPCU_DFI_PATH_SEL(n_DFI_PATH_DPCU);
// set MPLL_DIV to operation freq.
SP_REG(PHY_BASE_GRP + 0, 12) = MPLL_CFG1_DEF | MPLL_DIV(n_MPLL_DIV);
// set MPLL_DIV to operation freq.
SP_REG(PHY_BASE_GRP + 0, 3) = DPCU_INIT_TIMMER;
// Set DDRIO CFG
SP_REG(PHY_BASE_GRP + 0, 21) = DPCU_DDRIO_CFG3;
// set PZQ to internal mode for Q571
#ifdef USING_INTERNAL_PZQ_CAL
prn_string("\tDPCU initial : Using Internal PZQ!!\n");
SP_REG(PHY_BASE_GRP + 0, 18) = DPCU_PZQ_CFG0 | PZQ_REGI_ZQ_INTR(n_PZQ_ZQ_INTR_EN);
#else
prn_string("\tDPCU initial : Using External PZQ!!\n");
SP_REG(PHY_BASE_GRP + 0, 18) = DPCU_PZQ_CFG0;
#endif
// setting PZQ CFG1
SP_REG(PHY_BASE_GRP + 0, 19) = DPCU_PZQ_CFG1;
// setting AI CFG
#if (defined(PLATFORM_PENTAGRAM) || defined(PLATFORM_I143))
SP_REG(PHY_BASE_GRP + 0, 14) = (SP_REG(PHY_BASE_GRP + 0, 14) & 0xFFFDFFFF) | 0x00020000;
#endif
SP_REG(PHY_BASE_GRP + 0, 1) = DPCU_AI_CFG0_SELECT1;
// enable APHY_INIT start
SP_REG(PHY_BASE_GRP + 0, 1) = DPCU_AI_CFG0_SELECT1 | AI_INIT_START(n_AI_INIT_START_EN);
// wait aphy init done
wait_flag = 0;
do {
wait_flag = SP_REG(PHY_BASE_GRP + 0, 2) & 0x00000001;
} while ((wait_flag == 0));
rgst_value = (SP_REG(PHY_BASE_GRP + 0, 2) >> 8) & 0x0F;
aphy_select1_value = rgst_value;
// Disable DDR IO PAD Retention flag
// setting AI CFG
SP_REG(PHY_BASE_GRP + 0, 1) = DPCU_AI_CFG0_SELECT2;
// enable APHY_INIT start
SP_REG(PHY_BASE_GRP + 0, 1) = DPCU_AI_CFG0_SELECT2 | AI_INIT_START(n_AI_INIT_START_EN);
// wait aphy init done
wait_flag = 0;
do {
wait_flag = SP_REG(PHY_BASE_GRP + 0, 2) & 0x00000001;
} while ((wait_flag == 0));
rgst_value = (SP_REG(PHY_BASE_GRP + 0, 2) >> 8) & 0x0F;
aphy_select2_value = rgst_value;
aphy_select_value = (aphy_select1_value | aphy_select2_value);
#if (defined(PLATFORM_PENTAGRAM) || defined(PLATFORM_I143))
SP_REG(PHY_BASE_GRP + 0, 0) = SP_REG(PHY_BASE_GRP + 0, 0) & 0xFFFFFFBF;
#endif
if (rgst_value != 0) {
prn_string("<<< leave dram_booting_flow for DRAM");
prn_decimal(dram_id);
prn_string("\n");
return 0;
}