Stochastic Computing for Deep Neural Networks

Generating Posit-Based Accelerators With High-Level Synthesis

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Naive x86_64 assembly for big integer arithmetics and generating binary factorial tables

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

Course Taken @ UCMerced [2021]

Assignment codes for Introduction to Numerical Analysis (2020, FGV-EMAp).

Design and implementation of RISC-V processor with a multi-cycle datapath and controller.

Code for reproducing CoNGA 2023 results on approximate posit arithmetic

Code for reproducing CoNGA 2022 results on posit arithmetic operators

Simulations of the following computer arithmetic algorithms: Booth, Booth Radix4, Restoring, Non-Restoring, Radix4 SRT, Radix2 SRT

Study of Montgomery Modular Multiplication in Residue Number Systems

POPiX: Floating to Fixed-Point Code Generator

Design and implementation of RISC-V processor with a single-cycle datapath and controller.