Some exercises on verilog.
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Updated
Dec 21, 2023 - Verilog
Some exercises on verilog.
Smart Automation Controller for Precision Agriculture
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
FPGA Clock Configuration Device Driver Debian Package
Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.
Linux Kernel (6.1) Image, Device Trees, Debian Packages for Zynq , CycloneV SoC
A language learning solution to learn vocabulary from day-to-day objects with front-end on De1-SoC Cyclone V FPGA and backend on a Raspberry Pi, incorporating Microsoft Azure Cognitive Services
Digilent Atlys Board Linux Flash Image
Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board
Altera wrappers for C applications using Altera's 16550 UART Core through Avalon Bus on Cyclone V.
UltraZed Development
Audio Signal Processing SoC Project Website
Parse hardware design information to generate project specific machine configuration
Thesis: Custom Filter Designs on the Red Pitaya
FPGA Configuration Interface for Linux FPGA Manager Framework
Prebuilt images for Linux for the Pano Logic G2
uiomem is a Linux device driver for accessing a memory area outside the Linux Kernel management from user space.
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
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