An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Updated
Nov 12, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
😱 RoCC Accelerator Integration with Chipyard
SonicBOOM: The Berkeley Out-of-Order Machine
Network components (NIC, Switch) for FireBox
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
A fault-injection framework using Chisel and FIRRTL
BOOM's Simulation Accelerator.
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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