logic.txt

Logic for Bus Arbitrator
------------------------

if br[x] is active
    if bbusy is not active
        bg[x] and bbusy go active
    else if bg[y > x] is active
        bclr goes active
        if br[y > x] is not active
            bg[y > x] goes not active
            bg[x] and bbusy go active
    // else wait until the bus is not busy with a higher priority request


Logic for Interrupt Controller
------------------------------




Logic for a Bus Controller
--------------------------

if cpu's AS is active and the address decodes to an external bus address
    - (process) go through bus arbitration if necessary
    if external bus is clear
        // how do you determine what type of cycle to use? SIZ[1:0] is available
        - assert bus AS, DS[1:0], LWORD, A[1:0] according to modified type
        - put address modifier on the bus
        - configure the address and data transceivers accordingly
        wait until bus dtack is asserted
            - assert local dsack[1:0] accordingly
            wait until local AS is inactive
                - deassert local dsack
                - deassert bus AS, etc


    REFORMULATED
    ------------

wire [3:0] V_OE; // AH, AL, DH, DL

assign is_external = /* address matches */

if (L_AS == ACTIVE && is_external) begin
    V_OE <= 4'b1111;    // set all transceiver outputs to off
    V_DIR <= 4'b0000;
    L_DSACK0 <= INACTIVE;
    L_DSACK1 <= INACTIVE;

    V_BR <= ACTIVE;
    if (V_BGIN == ACTIVE) begin
        case (L_SIZ)
            2'b00: begin
                // TODO implement controls for DS, LWORD, etc
                V_LWORD <= 1'b0;
                V_OE <= 4'b0000;
            end
        endcase

        V_WRITE <= L_RW;
        if (L_RW == ACTIVE) begin
            V_DIR <= 4'b1100;
        end else begin
            V_DIR <= 4'b1111;
        end

        V_AS <= ACTIVE;

        if (V_DTACK == ACTIVE) begin
            L_DSACK0 <= ACTIVE;
            L_DSACK1 <= ACTIVE;
            V_AS <= INACTIVE;
        end
    end
end


Controller Buffer Truth Table
-----------------------------

CB_DH_OE
CB_DH_DIR
CB_DL_OE
CB_DL_DIR
CB_AH_OE
CB_AH_DIR
CB_AL_OE
CB_AL_DIR

DH_X_DL_OE
DH_X_DL_DIR
DH_X_AL_OE
DH_X_AL_DIR
AH_X_DL_OE
AH_X_DL_DIR