From 53c2206f689774ead285225814593b2083c911f4 Mon Sep 17 00:00:00 2001 From: Klimenty Tsoutsman Date: Thu, 7 Sep 2023 10:52:18 +1000 Subject: [PATCH] Remove reserved bit Signed-off-by: Klimenty Tsoutsman --- kernel/context_switch_regular/src/x86_64.rs | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/kernel/context_switch_regular/src/x86_64.rs b/kernel/context_switch_regular/src/x86_64.rs index 86c1b672cc..1dc3241874 100644 --- a/kernel/context_switch_regular/src/x86_64.rs +++ b/kernel/context_switch_regular/src/x86_64.rs @@ -32,17 +32,9 @@ impl ContextRegular { /// Task containing it to begin its execution at the given `rip`. pub fn new(rip: usize) -> ContextRegular { ContextRegular { - // From Intel Manual Volume 1, Chapter 3.4.3: - // - // > Following initialization of the processor the state of the - // > EFLAGS register is 00000002H. - // - // Technically speaking, I don't think it's strictly necessary to - // set the first bit, because `popfq` will ignore reserved bits - // anyway, but it doesn't hurt. - // - // The ninth bit is the interrupt enable flag. - rflags: 1 << 1 | 1 << 9, + // The ninth bit is the interrupt enable flag. When a task is first + // run, interrupts should already be enabled. + rflags: 1 << 9, r15: 0, r14: 0, r13: 0,