From a0c5281099e624b32d5b1b8840f6da59025e3761 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 27 Dec 2024 01:42:56 -0800 Subject: [PATCH] UPDATE: match chipyard DigitalTop --- src/main/scala/DigitalTop.scala | 2 +- src/main/scala/Elaborate.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/DigitalTop.scala b/src/main/scala/DigitalTop.scala index 2ed86e0..0164322 100644 --- a/src/main/scala/DigitalTop.scala +++ b/src/main/scala/DigitalTop.scala @@ -21,6 +21,6 @@ class DigitalTop extends BlackBox { val uart_0_txd = Output(Bool()) val uart_0_rxd = Input(Bool()) val clock_tap = Output(Clock()) - val axi4_lite_s_axi = new RawAXI4Lite() + val periph_axi4_s_axi = new RawAXI4Lite() }) } diff --git a/src/main/scala/Elaborate.scala b/src/main/scala/Elaborate.scala index 04754bc..0f0bedb 100644 --- a/src/main/scala/Elaborate.scala +++ b/src/main/scala/Elaborate.scala @@ -98,7 +98,7 @@ object GenerateBitstream extends App { ) - val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral").listFiles(new FileFilter { + val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.WithPeripheralAXI4LiteTinyRocketConfig/gen-collateral").listFiles(new FileFilter { def accept(file: File): Boolean = file.isFile || file.isDirectory }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath)) // Exclude files listed in excluded_sources