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  • Updated How to Read the Router Example (markdown)

    @manili manili committed Dec 31, 2020
    89c67b9

  • Updated How to Read the Router Example (markdown)

    @manili manili committed Dec 31, 2020
    483cd41

  • Updated Conditional Assignments and Memories (markdown)

    @manili manili committed Dec 31, 2020
    17acdcc

  • Updated Instantiating Modules (markdown)

    @manili manili committed Dec 31, 2020
    59c7ce6

  • Set programming language of Verilog code for correct syntax highlighting

    @piegamesde piegamesde committed Nov 24, 2019
    1a41856

  • Updated The Basics (markdown)

    @redpanda3 redpanda3 committed Oct 18, 2018
    aeb6858

  • Update filename to reflect source

    @aksell aksell committed Jul 8, 2018
    825e242

  • Update filename to reflect source

    @aksell aksell committed Jul 8, 2018
    5cb6c08

  • Edited small spelling errors

    @Arna-Maity Arna-Maity committed May 17, 2018
    e74edc0

  • Updated Conditional Assignments and Memories (markdown)

    @lucashmorais lucashmorais committed May 10, 2018
    6ec6c29

  • Updated Conditional Assignments and Memories (markdown)

    @lucashmorais lucashmorais committed May 10, 2018
    8406e24

  • remove 'a'

    @pranith pranith committed Feb 10, 2018
    a5077a4

  • update running command

    @pranith pranith committed Feb 8, 2018
    67d43ef

  • minor fix

    @schoeberl schoeberl committed Nov 21, 2017
    98d436d

  • minor fix

    @schoeberl schoeberl committed Nov 21, 2017
    7989998

  • Updated Conditional Assignments and Memories (markdown)

    @schoeberl schoeberl committed Nov 21, 2017
    0d063ea

  • Remove Latex comment

    @schoeberl schoeberl committed Nov 21, 2017
    d405e39

  • typo

    @schoeberl schoeberl committed Nov 20, 2017
    12bf59a

  • Remove duplicated text

    @schoeberl schoeberl committed Nov 20, 2017
    a73033d

  • Typo (Latex) in headers

    @schoeberl schoeberl committed Nov 20, 2017
    cc570bc

  • Minor fix so text fits to the code

    @schoeberl schoeberl committed Nov 20, 2017
    be256e8

  • Fix some *abc*+ typos to *abc*

    @schoeberl schoeberl committed Nov 6, 2017
    ff7ad49

  • Merge branch 'master' into wiki-master

    @ucbjrl ucbjrl committed Oct 19, 2017
    7659ccd

  • Merge branch 'wiki-master'

    @ucbjrl ucbjrl committed Oct 19, 2017
    31a20e8

  • Merge pull request #11 from ucb-bar/FAQ_backends Update 'Generating Verilog' instructions - --backend specification.

    @ucbjrl ucbjrl committed Oct 19, 2017
    0d3301b

  • 'Generating Verilog' example uses 'Adder' not 'GCD'.

    @ucbjrl ucbjrl committed Oct 19, 2017
    16e7640

  • Update 'Generating Verilog' instructions - --backend specification.

    @ucbjrl ucbjrl committed Oct 19, 2017
    ea3f92c

  • Merge pull request #10 from ucb-bar/fix-verilator-launch-doc Bring Wiki stuff up to date

    @chick chick committed Oct 9, 2017
    14b446e

  • Bring Wiki stuff up to date - Show --backend-name verilator method for launching - Fix what test_run_dir paths look like using run scripts

    @chick chick committed Sep 29, 2017
    1eceddc

  • Use markdown comment convention.

    @ucbjrl ucbjrl committed Sep 28, 2017
    e47cfad