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fpga/common/XUPP3R: Add RX_CLK_FROM_TX configuration parameter to XUPP3R 100G design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
1 parent 01c6d2f commit 9218698

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6 files changed

+46
-3
lines changed

6 files changed

+46
-3
lines changed

‎fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
151151
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
152152
dict set params AXIS_ETH_RX_PIPELINE "4"
153153
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
154+
dict set params ETH_RX_CLK_FROM_TX "0"
154155

155156
# Statistics counter subsystem
156157
dict set params STAT_ENABLE "1"

‎fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
151151
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
152152
dict set params AXIS_ETH_RX_PIPELINE "4"
153153
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
154+
dict set params ETH_RX_CLK_FROM_TX "0"
154155

155156
# Statistics counter subsystem
156157
dict set params STAT_ENABLE "1"

‎fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@ module fpga #
129129
parameter AXIS_ETH_TX_TS_PIPELINE = 4,
130130
parameter AXIS_ETH_RX_PIPELINE = 4,
131131
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
132+
parameter ETH_RX_CLK_FROM_TX = 0,
132133

133134
// Statistics counter subsystem
134135
parameter STAT_ENABLE = 1,
@@ -1034,6 +1035,8 @@ wire qsfp0_rx_axis_tvalid_int;
10341035
wire qsfp0_rx_axis_tlast_int;
10351036
wire [80+1-1:0] qsfp0_rx_axis_tuser_int;
10361037

1038+
wire qsfp0_rx_ptp_clk_int;
1039+
wire qsfp0_rx_ptp_rst_int;
10371040
wire [79:0] qsfp0_rx_ptp_time_int;
10381041

10391042
wire qsfp0_drp_clk = clk_125mhz_int;
@@ -1101,6 +1104,7 @@ cmac_gty_wrapper #(
11011104
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
11021105
.TX_SERDES_PIPELINE(0),
11031106
.RX_SERDES_PIPELINE(0),
1107+
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
11041108
.RS_FEC_ENABLE(1)
11051109
)
11061110
qsfp0_cmac_inst (
@@ -1166,6 +1170,8 @@ qsfp0_cmac_inst (
11661170
.rx_axis_tlast(qsfp0_rx_axis_tlast_int),
11671171
.rx_axis_tuser(qsfp0_rx_axis_tuser_int),
11681172

1173+
.rx_ptp_clk(qsfp0_rx_ptp_clk_int),
1174+
.rx_ptp_rst(qsfp0_rx_ptp_rst_int),
11691175
.rx_ptp_time(qsfp0_rx_ptp_time_int),
11701176

11711177
.rx_enable(qsfp0_rx_enable),
@@ -1203,6 +1209,8 @@ wire qsfp1_rx_axis_tvalid_int;
12031209
wire qsfp1_rx_axis_tlast_int;
12041210
wire [80+1-1:0] qsfp1_rx_axis_tuser_int;
12051211

1212+
wire qsfp1_rx_ptp_clk_int;
1213+
wire qsfp1_rx_ptp_rst_int;
12061214
wire [79:0] qsfp1_rx_ptp_time_int;
12071215

12081216
wire qsfp1_drp_clk = clk_125mhz_int;
@@ -1270,6 +1278,7 @@ cmac_gty_wrapper #(
12701278
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
12711279
.TX_SERDES_PIPELINE(0),
12721280
.RX_SERDES_PIPELINE(0),
1281+
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
12731282
.RS_FEC_ENABLE(1)
12741283
)
12751284
qsfp1_cmac_inst (
@@ -1335,6 +1344,8 @@ qsfp1_cmac_inst (
13351344
.rx_axis_tlast(qsfp1_rx_axis_tlast_int),
13361345
.rx_axis_tuser(qsfp1_rx_axis_tuser_int),
13371346

1347+
.rx_ptp_clk(qsfp1_rx_ptp_clk_int),
1348+
.rx_ptp_rst(qsfp1_rx_ptp_rst_int),
13381349
.rx_ptp_time(qsfp1_rx_ptp_time_int),
13391350

13401351
.rx_enable(qsfp1_rx_enable),
@@ -1372,6 +1383,8 @@ wire qsfp2_rx_axis_tvalid_int;
13721383
wire qsfp2_rx_axis_tlast_int;
13731384
wire [80+1-1:0] qsfp2_rx_axis_tuser_int;
13741385

1386+
wire qsfp2_rx_ptp_clk_int;
1387+
wire qsfp2_rx_ptp_rst_int;
13751388
wire [79:0] qsfp2_rx_ptp_time_int;
13761389

13771390
wire qsfp2_drp_clk = clk_125mhz_int;
@@ -1439,6 +1452,7 @@ cmac_gty_wrapper #(
14391452
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
14401453
.TX_SERDES_PIPELINE(0),
14411454
.RX_SERDES_PIPELINE(0),
1455+
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
14421456
.RS_FEC_ENABLE(1)
14431457
)
14441458
qsfp2_cmac_inst (
@@ -1504,6 +1518,8 @@ qsfp2_cmac_inst (
15041518
.rx_axis_tlast(qsfp2_rx_axis_tlast_int),
15051519
.rx_axis_tuser(qsfp2_rx_axis_tuser_int),
15061520

1521+
.rx_ptp_clk(qsfp2_rx_ptp_clk_int),
1522+
.rx_ptp_rst(qsfp2_rx_ptp_rst_int),
15071523
.rx_ptp_time(qsfp2_rx_ptp_time_int),
15081524

15091525
.rx_enable(qsfp2_rx_enable),
@@ -1541,6 +1557,8 @@ wire qsfp3_rx_axis_tvalid_int;
15411557
wire qsfp3_rx_axis_tlast_int;
15421558
wire [80+1-1:0] qsfp3_rx_axis_tuser_int;
15431559

1560+
wire qsfp3_rx_ptp_clk_int;
1561+
wire qsfp3_rx_ptp_rst_int;
15441562
wire [79:0] qsfp3_rx_ptp_time_int;
15451563

15461564
wire qsfp3_drp_clk = clk_125mhz_int;
@@ -1608,6 +1626,7 @@ cmac_gty_wrapper #(
16081626
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
16091627
.TX_SERDES_PIPELINE(0),
16101628
.RX_SERDES_PIPELINE(0),
1629+
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
16111630
.RS_FEC_ENABLE(1)
16121631
)
16131632
qsfp3_cmac_inst (
@@ -1673,6 +1692,8 @@ qsfp3_cmac_inst (
16731692
.rx_axis_tlast(qsfp3_rx_axis_tlast_int),
16741693
.rx_axis_tuser(qsfp3_rx_axis_tuser_int),
16751694

1695+
.rx_ptp_clk(qsfp3_rx_ptp_clk_int),
1696+
.rx_ptp_rst(qsfp3_rx_ptp_rst_int),
16761697
.rx_ptp_time(qsfp3_rx_ptp_time_int),
16771698

16781699
.rx_enable(qsfp3_rx_enable),
@@ -2391,6 +2412,7 @@ fpga_core #(
23912412
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
23922413
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
23932414
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
2415+
.ETH_RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
23942416

23952417
// Statistics counter subsystem
23962418
.STAT_ENABLE(STAT_ENABLE),
@@ -2536,6 +2558,8 @@ core_inst (
25362558
.qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int),
25372559
.qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int),
25382560
.qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int),
2561+
.qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
2562+
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
25392563
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
25402564

25412565
.qsfp0_rx_enable(qsfp0_rx_enable),
@@ -2594,6 +2618,8 @@ core_inst (
25942618
.qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int),
25952619
.qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int),
25962620
.qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int),
2621+
.qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
2622+
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
25972623
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
25982624

25992625
.qsfp1_rx_enable(qsfp1_rx_enable),
@@ -2652,6 +2678,8 @@ core_inst (
26522678
.qsfp2_rx_axis_tvalid(qsfp2_rx_axis_tvalid_int),
26532679
.qsfp2_rx_axis_tlast(qsfp2_rx_axis_tlast_int),
26542680
.qsfp2_rx_axis_tuser(qsfp2_rx_axis_tuser_int),
2681+
.qsfp2_rx_ptp_clk(qsfp2_rx_ptp_clk_int),
2682+
.qsfp2_rx_ptp_rst(qsfp2_rx_ptp_rst_int),
26552683
.qsfp2_rx_ptp_time(qsfp2_rx_ptp_time_int),
26562684

26572685
.qsfp2_rx_enable(qsfp2_rx_enable),
@@ -2710,6 +2738,8 @@ core_inst (
27102738
.qsfp3_rx_axis_tvalid(qsfp3_rx_axis_tvalid_int),
27112739
.qsfp3_rx_axis_tlast(qsfp3_rx_axis_tlast_int),
27122740
.qsfp3_rx_axis_tuser(qsfp3_rx_axis_tuser_int),
2741+
.qsfp3_rx_ptp_clk(qsfp3_rx_ptp_clk_int),
2742+
.qsfp3_rx_ptp_rst(qsfp3_rx_ptp_rst_int),
27132743
.qsfp3_rx_ptp_time(qsfp3_rx_ptp_time_int),
27142744

27152745
.qsfp3_rx_enable(qsfp3_rx_enable),

‎fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ module fpga_core #
151151
parameter AXIS_ETH_TX_TS_PIPELINE = 4,
152152
parameter AXIS_ETH_RX_PIPELINE = 4,
153153
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
154+
parameter ETH_RX_CLK_FROM_TX = 0,
154155

155156
// Statistics counter subsystem
156157
parameter STAT_ENABLE = 1,
@@ -300,6 +301,8 @@ module fpga_core #
300301
input wire qsfp0_rx_axis_tlast,
301302
input wire [80+1-1:0] qsfp0_rx_axis_tuser,
302303

304+
input wire qsfp0_rx_ptp_clk,
305+
input wire qsfp0_rx_ptp_rst,
303306
output wire [79:0] qsfp0_rx_ptp_time,
304307

305308
output wire qsfp0_rx_enable,
@@ -362,6 +365,8 @@ module fpga_core #
362365
input wire qsfp1_rx_axis_tlast,
363366
input wire [80+1-1:0] qsfp1_rx_axis_tuser,
364367

368+
input wire qsfp1_rx_ptp_clk,
369+
input wire qsfp1_rx_ptp_rst,
365370
output wire [79:0] qsfp1_rx_ptp_time,
366371

367372
output wire qsfp1_rx_enable,
@@ -424,6 +429,8 @@ module fpga_core #
424429
input wire qsfp2_rx_axis_tlast,
425430
input wire [80+1-1:0] qsfp2_rx_axis_tuser,
426431

432+
input wire qsfp2_rx_ptp_clk,
433+
input wire qsfp2_rx_ptp_rst,
427434
output wire [79:0] qsfp2_rx_ptp_time,
428435

429436
output wire qsfp2_rx_enable,
@@ -486,6 +493,8 @@ module fpga_core #
486493
input wire qsfp3_rx_axis_tlast,
487494
input wire [80+1-1:0] qsfp3_rx_axis_tuser,
488495

496+
input wire qsfp3_rx_ptp_clk,
497+
input wire qsfp3_rx_ptp_rst,
489498
output wire [79:0] qsfp3_rx_ptp_time,
490499

491500
output wire qsfp3_rx_enable,
@@ -1263,8 +1272,8 @@ mqnic_port_map_mac_axis_inst (
12631272
.mac_rx_clk({qsfp3_rx_clk, qsfp2_rx_clk, qsfp1_rx_clk, qsfp0_rx_clk}),
12641273
.mac_rx_rst({qsfp3_rx_rst, qsfp2_rx_rst, qsfp1_rx_rst, qsfp0_rx_rst}),
12651274

1266-
.mac_rx_ptp_clk(4'b0000),
1267-
.mac_rx_ptp_rst(4'b0000),
1275+
.mac_rx_ptp_clk({qsfp3_rx_ptp_clk, qsfp2_rx_ptp_clk, qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}),
1276+
.mac_rx_ptp_rst({qsfp3_rx_ptp_rst, qsfp2_rx_ptp_rst, qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}),
12681277
.mac_rx_ptp_ts_96({qsfp3_rx_ptp_time[47:0], qsfp2_rx_ptp_time[47:0], qsfp1_rx_ptp_time[47:0], qsfp0_rx_ptp_time[47:0]}),
12691278
.mac_rx_ptp_ts_step(),
12701279

@@ -1365,7 +1374,7 @@ mqnic_core_pcie_us #(
13651374
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
13661375
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
13671376
.PTP_SEPARATE_TX_CLOCK(0),
1368-
.PTP_SEPARATE_RX_CLOCK(0),
1377+
.PTP_SEPARATE_RX_CLOCK(ETH_RX_CLK_FROM_TX),
13691378
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
13701379
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
13711380
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

‎fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,6 +209,7 @@ export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4
209209
export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4
210210
export PARAM_AXIS_ETH_RX_PIPELINE := 4
211211
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4
212+
export PARAM_ETH_RX_CLK_FROM_TX := 0
212213

213214
# Statistics counter subsystem
214215
export PARAM_STAT_ENABLE := 1

‎fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -773,6 +773,7 @@ def test_fpga_core(request):
773773
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4
774774
parameters['AXIS_ETH_RX_PIPELINE'] = 4
775775
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4
776+
parameters['ETH_RX_CLK_FROM_TX'] = 0
776777

777778
# Statistics counter subsystem
778779
parameters['STAT_ENABLE'] = 1

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