4-bit Full Adder using Verilog HDL
This repository contains a Verilog implementation of a 4-bit full adder along with its testbench. The fulladd module takes two 4-bit binary inputs (a and b) and a carry-in bit (cin), producing a 4-bit sum (sum) and a carry-out bit (cout). The testbench (tb_fulladd) verifies the functionality of the fulladd module by applying various test cases and observing the outputs. The project provides a simple and efficient way to understand and simulate the working of a basic digital arithmetic circuit.
Schematic:
Results:
