diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml
index 4d23f7f0..28c710a9 100644
--- a/.github/workflows/c-cpp.yml
+++ b/.github/workflows/c-cpp.yml
@@ -15,15 +15,33 @@ jobs:
- uses: actions/checkout@v2
- name: Install arm-none-eabi
run: sudo apt install gcc-arm-none-eabi
+ - name: make Board-tester
+ run: |
+ cd Board-tester
+ make -f Makefile.GD32 clean
+ make -f Makefile.GD32
+ cd -
- name: make gd32_emac_artnet_dmx_multi
run: |
cd gd32_emac_artnet_dmx_multi
make -f Makefile.GD32 clean
make -f Makefile.GD32
cd -
+ - name: make gd32_emac_artnet_pixel_multi
+ run: |
+ cd gd32_emac_artnet_pixel_multi
+ make -f Makefile.GD32 clean
+ make -f Makefile.GD32
+ cd -
- name: make gd32_emac_e131_dmx_multi
run: |
cd gd32_emac_e131_dmx_multi
make -f Makefile.GD32 clean
make -f Makefile.GD32
cd -
+ - name: make gd32_emac_e131_pixel_multi
+ run: |
+ cd gd32_emac_e131_pixel_multi
+ make -f Makefile.GD32 clean
+ make -f Makefile.GD32
+ cd -
diff --git a/.gitignore b/.gitignore
index e36e1365..cf185ac9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -55,4 +55,12 @@
*.bin
udp_send
-do-tftp.sh
\ No newline at end of file
+
+gd32f1*.*
+lib-gd32/gd32f10x/*
+gd32f2*.*
+lib-gd32/gd32f20x/*
+gd32f3*.*
+lib-gd32/gd32f30x/*
+gd32fh*.*
+lib-gd32/gd32h7xx/*
diff --git a/CMSIS/.cproject b/CMSIS/.cproject
new file mode 100644
index 00000000..5f16a37f
--- /dev/null
+++ b/CMSIS/.cproject
@@ -0,0 +1,63 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/lib-uuid/.project b/CMSIS/.project
similarity index 93%
rename from lib-uuid/.project
rename to CMSIS/.project
index dd0edd7a..e2e0ca79 100644
--- a/lib-uuid/.project
+++ b/CMSIS/.project
@@ -1,26 +1,26 @@
-
-
- lib-uuid
-
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.genmakebuilder
- clean,full,incremental,
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
- full,incremental,
-
-
-
-
-
- org.eclipse.cdt.core.cnature
- org.eclipse.cdt.managedbuilder.core.managedBuildNature
- org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
-
-
+
+
+ CMSIS
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/lib-c/.settings/language.settings.xml b/CMSIS/.settings/language.settings.xml
similarity index 88%
rename from lib-c/.settings/language.settings.xml
rename to CMSIS/.settings/language.settings.xml
index 4367d277..ed16b203 100644
--- a/lib-c/.settings/language.settings.xml
+++ b/CMSIS/.settings/language.settings.xml
@@ -1,6 +1,6 @@
-
+
diff --git a/lib-c++/.settings/org.eclipse.core.resources.prefs b/CMSIS/.settings/org.eclipse.core.resources.prefs
similarity index 100%
rename from lib-c++/.settings/org.eclipse.core.resources.prefs
rename to CMSIS/.settings/org.eclipse.core.resources.prefs
diff --git a/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS/Core/Include/cachel1_armv7.h
new file mode 100644
index 00000000..abebc95f
--- /dev/null
+++ b/CMSIS/Core/Include/cachel1_armv7.h
@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file cachel1_armv7.h
+ * @brief CMSIS Level 1 Cache API for Armv7-M and later
+ * @version V1.0.1
+ * @date 19. April 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */
diff --git a/CMSIS/Core/Include/cmsis_armcc.h b/CMSIS/Core/Include/cmsis_armcc.h
new file mode 100644
index 00000000..a955d471
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_armcc.h
@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.3.2
+ * @date 27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+ __ISB();
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 00000000..69114177
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1503 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.4.3
+ * @date 27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/CMSIS/Core/Include/cmsis_armclang_ltm.h b/CMSIS/Core/Include/cmsis_armclang_ltm.h
new file mode 100644
index 00000000..1e255d59
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1928 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.5.3
+ * @date 27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/CMSIS/Core/Include/cmsis_compiler.h b/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 00000000..adbf296f
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/CMSIS/Core/Include/cmsis_gcc.h b/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 00000000..67bda4ef
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2211 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.4.1
+ * @date 27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL __StackSeal
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+ uint32_t result;
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+ __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+ } else {
+ result = __SXTB16(__ROR(op1, rotate)) ;
+ }
+ return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+ uint32_t result;
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+ __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
+ } else {
+ result = __SXTAB16(op1, __ROR(op2, rotate));
+ }
+ return result;
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..65b824b0
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,1002 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.3.0
+ * @date 14. April 2021
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2021 IAR Systems
+// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#undef __WEAK /* undo the definition from DLib_Defaults.h */
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL STACKSEAL$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __arm_wsr("CONTROL", control);
+ __iar_builtin_ISB();
+}
+
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __arm_wsr("CONTROL_NS", control);
+ __iar_builtin_ISB();
+}
+
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ __iar_builtin_ISB();
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/CMSIS/Core/Include/cmsis_version.h b/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 00000000..8b4765f1
--- /dev/null
+++ b/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.5
+ * @date 02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/CMSIS/Core/Include/core_cm3.h b/CMSIS/Core/Include/core_cm3.h
new file mode 100644
index 00000000..74fb87e5
--- /dev/null
+++ b/CMSIS/Core/Include/core_cm3.h
@@ -0,0 +1,1943 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 04. June 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/Core/Include/core_cm4.h b/CMSIS/Core/Include/core_cm4.h
new file mode 100644
index 00000000..e21cd149
--- /dev/null
+++ b/CMSIS/Core/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 04. June 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/Core/Include/core_cm7.h b/CMSIS/Core/Include/core_cm7.h
new file mode 100644
index 00000000..010506e9
--- /dev/null
+++ b/CMSIS/Core/Include/core_cm7.h
@@ -0,0 +1,2366 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.1.6
+ * @date 04. June 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+ uint32_t RESERVED7[5U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */
+#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/Core/Include/mpu_armv7.h b/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 00000000..d9eedf81
--- /dev/null
+++ b/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.2
+ * @date 25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/CMSIS/Core/Include/tz_context.h b/CMSIS/Core/Include/tz_context.h
new file mode 100644
index 00000000..0d09749f
--- /dev/null
+++ b/CMSIS/Core/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/CMSIS/LICENSE.txt b/CMSIS/LICENSE.txt
new file mode 100644
index 00000000..8dada3ed
--- /dev/null
+++ b/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
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+ 6. Trademarks. This License does not grant permission to use the trade
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+ 7. Disclaimer of Warranty. Unless required by applicable law or
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+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
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+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
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+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
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+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/README.md b/README.md
index 36b86dcb..fa187211 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
![GitHub](https://img.shields.io/github/license/vanvught/GD32F407RE-DMX512-RDM)
-[![C++ Standard](https://img.shields.io/badge/C%2B%2B-11-blue.svg)](https://img.shields.io/badge/C%2B%2B-11%-blue.svg)
+[![C++ Standard](https://img.shields.io/badge/C%2B%2B-20-blue.svg)](https://img.shields.io/badge/C%2B%2B-11%-blue.svg)
![GitHub issues](https://img.shields.io/github/issues-raw/vanvught/GD32F407RE-DMX512-RDM)
![GitHub contributors](https://img.shields.io/github/contributors/vanvught/GD32F407RE-DMX512-RDM)
![GitHub Sponsors](https://img.shields.io/github/sponsors/vanvught)
@@ -20,11 +20,20 @@ The ready to use firmware is build to use with the bootloader TFTP server -> [ht
* Full Art-Net 4 implementation
* Default firmware is using USART2 en USART5
+### Art-Net 4 Pixel 8x 4 Universes
+* Full Art-Net 4 implementation
+* No FPS limitation, except for what there is with the pixel chip protocol
+
### sACN E1.31 DMX 1-4 ports
* Full sACN E1.31 implementation
* Default firmware is using USART2 en USART5
* RDMNet LLRP Device only
+### sACN E1.31 Pixel 8x 4 Universes
+* Full sACN E1.31 implementation
+* No FPS limitation, except for what there is with the pixel chip protocol
+* RDMNet LLRP Device only
+
## Remote Configuration Manager
[https://github.com/vanvught/Remote-Config-UI/releases](https://github.com/vanvught/Remote-Config-UI/releases)
\ No newline at end of file
diff --git a/firmware-template-gd32/Artnet.mk b/firmware-template-gd32/Artnet.mk
new file mode 100644
index 00000000..7c46203a
--- /dev/null
+++ b/firmware-template-gd32/Artnet.mk
@@ -0,0 +1,5 @@
+ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4)
+ ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN)
+ DEFINES+=-DE131_HAVE_DMXIN
+ endif
+endif
\ No newline at end of file
diff --git a/firmware-template-gd32/Board.mk b/firmware-template-gd32/Board.mk
new file mode 100644
index 00000000..bc44a934
--- /dev/null
+++ b/firmware-template-gd32/Board.mk
@@ -0,0 +1,108 @@
+$(info "Board.mk")
+
+ifndef BOARD
+ $(error BOARD is not set)
+endif
+
+ifndef DEFINES
+ DEFINES=
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F103RC)
+ MCU=GD32F103RC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+ DEFINES+=-DNO_EMAC
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F107RC)
+ MCU=GD32F107RC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F207RG)
+ MCU=GD32F207RG
+ DEFINES+=-DCONFIG_STORE_USE_SPI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F207VC_2)
+ MCU=GD32F207VC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+ BITBANGING595=1
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F207VC_4)
+ MCU=GD32F207VC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+ BITBANGING595=1
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F303RC)
+ MCU=GD32F303RC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+ DEFINES+=-DNO_EMAC
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F407RE)
+ MCU=GD32F407RE
+ DEFINES+=-DCONFIG_STORE_USE_SPI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F450VE)
+ MCU=GD32F450VE
+ DEFINES+=-DCONFIG_STORE_USE_RAM
+ BITBANGING595=1
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F450VI)
+ MCU=GD32F450VI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_16X4U_PIXEL)
+ MCU=GD32F450VI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F470VG)
+ MCU=GD32F470VG
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F207C_EVAL)
+ MCU=GD32F207VC
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32F470Z_EVAL)
+ MCU=GD32F470ZK
+ DEFINES+=-DCONFIG_STORE_USE_RAM
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_GD32H759I_EVAL)
+ MCU=GD32H759IM
+ DEFINES+=-DCONFIG_STORE_USE_ROM
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_BW_OPIDMX4)
+ BOARD_DMX=4
+ DEFINES+=-DCONFIG_STORE_USE_SPI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_DMX3)
+ BOARD_DMX=3
+ DEFINES+=-DCONFIG_STORE_USE_SPI
+endif
+
+ifeq ($(strip $(BOARD)),BOARD_DMX4)
+ DEFINES+=-DCONFIG_STORE_USE_SPI
+ BOARD_DMX=4
+endif
+
+ifdef BOARD_DMX
+ ifeq ($(MCU),GD32F207RG)
+ else ifeq ($(MCU),GD32F407RE)
+ else
+ $(error MCU is not support for BOARD_DMX)
+ endif
+endif
+
+ifndef MCU
+ $(error BOARD is not configured)
+endif
\ No newline at end of file
diff --git a/firmware-template-gd32/Includes.mk b/firmware-template-gd32/Includes.mk
index ce9b5765..71aadc06 100644
--- a/firmware-template-gd32/Includes.mk
+++ b/firmware-template-gd32/Includes.mk
@@ -1,13 +1,14 @@
-INCLUDES:=-I./include -I../include -I../lib-hal/include -I../lib-debug/include
-INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES))
+$(info "Includes.mk")
+
+INCLUDES:=-I./include -I../include
INCLUDES+=-I../firmware-template-gd32/include
INCLUDES+=-I../firmware-template-gd32/template
+INCLUDES+=-I../CMSIS/Core/Include
INCLUDES+=-I../lib-gd32/${FAMILY}/${FAMILY_UC}_standard_peripheral/Include
-INCLUDES+=-I../lib-gd32/${FAMILY}/CMSIS
INCLUDES+=-I../lib-gd32/${FAMILY}/CMSIS/GD/${FAMILY_UC}/Include
INCLUDES+=-I../lib-gd32/include
+INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES))
-USB_HOST=
ifeq ($(findstring ENABLE_USB_HOST,$(DEFINES)), ENABLE_USB_HOST)
USB_HOST=1
endif
@@ -15,7 +16,6 @@ ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST)
USB_HOST=1
endif
-USB_HOST_MSC=
ifeq ($(findstring ENABLE_USB_HOST,$(DEFINES)), ENABLE_USB_HOST)
USB_HOST_MSC=1
endif
@@ -52,6 +52,18 @@ ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx)
endif
endif
+ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx)
+ ifdef USB_HOST
+ INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/driver/Include
+ INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/host/core/Include
+ INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/ustd/common
+ ifdef USB_HOST_MSC
+ INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/host/class/msc/Include
+ INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/ustd/class/msc
+ endif
+ endif
+endif
+
ifdef USB_HOST_MSC
- EXTRA_INCLUDES+=../lib-hal/ff12c
+ INCLUDES+=-I../lib-hal/ff14b/source
endif
\ No newline at end of file
diff --git a/firmware-template-gd32/Mcu.mk b/firmware-template-gd32/Mcu.mk
index 63127eec..46058e8f 100644
--- a/firmware-template-gd32/Mcu.mk
+++ b/firmware-template-gd32/Mcu.mk
@@ -1,7 +1,12 @@
+$(info "Mcu.mk")
+
ifndef MCU
$(error MCU is not set)
endif
+$(info $$MCU [${MCU}])
+
+# Extract upper and lower case versions of MCU name
MCU_UC=$(shell echo $(MCU) | rev | cut -c3- | rev )
MCU_LC=$(shell echo $(MCU_UC) | tr A-Z a-z )
@@ -9,6 +14,8 @@ $(info $$MCU [${MCU}])
$(info $$MCU_LC [${MCU_LC}])
$(info $$MCU_UC [${MCU_UC}])
+# Set LINKER, FAMILY, and LINE based on MCU
+
ifeq ($(strip $(MCU)),GD32F103RC)
LINKER=$(FIRMWARE_DIR)gd32f103rc_flash.ld
FAMILY=gd32f10x
@@ -57,16 +64,76 @@ ifeq ($(strip $(MCU)),GD32F450VI)
LINE=gd32f450
endif
+ifeq ($(strip $(MCU)),GD32F470VG)
+ LINKER=$(FIRMWARE_DIR)gd32f470vg_flash.ld
+ FAMILY=gd32f4xx
+ LINE=gd32f470
+endif
+
+ifeq ($(strip $(MCU)),GD32F470ZK)
+ LINKER=$(FIRMWARE_DIR)gd32f470zk_flash.ld
+ FAMILY=gd32f4xx
+ LINE=gd32f470
+endif
+
+ifeq ($(strip $(MCU)),GD32H759IM)
+ LINKER=$(FIRMWARE_DIR)gd32h7xx_xM_flash.ld
+ FAMILY=gd32h7xx
+ LINE=gd32h759
+endif
+
ifndef LINKER
$(error MCU is not configured)
endif
+# Common ARM options for Cortex-M3
+ARMOPS_CM3=-mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+
+# Common ARM options for Cortex-M4
+ARMOPS_CM4=-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+
+# Common ARM options for Cortex-M7
+ARMOPS_CM7=-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fsingle-precision-constant
+
+# CMSIS options for FPU present
+CMSISOPS_FPU_PRESENT = -D__FPU_PRESENT=1 -DARM_MATH_CM4
+
+# Common CMSIS options
+CMSISOPS=-D__Vendor_SysTickConfig=0
+
+# Set ARM options and CMSIS options based on FAMILY
+
+ifeq ($(FAMILY),gd32f10x)
+ ARMOPS=$(ARMOPS_CM3)
+endif
+
+ifeq ($(FAMILY),gd32f20x)
+ ARMOPS=$(ARMOPS_CM3)
+endif
+
+ifeq ($(FAMILY),gd32f30x)
+ ARMOPS=$(ARMOPS_CM4)
+ CMSISOPS+=$(CMSISOPS_FPU_PRESENT)
+endif
+
+ifeq ($(FAMILY),gd32f4xx)
+ ARMOPS=$(ARMOPS_CM4)
+ CMSISOPS+=$(CMSISOPS_FPU_PRESENT)
+endif
+
+ifeq ($(FAMILY),gd32h7xx)
+ ARMOPS=$(ARMOPS_CM7)
+ CMSISOPS+=-D__FPU_PRESENT=1 -DARM_MATH_CM7
+endif
+
FAMILY_UC=$(shell echo $(FAMILY) | tr a-w A-W)
+FAMILY_UCA=$(shell echo $(FAMILY) | tr a-z A-Z)
+LINE_UC=$(shell echo $(LINE) | tr a-z A-Z)
+
$(info $$FAMILY [${FAMILY}])
$(info $$FAMILY_UC [${FAMILY_UC}])
-
-LINE_UC=$(shell echo $(LINE) | tr a-z A-Z)
+$(info $$FAMILY_UCA [${FAMILY_UCA}])
$(info $$LINE [${LINE}])
$(info $$LINE_UC [${LINE_UC}])
\ No newline at end of file
diff --git a/firmware-template-gd32/Rules.mk b/firmware-template-gd32/Rules.mk
index 235312be..42cd4fbd 100644
--- a/firmware-template-gd32/Rules.mk
+++ b/firmware-template-gd32/Rules.mk
@@ -11,33 +11,26 @@ AR = $(PREFIX)ar
BOARD?=BOARD_GD32F407RE
ENET_PHY?=DP83848
-# Output
TARGET=$(FAMILY).bin
LIST=$(FAMILY).list
MAP=$(FAMILY).map
SIZE=$(FAMILY).size
BUILD=build_gd32/
-# Input
-SOURCE=./
FIRMWARE_DIR=./../firmware-template-gd32/
DEFINES:=$(addprefix -D,$(DEFINES))
-ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4)
- ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN)
- DEFINES+=-DE131_HAVE_DMXIN
- endif
-endif
-
MCU=GD32F407RE
+include ../firmware-template-gd32/Board.mk
include ../firmware-template-gd32/Mcu.mk
include ../firmware-template/libs.mk
-
-LIBS+=c++ c gd32
-
include ../firmware-template-gd32/Includes.mk
+include ../firmware-template-gd32/Artnet.mk
+include ../firmware-template-gd32/Validate.mk
+
+LIBS+=gd32 clib
# The variable for the libraries include directory
LIBINCDIRS:=$(addprefix -I../lib-,$(LIBS))
@@ -47,37 +40,32 @@ LIBINCDIRS+=$(addsuffix /include, $(LIBINCDIRS))
LIBGD32=$(addprefix -L../lib-,$(LIBS))
LIBGD32:=$(addsuffix /lib_gd32, $(LIBGD32))
-# The variable for the ld -l flag
+# The variable for the ld -l flag
LDLIBS:=$(addprefix -l,$(LIBS))
-# The variables for the dependency check
+# The variables for the dependency check
LIBDEP=$(addprefix ../lib-,$(LIBS))
-$(info $$BOARD [${BOARD}])
-$(info $$ENET_PHY [${ENET_PHY}])
-$(info $$DEFINES [${DEFINES}])
-$(info $$LIBS [${LIBS}])
-$(info $$LIBDEP [${LIBDEP}])
-
-COPS=-DBARE_METAL -DGD32 -DGD32F407 -D$(BOARD) -DPHY_TYPE=$(ENET_PHY)
-COPS+=$(DEFINES) $(MAKE_FLAGS) $(INCLUDES) $(LIBINCDIRS)
-COPS+=-Os -mcpu=cortex-m4 -mthumb -g -mfloat-abi=hard -fsingle-precision-constant -mfpu=fpv4-sp-d16 -DARM_MATH_CM4 -D__FPU_PRESENT=1
-COPS+=-nostartfiles -ffreestanding -nostdlib
+COPS=-DGD32 -D$(FAMILY_UCA) -D$(LINE_UC) -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY)
+COPS+=$(strip $(DEFINES) $(MAKE_FLAGS) $(INCLUDES) $(LIBINCDIRS))
+COPS+=$(strip $(ARMOPS) $(CMSISOPS))
+COPS+=-Os -nostartfiles -ffreestanding -nostdlib
COPS+=-fstack-usage
COPS+=-ffunction-sections -fdata-sections
-COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion
-COPS+=-Wduplicated-cond -Wlogical-op
+COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -Wduplicated-cond -Wlogical-op
-CPPOPS=-std=c++11
+CPPOPS=-std=c++20
CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables
CPPOPS+=-Wuseless-cast -Wold-style-cast
CPPOPS+=-fno-threadsafe-statics
-LDOPS=--gc-sections --print-gc-sections
+LDOPS=--gc-sections --print-gc-sections --print-memory-usage
PLATFORM_LIBGCC+= -L $(shell dirname `$(CC) $(COPS) -print-libgcc-file-name`)
+PLATFORM_LIBC+= -L $(shell dirname `$(CC) $(COPS) --print-file-name=libc.a`)
$(info $$PLATFORM_LIBGCC [${PLATFORM_LIBGCC}])
+$(info $$PLATFORM_LIBC [${PLATFORM_LIBC}])
C_OBJECTS=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.c,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.c)))
C_OBJECTS+=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.cpp,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.cpp)))
@@ -88,18 +76,18 @@ BUILD_DIRS:=$(addprefix $(BUILD),$(SRCDIR))
OBJECTS:=$(ASM_OBJECTS) $(C_OBJECTS)
define compile-objects
-$(BUILD)$1/%.o: $(SOURCE)$1/%.cpp
- $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@
+$(BUILD)$1/%.o: $1/%.cpp
+ $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@
-$(BUILD)$1/%.o: $(SOURCE)$1/%.c
+$(BUILD)$1/%.o: $1/%.c
$(CC) $(COPS) -c $$< -o $$@
-
-$(BUILD)$1/%.o: $(SOURCE)$1/%.S
+
+$(BUILD)$1/%.o: $1/%.S
$(CC) $(COPS) -D__ASSEMBLY__ -c $$< -o $$@
endef
all : builddirs prerequisites $(TARGET)
-
+
.PHONY: clean builddirs
builddirs:
@@ -112,7 +100,6 @@ clean: $(LIBDEP)
rm -f $(TARGET)
rm -f $(MAP)
rm -f $(LIST)
- rm -f $(SIZE)
#
# Libraries
@@ -123,7 +110,7 @@ clean: $(LIBDEP)
lisdep: $(LIBDEP)
$(LIBDEP):
- $(MAKE) -f Makefile.GD32 $(MAKECMDGOALS) 'FAMILY=${FAMILY}' 'MCU=${MCU}' 'BOARD=${BOARD}' 'ENET_PHY=${ENET_PHY}' 'MAKE_FLAGS=$(DEFINES)' -C $@
+ $(MAKE) -f Makefile.GD32 $(MAKECMDGOALS) 'FAMILY=${FAMILY}' 'BOARD=${BOARD}' 'ENET_PHY=${ENET_PHY}' 'MAKE_FLAGS=$(DEFINES)' -C $@
#
# Build bin
@@ -132,20 +119,18 @@ $(LIBDEP):
$(BUILD_DIRS) :
mkdir -p $(BUILD_DIRS)
-$(BUILD)startup_$(MCU_LC).o : $(FIRMWARE_DIR)/startup_$(MCU_LC).S
- $(AS) $(COPS) -D__ASSEMBLY__ -c $(FIRMWARE_DIR)/startup_$(MCU_LC).S -o $(BUILD)startup_$(MCU_LC).o
-
-$(BUILD)main.elf: Makefile.GD32 $(LINKER) $(BUILD)startup_$(MCU_LC).o $(OBJECTS) $(LIBDEP)
- $(LD) $(BUILD)startup_$(MCU_LC).o $(OBJECTS) -Map $(MAP) -T $(LINKER) $(LDOPS) -o $(BUILD)main.elf $(LIBGD32) $(LDLIBS) $(PLATFORM_LIBGCC) -lgcc
+$(BUILD)startup_$(LINE).o : $(FIRMWARE_DIR)/startup_$(LINE).S
+ $(AS) $(COPS) -D__ASSEMBLY__ -c $(FIRMWARE_DIR)/startup_$(LINE).S -o $(BUILD)startup_$(LINE).o
+
+$(BUILD)hardfault_handler.o : $(FIRMWARE_DIR)/hardfault_handler.c
+ $(CC) $(COPS) -c $(FIRMWARE_DIR)/hardfault_handler.c -o $(BUILD)hardfault_handler.o
+
+$(BUILD)main.elf: Makefile.GD32 $(LINKER) $(BUILD)startup_$(LINE).o $(BUILD)hardfault_handler.o $(OBJECTS) $(LIBDEP)
+ $(LD) $(BUILD)startup_$(LINE).o $(BUILD)hardfault_handler.o $(OBJECTS) -Map $(MAP) -T $(LINKER) $(LDOPS) -o $(BUILD)main.elf $(LIBGD32) $(LDLIBS) $(PLATFORM_LIBGCC) -lgcc
$(PREFIX)objdump -D $(BUILD)main.elf | $(PREFIX)c++filt > $(LIST)
- $(PREFIX)size -A -x $(BUILD)main.elf > $(FAMILY).size
- $(MAKE) -f Makefile.GD32 calculate_unused_ram SIZE_FILE=$(FAMILY).size LINKER_SCRIPT=$(LINKER)
+ $(PREFIX)size -A -x $(BUILD)main.elf
-$(TARGET) : $(BUILD)main.elf
- $(PREFIX)objcopy $(BUILD)main.elf --remove-section=.tcmsram* --remove-section=.sram1* --remove-section=.sram2* --remove-section=.bkpsram* -O binary $(TARGET)
-
-$(foreach bdir,$(SRCDIR),$(eval $(call compile-objects,$(bdir))))
+$(TARGET) : $(BUILD)main.elf
+ $(PREFIX)objcopy $(BUILD)main.elf -O binary $(TARGET) --remove-section=.tcmsram* --remove-section=.sram1* --remove-section=.sram2* --remove-section=.ramadd* --remove-section=.bkpsram*
-.PHONY: calculate_unused_ram
-calculate_unused_ram: $(FAMILY).size $(LINKER)
- @$(FIRMWARE_DIR)/calculate_unused_ram.sh $(FAMILY).size $(LINKER)
+$(foreach bdir,$(SRCDIR),$(eval $(call compile-objects,$(bdir))))
diff --git a/firmware-template-gd32/Validate.mk b/firmware-template-gd32/Validate.mk
new file mode 100644
index 00000000..9531da32
--- /dev/null
+++ b/firmware-template-gd32/Validate.mk
@@ -0,0 +1,33 @@
+$(info "Validate.mk")
+$(info $$MAKE_FLAGS [${MAKE_FLAGS}])
+$(info $$DEFINES [${DEFINES}])
+
+FLAGS:=$(MAKE_FLAGS)
+ifeq ($(FLAGS),)
+ FLAGS:=$(DEFINES)
+endif
+
+ifneq (,$(findstring OUTPUT_DMX_SEND,$(FLAGS))$(findstring CONFIG_RDM,$(FLAGS))$(findstring RDM_CONTROLLER,$(FLAGS))$(findstring LTC,$(FLAGS)))
+ TIMER6_HAVE_IRQ_HANDLER=1
+ ifneq (,$(findstring CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER,$(MAKE_FLAGS)))
+ $(error CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER is set)
+ endif
+endif
+
+ifndef TIMER6_HAVE_IRQ_HANDLER
+ DEFINES+=-DCONFIG_TIMER6_HAVE_NO_IRQ_HANDLER
+endif
+
+ifneq ($(findstring USE_FREE_RTOS,$(FLAGS)),USE_FREE_RTOS)
+ DEFINES+=-DCONFIG_HAL_USE_SYSTICK
+else
+ DEFINES+=-DCONFIG_HAL_USE_SYSTICK # Temporarily need to fix TIMER10
+endif
+
+ifeq ($(findstring ENABLE_TFTP_SERVER,$(FLAGS)),ENABLE_TFTP_SERVER)
+ ifneq ($(findstring CONFIG_HAL_USE_SYSTICK,$(FLAGS)),CONFIG_HAL_USE_SYSTICK)
+ DEFINES+=-DCONFIG_HAL_USE_SYSTICK
+ endif
+endif
+
+$(info $$DEFINES [${DEFINES}])
diff --git a/firmware-template-gd32/calculate_unused_ram.sh b/firmware-template-gd32/calculate_unused_ram.sh
deleted file mode 100755
index 21b75d96..00000000
--- a/firmware-template-gd32/calculate_unused_ram.sh
+++ /dev/null
@@ -1,45 +0,0 @@
-#!/bin/bash
-
-if [ $# -lt 2 ]; then
- echo "Usage: $0 "
- exit 1
-fi
-
-size_file="$1"
-linker_script="$2"
-
-used_stack=$(grep ".stack" "$size_file" | awk '{print $2}')
-used_tcmsram=$(grep ".tcmsram" "$size_file" | awk '{print $2}')
-used_heap=$(grep ".heap" "$size_file" | awk '{print $2}')
-
-total_tcmsram=$(grep "TCMSRAM (rw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}')
-unused_tcmsram=$(( $(echo $total_tcmsram) - $(echo $used_stack) - $(echo $used_tcmsram) - $(echo $used_heap) ))
-
-used_data=$(grep '.data' "$size_file" | tail -n 1 | awk '{print $2}')
-used_bss=$(grep ".bss" "$size_file" | awk '{print $2}')
-
-total_ram=$(grep "RAM (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}')
-unused_ram=$(( $(echo $total_ram) - $(echo $used_data) - $(echo $used_bss) ))
-
-used_ram1=$(grep ".sram1" "$size_file" | awk '{print $2}')
-
-total_ram1=$(grep "RAM1 (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}')
-unused_ram1=$(( $(echo $total_ram1) - $(echo $used_ram1)))
-
-used_ram2=$(grep ".sram2" "$size_file" | awk '{print $2}')
-
-total_ram2=$(grep "RAM2 (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}')
-unused_ram2=$(( $(echo $total_ram2) - $(echo $used_ram2)))
-
-used_ramadd=$(grep ".ramadd" "$size_file" | awk '{print $2}')
-
-total_ramadd=$(grep "RAMADD (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}')
-unused_ramadd=$(( $(echo $total_ramadd) - $(echo $used_ramadd)))
-
-cat $1
-echo "TCMSRAM $total_tcmsram bytes, Unused TCMSRAM: $unused_tcmsram bytes"
-echo "SRAM0 $total_ram bytes, Unused: $unused_ram bytes"
-echo "SRAM1 $total_ram1 bytes, Unused: $unused_ram1 bytes"
-echo "SRAM2 $total_ram2 bytes, Unused: $unused_ram2 bytes"
-echo "RAMADD $total_ramadd bytes, Unused: $unused_ramadd bytes"
-echo
\ No newline at end of file
diff --git a/firmware-template-gd32/gd32f407re_flash.ld b/firmware-template-gd32/gd32f407re_flash.ld
index 73d21eda..1e2cb3d0 100644
--- a/firmware-template-gd32/gd32f407re_flash.ld
+++ b/firmware-template-gd32/gd32f407re_flash.ld
@@ -39,31 +39,37 @@ SECTIONS
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
-
- . = ALIGN(8);
-
+ } >FLASH
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
-
+ } >FLASH
+
+ .init_array :
+ {
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
-
+ } >FLASH
+
+ .fini_array :
+ {
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
-
- } >FLASH
-
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata)
- *(.rodata*)
- . = ALIGN(4);
} >FLASH
.stack :
@@ -81,11 +87,10 @@ SECTIONS
*(.tcmsram)
*(.tcmsram*)
. = ALIGN(4);
- _snetwork = .;
- *(.network*)
- . = ALIGN(4);
- _enetwork = .;
+ _snetwork = .;
+ *(.network*)
. = ALIGN(4);
+ _enetwork = .;
} >TCMSRAM
.heap :
@@ -155,9 +160,9 @@ SECTIONS
. = ALIGN(4);
*(.ramadd)
*(.ramadd*)
- . = ALIGN(4);
+ . = ALIGN(4);
_eramadd = .;
- } >RAMADD AT>RAMADD
+ } >RAMADD
.bkpsram :
{
@@ -165,7 +170,7 @@ SECTIONS
*(.bkpsram)
*(.bkpsram*)
*(.configstore*)
- } >BKPSRAM AT>BKPSRAM
+ } >BKPSRAM
/DISCARD/ :
{
@@ -175,5 +180,4 @@ SECTIONS
}
}
- /* input sections */
-GROUP(libgcc.a libc.a)
\ No newline at end of file
+GROUP(libgcc.a)
diff --git a/firmware-template-gd32/hardfault_handler.c b/firmware-template-gd32/hardfault_handler.c
new file mode 100644
index 00000000..039d1f9d
--- /dev/null
+++ b/firmware-template-gd32/hardfault_handler.c
@@ -0,0 +1,77 @@
+/*
+ * hardfault_handler.c
+ */
+/**
+ * Using Cortex-M3/M4/M7 Fault Exceptions
+ * MDK Tutorial
+ * AN209, Summer 2017, V 5.0
+ */
+
+#include
+
+#include "gd32.h"
+
+void HardFault_Handler() {
+ __asm volatile(
+ "TST LR, #4\n"
+ "ITE EQ\n"
+ "MRSEQ R0, MSP\n"
+ "MRSNE R0, PSP\n"
+ "MOV R1, LR\n"
+ "B hardfault_handler\n"
+ );
+}
+
+void hardfault_handler(unsigned long *hardfault_args, unsigned int lr_value) {
+ unsigned long stacked_r0;
+ unsigned long stacked_r1;
+ unsigned long stacked_r2;
+ unsigned long stacked_r3;
+ unsigned long stacked_r12;
+ unsigned long stacked_lr;
+ unsigned long stacked_pc;
+ unsigned long stacked_psr;
+ unsigned long cfsr;
+ unsigned long bus_fault_address;
+ unsigned long memmanage_fault_address;
+
+ bus_fault_address = SCB->BFAR;
+ memmanage_fault_address = SCB->MMFAR;
+ cfsr = SCB->CFSR;
+
+ stacked_r0 = ((unsigned long) hardfault_args[0]);
+ stacked_r1 = ((unsigned long) hardfault_args[1]);
+ stacked_r2 = ((unsigned long) hardfault_args[2]);
+ stacked_r3 = ((unsigned long) hardfault_args[3]);
+ stacked_r12 = ((unsigned long) hardfault_args[4]);
+ stacked_lr = ((unsigned long) hardfault_args[5]);
+ stacked_pc = ((unsigned long) hardfault_args[6]);
+ stacked_psr = ((unsigned long) hardfault_args[7]);
+
+ printf("[HardFault]\n");
+ printf("- Stack frame:\n");
+ printf(" R0 = %x\n", (unsigned int) stacked_r0);
+ printf(" R1 = %x\n", (unsigned int) stacked_r1);
+ printf(" R2 = %x\n", (unsigned int) stacked_r2);
+ printf(" R3 = %x\n", (unsigned int) stacked_r3);
+ printf(" R12 = %x\n", (unsigned int) stacked_r12);
+ printf(" LR = %x\n", (unsigned int) stacked_lr);
+ printf(" PC = %x\n", (unsigned int) stacked_pc);
+ printf(" PSR = %x\n", (unsigned int) stacked_psr);
+ printf("- FSR/FAR:\n");
+ printf(" CFSR = %x\n", (unsigned int) cfsr);
+ printf(" HFSR = %x\n", (unsigned int) SCB->HFSR);
+ printf(" DFSR = %x\n", (unsigned int) SCB->DFSR);
+ printf(" AFSR = %x\n", (unsigned int) SCB->AFSR);
+ if (cfsr & 0x0080) {
+ printf(" MMFAR = %x\n", (unsigned int) memmanage_fault_address);
+ }
+ if (cfsr & 0x8000) {
+ printf(" BFAR = %x\n", (unsigned int) bus_fault_address);
+ }
+ printf("- Misc\n");
+ printf(" LR/EXC_RETURN= %x\n", lr_value);
+
+ while (1)
+ ;
+}
diff --git a/firmware-template-gd32/include/software_version.h b/firmware-template-gd32/include/software_version.h
index 46a34e9d..58b56824 100644
--- a/firmware-template-gd32/include/software_version.h
+++ b/firmware-template-gd32/include/software_version.h
@@ -2,7 +2,7 @@
* @file software_version.h
*
*/
-/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org
+/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,6 +26,6 @@
#ifndef SOFTWARE_VERSION_H_
#define SOFTWARE_VERSION_H_
-constexpr char SOFTWARE_VERSION[] = "2.0";
+constexpr char SOFTWARE_VERSION[] = "2.1";
#endif /* SOFTWARE_VERSION_H_ */
diff --git a/firmware-template-gd32/lib/Rules.mk b/firmware-template-gd32/lib/Rules.mk
index 5eae9ace..e15a3666 100644
--- a/firmware-template-gd32/lib/Rules.mk
+++ b/firmware-template-gd32/lib/Rules.mk
@@ -9,50 +9,40 @@ AS = $(CC)
LD = $(PREFIX)ld
AR = $(PREFIX)ar
-FAMILY?=gd32f4xx
-MCU?=GD32F407RE
BOARD?=BOARD_GD32F407RE
ENET_PHY?=DP83848
-FAMILY:=$(shell echo $(FAMILY) | tr A-Z a-z)
-FAMILY_UC=$(shell echo $(FAMILY) | tr a-w A-W)
-
-$(info $$FAMILY [${FAMILY}])
-$(info $$FAMILY_UC [${FAMILY_UC}])
$(info $$BOARD [${BOARD}])
$(info $$ENET_PHY [${ENET_PHY}])
SRCDIR=src src/gd32 $(EXTRA_SRCDIR)
-include ../firmware-template-gd32/Includes.mk
-
DEFINES:=$(addprefix -D,$(DEFINES))
DEFINES+=-D_TIME_STAMP_YEAR_=$(shell date +"%Y") -D_TIME_STAMP_MONTH_=$(shell date +"%-m") -D_TIME_STAMP_DAY_=$(shell date +"%-d")
-ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4)
- ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN)
- DEFINES+=-DE131_HAVE_DMXIN
- endif
-endif
-
-COPS=-DBARE_METAL -DGD32 -DGD32F407 -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY)
-COPS+=$(DEFINES) $(MAKE_FLAGS) $(INCLUDES)
-COPS+=-Os -mcpu=cortex-m4 -mthumb -g -mfloat-abi=hard -fsingle-precision-constant -mfpu=fpv4-sp-d16
-COPS+=-DARM_MATH_CM4 -D__FPU_PRESENT=1
-COPS+=-nostartfiles -ffreestanding -nostdlib
-COPS+=-fstack-usage -Wstack-usage=10240
+MCU=GD32F407RE
+
+include ../firmware-template-gd32/Board.mk
+include ../firmware-template-gd32/Mcu.mk
+include ../firmware-template-gd32/Includes.mk
+include ../firmware-template-gd32/Artnet.mk
+include ../firmware-template-gd32/Validate.mk
+
+INCLUDES+=-I../lib-configstore/include -I../lib-device/include -I../lib-display/include -I../lib-flash/include -I../lib-flashcode/include -I../lib-hal/include -I../lib-lightset/include -I../lib-network/include
+
+COPS=-DGD32 -D$(FAMILY_UCA) -D$(LINE_UC) -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY)
+COPS+=$(strip $(DEFINES)) $(MAKE_FLAGS) $(INCLUDES)
+COPS+=$(strip $(ARMOPS) $(CMSISOPS))
+COPS+=-Os -nostartfiles -ffreestanding -nostdlib
+COPS+=-fstack-usage
COPS+=-ffunction-sections -fdata-sections
-COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion
-COPS+=-Wduplicated-cond -Wlogical-op
+COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -Wduplicated-cond -Wlogical-op
-CPPOPS=-std=c++11
+CPPOPS=-std=c++20
CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables
CPPOPS+=-Wuseless-cast -Wold-style-cast
CPPOPS+=-fno-threadsafe-statics
-CURR_DIR:=$(notdir $(patsubst %/,%,$(CURDIR)))
-LIB_NAME:=$(patsubst lib-%,%,$(CURR_DIR))
-
BUILD=build_gd32/
BUILD_DIRS:=$(addprefix build_gd32/,$(SRCDIR))
$(info $$BUILD_DIRS [${BUILD_DIRS}])
@@ -61,19 +51,28 @@ C_OBJECTS=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.c,$(BUILD)$(sdir)/%.o,$(
CPP_OBJECTS=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.cpp,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.cpp)))
ASM_OBJECTS=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.S,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.S)))
-OBJECTS:=$(ASM_OBJECTS) $(C_OBJECTS) $(CPP_OBJECTS)
+EXTRA_C_OBJECTS=$(patsubst %.c,$(BUILD)%.o,$(EXTRA_C_SOURCE_FILES))
+EXTRA_C_DIRECTORIES=$(shell dirname $(EXTRA_C_SOURCE_FILES))
+EXTRA_BUILD_DIRS:=$(addsuffix $(EXTRA_C_DIRECTORIES), $(BUILD))
-TARGET=lib_gd32/lib$(LIB_NAME).a
-$(info $$TARGET [${TARGET}])
+OBJECTS:=$(strip $(ASM_OBJECTS) $(C_OBJECTS) $(CPP_OBJECTS) $(EXTRA_C_OBJECTS))
+
+CURR_DIR:=$(notdir $(patsubst %/,%,$(CURDIR)))
+LIB_NAME:=$(patsubst lib-%,%,$(CURR_DIR))
+TARGET=lib_gd32/lib$(LIB_NAME).a
-LIST = lib.list
+$(info $$DEFINES [${DEFINES}])
+$(info $$MAKE_FLAGS [${MAKE_FLAGS}])
+$(info $$OBJECTS [${OBJECTS}])
+$(info $$TARGET [${TARGET}])
define compile-objects
+$(info $1)
$(BUILD)$1/%.o: $1/%.c
$(CC) $(COPS) -c $$< -o $$@
$(BUILD)$1/%.o: $1/%.cpp
- $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@
+ $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@
$(BUILD)$1/%.o: $1/%.S
$(CC) $(COPS) -D__ASSEMBLY__ -c $$< -o $$@
@@ -85,18 +84,22 @@ all : builddirs $(TARGET)
builddirs:
mkdir -p $(BUILD_DIRS)
+ mkdir -p $(EXTRA_BUILD_DIRS)
mkdir -p lib_gd32
clean:
rm -rf build_gd32
rm -rf lib_gd32
+$(BUILD)%.o: %.c
+ $(CC) $(COPS) -c $< -o $@
+
$(BUILD_DIRS) :
mkdir -p $(BUILD_DIRS)
mkdir -p lib_gd32
$(TARGET): Makefile.GD32 $(OBJECTS)
$(AR) -r $(TARGET) $(OBJECTS)
- $(PREFIX)objdump -d $(TARGET) | $(PREFIX)c++filt > lib_gd32/$(LIST)
+ $(PREFIX)objdump -d $(TARGET) | $(PREFIX)c++filt > lib_gd32/lib.list
$(foreach bdir,$(SRCDIR),$(eval $(call compile-objects,$(bdir))))
\ No newline at end of file
diff --git a/firmware-template-gd32/startup_gd32f407.S b/firmware-template-gd32/startup_gd32f407.S
index bb4881dc..d2d4c75c 100644
--- a/firmware-template-gd32/startup_gd32f407.S
+++ b/firmware-template-gd32/startup_gd32f407.S
@@ -1,62 +1,96 @@
+/**
+ * @file startup_gd32f407.S
+ *
+ */
+/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
-.global Default_Handler
+.global Default_Handler
-.word _sidata
-.word _sdata
-.word _edata
-.word _sbss
-.word _ebss
+/* Necessary symbols defined in linker script to initialize data */
+.word _sdata
+.word _sidata
+.word _edata
+.word _sbss
+.word _ebss
-.section .text.Reset_Handler
+.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
- movs r1, #0
- b DataInit
-
+/* Copy .data section from FLASH to RAM */
CopyData:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-DataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyData
- ldr r2, =_sbss
- b Zerobss
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-Zerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ ldr r1, =_sdata /* Load the start address of .data section (RAM) into r1 */
+ ldr r2, =_sidata /* Load the start address of .data section (FLASH) into r2 */
+ ldr r3, =_edata /* Load the end address of .data section (RAM) into r3 */
+ subs r3, r3, r1 /* Calculate the size of .data section by subtracting start from end */
+ beq ZeroBSS /* If size is zero, jump to ZeroBSS */
+CopyDataLoop:
+ ldrb r4, [r2], #1 /* Load a byte from Flash (source), post-increment r2 by 1 */
+ strb r4, [r1], #1 /* Store the byte to RAM (destination), post-increment r1 by 1 */
+ subs r3, r3, #1 /* Decrement the remaining byte count by 1 */
+ bgt CopyDataLoop /* If there are still bytes left, continue looping */
+/* Initialize .bss section to zero */
+ZeroBSS:
+ ldr r2, =_sbss /* Load the start address of the .bss section */
+ ldr r3, =_ebss /* Load the end address of the .bss section */
+ sub r3, r3, r2 /* Calculate bytes count (r3 = (end - start) */
+ mov r4, #0 /* Load zero into r4 */
+ZeroBSSLoop:
+ str r4, [r2], #4 /* Store zero to memory location, increment address */
+ subs r3, r3, #4 /* Subtract 4 bytes from the remaining byte count */
+ bgt ZeroBSSLoop /* If there are still bytes left, continue looping */
+/* Call stack_debug_init function if in debug mode */
#if defined (DEBUG_STACK)
- bl stack_debug_init
+ bl stack_debug_init /* Branch to stack_debug_init if DEBUG_STACK is defined */
#endif
+/* Call SystemInit function to perform system-specific initialization */
bl SystemInit
+/* Call static constructors to initialize global objects */
+ bl __libc_init_array
+/* Call the main function to start the application */
bl main
+/* Return from main (in case main returns) */
bx lr
+/* NOP to align the code (optional) */
+ nop /* No operation; used for code alignment and readability */
+
.size Reset_Handler, .-Reset_Handler
.section .text.Default_Handler,"ax",%progbits
+
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- .size Default_Handler, .-Default_Handler
- .section .vectors,"a",%progbits
- .global __gVectors
+.size Default_Handler, .-Default_Handler
+
+.section .vectors,"a",%progbits
+.global __gVectors
__gVectors:
.word _sp /* Top of Stack */
@@ -75,8 +109,7 @@ __gVectors:
.word 0 /* Reserved */
.word PendSV_Handler /* 14:PendSV Handler */
.word SysTick_Handler /* 15:SysTick Handler */
-
- /* external interrupts handler */
+ /* External Interrupts */
.word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
.word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
.word TAMPER_STAMP_IRQHandler /* 18:Tamper and TimeStamp through EXTI Line detect */
@@ -162,6 +195,12 @@ __gVectors:
.size __gVectors, . - __gVectors
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*******************************************************************************/
+
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
diff --git a/firmware-template/libs.mk b/firmware-template/libs.mk
index e83c9570..b69667cd 100644
--- a/firmware-template/libs.mk
+++ b/firmware-template/libs.mk
@@ -19,92 +19,44 @@ ifeq ($(findstring NODE_E131,$(DEFINES)),NODE_E131)
endif
endif
-ifeq ($(findstring NODE_DDP_DISPLAY,$(DEFINES)),NODE_DDP_DISPLAY)
- LIBS+=ddp
+ifeq ($(findstring NODE_OSC_CLIENT,$(DEFINES)),NODE_OSC_CLIENT)
+ LIBS+=osc
endif
-ifeq ($(findstring NODE_PP,$(DEFINES)),NODE_PP)
- LIBS+=pp
+ifeq ($(findstring NODE_OSC_SERVER,$(DEFINES)),NODE_OSC_SERVER)
+ LIBS+=osc
endif
-RDM=
-
ifeq ($(findstring RDM_CONTROLLER,$(DEFINES)),RDM_CONTROLLER)
RDM=1
- ifeq ($(findstring NO_EMAC,$(DEFINES)),NO_EMAC)
- else
- LIBS+=rdmdiscovery
- endif
-endif
-
-ifeq ($(findstring RDM_RESPONDER,$(DEFINES)),RDM_RESPONDER)
- ifneq ($(findstring rdmresponder,$(LIBS)),rdmresponder)
- LIBS+=rdmresponder
- endif
- ifneq ($(findstring rdmsensor,$(LIBS)),rdmsensor)
- LIBS+=rdmsensor device
- endif
- ifneq ($(findstring rdmsubdevice,$(LIBS)),rdmsubdevice)
- LIBS+=rdmsubdevice
- endif
- LIBS+=dmxreceiver dmx
- RDM=1
+ DMX=1
endif
ifeq ($(findstring NODE_RDMNET_LLRP_ONLY,$(DEFINES)),NODE_RDMNET_LLRP_ONLY)
- ifneq ($(findstring rdmnet,$(LIBS)),rdmnet)
- LIBS+=rdmnet
- endif
+ RDM=1
ifneq ($(findstring e131,$(LIBS)),e131)
LIBS+=e131
endif
- ifneq ($(findstring rdmsensor,$(LIBS)),rdmsensor)
- LIBS+=rdmsensor
- endif
- ifneq ($(findstring rdmsubdevice,$(LIBS)),rdmsubdevice)
- LIBS+=rdmsubdevice
- endif
- RDM=1
endif
ifdef RDM
LIBS+=rdm
endif
-ifeq ($(findstring e131,$(LIBS)),e131)
- LIBS+=uuid
-endif
-
-ifeq ($(findstring OUTPUT_DMX_MONITOR,$(DEFINES)),OUTPUT_DMX_MONITOR)
- LIBS+=dmxmonitor
-endif
-
ifeq ($(findstring OUTPUT_DMX_SEND,$(DEFINES)),OUTPUT_DMX_SEND)
- LIBS+=dmxsend dmx
+ LIBS+= dmx
endif
-ifeq ($(findstring OUTPUT_DDP_PIXEL_MULTI,$(DEFINES)),OUTPUT_DDP_PIXEL_MULTI)
+ifeq ($(findstring OUTPUT_DMX_PIXEL,$(DEFINES)),OUTPUT_DMX_PIXEL)
LIBS+=ws28xxdmx ws28xx
-else
- ifeq ($(findstring OUTPUT_DMX_PIXEL_MULTI,$(DEFINES)),OUTPUT_DMX_PIXEL_MULTI)
- LIBS+=ws28xxdmx ws28xx
- else
- ifeq ($(findstring OUTPUT_DMX_PIXEL,$(DEFINES)),OUTPUT_DMX_PIXEL)
- LIBS+=ws28xxdmx ws28xx
- endif
- endif
-endif
-
-ifeq ($(findstring OUTPUT_DDP_PIXEL,$(DEFINES)),OUTPUT_DDP_PIXEL)
- LIBS+=ws28xx
endif
-LIBS+=configstore network lightset
+LIBS+=configstore network
ifeq ($(findstring DISPLAY_UDF,$(DEFINES)),DISPLAY_UDF)
LIBS+=displayudf
endif
-LIBS+=flash properties display hal
+LIBS+=lightset flash properties display device hal
-$(info $$LIBS [${LIBS}])
\ No newline at end of file
+$(info $$LIBS [${LIBS}])
diff --git a/gd32_emac_artnet_dmx_multi/.cproject b/gd32_emac_artnet_dmx_multi/.cproject
index 3e7a3aca..60771f55 100644
--- a/gd32_emac_artnet_dmx_multi/.cproject
+++ b/gd32_emac_artnet_dmx_multi/.cproject
@@ -31,14 +31,12 @@
-
diff --git a/gd32_emac_artnet_dmx_multi/Common.mk b/gd32_emac_artnet_dmx_multi/Common.mk
new file mode 100644
index 00000000..13051062
--- /dev/null
+++ b/gd32_emac_artnet_dmx_multi/Common.mk
@@ -0,0 +1,19 @@
+DEFINES+=NODE_ARTNET_MULTI ARTNET_VERSION=4
+DEFINES+=ARTNET_HAVE_DMXIN
+DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
+
+DEFINES+=OUTPUT_DMX_SEND_MULTI
+DEFINES+=OUTPUT_HAVE_STYLESWITCH
+
+DEFINES+=RDM_CONTROLLER
+
+DEFINES+=CONFIG_STORE_USE_SPI
+
+DEFINES+=RTL8201F_LED1_LINK_ALL
+
+DEFINES+=DISPLAY_UDF
+
+DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
+
+DEFINES+=DISABLE_RTC
+DEFINES+=DISABLE_FS
\ No newline at end of file
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart.GD32
deleted file mode 100644
index a78baa95..00000000
--- a/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart.GD32
+++ /dev/null
@@ -1,32 +0,0 @@
-BOARD=BOARD_BW_OPIDMX4
-
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
-
-DEFINES+=RDM_CONTROLLER
-
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
-
-DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
-DEFINES+=CONFIG_USE_SOFTUART0
-
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
-
-DEFINES+=NDEBUG
-
-LIBS=
-
-SRCDIR=firmware lib
-
-include ../firmware-template-gd32/Rules.mk
-
-prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32
new file mode 100644
index 00000000..1598b18e
--- /dev/null
+++ b/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32
@@ -0,0 +1,21 @@
+BOARD=BOARD_BW_OPIDMX4
+
+DEFINES=LIGHTSET_PORTS=4
+
+DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
+
+#
+
+DEFINES+=CONFIG_USE_SOFTUART0
+
+DEFINES+=DEBUG_STACK
+DEFINES+=NDEBUG
+
+LIBS=
+
+SRCDIR=firmware lib
+
+include Common.mk
+include ../firmware-template-gd32/Rules.mk
+
+prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32
index 8c49a0b7..c0eec0f1 100644
--- a/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32
+++ b/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32
@@ -1,33 +1,21 @@
BOARD=BOARD_BW_OPIDMX4
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
-
-DEFINES+=RDM_CONTROLLER
-
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
+DEFINES=LIGHTSET_PORTS=4
DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
+#
DEFINES+=CONSOLE_NULL
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
-
+DEFINES+=DEBUG_STACK
DEFINES+=NDEBUG
LIBS=
SRCDIR=firmware lib
+include Common.mk
include ../firmware-template-gd32/Rules.mk
prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32
index 990f171d..78ce4ffa 100644
--- a/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32
+++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32
@@ -1,31 +1,21 @@
BOARD=BOARD_DMX3
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=3
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
-
-DEFINES+=RDM_CONTROLLER
-
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
+DEFINES=LIGHTSET_PORTS=3
DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
+#
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
+#
+DEFINES+=DEBUG_STACK
DEFINES+=NDEBUG
LIBS=
SRCDIR=firmware lib
+include Common.mk
include ../firmware-template-gd32/Rules.mk
prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart.GD32
deleted file mode 100644
index 7ce13661..00000000
--- a/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart.GD32
+++ /dev/null
@@ -1,32 +0,0 @@
-BOARD=BOARD_DMX4
-
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
-
-DEFINES+=RDM_CONTROLLER
-
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
-
-DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
-DEFINES+=CONFIG_USE_SOFTUART0
-
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
-
-DEFINES+=NDEBUG
-
-LIBS=
-
-SRCDIR=firmware lib
-
-include ../firmware-template-gd32/Rules.mk
-
-prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32
new file mode 100644
index 00000000..28dab1bf
--- /dev/null
+++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32
@@ -0,0 +1,21 @@
+BOARD=BOARD_DMX4
+
+DEFINES=LIGHTSET_PORTS=4
+
+DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
+
+DEFINES+=LEDPANEL_595_COUNT=2
+
+DEFINES+=CONFIG_USE_SOFTUART0
+
+DEFINES+=DEBUG_STACK
+DEFINES+=NDEBUG
+
+LIBS=
+
+SRCDIR=firmware lib
+
+include Common.mk
+include ../firmware-template-gd32/Rules.mk
+
+prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32
index 253b6863..8cb4d0ac 100644
--- a/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32
+++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32
@@ -1,33 +1,21 @@
BOARD=BOARD_DMX4
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
-
-DEFINES+=RDM_CONTROLLER
-
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
+DEFINES=LIGHTSET_PORTS=4
DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
+DEFINES+=LEDPANEL_595_COUNT=2
DEFINES+=CONSOLE_NULL
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
-
+DEFINES+=DEBUG_STACK
DEFINES+=NDEBUG
LIBS=
SRCDIR=firmware lib
+include Common.mk
include ../firmware-template-gd32/Rules.mk
prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/Makefile.GD32 b/gd32_emac_artnet_dmx_multi/Makefile.GD32
index 2462fda1..02db4c1a 100644
--- a/gd32_emac_artnet_dmx_multi/Makefile.GD32
+++ b/gd32_emac_artnet_dmx_multi/Makefile.GD32
@@ -1,31 +1,21 @@
BOARD=BOARD_GD32F407RE
-DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=2
-DEFINES+=ARTNET_HAVE_DMXIN
-DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD
+DEFINES=LIGHTSET_PORTS=2
-DEFINES+=RDM_CONTROLLER
+DEFINES+=ENET_RXBUF_NUM=8 ENET_TXBUF_NUM=4
-DEFINES+=OUTPUT_DMX_SEND_MULTI
-DEFINES+=OUTPUT_HAVE_STYLESWITCH
+#
-DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4
-
-DEFINES+=DISPLAY_UDF
-
-DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
-
-DEFINES+=CONFIG_STORE_USE_SPI
-
-DEFINES+=DISABLE_RTC
-DEFINES+=DISABLE_FS
+#
+DEFINES+=DEBUG_STACK
DEFINES+=NDEBUG
LIBS=
SRCDIR=firmware lib
+include Common.mk
include ../firmware-template-gd32/Rules.mk
prerequisites:
diff --git a/gd32_emac_artnet_dmx_multi/do-tftp.sh b/gd32_emac_artnet_dmx_multi/do-tftp.sh
index 8066e8dc..66bc49c3 100755
--- a/gd32_emac_artnet_dmx_multi/do-tftp.sh
+++ b/gd32_emac_artnet_dmx_multi/do-tftp.sh
@@ -11,6 +11,15 @@ echo '!tftp#1' | udp_send $1
ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
echo [$ON_LINE]
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
while [ "$ON_LINE" == "tftp:Off" ]
do
sleep 1
@@ -18,6 +27,8 @@ while [ "$ON_LINE" == "tftp:Off" ]
ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
done
+echo [$ON_LINE]
+
sleep 1
echo -e "Rebooting..."
echo '?reboot##' | udp_send $1
@@ -30,7 +41,26 @@ while [ "$ON_LINE" == "" ]
done
echo '!tftp#1' | udp_send $1
-echo '?tftp#' | udp_send $1
+ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "tftp:Off" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
tftp $1 << -EOF
binary
@@ -39,9 +69,27 @@ quit
-EOF
echo '!tftp#0' | udp_send $1
-sleep 1
-echo '?tftp#' | udp_send $1
-sleep 2
+ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#0' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "tftp:On" ]
+ do
+ sleep 1
+ echo '!tftp#0' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
echo -e "Rebooting..."
echo '?reboot##' | udp_send $1
diff --git a/gd32_emac_artnet_dmx_multi/firmware/main.cpp b/gd32_emac_artnet_dmx_multi/firmware/main.cpp
index 0439baa4..842d13ed 100644
--- a/gd32_emac_artnet_dmx_multi/firmware/main.cpp
+++ b/gd32_emac_artnet_dmx_multi/firmware/main.cpp
@@ -2,7 +2,7 @@
* @file main.cpp
*
*/
-/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org
+/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -30,16 +30,15 @@
#include "network.h"
#include "networkconst.h"
-#include "mdns.h"
+#include "net/apps/mdns.h"
-#if defined (ENABLE_HTTPD)
-# include "httpd/httpd.h"
+#if defined (ENABLE_NTP_CLIENT)
+# include "net/apps/ntpclient.h"
#endif
#include "displayudf.h"
#include "displayudfparams.h"
#include "displayhandler.h"
-#include "display_timeout.h"
#include "artnetnode.h"
#include "artnetparams.h"
@@ -51,83 +50,66 @@
#include "rdmdeviceparams.h"
#include "dmxconfigudp.h"
+#if defined (NODE_SHOWFILE)
+# include "showfile.h"
+# include "showfileparams.h"
+#endif
+
#include "remoteconfig.h"
#include "remoteconfigparams.h"
#include "configstore.h"
-#include "storeartnet.h"
-#include "storedisplayudf.h"
-#include "storedmxsend.h"
-#include "storenetwork.h"
-#include "storerdmdevice.h"
-#include "storeremoteconfig.h"
#include "firmwareversion.h"
#include "software_version.h"
-static constexpr uint32_t DMXPORT_OFFSET = 0;
+namespace artnetnode {
+namespace configstore {
+uint32_t DMXPORT_OFFSET = 0;
+} // namespace configstore
+} // namespace artnetnode
void Hardware::RebootHandler() {
Dmx::Get()->Blackout();
ArtNetNode::Get()->Stop();
}
-void main() {
+int main() {
Hardware hw;
DisplayUdf display;
ConfigStore configStore;
- display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW);
- StoreNetwork storeNetwork;
- Network nw(&storeNetwork);
- display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN);
+ display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW);
+ Network nw;
+ MDNS mDns;
+ display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN);
FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__);
fw.Print("Art-Net 4 DMX/RDM controller {" STR(LIGHTSET_PORTS) " Universes}");
- nw.Print();
-
- display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW);
-
- MDNS mDns;
- mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=Art-Net 4 DMX/RDM");
-#if defined (ENABLE_HTTPD)
- mDns.AddServiceRecord(nullptr, mdns::Services::HTTP);
-#endif
- mDns.Print();
-#if defined (ENABLE_HTTPD)
- HttpDaemon httpDaemon;
+#if defined (ENABLE_NTP_CLIENT)
+ NtpClient ntpClient;
+ ntpClient.Start();
+ ntpClient.Print();
#endif
- display.TextStatus(ArtNetMsgConst::PARAMS, Display7SegmentMessage::INFO_NODE_PARMAMS, CONSOLE_YELLOW);
-
ArtNetNode node;
- StoreArtNet storeArtNet(DMXPORT_OFFSET);
- node.SetArtNetStore(&storeArtNet);
-
- ArtNetParams artnetParams(&storeArtNet);
-
- if (artnetParams.Load()) {
- artnetParams.Dump();
- artnetParams.Set(DMXPORT_OFFSET);
- }
+ ArtNetParams artnetParams;
+ artnetParams.Load();
+ artnetParams.Set();
for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) {
node.SetUniverse(nPortIndex, artnetParams.GetDirection(nPortIndex), artnetParams.GetUniverse(nPortIndex));
}
- StoreDmxSend storeDmxSend;
- DmxParams dmxparams(&storeDmxSend);
-
Dmx dmx;
- if (dmxparams.Load()) {
- dmxparams.Dump();
- dmxparams.Set(&dmx);
- }
+ DmxParams dmxparams;
+ dmxparams.Load();
+ dmxparams.Set(&dmx);
- for (uint32_t nPortIndex = DMXPORT_OFFSET; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) {
- const auto nDmxPortIndex = nPortIndex - DMXPORT_OFFSET;
+ for (uint32_t nPortIndex = artnetnode::configstore::DMXPORT_OFFSET; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) {
+ const auto nDmxPortIndex = nPortIndex - artnetnode::configstore::DMXPORT_OFFSET;
const auto portDirection = (node.GetPortDirection(nPortIndex) == lightset::PortDir::OUTPUT ? dmx::PortDirection::OUTP : dmx::PortDirection::INP);
dmx.SetPortDirection(nDmxPortIndex, portDirection , false);
}
@@ -137,33 +119,26 @@ void main() {
node.SetOutput(&dmxSend);
- DmxConfigUdp dmxConfigUdp;
-
- StoreRDMDevice storeRdmDevice;
-
+ RDMDeviceParams rdmDeviceParams;
ArtNetRdmController artNetRdmController;
- if (artnetParams.IsRdm()) {
- RDMDeviceParams rdmDeviceParams(&storeRdmDevice);
+ rdmDeviceParams.Load();
+ rdmDeviceParams.Set(&artNetRdmController);
- if (rdmDeviceParams.Load()) {
- rdmDeviceParams.Dump();
- rdmDeviceParams.Set(&artNetRdmController);
- }
+ artNetRdmController.Init();
+ artNetRdmController.Print();
- artNetRdmController.Init();
- artNetRdmController.Print();
+ node.SetRdmController(&artNetRdmController, artnetParams.IsRdm());
- display.TextStatus(ArtNetMsgConst::RDM_RUN, Display7SegmentMessage::INFO_RDM_RUN, CONSOLE_YELLOW);
+#if defined (NODE_SHOWFILE)
+ ShowFile showFile;
- for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) {
- if (node.GetRdm(nPortIndex) && (node.GetPortDirection(nPortIndex) == lightset::PortDir::OUTPUT)) {
- artNetRdmController.Full(nPortIndex);
- }
- }
+ ShowFileParams showFileParams;
+ showFileParams.Load();
+ showFileParams.Set();
- node.SetRdmHandler(&artNetRdmController);
- }
+ showFile.Print();
+#endif
node.Print();
@@ -175,34 +150,29 @@ void main() {
display.Set(4, displayudf::Labels::UNIVERSE_PORT_A);
display.Set(5, displayudf::Labels::UNIVERSE_PORT_B);
- StoreDisplayUdf storeDisplayUdf;
- DisplayUdfParams displayUdfParams(&storeDisplayUdf);
+ DisplayUdfParams displayUdfParams;
- if (displayUdfParams.Load()) {
- displayUdfParams.Dump();
- displayUdfParams.Set(&display);
- }
+ displayUdfParams.Load();
+ displayUdfParams.Set(&display);
- display.Show(&node);
+ display.Show();
RemoteConfig remoteConfig(remoteconfig::Node::ARTNET, artnetParams.IsRdm() ? remoteconfig::Output::RDM : remoteconfig::Output::DMX, nActivePorts);
- StoreRemoteConfig storeRemoteConfig;
- RemoteConfigParams remoteConfigParams(&storeRemoteConfig);
-
- if (remoteConfigParams.Load()) {
- remoteConfigParams.Dump();
- remoteConfigParams.Set(&remoteConfig);
- }
+ RemoteConfigParams remoteConfigParams;
+ remoteConfigParams.Load();
+ remoteConfigParams.Set(&remoteConfig);
while (configStore.Flash())
;
- display.TextStatus(ArtNetMsgConst::START, Display7SegmentMessage::INFO_NODE_START, CONSOLE_YELLOW);
+ mDns.Print();
+
+ display.TextStatus(ArtNetMsgConst::START, CONSOLE_YELLOW);
node.Start();
- display.TextStatus(ArtNetMsgConst::STARTED, Display7SegmentMessage::INFO_NODE_STARTED, CONSOLE_GREEN);
+ display.TextStatus(ArtNetMsgConst::STARTED, CONSOLE_GREEN);
hw.WatchdogInit();
@@ -210,14 +180,14 @@ void main() {
hw.WatchdogFeed();
nw.Run();
node.Run();
+#if defined (NODE_SHOWFILE)
+ showFile.Run();
+#endif
remoteConfig.Run();
configStore.Flash();
- if (node.GetActiveOutputPorts() != 0) {
- dmxConfigUdp.Run();
- }
mDns.Run();
-#if defined (ENABLE_HTTPD)
- httpDaemon.Run();
+#if defined (ENABLE_NTP_CLIENT)
+ ntpClient.Run();
#endif
display.Run();
hw.Run();
diff --git a/gd32_emac_artnet_dmx_multi/gd32f4xx.map b/gd32_emac_artnet_dmx_multi/gd32f4xx.map
index 057bff07..e842ba11 100644
--- a/gd32_emac_artnet_dmx_multi/gd32f4xx.map
+++ b/gd32_emac_artnet_dmx_multi/gd32f4xx.map
@@ -1,43 +1,31 @@
Archive member included to satisfy reference by file (symbol)
-../lib-c/lib_gd32/libc.a(printf.o)
- build_gd32/lib/debug_dump.o (printf)
-../lib-c/lib_gd32/libc.a(puts.o)
- build_gd32/firmware/main.o (puts)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (__aeabi_d2f)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (__aeabi_uldivmod)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
- /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
- /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- build_gd32/firmware/main.o (RemoteConfig::RemoteConfig(remoteconfig::Node, remoteconfig::Output, unsigned long))
+ build_gd32/firmware/main.o (RemoteConfig::s_pUdpBuffer)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigfactory.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::HandleFactory())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
- build_gd32/firmware/main.o (RemoteConfigParams::RemoteConfigParams(RemoteConfigParamsStore*))
-../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparamsdump.o)
- build_gd32/firmware/main.o (RemoteConfigParams::Dump())
+ build_gd32/firmware/main.o (RemoteConfigParams::RemoteConfigParams())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigreboot.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::HandleReboot())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigstatic.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::GetIndex(void const*, unsigned long&))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::PlatformHandleTftpSet())
-../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- build_gd32/firmware/main.o (HttpDaemon::HttpDaemon())
+../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (HttpDaemon::HttpDaemon())
+../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ build_gd32/firmware/main.o (HttpDeamonHandleRequest::HandleRequest(unsigned long, char*))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigconst.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (RemoteConfigConst::PARAMS_DISPLAY_NAME)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (remoteconfig::json_get_list(char*, unsigned short))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::json_get_list(char*, unsigned long))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (get_file_content(char const*, char*, http::contentTypes&))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (get_file_content(char const*, unsigned long&, http::contentTypes&))
../lib-artnet/lib_gd32/libartnet.a(artnetmsgconst.o)
- build_gd32/firmware/main.o (ArtNetMsgConst::RDM_RUN)
+ build_gd32/firmware/main.o (ArtNetMsgConst::STARTED)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- build_gd32/firmware/main.o (ArtNetNode::Start())
+ build_gd32/firmware/main.o (ArtNetNode::Stop())
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::SetLocalMerging())
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
@@ -45,7 +33,7 @@ Archive member included to satisfy reference by file (symbol)
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleIpProg())
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
- ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::SendPollRelply(unsigned long, unsigned long, artnetnode::ArtPollQueue*))
+ ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::SendPollRelply(unsigned long, unsigned long, artnet::ArtPollQueue*))
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlesync.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleSync())
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandletimesync.o)
@@ -53,19 +41,35 @@ Archive member included to satisfy reference by file (symbol)
../lib-artnet/lib_gd32/libartnet.a(artnetnodeprint.o)
build_gd32/firmware/main.o (ArtNetNode::Print())
../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- build_gd32/firmware/main.o (ArtNetParams::ArtNetParams(ArtNetParamsStore*))
+ build_gd32/firmware/main.o (ArtNetParams::ArtNetParams())
../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
../lib-artnet/lib_gd32/libartnet.a(artnetparams.o) (ArtNetParamsConst::MAP_UNIVERSE0)
-../lib-artnet/lib_gd32/libartnet.a(artnetparamsdump.o)
- build_gd32/firmware/main.o (ArtNetParams::Dump())
../lib-artnet/lib_gd32/libartnet.a(handledmxin.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleDmxIn())
../lib-artnet/lib_gd32/libartnet.a(handleinput.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleInput())
../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o) (ArtNetNode::SetRmd(unsigned long, bool))
+ ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleTodRequest())
+../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o) (ArtNetNode::SetRdm(unsigned long, bool))
+../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o)
+ build_gd32/firmware/main.o (ArtNetRdmController::m_pRDMTod)
+../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleTodControl())
../lib-artnet/lib_gd32/libartnet.a(handlerdmin.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleRdmIn())
+../lib-artnet/lib_gd32/libartnet.a(handlerdmsub.o)
+ ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (ArtNetNode::HandleRdmSub())
+../lib-artnet/lib_gd32/libartnet.a(json_get_portstatus.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::rdm::json_get_portstatus(char*, unsigned long))
+../lib-artnet/lib_gd32/libartnet.a(json_get_queue.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::rdm::json_get_queue(char*, unsigned long))
+../lib-artnet/lib_gd32/libartnet.a(json_get_rdm.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::rdm::json_get_rdm(char*, unsigned long))
+../lib-artnet/lib_gd32/libartnet.a(json_get_tod.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::rdm::json_get_tod(char, char*, unsigned long))
+../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ build_gd32/firmware/main.o (ArtNetNode::SetRdmController(ArtNetRdmController*, bool))
../lib-artnet/lib_gd32/libartnet.a(artnetnodefailsafe.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o) (ArtNetNode::FailSafeRecord())
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
@@ -86,138 +90,112 @@ Archive member included to satisfy reference by file (symbol)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E131Bridge::FillDataPacket())
../lib-e131/lib_gd32/libe131.a(e117const.o)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E117Const::ACN_PACKET_IDENTIFIER)
-../lib-e131/lib_gd32/libe131.a(e131bridgeconst.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (E131BridgeConst::VERSION)
-../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memcpy)
-../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdm_send.o)
- ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o) (artnet::rdm_send(unsigned long, unsigned char const*))
-../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o) (RDMDiscovery::RDMDiscovery(unsigned char const*))
+../lib-e131/lib_gd32/libe131.a(e131const.o)
+ ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (E131Const::VERSION)
../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o) (RDMDevice::RDMDevice())
+ build_gd32/firmware/main.o (RDMDevice::RDMDevice())
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- build_gd32/firmware/main.o (RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*))
+ build_gd32/firmware/main.o (RDMDeviceParams::RDMDeviceParams())
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparamsconst.o)
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (RDMDeviceParamsConst::PRODUCT_DETAIL)
+../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ build_gd32/firmware/main.o (RDMDiscovery::RDMDiscovery(unsigned char const*))
../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
../lib-rdm/lib_gd32/librdm.a(rdmdevice.o) (RDMConst::MANUFACTURER_ID)
-../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (uuid_unparse)
-../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- build_gd32/firmware/main.o (DmxSend::Print())
+../lib-rdm/lib_gd32/librdm.a(rdm.o)
+ ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o) (Rdm::s_TransactionNumber)
../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- build_gd32/firmware/main.o (DmxParams::DmxParams(DmxParamsStore*))
+ build_gd32/firmware/main.o (DmxParams::DmxParams())
../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
../lib-dmx/lib_gd32/libdmx.a(dmxparams.o) (DmxParamsConst::SLOTS_COUNT)
-../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o) (Rdm::Receive(unsigned long))
+../lib-dmx/lib_gd32/libdmx.a(json_get_ports.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::dmx::json_get_ports(char*, unsigned long))
+../lib-dmx/lib_gd32/libdmx.a(json_get_portstatus.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::dmx::json_get_portstatus(char, char*, unsigned long))
../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- build_gd32/firmware/main.o (Dmx::Dmx())
-../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o) (Rdm::Send(unsigned long, TRdmMessage*, unsigned long))
-../lib-dmx/lib_gd32/libdmx.a(dmxconfigudp.o)
- build_gd32/firmware/main.o (DmxConfigUdp::s_pUdpBuffer)
+ ../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o) (gsv_RdmDataReceiveEnd)
../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- build_gd32/firmware/main.o (ConfigStore::ConfigStore())
-../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- build_gd32/firmware/main.o (StoreDisplayUdf::StoreDisplayUdf())
-../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- build_gd32/firmware/main.o (StoreDmxSend::StoreDmxSend())
-../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- build_gd32/firmware/main.o (StoreNetwork::StoreNetwork())
-../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- build_gd32/firmware/main.o (StoreRemoteConfig::StoreRemoteConfig())
+ build_gd32/firmware/main.o (ConfigStore::s_pThis)
+../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (EnvParams::EnvParams())
+../lib-configstore/lib_gd32/libconfigstore.a(envparamsconst.o)
+ ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o) (EnvParamsConst::UTC_OFFSET)
../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
../lib-configstore/lib_gd32/libconfigstore.a(configstore.o) (StoreDevice::StoreDevice())
-../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- build_gd32/firmware/main.o (StoreArtNet::StoreArtNet(unsigned long))
-../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- build_gd32/firmware/main.o (StoreRDMDevice::StoreRDMDevice())
../lib-network/lib_gd32/libnetwork.a(networkconst.o)
- build_gd32/firmware/main.o (NetworkConst::MSG_MDNS_CONFIG)
+ build_gd32/firmware/main.o (NetworkConst::MSG_NETWORK_STARTED)
../lib-network/lib_gd32/libnetwork.a(mdns.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigreboot.o) (network::mdns_shutdown())
+ build_gd32/firmware/main.o (MDNS::s_nHandle)
../lib-network/lib_gd32/libnetwork.a(network.o)
- build_gd32/firmware/main.o (Network::Network(NetworkParamsStore*))
-../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (NetworkParams::NetworkParams(NetworkParamsStore*))
-../lib-network/lib_gd32/libnetwork.a(networkparamsdump.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (NetworkParams::Dump())
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o) (Network::s_pThis)
+../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::autoip_start())
+../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::dhcp_start())
../lib-network/lib_gd32/libnetwork.a(igmp.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridge.o) (igmp_join(unsigned long))
+ ../lib-e131/lib_gd32/libe131.a(e131bridge.o) (net::igmp_join(unsigned long))
../lib-network/lib_gd32/libnetwork.a(net.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (net_init(unsigned char const*, IpInfo*, char const*, bool*, bool*))
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::net_set_primary_ip(net::ip_addr))
../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
- ../lib-network/lib_gd32/libnetwork.a(igmp.o) (net_chksum(void const*, unsigned long))
-../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (net_timers_run())
-../lib-network/lib_gd32/libnetwork.a(rfc3927.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (rfc3927())
+ ../lib-network/lib_gd32/libnetwork.a(igmp.o) (net::net_chksum(void const*, unsigned long))
+../lib-network/lib_gd32/libnetwork.a(netif.o)
+ build_gd32/firmware/main.o (net::globals::netif_default)
../lib-network/lib_gd32/libnetwork.a(tcp.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (tcp_begin(unsigned short))
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::tcp_shutdown())
../lib-network/lib_gd32/libnetwork.a(udp.o)
- build_gd32/firmware/main.o (udp_begin(unsigned short))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (net::udp_begin(unsigned short))
+../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (NetworkParams::NetworkParams())
+../lib-network/lib_gd32/libnetwork.a(networkparamsconst.o)
+ ../lib-network/lib_gd32/libnetwork.a(networkparams.o) (NetworkParamsConst::NTP_SERVER)
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
../lib-network/lib_gd32/libnetwork.a(network.o) (net::phy_customized_led())
-../lib-network/lib_gd32/libnetwork.a(net.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (emac_eth_recv)
-../lib-network/lib_gd32/libnetwork.a(networkparamsconst.o)
- ../lib-network/lib_gd32/libnetwork.a(networkparams.o) (NetworkParamsConst::HOSTNAME)
../lib-network/lib_gd32/libnetwork.a(emac.o)
../lib-network/lib_gd32/libnetwork.a(network.o) (emac_config())
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
../lib-network/lib_gd32/libnetwork.a(net_phy.o) (net::phy_read(unsigned long, unsigned long, unsigned short&))
+../lib-network/lib_gd32/libnetwork.a(emac.o)
+ ../lib-network/lib_gd32/libnetwork.a(emac.o) (enet_gpio_config())
+../lib-network/lib_gd32/libnetwork.a(net.o)
+ ../lib-network/lib_gd32/libnetwork.a(net.o) (emac_eth_recv(unsigned char**))
+../lib-network/lib_gd32/libnetwork.a(acd.o)
+ ../lib-network/lib_gd32/libnetwork.a(autoip.o) (net::acd_start(net::acd::Acd*, net::ip_addr))
../lib-network/lib_gd32/libnetwork.a(arp.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (arp_init())
-../lib-network/lib_gd32/libnetwork.a(arp_cache.o)
- ../lib-network/lib_gd32/libnetwork.a(arp.o) (arp_cache_init())
-../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (dhcp_client(char const*))
+ ../lib-network/lib_gd32/libnetwork.a(net.o) (net::arp_init())
../lib-network/lib_gd32/libnetwork.a(ip.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (ip_set_ip())
+ ../lib-network/lib_gd32/libnetwork.a(netif.o) (net::ip_set_ip())
../lib-network/lib_gd32/libnetwork.a(net_link_check.o)
../lib-network/lib_gd32/libnetwork.a(net_phy.o) (net::link_status_read())
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- ../lib-network/lib_gd32/libnetwork.a(emac.o) (net::phy_start(unsigned long, net::PhyStatus&))
+ ../lib-network/lib_gd32/libnetwork.a(net_link_check.o) (net::phy_get_link(unsigned long))
../lib-network/lib_gd32/libnetwork.a(icmp.o)
- ../lib-network/lib_gd32/libnetwork.a(ip.o) (icmp_handle(t_icmp*))
-../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o) (LightSet::GetDmxStartAddress())
-../lib-lightset/lib_gd32/liblightset.a(lightsetgetslotinfo.o)
- ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o) (LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&))
-../lib-lightset/lib_gd32/liblightset.a(lightsetparamsconst.o)
- ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o) (LightSetParamsConst::FAILSAFE)
+ ../lib-network/lib_gd32/libnetwork.a(ip.o) (net::icmp_handle(t_icmp*))
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
build_gd32/firmware/main.o (DisplayUdf::DisplayUdf())
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- build_gd32/firmware/main.o (DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*))
+ build_gd32/firmware/main.o (DisplayUdfParams::DisplayUdfParams())
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparamsconst.o)
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o) (DisplayUdfParamsConst::DMX_DIRECTION)
../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
../lib-artnet/lib_gd32/libartnet.a(artnetnode.o) (artnet::display_longname(char const*))
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
- ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o) (DisplayUdf::ShowUniverse(ArtNetNode*))
+ ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o) (DisplayUdf::ShowUniverseArtNetNode())
../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (network::display_emac_config())
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::display_emac_config())
+../lib-lightset/lib_gd32/liblightset.a(lightsetparamsconst.o)
+ ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o) (LightSetParamsConst::FAILSAFE)
../lib-flash/lib_gd32/libflash.a(spi_flash.o)
../lib-artnet/lib_gd32/libartnet.a(failsafe.o) (spi_flash_get_size())
../lib-flash/lib_gd32/libflash.a(winbond.o)
../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_flash_probe_winbond(spi_flash*, unsigned char*))
../lib-flash/lib_gd32/libflash.a(spi_flash.o)
../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_init())
-../lib-flash/lib_gd32/libflash.a(get_timer.o)
- ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (get_timer(unsigned long))
-../lib-flash/lib_gd32/libflash.a(gigadevice.o)
- ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_flash_probe_gigadevice(spi_flash*, unsigned char*))
-../lib-flash/lib_gd32/libflash.a(macronix.o)
- ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_flash_probe_macronix(spi_flash*, unsigned char*))
../lib-properties/lib_gd32/libproperties.a(properties.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (properties::convert_json_file(char*, unsigned long, bool))
../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long))
../lib-properties/lib_gd32/libproperties.a(propertiesbuilderaddhex.o)
- ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (PropertiesBuilder::AddHex(char const*, unsigned long, bool, unsigned long))
+ ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (PropertiesBuilder::AddHex(char const*, unsigned long, bool, int))
../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (PropertiesConfig::s_Config)
../lib-properties/lib_gd32/libproperties.a(readconfigfile.o)
@@ -232,46 +210,26 @@ Archive member included to satisfy reference by file (symbol)
../lib-artnet/lib_gd32/libartnet.a(artnetparams.o) (Sscan::Uint16(char const*, char const*, unsigned short&))
../lib-properties/lib_gd32/libproperties.a(sscanuint8.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (Sscan::Uint8(char const*, char const*, unsigned char&))
+../lib-properties/lib_gd32/libproperties.a(sscanutcoffset.o)
+ ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o) (Sscan::UtcOffset(char const*, char const*, signed char&, unsigned char&))
../lib-properties/lib_gd32/libproperties.a(sscan.o)
../lib-properties/lib_gd32/libproperties.a(sscanchar.o) (Sscan::checkName(char const*, char const*))
../lib-display/lib_gd32/libdisplay.a(display.o)
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o) (Display::Display())
../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
../lib-display/lib_gd32/libdisplay.a(display.o) (Ssd1306::Ssd1306(TOledPanel))
-../lib-hal/lib_gd32/libhal.a(console.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (console_putc)
../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- build_gd32/firmware/main.o (FirmwareVersion::FirmwareVersion(char const*, char const*, char const*))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o) (FirmwareVersion::s_FirmwareVersion)
../lib-hal/lib_gd32/libhal.a(hardware.o)
build_gd32/firmware/main.o (Hardware::SetMode(hardware::ledblink::Mode))
+../lib-hal/lib_gd32/libhal.a(json_datetime.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::timedate::json_get_timeofday(char*, unsigned long))
../lib-hal/lib_gd32/libhal.a(hardware.o)
- build_gd32/firmware/main.o (Hardware::Hardware())
-../lib-c++/lib_gd32/libc++.a(delete.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o) (operator delete(void*))
-../lib-c++/lib_gd32/libc++.a(dso_handle.o)
- ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o) (__aeabi_atexit)
-../lib-c++/lib_gd32/libc++.a(new.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridge.o) (operator new(unsigned int))
-../lib-c/lib_gd32/libc.a(init.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (__libc_init_array)
-../lib-c/lib_gd32/libc.a(malloc.o)
- ../lib-c++/lib_gd32/libc++.a(new.o) (malloc)
-../lib-c/lib_gd32/libc.a(memmove.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memmove)
-../lib-c/lib_gd32/libc.a(memset.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memset)
-../lib-c/lib_gd32/libc.a(putchar.o)
- ../lib-network/lib_gd32/libnetwork.a(mdns.o) (putchar)
-../lib-c/lib_gd32/libc.a(strtok.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (strtok)
-../lib-c/lib_gd32/libc.a(time.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (localtime)
-../lib-c/lib_gd32/libc.a(time.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (settimeofday)
-../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_puts)
-../lib-gd32/lib_gd32/libgd32.a(systick.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (systick_config)
+ build_gd32/firmware/main.o (Hardware::s_pThis)
+../lib-hal/lib_gd32/libhal.a(console.o)
+ ../lib-network/lib_gd32/libnetwork.a(dhcp.o) (console_error)
+../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ build_gd32/startup_gd32f407.o (stack_debug_init)
../lib-gd32/lib_gd32/libgd32.a(system_gd32f4xx.o)
build_gd32/startup_gd32f407.o (SystemInit)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
@@ -281,6926 +239,5159 @@ Archive member included to satisfy reference by file (symbol)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
build_gd32/firmware/main.o (fwdgt_enable)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- build_gd32/firmware/main.o (gpio_mode_set)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gpio_mode_set)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
../lib-hal/lib_gd32/libhal.a(hardware.o) (pmu_backup_ldo_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- build_gd32/firmware/main.o (rcu_periph_clock_enable)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (rcu_periph_clock_enable)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
../lib-network/lib_gd32/libnetwork.a(emac.o) (syscfg_enet_phy_interface_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
../lib-dmx/lib_gd32/libdmx.a(dmx.o) (timer_deinit)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (usart_dma_transmit_config)
-../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_init)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (usart_flag_get)
../lib-gd32/lib_gd32/libgd32.a(bkp.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (bkp_data_write(bkp_data_register_enum, unsigned short))
+../lib-gd32/lib_gd32/libgd32.a(gd32_uart.o)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gd32_uart_begin(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long))
+../lib-gd32/lib_gd32/libgd32.a(mac_address.o)
+ ../lib-network/lib_gd32/libnetwork.a(emac.o) (mac_address_get(unsigned char*))
+../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (timer6_config())
+../lib-gd32/lib_gd32/libgd32.a(udelay.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (udelay_init())
+../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (systick_config)
../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o)
../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_adc_init())
../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_i2c_begin)
../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
../lib-flash/lib_gd32/libflash.a(spi_flash.o) (gd32_spi_begin())
-../lib-gd32/lib_gd32/libgd32.a(gd32_uart.o)
- ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gd32_uart_begin)
-../lib-gd32/lib_gd32/libgd32.a(mac_address.o)
- ../lib-network/lib_gd32/libnetwork.a(emac.o) (mac_address_get(unsigned char*))
-../lib-gd32/lib_gd32/libgd32.a(udelay.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (udelay_init())
+../lib-gd32/lib_gd32/libgd32.a(uart0.o)
+ ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_init)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o) (adc_clock_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o) (i2c_clock_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o) (spi_i2s_deinit)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+../lib-clib/lib_gd32/libclib.a(init.o)
+ build_gd32/startup_gd32f407.o (__libc_init_array)
+../lib-clib/lib_gd32/libclib.a(memcpy.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memcpy)
+../lib-clib/lib_gd32/libclib.a(memmove.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memmove)
+../lib-clib/lib_gd32/libclib.a(memset.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memset)
+../lib-clib/lib_gd32/libclib.a(printf.o)
+ build_gd32/hardfault_handler.o (printf)
+../lib-clib/lib_gd32/libclib.a(putchar.o)
+ ../lib-network/lib_gd32/libnetwork.a(mdns.o) (putchar)
+../lib-clib/lib_gd32/libclib.a(puts.o)
+ build_gd32/firmware/main.o (puts)
+../lib-clib/lib_gd32/libclib.a(random.o)
+ ../lib-network/lib_gd32/libnetwork.a(igmp.o) (random)
+../lib-clib/lib_gd32/libclib.a(strtok.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (strtok)
+../lib-clib/lib_gd32/libclib.a(uuid_unparse.o)
+ ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (uuid_unparse)
+../lib-clib/lib_gd32/libclib.a(assert.o)
+ ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o) (__assert_func)
+../lib-clib/lib_gd32/libclib.a(time.o)
+ ../lib-hal/lib_gd32/libhal.a(json_datetime.o) (localtime)
+../lib-clib/lib_gd32/libclib.a(uuid.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (hal::uuid_init(unsigned char*))
+../lib-clib/lib_gd32/libclib.a(time.o)
+ ../lib-hal/lib_gd32/libhal.a(json_datetime.o) (gettimeofday)
+../lib-clib/lib_gd32/libclib.a(delete.o)
+ ../lib-network/lib_gd32/libnetwork.a(mdns.o) (operator delete[](void*))
+../lib-clib/lib_gd32/libclib.a(new.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (operator new(unsigned int))
+../lib-clib/lib_gd32/libclib.a(malloc.o)
+ ../lib-clib/lib_gd32/libclib.a(new.o) (malloc)
+/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ ../lib-clib/lib_gd32/libclib.a(printf.o) (__aeabi_d2f)
+/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
../lib-network/lib_gd32/libnetwork.a(network.o) (__popcountsi2)
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+ 0x00000000 0x34 ../lib-clib/lib_gd32/libclib.a(malloc.o)
+ .data 0x00000000 0x0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ .bss 0x00000000 0x0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ .ARM.attributes
+ 0x00000000 0x22 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ .text 0x00000000 0x0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+ .data 0x00000000 0x0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+ .bss 0x00000000 0x0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+ .comment 0x00000000 0x39 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+ .ARM.attributes
+ 0x00000000 0x34 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
Memory Configuration
Name Origin Length Attributes
-FLASH 0x0000000008008000 0x000000000001a800 xr
-TCMSRAM 0x0000000010000000 0x0000000000010000 rw
-RAM 0x0000000020000000 0x000000000001c000 xrw
-RAM1 0x000000002001c000 0x0000000000004000 xrw
-RAM2 0x0000000020020000 0x0000000000000000 xrw
-RAMADD 0x0000000020030000 0x0000000000000000 xrw
-BKPSRAM 0x0000000040024000 0x0000000000001000 rw
-*default* 0x0000000000000000 0xffffffffffffffff
+FLASH 0x08008000 0x0001a800 xr
+TCMSRAM 0x10000000 0x00010000 rw
+RAM 0x20000000 0x0001c000 xrw
+RAM1 0x2001c000 0x00004000 xrw
+RAM2 0x20020000 0x00000000 xrw
+RAMADD 0x20030000 0x00000000 xrw
+BKPSRAM 0x40024000 0x00001000 rw
+*default* 0x00000000 0xffffffff
Linker script and memory map
LOAD build_gd32/startup_gd32f407.o
-LOAD build_gd32/lib/debug_dump.o
+LOAD build_gd32/hardfault_handler.o
LOAD build_gd32/firmware/main.o
LOAD build_gd32/lib/rdmsoftwareversion.o
- 0x0000000000001000 __heap_size = DEFINED (__heap_size)?__heap_size:0x1000
- 0x0000000000002800 __stack_size = DEFINED (__stack_size)?__stack_size:0x2800
+LOAD build_gd32/lib/showfileusb.o
+ 0x00001000 __heap_size = DEFINED (__heap_size)?__heap_size:0x1000
+ 0x00002800 __stack_size = DEFINED (__stack_size)?__stack_size:0x2800
-.vectors 0x0000000008008000 0x188
- 0x0000000008008000 . = ALIGN (0x4)
+.vectors 0x08008000 0x188
+ 0x08008000 . = ALIGN (0x4)
*(.vectors)
- .vectors 0x0000000008008000 0x188 build_gd32/startup_gd32f407.o
- 0x0000000008008000 __gVectors
- 0x0000000008008188 . = ALIGN (0x4)
- 0x0000000008008188 __Vectors_End = .
- 0x0000000008008188 __Vectors_Size = (__Vectors_End - __gVectors)
+ .vectors 0x08008000 0x188 build_gd32/startup_gd32f407.o
+ 0x08008000 __gVectors
+ 0x08008188 . = ALIGN (0x4)
+ 0x08008188 __Vectors_End = .
+ 0x08008188 __Vectors_Size = (__Vectors_End - __gVectors)
-.text 0x0000000008008188 0x10a44
- 0x0000000008008188 . = ALIGN (0x4)
+.text 0x08008188 0x120bc
+ 0x08008188 . = ALIGN (0x4)
*(.text.unlikely*)
- .text.unlikely._Z9igmp_initv
- 0x0000000008008188 0x90 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x0000000008008188 igmp_init()
- .text.unlikely._Z13igmp_shutdownv
- 0x0000000008008218 0x1c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x0000000008008218 igmp_shutdown()
- .text.unlikely._Z8net_initPKhP6IpInfoPKcPbS5_
- 0x0000000008008234 0xa8 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008008234 net_init(unsigned char const*, IpInfo*, char const*, bool*, bool*)
- .text.unlikely._Z12net_shutdownv
- 0x00000000080082dc 0x1c ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080082dc net_shutdown()
- .text.unlikely._Z8tcp_initv
- 0x00000000080082f8 0x28 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x00000000080082f8 tcp_init()
- .text.unlikely._Z8udp_initv
- 0x0000000008008320 0x3c ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x0000000008008320 udp_init()
+ .text.unlikely._ZN3net9igmp_initEv
+ 0x08008188 0xec ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08008188 net::igmp_init()
+ .text.unlikely._ZN3net13igmp_shutdownEv
+ 0x08008274 0x1c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08008274 net::igmp_shutdown()
+ .text.unlikely._ZN3net8net_initENS_4LinkENS_7ip_addrES1_S1_Rb
+ 0x08008290 0x70 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08008290 net::net_init(net::Link, net::ip_addr, net::ip_addr, net::ip_addr, bool&)
+ .text.unlikely._ZN3net8tcp_initEv
+ 0x08008300 0x34 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08008300 net::tcp_init()
+ .text.unlikely._ZN3net8udp_initEv
+ 0x08008334 0x48 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08008334 net::udp_init()
.text.unlikely._Z11emac_configv
- 0x000000000800835c 0x1e4 ../lib-network/lib_gd32/libnetwork.a(emac.o)
- 0x000000000800835c emac_config()
+ 0x0800837c 0x48 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x0800837c emac_config()
.text.unlikely._Z10emac_startPhRN3net4LinkE
- 0x0000000008008540 0xc4 ../lib-network/lib_gd32/libnetwork.a(emac.o)
- 0x0000000008008540 emac_start(unsigned char*, net::Link&)
- .text.unlikely._Z8arp_initv
- 0x0000000008008604 0xb4 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008008604 arp_init()
- .text.unlikely._Z14arp_cache_initv
- 0x00000000080086b8 0x24 ../lib-network/lib_gd32/libnetwork.a(arp_cache.o)
- 0x00000000080086b8 arp_cache_init()
- .text.unlikely._Z7ip_initv
- 0x00000000080086dc 0x12 ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x00000000080086dc ip_init()
- .text.unlikely._Z11ip_shutdownv
- 0x00000000080086ee 0xe ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x00000000080086ee ip_shutdown()
- .text.unlikely.console_init
- 0x00000000080086fc 0x20 ../lib-hal/lib_gd32/libhal.a(console.o)
- 0x00000000080086fc console_init
+ 0x080083c4 0x60 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x080083c4 emac_start(unsigned char*, net::Link&)
+ .text.unlikely._ZN3net8arp_initEv
+ 0x08008424 0x13c ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08008424 net::arp_init()
+ .text.unlikely._ZN3net7ip_initEv
+ 0x08008560 0x12 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08008560 net::ip_init()
+ *fill* 0x08008572 0x2
+ .text.unlikely._Z12console_initv
+ 0x08008574 0x20 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x08008574 console_init()
*(.text.hot*)
- .text.hot._Z11igmp_handleP6t_igmp
- 0x000000000800871c 0x98 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x000000000800871c igmp_handle(t_igmp*)
- .text.hot._Z10net_handlev
- 0x00000000080087b4 0x38 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080087b4 net_handle()
- .text.hot._Z7tcp_runv
- 0x00000000080087ec 0x44 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x00000000080087ec tcp_run()
- .text.hot._Z10tcp_handleP5t_tcp
- 0x0000000008008830 0x4e8 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008008830 tcp_handle(t_tcp*)
- .text.hot._Z10udp_handleP5t_udp
- 0x0000000008008d18 0x74 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x0000000008008d18 udp_handle(t_udp*)
- .text.hot._Z10arp_handleP5t_arp
- 0x0000000008008d8c 0x18 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008008d8c arp_handle(t_arp*)
- .text.hot._Z9ip_handleP5t_ip4
- 0x0000000008008da4 0x42 ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x0000000008008da4 ip_handle(t_ip4*)
- *fill* 0x0000000008008de6 0x2
- .text.hot._Z11icmp_handleP6t_icmp
- 0x0000000008008de8 0x7c ../lib-network/lib_gd32/libnetwork.a(icmp.o)
- 0x0000000008008de8 icmp_handle(t_icmp*)
+ .text.hot._ZN3net11igmp_handleEP6t_igmp
+ 0x08008594 0xac ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08008594 net::igmp_handle(t_igmp*)
+ .text.hot._ZN3net10net_handleEv
+ 0x08008640 0x38 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08008640 net::net_handle()
+ .text.hot._ZN3net7tcp_runEv
+ 0x08008678 0x4c ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08008678 net::tcp_run()
+ .text.hot._ZN3net10tcp_handleEP5t_tcp
+ 0x080086c4 0x620 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080086c4 net::tcp_handle(t_tcp*)
+ .text.hot._ZN3net10udp_handleEP5t_udp
+ 0x08008ce4 0x84 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08008ce4 net::udp_handle(t_udp*)
+ .text.hot._ZN3net10arp_handleEP5t_arp
+ 0x08008d68 0x114 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08008d68 net::arp_handle(t_arp*)
+ .text.hot._ZN3net9ip_handleEP5t_ip4
+ 0x08008e7c 0x54 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08008e7c net::ip_handle(t_ip4*)
+ .text.hot._ZN3net11icmp_handleEP6t_icmp
+ 0x08008ed0 0x80 ../lib-network/lib_gd32/libnetwork.a(icmp.o)
+ 0x08008ed0 net::icmp_handle(t_icmp*)
*(.text)
- .text 0x0000000008008e64 0xa0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
- 0x0000000008008e64 __aeabi_d2f
- 0x0000000008008e64 __truncdfsf2
- .text 0x0000000008008f04 0x30 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
- 0x0000000008008f04 __aeabi_uldivmod
- .text 0x0000000008008f34 0x4 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
- 0x0000000008008f34 __aeabi_ldiv0
- 0x0000000008008f34 __aeabi_idiv0
+ .text 0x08008f50 0xa0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ 0x08008f50 __aeabi_d2f
+ 0x08008f50 __truncdfsf2
*(.text*)
.text.Reset_Handler
- 0x0000000008008f38 0x44 build_gd32/startup_gd32f407.o
- 0x0000000008008f38 Reset_Handler
+ 0x08008ff0 0x54 build_gd32/startup_gd32f407.o
+ 0x08008ff0 Reset_Handler
.text.Default_Handler
- 0x0000000008008f7c 0x2 build_gd32/startup_gd32f407.o
- 0x0000000008008f7c USBHS_EP1_Out_IRQHandler
- 0x0000000008008f7c EXTI2_IRQHandler
- 0x0000000008008f7c DebugMon_Handler
- 0x0000000008008f7c LVD_IRQHandler
- 0x0000000008008f7c CAN1_EWMC_IRQHandler
- 0x0000000008008f7c HardFault_Handler
- 0x0000000008008f7c TIMER7_UP_TIMER12_IRQHandler
- 0x0000000008008f7c SDIO_IRQHandler
- 0x0000000008008f7c PendSV_Handler
- 0x0000000008008f7c NMI_Handler
- 0x0000000008008f7c EXTI3_IRQHandler
- 0x0000000008008f7c DCI_IRQHandler
- 0x0000000008008f7c USBFS_WKUP_IRQHandler
- 0x0000000008008f7c USBHS_IRQHandler
- 0x0000000008008f7c TIMER5_DAC_IRQHandler
- 0x0000000008008f7c TIMER0_TRG_CMT_TIMER10_IRQHandler
- 0x0000000008008f7c USBFS_IRQHandler
- 0x0000000008008f7c DMA0_Channel6_IRQHandler
- 0x0000000008008f7c I2C0_EV_IRQHandler
- 0x0000000008008f7c EXTI0_IRQHandler
- 0x0000000008008f7c I2C2_EV_IRQHandler
- 0x0000000008008f7c CAN1_RX0_IRQHandler
- 0x0000000008008f7c FPU_IRQHandler
- 0x0000000008008f7c TIMER7_TRG_CMT_TIMER13_IRQHandler
- 0x0000000008008f7c UsageFault_Handler
- 0x0000000008008f7c SPI1_IRQHandler
- 0x0000000008008f7c DMA0_Channel0_IRQHandler
- 0x0000000008008f7c TIMER0_BRK_TIMER8_IRQHandler
- 0x0000000008008f7c DMA1_Channel0_IRQHandler
- 0x0000000008008f7c TIMER7_BRK_TIMER11_IRQHandler
- 0x0000000008008f7c DMA1_Channel4_IRQHandler
- 0x0000000008008f7c I2C0_ER_IRQHandler
- 0x0000000008008f7c TIMER0_UP_TIMER9_IRQHandler
- 0x0000000008008f7c DMA1_Channel7_IRQHandler
- 0x0000000008008f7c CAN1_RX1_IRQHandler
- 0x0000000008008f7c DMA0_Channel2_IRQHandler
- 0x0000000008008f7c I2C1_EV_IRQHandler
- 0x0000000008008f7c UART4_IRQHandler
- 0x0000000008008f7c EXTI10_15_IRQHandler
- 0x0000000008008f7c DMA1_Channel1_IRQHandler
- 0x0000000008008f7c Default_Handler
- 0x0000000008008f7c TIMER7_Channel_IRQHandler
- 0x0000000008008f7c DMA0_Channel7_IRQHandler
- 0x0000000008008f7c ADC_IRQHandler
- 0x0000000008008f7c CAN0_TX_IRQHandler
- 0x0000000008008f7c WWDGT_IRQHandler
- 0x0000000008008f7c EXMC_IRQHandler
- 0x0000000008008f7c TAMPER_STAMP_IRQHandler
- 0x0000000008008f7c RTC_WKUP_IRQHandler
- 0x0000000008008f7c SPI2_IRQHandler
- 0x0000000008008f7c MemManage_Handler
- 0x0000000008008f7c CAN1_TX_IRQHandler
- 0x0000000008008f7c SVC_Handler
- 0x0000000008008f7c RCU_CTC_IRQHandler
- 0x0000000008008f7c DMA1_Channel5_IRQHandler
- 0x0000000008008f7c EXTI4_IRQHandler
- 0x0000000008008f7c CAN0_RX1_IRQHandler
- 0x0000000008008f7c DMA0_Channel5_IRQHandler
- 0x0000000008008f7c DMA1_Channel3_IRQHandler
- 0x0000000008008f7c EXTI5_9_IRQHandler
- 0x0000000008008f7c DMA0_Channel1_IRQHandler
- 0x0000000008008f7c TIMER0_Channel_IRQHandler
- 0x0000000008008f7c EXTI1_IRQHandler
- 0x0000000008008f7c ENET_WKUP_IRQHandler
- 0x0000000008008f7c USBHS_EP1_In_IRQHandler
- 0x0000000008008f7c SPI0_IRQHandler
- 0x0000000008008f7c CAN0_EWMC_IRQHandler
- 0x0000000008008f7c CAN0_RX0_IRQHandler
- 0x0000000008008f7c I2C2_ER_IRQHandler
- 0x0000000008008f7c DMA1_Channel2_IRQHandler
- 0x0000000008008f7c BusFault_Handler
- 0x0000000008008f7c USART1_IRQHandler
- 0x0000000008008f7c UART3_IRQHandler
- 0x0000000008008f7c I2C1_ER_IRQHandler
- 0x0000000008008f7c FMC_IRQHandler
- 0x0000000008008f7c USBHS_WKUP_IRQHandler
- 0x0000000008008f7c DMA0_Channel4_IRQHandler
- 0x0000000008008f7c TRNG_IRQHandler
- 0x0000000008008f7c ENET_IRQHandler
- 0x0000000008008f7c RTC_Alarm_IRQHandler
- .text._ZN12dmxconfigudpL4atoiEPKcm
- 0x0000000008008f7e 0x24 build_gd32/firmware/main.o
+ 0x08009044 0x2 build_gd32/startup_gd32f407.o
+ 0x08009044 USBHS_EP1_Out_IRQHandler
+ 0x08009044 EXTI2_IRQHandler
+ 0x08009044 TIMER2_IRQHandler
+ 0x08009044 DebugMon_Handler
+ 0x08009044 LVD_IRQHandler
+ 0x08009044 CAN1_EWMC_IRQHandler
+ 0x08009044 TIMER7_UP_TIMER12_IRQHandler
+ 0x08009044 SDIO_IRQHandler
+ 0x08009044 PendSV_Handler
+ 0x08009044 NMI_Handler
+ 0x08009044 EXTI3_IRQHandler
+ 0x08009044 DCI_IRQHandler
+ 0x08009044 USBFS_WKUP_IRQHandler
+ 0x08009044 USBHS_IRQHandler
+ 0x08009044 TIMER5_DAC_IRQHandler
+ 0x08009044 TIMER0_TRG_CMT_TIMER10_IRQHandler
+ 0x08009044 USBFS_IRQHandler
+ 0x08009044 TIMER3_IRQHandler
+ 0x08009044 DMA0_Channel6_IRQHandler
+ 0x08009044 I2C0_EV_IRQHandler
+ 0x08009044 EXTI0_IRQHandler
+ 0x08009044 I2C2_EV_IRQHandler
+ 0x08009044 CAN1_RX0_IRQHandler
+ 0x08009044 FPU_IRQHandler
+ 0x08009044 TIMER7_TRG_CMT_TIMER13_IRQHandler
+ 0x08009044 UsageFault_Handler
+ 0x08009044 SPI1_IRQHandler
+ 0x08009044 DMA0_Channel0_IRQHandler
+ 0x08009044 TIMER0_BRK_TIMER8_IRQHandler
+ 0x08009044 DMA1_Channel0_IRQHandler
+ 0x08009044 TIMER7_BRK_TIMER11_IRQHandler
+ 0x08009044 DMA1_Channel4_IRQHandler
+ 0x08009044 I2C0_ER_IRQHandler
+ 0x08009044 TIMER0_UP_TIMER9_IRQHandler
+ 0x08009044 DMA1_Channel7_IRQHandler
+ 0x08009044 CAN1_RX1_IRQHandler
+ 0x08009044 DMA0_Channel2_IRQHandler
+ 0x08009044 I2C1_EV_IRQHandler
+ 0x08009044 UART4_IRQHandler
+ 0x08009044 EXTI10_15_IRQHandler
+ 0x08009044 DMA1_Channel1_IRQHandler
+ 0x08009044 Default_Handler
+ 0x08009044 TIMER7_Channel_IRQHandler
+ 0x08009044 DMA0_Channel7_IRQHandler
+ 0x08009044 ADC_IRQHandler
+ 0x08009044 CAN0_TX_IRQHandler
+ 0x08009044 WWDGT_IRQHandler
+ 0x08009044 EXMC_IRQHandler
+ 0x08009044 TAMPER_STAMP_IRQHandler
+ 0x08009044 RTC_WKUP_IRQHandler
+ 0x08009044 SPI2_IRQHandler
+ 0x08009044 MemManage_Handler
+ 0x08009044 CAN1_TX_IRQHandler
+ 0x08009044 SVC_Handler
+ 0x08009044 RCU_CTC_IRQHandler
+ 0x08009044 DMA1_Channel5_IRQHandler
+ 0x08009044 EXTI4_IRQHandler
+ 0x08009044 CAN0_RX1_IRQHandler
+ 0x08009044 DMA0_Channel5_IRQHandler
+ 0x08009044 DMA1_Channel3_IRQHandler
+ 0x08009044 EXTI5_9_IRQHandler
+ 0x08009044 DMA0_Channel1_IRQHandler
+ 0x08009044 TIMER0_Channel_IRQHandler
+ 0x08009044 EXTI1_IRQHandler
+ 0x08009044 ENET_WKUP_IRQHandler
+ 0x08009044 USBHS_EP1_In_IRQHandler
+ 0x08009044 SPI0_IRQHandler
+ 0x08009044 CAN0_EWMC_IRQHandler
+ 0x08009044 CAN0_RX0_IRQHandler
+ 0x08009044 I2C2_ER_IRQHandler
+ 0x08009044 DMA1_Channel2_IRQHandler
+ 0x08009044 BusFault_Handler
+ 0x08009044 USART1_IRQHandler
+ 0x08009044 UART3_IRQHandler
+ 0x08009044 I2C1_ER_IRQHandler
+ 0x08009044 FMC_IRQHandler
+ 0x08009044 USBHS_WKUP_IRQHandler
+ 0x08009044 DMA0_Channel4_IRQHandler
+ 0x08009044 TRNG_IRQHandler
+ 0x08009044 ENET_IRQHandler
+ 0x08009044 RTC_Alarm_IRQHandler
+ .text.HardFault_Handler
+ 0x08009046 0x16 build_gd32/hardfault_handler.o
+ 0x08009046 HardFault_Handler
+ .text.hardfault_handler
+ 0x0800905c 0x114 build_gd32/hardfault_handler.o
+ 0x0800905c hardfault_handler
+ .text._ZN8LightSet18SetDmxStartAddressEt
+ 0x08009170 0x4 build_gd32/firmware/main.o
+ 0x08009170 LightSet::SetDmxStartAddress(unsigned short)
+ .text._ZN8LightSet18GetDmxStartAddressEv
+ 0x08009174 0x4 build_gd32/firmware/main.o
+ 0x08009174 LightSet::GetDmxStartAddress()
+ .text._ZN8LightSet15GetDmxFootprintEv
+ 0x08009178 0x6 build_gd32/firmware/main.o
+ 0x08009178 LightSet::GetDmxFootprint()
+ .text._ZN8LightSet11GetSlotInfoEtRN8lightset8SlotInfoE
+ 0x0800917e 0xa build_gd32/firmware/main.o
+ 0x0800917e LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&)
+ .text._ZN7DmxSend14GetRefreshRateEv
+ 0x08009188 0x18 build_gd32/firmware/main.o
+ 0x08009188 DmxSend::GetRefreshRate()
+ .text._ZN7DmxSendD2Ev
+ 0x080091a0 0x2 build_gd32/firmware/main.o
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.text._ZN7Display12SetCursorPosEmm.isra.0
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.text._ZN7Display8SetSleepEb
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.text._ZN10E131Bridge3RunEv
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.text._ZN8Hardware13RebootHandlerEv
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.text.startup.main
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.text._ZN12RemoteConfig16HandleDisplayGetEv
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.text._ZN12RemoteConfig12HandleUptimeEv
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.text._ZN12RemoteConfig16HandleDisplaySetEv
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.text._ZN12RemoteConfig13HandleTftpSetEv
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.text._ZN12RemoteConfigC2EN12remoteconfig4NodeENS0_6OutputEm
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.text._ZNK12RemoteConfig13GetStringNodeEv
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.text._ZNK12RemoteConfig15GetStringOutputEv
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.text._ZN12RemoteConfig10SetDisableEb
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.text._ZN12RemoteConfig14SetDisplayNameEPKc
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.text._ZN12RemoteConfig9HandleGetEPvm
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.text._ZN12RemoteConfig17HandleGetNoParamsEv
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.text._ZN12RemoteConfig19HandleGetRconfigTxtERm
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.text._ZN12RemoteConfig19HandleGetNetworkTxtERm
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.text._ZN12RemoteConfig18HandleGetArtnetTxtERm
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.text._ZN12RemoteConfig18HandleGetParamsTxtERm
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.text._ZN12RemoteConfig19HandleGetDisplayTxtERm
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.text._ZN12RemoteConfig9HandleSetEPvm
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.text._ZN12RemoteConfig13HandleRequestEv
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.text._ZN12RemoteConfig19HandleSetNetworkTxtEv
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.text._ZN12RemoteConfig18HandleSetArtnetTxtEv
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.text._ZN12RemoteConfig18HandleSetParamsTxtEv
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.text._ZN12RemoteConfig19HandleSetDisplayTxtEv
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.text._ZN12RemoteConfig13HandleFactoryEv
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.text._ZN18RemoteConfigParams4LoadEv
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.text._ZN18RemoteConfigParams4LoadEPKcm
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.text._ZN18RemoteConfigParams7SetBoolEhm
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.text._ZN18RemoteConfigParams16callbackFunctionEPKc
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.text._ZN18RemoteConfigParams22staticCallbackFunctionEPvPKc
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+ .text._ZN18RemoteConfigParams7BuilderEPKN18remoteconfigparams6ParamsEPcmRm
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+ 0x0800a418 RemoteConfigParams::Builder(remoteconfigparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN18RemoteConfigParams3SetEP12RemoteConfig
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+ .text._ZN7Display10TextStatusEPKc
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.text._ZN12RemoteConfig12HandleRebootEv
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- 0x000000000800abb8 RemoteConfig::HandleReboot()
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+ 0x0800a600 RemoteConfig::HandleReboot()
.text._ZN12RemoteConfig8GetIndexEPKvRm
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+ 0x0800a660 RemoteConfig::GetIndex(void const*, unsigned long&)
.text._ZN12RemoteConfig21PlatformHandleTftpSetEv
- 0x000000000800aca4 0x40 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800aca4 RemoteConfig::PlatformHandleTftpSet()
+ 0x0800a6b8 0x48 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a6b8 RemoteConfig::PlatformHandleTftpSet()
.text._ZN12RemoteConfig21PlatformHandleTftpGetEv
- 0x000000000800ace4 0x1a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800ace4 RemoteConfig::PlatformHandleTftpGet()
- .text.strcmp 0x000000000800acfe 0x1a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800acfe strcmp
- .text.strcasecmp
- 0x000000000800ad18 0x34 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800ad18 strcasecmp
- .text._ZN16PropertiesConfig10EnableJSONEb
- 0x000000000800ad4c 0x18 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800ad4c PropertiesConfig::EnableJSON(bool)
+ 0x0800a700 0x1a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a700 RemoteConfig::PlatformHandleTftpGet()
+ *fill* 0x0800a71a 0x2
.text._ZN10HttpDaemonC2Ev
- 0x000000000800ad64 0x3c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800ad64 HttpDaemon::HttpDaemon()
- 0x000000000800ad64 HttpDaemon::HttpDaemon()
- .text._ZN10HttpDaemon11ParseMethodEPc
- 0x000000000800ada0 0x8c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800ada0 HttpDaemon::ParseMethod(char*)
- .text._ZN10HttpDaemon16ParseHeaderFieldEPc
- 0x000000000800ae2c 0x90 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800ae2c HttpDaemon::ParseHeaderField(char*)
- .text._ZN10HttpDaemon12ParseRequestEv
- 0x000000000800aebc 0x6a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800aebc HttpDaemon::ParseRequest()
- *fill* 0x000000000800af26 0x2
- .text._ZN10HttpDaemon12HandleGetTxtEv
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- .text._ZN10HttpDaemon9HandleGetEv
- 0x000000000800afb0 0x110 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800afb0 HttpDaemon::HandleGet()
- .text._ZN10HttpDaemon10HandlePostEb
- 0x000000000800b0c0 0x15c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b0c0 HttpDaemon::HandlePost(bool)
- .text._ZN10HttpDaemon13HandleRequestEm
- 0x000000000800b21c 0x140 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b21c HttpDaemon::HandleRequest(unsigned long)
- .text._ZN12remoteconfig13json_get_listEPct
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- 0x000000000800b35c remoteconfig::json_get_list(char*, unsigned short)
- .text._ZN12remoteconfig16json_get_versionEPct
- 0x000000000800b3bc 0x38 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b3bc remoteconfig::json_get_version(char*, unsigned short)
- .text._ZN12remoteconfig15json_get_uptimeEPct
- 0x000000000800b3f4 0x20 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b3f4 remoteconfig::json_get_uptime(char*, unsigned short)
- .text._ZN12remoteconfig16json_get_displayEPct
- 0x000000000800b414 0x20 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b414 remoteconfig::json_get_display(char*, unsigned short)
- .text._ZN12remoteconfig18json_get_directoryEPct
- 0x000000000800b434 0x10 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b434 remoteconfig::json_get_directory(char*, unsigned short)
- .text._Z16get_file_contentPKcPcRN4http12contentTypesE
- 0x000000000800b444 0x4c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
- 0x000000000800b444 get_file_content(char const*, char*, http::contentTypes&)
+ 0x0800a71c 0x6c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o)
+ 0x0800a71c HttpDaemon::HttpDaemon()
+ 0x0800a71c HttpDaemon::HttpDaemon()
+ .text._ZN10DisplaySet8SetSleepEb
+ 0x0800a788 0x4 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a788 DisplaySet::SetSleep(bool)
+ .text._ZN23HttpDeamonHandleRequest11ParseMethodEPc
+ 0x0800a78c 0xc8 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a78c HttpDeamonHandleRequest::ParseMethod(char*)
+ .text._ZN23HttpDeamonHandleRequest16ParseHeaderFieldEPc
+ 0x0800a854 0x124 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a854 HttpDeamonHandleRequest::ParseHeaderField(char*)
+ .text._ZN23HttpDeamonHandleRequest12ParseRequestEv
+ 0x0800a978 0x7c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a978 HttpDeamonHandleRequest::ParseRequest()
+ .text._ZN23HttpDeamonHandleRequest12HandleGetTxtEv
+ 0x0800a9f4 0x9c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a9f4 HttpDeamonHandleRequest::HandleGetTxt()
+ .text._ZN23HttpDeamonHandleRequest9HandleGetEv
+ 0x0800aa90 0x2e4 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800aa90 HttpDeamonHandleRequest::HandleGet()
+ .text._ZN23HttpDeamonHandleRequest10HandlePostEb
+ 0x0800ad74 0x1fc ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800ad74 HttpDeamonHandleRequest::HandlePost(bool)
+ .text._ZN23HttpDeamonHandleRequest13HandleRequestEmPc
+ 0x0800af70 0x170 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800af70 HttpDeamonHandleRequest::HandleRequest(unsigned long, char*)
+ .text._ZN12remoteconfig13json_get_listEPcm
+ 0x0800b0e0 0x64 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b0e0 remoteconfig::json_get_list(char*, unsigned long)
+ .text._ZN12remoteconfig16json_get_versionEPcm
+ 0x0800b144 0x38 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b144 remoteconfig::json_get_version(char*, unsigned long)
+ .text._ZN12remoteconfig15json_get_uptimeEPcm
+ 0x0800b17c 0x14 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b17c remoteconfig::json_get_uptime(char*, unsigned long)
+ .text._ZN12remoteconfig16json_get_displayEPcm
+ 0x0800b190 0x18 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b190 remoteconfig::json_get_display(char*, unsigned long)
+ .text._ZN12remoteconfig18json_get_directoryEPcm
+ 0x0800b1a8 0xc ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b1a8 remoteconfig::json_get_directory(char*, unsigned long)
+ .text._Z16get_file_contentPKcRmRN4http12contentTypesE
+ 0x0800b1b4 0x40 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
+ 0x0800b1b4 get_file_content(char const*, unsigned long&, http::contentTypes&)
.text.strncpy.isra.0
- 0x000000000800b490 0x22 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- *fill* 0x000000000800b4b2 0x2
- .text._ZN8lightset4Data11ClearLengthEm
- 0x000000000800b4b4 0x28 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b4b4 lightset::Data::ClearLength(unsigned long)
- .text._ZN10ArtNetNode14SetOutputStyleEmN8lightset11OutputStyleE
- 0x000000000800b4dc 0xa6 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b4dc ArtNetNode::SetOutputStyle(unsigned long, lightset::OutputStyle)
- *fill* 0x000000000800b582 0x2
- .text._ZN10ArtNetNode5StartEv
- 0x000000000800b584 0x120 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b584 ArtNetNode::Start()
+ 0x0800b1f4 0x22 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ *fill* 0x0800b216 0x2
+ .text._ZN11ArtNetStore15SaveOutputStyleEmN8lightset11OutputStyleE
+ 0x0800b218 0x68 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b218 ArtNetStore::SaveOutputStyle(unsigned long, lightset::OutputStyle)
.text._ZN10ArtNetNode4StopEv
- 0x000000000800b6a4 0x90 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b6a4 ArtNetNode::Stop()
+ 0x0800b280 0x9c ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b280 ArtNetNode::Stop()
.text._ZN10ArtNetNode12SetShortNameEmPKc
- 0x000000000800b734 0x58 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b734 ArtNetNode::SetShortName(unsigned long, char const*)
+ 0x0800b31c 0x7c ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b31c ArtNetNode::SetShortName(unsigned long, char const*)
.text._ZN10ArtNetNode18GetLongNameDefaultEPc
- 0x000000000800b78c 0x30 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b78c ArtNetNode::GetLongNameDefault(char*)
+ 0x0800b398 0x30 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b398 ArtNetNode::GetLongNameDefault(char*)
.text._ZN10ArtNetNode11SetLongNameEPKc
- 0x000000000800b7bc 0x42 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b7bc ArtNetNode::SetLongName(char const*)
- *fill* 0x000000000800b7fe 0x2
+ 0x0800b3c8 0x54 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b3c8 ArtNetNode::SetLongName(char const*)
.text._ZN10ArtNetNodeC2Ev
- 0x000000000800b800 0x1dc ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b800 ArtNetNode::ArtNetNode()
- 0x000000000800b800 ArtNetNode::ArtNetNode()
+ 0x0800b41c 0x1ec ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b41c ArtNetNode::ArtNetNode()
+ 0x0800b41c ArtNetNode::ArtNetNode()
+ .text._ZNK10ArtNetNode14GetOutputStyleEm
+ 0x0800b608 0x10 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b608 ArtNetNode::GetOutputStyle(unsigned long) const
+ .text._ZN10ArtNetNode14SetOutputStyleEmN8lightset11OutputStyleE
+ 0x0800b618 0x78 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b618 ArtNetNode::SetOutputStyle(unsigned long, lightset::OutputStyle)
+ .text._ZN10ArtNetNode5StartEv
+ 0x0800b690 0x108 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b690 ArtNetNode::Start()
.text._ZN10ArtNetNode27SetNetworkDataLossConditionEv
- 0x000000000800b9dc 0x8c ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800b9dc ArtNetNode::SetNetworkDataLossCondition()
- .text._ZN10ArtNetNode7ProcessEt
- 0x000000000800ba68 0x278 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800ba68 ArtNetNode::Process(unsigned short)
- .text._ZN8lightset4Data11OutputClearEP8LightSetm
- 0x000000000800bce0 0x58 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bce0 lightset::Data::OutputClear(LightSet*, unsigned long)
- .text._ZN10ArtNetNode15SetLocalMergingEv
- 0x000000000800bd38 0x78 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bd38 ArtNetNode::SetLocalMerging()
+ 0x0800b798 0x90 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b798 ArtNetNode::SetNetworkDataLossCondition()
+ .text._ZN10ArtNetNode7ProcessEm
+ 0x0800b828 0x280 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800b828 ArtNetNode::Process(unsigned long)
+ .text._ZN8lightset4Data12IOutputClearEP8LightSetm
+ 0x0800baa8 0x42 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800baa8 lightset::Data::IOutputClear(LightSet*, unsigned long)
.text._ZN10ArtNetNode15MakePortAddressEtm
- 0x000000000800bdb0 0x24 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bdb0 ArtNetNode::MakePortAddress(unsigned short, unsigned long)
+ 0x0800baea 0x24 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800baea ArtNetNode::MakePortAddress(unsigned short, unsigned long)
+ *fill* 0x0800bb0e 0x2
+ .text._ZN11ArtNetStore13SaveMergeModeEmN8lightset9MergeModeE
+ 0x0800bb10 0x70 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bb10 ArtNetStore::SaveMergeMode(unsigned long, lightset::MergeMode)
+ .text._ZN11ArtNetStore12SaveUniverseEm
+ 0x0800bb80 0x5c ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bb80 ArtNetStore::SaveUniverse(unsigned long)
+ .text._ZN10ArtNetNode15SetLocalMergingEv
+ 0x0800bbdc 0x70 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bbdc ArtNetNode::SetLocalMerging()
.text._ZN10ArtNetNode17SetUniverseSwitchEmN8lightset7PortDirEh
- 0x000000000800bdd4 0x124 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bdd4 ArtNetNode::SetUniverseSwitch(unsigned long, lightset::PortDir, unsigned char)
+ 0x0800bc4c 0x11a ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bc4c ArtNetNode::SetUniverseSwitch(unsigned long, lightset::PortDir, unsigned char)
.text._ZN10ArtNetNode11SetUniverseEmN8lightset7PortDirEt
- 0x000000000800bef8 0x22 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bef8 ArtNetNode::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
+ 0x0800bd66 0x22 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bd66 ArtNetNode::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
.text._ZN10ArtNetNode15SetSubnetSwitchEmh
- 0x000000000800bf1a 0x42 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bf1a ArtNetNode::SetSubnetSwitch(unsigned long, unsigned char)
+ 0x0800bd88 0x2e ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bd88 ArtNetNode::SetSubnetSwitch(unsigned long, unsigned char)
.text._ZN10ArtNetNode12SetNetSwitchEmh
- 0x000000000800bf5c 0x42 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bf5c ArtNetNode::SetNetSwitch(unsigned long, unsigned char)
+ 0x0800bdb6 0x2e ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bdb6 ArtNetNode::SetNetSwitch(unsigned long, unsigned char)
.text._ZN10ArtNetNode12SetMergeModeEmN8lightset9MergeModeE
- 0x000000000800bf9e 0x4c ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bf9e ArtNetNode::SetMergeMode(unsigned long, lightset::MergeMode)
+ 0x0800bde4 0x4c ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800bde4 ArtNetNode::SetMergeMode(unsigned long, lightset::MergeMode)
.text._ZN10ArtNetNode11SetFailSafeEN10artnetnode8FailSafeE
- 0x000000000800bfea 0x6a ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800bfea ArtNetNode::SetFailSafe(artnetnode::FailSafe)
+ 0x0800be30 0x88 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800be30 ArtNetNode::SetFailSafe(artnetnode::FailSafe)
.text._ZN10ArtNetNode13HandleAddressEv
- 0x000000000800c054 0x2d0 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
- 0x000000000800c054 ArtNetNode::HandleAddress()
- .text._ZN8lightset4Data13IMergeSourceAEmPKhmNS_9MergeModeE.part.0
- 0x000000000800c324 0x28 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- .text.memcpy.isra.0
- 0x000000000800c34c 0x14 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- .text._ZN8lightset4Data3GetEv
- 0x000000000800c360 0x18 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c360 lightset::Data::Get()
- .text._ZN8lightset4Data10SetSourceAEmPKhm
- 0x000000000800c378 0x3c ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c378 lightset::Data::SetSourceA(unsigned long, unsigned char const*, unsigned long)
- .text._ZN8lightset4Data12MergeSourceAEmPKhmNS_9MergeModeE
- 0x000000000800c3b4 0x52 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c3b4 lightset::Data::MergeSourceA(unsigned long, unsigned char const*, unsigned long, lightset::MergeMode)
- .text._ZN8lightset4Data12MergeSourceBEmPKhmNS_9MergeModeE
- 0x000000000800c406 0x54 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c406 lightset::Data::MergeSourceB(unsigned long, unsigned char const*, unsigned long, lightset::MergeMode)
- .text._ZN10ArtNetNode17UpdateMergeStatusEm
- 0x000000000800c45a 0x20 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c45a ArtNetNode::UpdateMergeStatus(unsigned long)
+ 0x0800beb8 0x2d8 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleaddress.o)
+ 0x0800beb8 ArtNetNode::HandleAddress()
.text._ZN10ArtNetNode18CheckMergeTimeoutsEm
- 0x000000000800c47a 0x66 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c47a ArtNetNode::CheckMergeTimeouts(unsigned long)
+ 0x0800c190 0x74 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
+ 0x0800c190 ArtNetNode::CheckMergeTimeouts(unsigned long)
.text._ZN10ArtNetNode9HandleDmxEv
- 0x000000000800c4e0 0x2dc ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
- 0x000000000800c4e0 ArtNetNode::HandleDmx()
+ 0x0800c204 0x694 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandledmx.o)
+ 0x0800c204 ArtNetNode::HandleDmx()
.text.memcpy.isra.0
- 0x000000000800c7bc 0x14 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
+ 0x0800c898 0x12 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
+ .text.memcmp 0x0800c8aa 0x20 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
+ 0x0800c8aa memcmp
+ *fill* 0x0800c8ca 0x2
.text._ZN10ArtNetNode12HandleIpProgEv
- 0x000000000800c7d0 0x198 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
- 0x000000000800c7d0 ArtNetNode::HandleIpProg()
+ 0x0800c8cc 0x1b8 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandleipprog.o)
+ 0x0800c8cc ArtNetNode::HandleIpProg()
.text._ZN10ArtNetNode17ProcessPollRelplyEmRmS0_
- 0x000000000800c968 0xbc ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
- 0x000000000800c968 ArtNetNode::ProcessPollRelply(unsigned long, unsigned long&, unsigned long&)
- .text._ZN10ArtNetNode14SendPollRelplyEmmPN10artnetnode12ArtPollQueueE
- 0x000000000800ca24 0x134 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
- 0x000000000800ca24 ArtNetNode::SendPollRelply(unsigned long, unsigned long, artnetnode::ArtPollQueue*)
+ 0x0800ca84 0xbe ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
+ 0x0800ca84 ArtNetNode::ProcessPollRelply(unsigned long, unsigned long&, unsigned long&)
+ *fill* 0x0800cb42 0x2
+ .text._ZN10ArtNetNode14SendPollRelplyEmmPN6artnet12ArtPollQueueE
+ 0x0800cb44 0x150 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
+ 0x0800cb44 ArtNetNode::SendPollRelply(unsigned long, unsigned long, artnet::ArtPollQueue*)
.text._ZN10ArtNetNode10HandlePollEv
- 0x000000000800cb58 0xc4 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
- 0x000000000800cb58 ArtNetNode::HandlePoll()
+ 0x0800cc94 0xc4 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlepoll.o)
+ 0x0800cc94 ArtNetNode::HandlePoll()
.text._ZN10ArtNetNode10HandleSyncEv
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- 0x000000000800cc1c ArtNetNode::HandleSync()
- *fill* 0x000000000800cc9e 0x2
+ 0x0800cd58 0x7a ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandlesync.o)
+ 0x0800cd58 ArtNetNode::HandleSync()
.text._ZN10ArtNetNode14HandleTimeSyncEv
- 0x000000000800cca0 0x3c ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandletimesync.o)
- 0x000000000800cca0 ArtNetNode::HandleTimeSync()
+ 0x0800cdd2 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetnodehandletimesync.o)
+ 0x0800cdd2 ArtNetNode::HandleTimeSync()
.text._ZN10ArtNetNode5PrintEv
- 0x000000000800ccdc 0x194 ../lib-artnet/lib_gd32/libartnet.a(artnetnodeprint.o)
- 0x000000000800ccdc ArtNetNode::Print()
- .text._ZN17PropertiesBuilder3AddIPKcEEbS2_T_bm.isra.0
- 0x000000000800ce70 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800cdd4 0x17c ../lib-artnet/lib_gd32/libartnet.a(artnetnodeprint.o)
+ 0x0800cdd4 ArtNetNode::Print()
+ .text._ZN17PropertiesBuilder3AddIPKcEEbS2_T_bi.isra.0
+ 0x0800cf50 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
.text._ZN17PropertiesBuilder3AddEPKcb.isra.0
- 0x000000000800cec0 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- .text._ZN12ArtNetParamsC2EP17ArtNetParamsStore
- 0x000000000800cf10 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800cf10 ArtNetParams::ArtNetParams(ArtNetParamsStore*)
- 0x000000000800cf10 ArtNetParams::ArtNetParams(ArtNetParamsStore*)
+ 0x0800cfa0 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ .text._ZN17ArtNetParamsStore4CopyEPN12artnetparams6ParamsE
+ 0x0800cff0 0x24 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800cff0 ArtNetParamsStore::Copy(artnetparams::Params*)
+ .text._ZN12ArtNetParamsC2Ev
+ 0x0800d014 0x4c ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d014 ArtNetParams::ArtNetParams()
+ 0x0800d014 ArtNetParams::ArtNetParams()
.text._ZN12ArtNetParams4LoadEv
- 0x000000000800cf60 0x18 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800cf60 ArtNetParams::Load()
+ 0x0800d060 0x14 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d060 ArtNetParams::Load()
.text._ZN12ArtNetParams4LoadEPKcm
- 0x000000000800cf78 0x3c ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800cf78 ArtNetParams::Load(char const*, unsigned long)
+ 0x0800d074 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d074 ArtNetParams::Load(char const*, unsigned long)
.text._ZN12ArtNetParams7SetBoolEhm
- 0x000000000800cfb4 0x10 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800cfb4 ArtNetParams::SetBool(unsigned char, unsigned long)
+ 0x0800d0c4 0x10 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d0c4 ArtNetParams::SetBool(unsigned char, unsigned long)
.text._ZN12ArtNetParams16callbackFunctionEPKc
- 0x000000000800cfc4 0x4bc ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800cfc4 ArtNetParams::callbackFunction(char const*)
+ 0x0800d0d4 0x4c8 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d0d4 ArtNetParams::callbackFunction(char const*)
.text._ZN12ArtNetParams22staticCallbackFunctionEPvPKc
- 0x000000000800d480 0x4 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800d480 ArtNetParams::staticCallbackFunction(void*, char const*)
+ 0x0800d59c 0x4 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d59c ArtNetParams::staticCallbackFunction(void*, char const*)
.text._ZN12ArtNetParams7BuilderEPKN12artnetparams6ParamsEPcmRm
- 0x000000000800d484 0x400 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800d484 ArtNetParams::Builder(artnetparams::Params const*, char*, unsigned long, unsigned long&)
- .text._ZN12ArtNetParams3SetEm
- 0x000000000800d884 0x15c ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x000000000800d884 ArtNetParams::Set(unsigned long)
- .text._ZN12ArtNetParams4DumpEv
- 0x000000000800d9e0 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetparamsdump.o)
- 0x000000000800d9e0 ArtNetParams::Dump()
- *fill* 0x000000000800d9e2 0x2
+ 0x0800d5a0 0x41c ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d5a0 ArtNetParams::Builder(artnetparams::Params const*, char*, unsigned long, unsigned long&)
+ .text._ZN12ArtNetParams3SetEv
+ 0x0800d9bc 0x158 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
+ 0x0800d9bc ArtNetParams::Set()
.text._ZN10ArtNetNode11HandleDmxInEv
- 0x000000000800d9e4 0x1f0 ../lib-artnet/lib_gd32/libartnet.a(handledmxin.o)
- 0x000000000800d9e4 ArtNetNode::HandleDmxIn()
+ 0x0800db14 0x240 ../lib-artnet/lib_gd32/libartnet.a(handledmxin.o)
+ 0x0800db14 ArtNetNode::HandleDmxIn()
.text._ZN10ArtNetNode11HandleInputEv
- 0x000000000800dbd4 0x60 ../lib-artnet/lib_gd32/libartnet.a(handleinput.o)
- 0x000000000800dbd4 ArtNetNode::HandleInput()
- .text._ZN10ArtNetNode6SetRmdEmb
- 0x000000000800dc34 0x4e ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800dc34 ArtNetNode::SetRmd(unsigned long, bool)
+ 0x0800dd54 0x60 ../lib-artnet/lib_gd32/libartnet.a(handleinput.o)
+ 0x0800dd54 ArtNetNode::HandleInput()
+ .text._ZN10ArtNetNode16HandleTodRequestEv
+ 0x0800ddb4 0x6a ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800ddb4 ArtNetNode::HandleTodRequest()
+ *fill* 0x0800de1e 0x2
+ .text._ZN11ArtNetStore14SaveRdmEnabledEmb
+ 0x0800de20 0x74 ../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ 0x0800de20 ArtNetStore::SaveRdmEnabled(unsigned long, bool)
+ .text._ZN10ArtNetNode6SetRdmEmb
+ 0x0800de94 0x4e ../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ 0x0800de94 ArtNetNode::SetRdm(unsigned long, bool)
+ *fill* 0x0800dee2 0x2
+ .text._ZL19respond_message_ackmP11TRdmMessage.constprop.0
+ 0x0800dee4 0x90 ../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o)
+ .text._ZN6RDMTodC2Ev
+ 0x0800df74 0x48 ../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o)
+ 0x0800df74 RDMTod::RDMTod()
+ 0x0800df74 RDMTod::RDMTod()
+ .text._ZN19ArtNetRdmController10RdmReceiveEmPKh
+ 0x0800dfbc 0x290 ../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o)
+ 0x0800dfbc ArtNetRdmController::RdmReceive(unsigned long, unsigned char const*)
+ .text.startup._GLOBAL__sub_I__ZN19ArtNetRdmController9m_pRDMTodE
+ 0x0800e24c 0x18 ../lib-artnet/lib_gd32/libartnet.a(artnetrdmcontroller.o)
+ .text.memcpy.isra.0
+ 0x0800e264 0x12 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ *fill* 0x0800e276 0x2
+ .text._ZN6RDMTod5ResetEv
+ 0x0800e278 0x3c ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e278 RDMTod::Reset()
+ .text._ZN3Rdm7SendRawEmPKhm
+ 0x0800e2b4 0x40 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e2b4 Rdm::SendRaw(unsigned long, unsigned char const*, unsigned long)
+ .text._ZN10ArtNetNode16HandleTodControlEv
+ 0x0800e2f4 0xd0 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e2f4 ArtNetNode::HandleTodControl()
.text._ZN10ArtNetNode13HandleTodDataEv
- 0x000000000800dc82 0x5a ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800dc82 ArtNetNode::HandleTodData()
+ 0x0800e3c4 0xbc ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e3c4 ArtNetNode::HandleTodData()
.text._ZN10ArtNetNode7SendTodEm
- 0x000000000800dcdc 0xdc ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800dcdc ArtNetNode::SendTod(unsigned long)
- .text._ZN10ArtNetNode16HandleTodControlEv
- 0x000000000800ddb8 0x8e ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800ddb8 ArtNetNode::HandleTodControl()
- .text._ZN10ArtNetNode16HandleTodRequestEv
- 0x000000000800de46 0x6a ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800de46 ArtNetNode::HandleTodRequest()
+ 0x0800e480 0xe4 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e480 ArtNetNode::SendTod(unsigned long)
.text._ZN10ArtNetNode14SendTodRequestEm
- 0x000000000800deb0 0xa4 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800deb0 ArtNetNode::SendTodRequest(unsigned long)
- .text._ZN10ArtNetNode13SetRdmHandlerEP9ArtNetRdmb
- 0x000000000800df54 0x1e ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800df54 ArtNetNode::SetRdmHandler(ArtNetRdm*, bool)
+ 0x0800e564 0xa0 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e564 ArtNetNode::SendTodRequest(unsigned long)
.text._ZN10ArtNetNode9HandleRdmEv
- 0x000000000800df72 0x10c ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
- 0x000000000800df72 ArtNetNode::HandleRdm()
- *fill* 0x000000000800e07e 0x2
+ 0x0800e604 0xaa ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0800e604 ArtNetNode::HandleRdm()
+ *fill* 0x0800e6ae 0x2
.text._ZN10ArtNetNode11HandleRdmInEv
- 0x000000000800e080 0xa4 ../lib-artnet/lib_gd32/libartnet.a(handlerdmin.o)
- 0x000000000800e080 ArtNetNode::HandleRdmIn()
+ 0x0800e6b0 0x154 ../lib-artnet/lib_gd32/libartnet.a(handlerdmin.o)
+ 0x0800e6b0 ArtNetNode::HandleRdmIn()
+ .text._ZN10ArtNetNode12HandleRdmSubEv
+ 0x0800e804 0x2 ../lib-artnet/lib_gd32/libartnet.a(handlerdmsub.o)
+ 0x0800e804 ArtNetNode::HandleRdmSub()
+ *fill* 0x0800e806 0x2
+ .text._ZN12remoteconfig3rdm19json_get_portstatusEPcm
+ 0x0800e808 0x100 ../lib-artnet/lib_gd32/libartnet.a(json_get_portstatus.o)
+ 0x0800e808 remoteconfig::rdm::json_get_portstatus(char*, unsigned long)
+ .text._ZN12remoteconfig3rdm14json_get_queueEPcm
+ 0x0800e908 0x40 ../lib-artnet/lib_gd32/libartnet.a(json_get_queue.o)
+ 0x0800e908 remoteconfig::rdm::json_get_queue(char*, unsigned long)
+ .text._ZN12remoteconfig3rdm12json_get_rdmEPcm
+ 0x0800e948 0x18 ../lib-artnet/lib_gd32/libartnet.a(json_get_rdm.o)
+ 0x0800e948 remoteconfig::rdm::json_get_rdm(char*, unsigned long)
+ .text._ZN12remoteconfig3rdm12json_get_todEcPcm
+ 0x0800e960 0xe0 ../lib-artnet/lib_gd32/libartnet.a(json_get_tod.o)
+ 0x0800e960 remoteconfig::rdm::json_get_tod(char, char*, unsigned long)
+ .text._ZN10ArtNetNode16SetRdmControllerEP19ArtNetRdmControllerb
+ 0x0800ea40 0x36 ../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ 0x0800ea40 ArtNetNode::SetRdmController(ArtNetRdmController*, bool)
+ .text._ZN10ArtNetNode6SetRdmEb
+ 0x0800ea76 0xe ../lib-artnet/lib_gd32/libartnet.a(setrdm.o)
+ 0x0800ea76 ArtNetNode::SetRdm(bool)
.text._ZN10ArtNetNode14FailSafeRecordEv
- 0x000000000800e124 0x3c ../lib-artnet/lib_gd32/libartnet.a(artnetnodefailsafe.o)
- 0x000000000800e124 ArtNetNode::FailSafeRecord()
+ 0x0800ea84 0x38 ../lib-artnet/lib_gd32/libartnet.a(artnetnodefailsafe.o)
+ 0x0800ea84 ArtNetNode::FailSafeRecord()
.text._ZN10ArtNetNode16FailSafePlaybackEv
- 0x000000000800e160 0x9a ../lib-artnet/lib_gd32/libartnet.a(artnetnodefailsafe.o)
- 0x000000000800e160 ArtNetNode::FailSafePlayback()
+ 0x0800eabc 0x80 ../lib-artnet/lib_gd32/libartnet.a(artnetnodefailsafe.o)
+ 0x0800eabc ArtNetNode::FailSafePlayback()
+ .text._ZN11ArtNetStore16SavePortProtocolEmN6artnet12PortProtocolE
+ 0x0800eb3c 0x70 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800eb3c ArtNetStore::SavePortProtocol(unsigned long, artnet::PortProtocol)
.text._ZN10ArtNetNode16SetPortProtocol4EmN6artnet12PortProtocolE
- 0x000000000800e1fa 0x50 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800e1fa ArtNetNode::SetPortProtocol4(unsigned long, artnet::PortProtocol)
+ 0x0800ebac 0x52 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800ebac ArtNetNode::SetPortProtocol4(unsigned long, artnet::PortProtocol)
.text._ZN10ArtNetNode12SetUniverse4EmN8lightset7PortDirE
- 0x000000000800e24a 0x5c ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800e24a ArtNetNode::SetUniverse4(unsigned long, lightset::PortDir)
- *fill* 0x000000000800e2a6 0x2
+ 0x0800ebfe 0x58 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800ebfe ArtNetNode::SetUniverse4(unsigned long, lightset::PortDir)
+ *fill* 0x0800ec56 0x2
.text._ZN10ArtNetNode16SetLedBlinkMode4EN8hardware8ledblink4ModeE
- 0x000000000800e2a8 0x34 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800e2a8 ArtNetNode::SetLedBlinkMode4(hardware::ledblink::Mode)
+ 0x0800ec58 0x34 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800ec58 ArtNetNode::SetLedBlinkMode4(hardware::ledblink::Mode)
.text._ZN10ArtNetNode14GetGoodOutput4Em
- 0x000000000800e2dc 0x2e ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
- 0x000000000800e2dc ArtNetNode::GetGoodOutput4(unsigned long)
- *fill* 0x000000000800e30a 0x2
+ 0x0800ec8c 0x2c ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
+ 0x0800ec8c ArtNetNode::GetGoodOutput4(unsigned long)
.text._ZN10artnetnodeL16check_have_flashEv
- 0x000000000800e30c 0x40 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ecb8 0x44 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
.text._ZN10artnetnode20failsafe_write_startEv
- 0x000000000800e34c 0x2c ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e34c artnetnode::failsafe_write_start()
+ 0x0800ecfc 0x2c ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ecfc artnetnode::failsafe_write_start()
.text._ZN10artnetnode14failsafe_writeEmPKh
- 0x000000000800e378 0x24 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e378 artnetnode::failsafe_write(unsigned long, unsigned char const*)
+ 0x0800ed28 0x24 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ed28 artnetnode::failsafe_write(unsigned long, unsigned char const*)
.text._ZN10artnetnode18failsafe_write_endEv
- 0x000000000800e39c 0x2 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e39c artnetnode::failsafe_write_end()
- *fill* 0x000000000800e39e 0x2
+ 0x0800ed4c 0x2 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ed4c artnetnode::failsafe_write_end()
+ *fill* 0x0800ed4e 0x2
.text._ZN10artnetnode19failsafe_read_startEv
- 0x000000000800e3a0 0x14 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e3a0 artnetnode::failsafe_read_start()
+ 0x0800ed50 0x14 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ed50 artnetnode::failsafe_read_start()
.text._ZN10artnetnode13failsafe_readEmPh
- 0x000000000800e3b4 0x24 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e3b4 artnetnode::failsafe_read(unsigned long, unsigned char*)
+ 0x0800ed64 0x24 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ed64 artnetnode::failsafe_read(unsigned long, unsigned char*)
.text._ZN10artnetnode17failsafe_read_endEv
- 0x000000000800e3d8 0x2 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
- 0x000000000800e3d8 artnetnode::failsafe_read_end()
- .text.memset.isra.0
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- .text.memcpy.isra.0
- 0x000000000800e3e8 0x14 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ed88 0x2 ../lib-artnet/lib_gd32/libartnet.a(failsafe.o)
+ 0x0800ed88 artnetnode::failsafe_read_end()
+ *fill* 0x0800ed8a 0x2
+ .text._ZN8LightSet8BlackoutEb
+ 0x0800ed8c 0x4 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ed8c LightSet::Blackout(bool)
+ .text._ZN8LightSet6FullOnEv
+ 0x0800ed90 0x4 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ed90 LightSet::FullOn()
.text._ZN10E131BridgeC2Ev
- 0x000000000800e3fc 0xe8 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e3fc E131Bridge::E131Bridge()
- 0x000000000800e3fc E131Bridge::E131Bridge()
+ 0x0800ed94 0x110 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ed94 E131Bridge::E131Bridge()
+ 0x0800ed94 E131Bridge::E131Bridge()
.text._ZN10E131Bridge4StopEv
- 0x000000000800e4e4 0x78 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e4e4 E131Bridge::Stop()
- .text._ZN10E131Bridge13LeaveUniverseEmt
- 0x000000000800e55c 0x2e ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e55c E131Bridge::LeaveUniverse(unsigned long, unsigned short)
+ 0x0800eea4 0x84 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800eea4 E131Bridge::Stop()
.text._ZN10E131Bridge25SetSynchronizationAddressEbbt
- 0x000000000800e58a 0x44 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e58a E131Bridge::SetSynchronizationAddress(bool, bool, unsigned short)
- *fill* 0x000000000800e5ce 0x2
+ 0x0800ef28 0x50 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ef28 E131Bridge::SetSynchronizationAddress(bool, bool, unsigned short)
.text._ZN10E131Bridge15SetLocalMergingEv
- 0x000000000800e5d0 0x78 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e5d0 E131Bridge::SetLocalMerging()
+ 0x0800ef78 0x7c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800ef78 E131Bridge::SetLocalMerging()
.text._ZN10E131Bridge5StartEv
- 0x000000000800e648 0xe8 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e648 E131Bridge::Start()
+ 0x0800eff4 0xb0 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800eff4 E131Bridge::Start()
.text._ZN10E131Bridge11SetUniverseEmN8lightset7PortDirEt
- 0x000000000800e730 0xe6 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e730 E131Bridge::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
- .text._ZN10E131Bridge17UpdateMergeStatusEm
- 0x000000000800e816 0x1e ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e816 E131Bridge::UpdateMergeStatus(unsigned long)
+ 0x0800f0a4 0x108 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f0a4 E131Bridge::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
.text._ZN10E131Bridge18CheckMergeTimeoutsEm
- 0x000000000800e834 0x72 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e834 E131Bridge::CheckMergeTimeouts(unsigned long)
+ 0x0800f1ac 0x7c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f1ac E131Bridge::CheckMergeTimeouts(unsigned long)
.text._ZNK10E131Bridge17IsPriorityTimeOutEm
- 0x000000000800e8a6 0x4a ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e8a6 E131Bridge::IsPriorityTimeOut(unsigned long) const
- .text._ZNK10E131Bridge12isIpCidMatchEPKN10e131bridge6SourceE
- 0x000000000800e8f0 0x30 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e8f0 E131Bridge::isIpCidMatch(e131bridge::Source const*) const
+ 0x0800f228 0x44 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f228 E131Bridge::IsPriorityTimeOut(unsigned long) const
.text._ZN10E131Bridge27SetNetworkDataLossConditionEbb
- 0x000000000800e920 0x14c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800e920 E131Bridge::SetNetworkDataLossCondition(bool, bool)
+ 0x0800f26c 0x128 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f26c E131Bridge::SetNetworkDataLossCondition(bool, bool)
.text._ZN10E131Bridge9HandleDmxEv
- 0x000000000800ea6c 0x342 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800ea6c E131Bridge::HandleDmx()
- *fill* 0x000000000800edae 0x2
+ 0x0800f394 0x63c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f394 E131Bridge::HandleDmx()
.text._ZN10E131Bridge11IsValidRootEv
- 0x000000000800edb0 0x40 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800edb0 E131Bridge::IsValidRoot()
- .text._ZN10E131Bridge17IsValidDataPacketEv
- 0x000000000800edf0 0x2c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800edf0 E131Bridge::IsValidDataPacket()
+ 0x0800f9d0 0x50 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800f9d0 E131Bridge::IsValidRoot()
.text._ZN10E131Bridge7ProcessEv
- 0x000000000800ee1c 0x98 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800ee1c E131Bridge::Process()
+ 0x0800fa20 0xbc ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800fa20 E131Bridge::Process()
.text._ZN10E131Bridge21HandleSynchronizationEv
- 0x000000000800eeb4 0xa8 ../lib-e131/lib_gd32/libe131.a(e131bridgehandlesynchronization.o)
- 0x000000000800eeb4 E131Bridge::HandleSynchronization()
+ 0x0800fadc 0xac ../lib-e131/lib_gd32/libe131.a(e131bridgehandlesynchronization.o)
+ 0x0800fadc E131Bridge::HandleSynchronization()
.text._ZN10E131Bridge5PrintEv
- 0x000000000800ef5c 0xf0 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
- 0x000000000800ef5c E131Bridge::Print()
+ 0x0800fb88 0xd4 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
+ 0x0800fb88 E131Bridge::Print()
.text._ZN10E131Bridge19FillDiscoveryPacketEv
- 0x000000000800f04c 0xd8 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
- 0x000000000800f04c E131Bridge::FillDiscoveryPacket()
+ 0x0800fc5c 0xb4 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
+ 0x0800fc5c E131Bridge::FillDiscoveryPacket()
.text._ZN10E131Bridge19SendDiscoveryPacketEv
- 0x000000000800f124 0x5a ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
- 0x000000000800f124 E131Bridge::SendDiscoveryPacket()
+ 0x0800fd10 0x60 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
+ 0x0800fd10 E131Bridge::SendDiscoveryPacket()
.text.memcpy.isra.0
- 0x000000000800f17e 0x14 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- *fill* 0x000000000800f192 0x2
+ 0x0800fd70 0x12 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ *fill* 0x0800fd82 0x2
.text._ZN10E131Bridge14FillDataPacketEv
- 0x000000000800f194 0x8c ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- 0x000000000800f194 E131Bridge::FillDataPacket()
+ 0x0800fd84 0x7c ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ 0x0800fd84 E131Bridge::FillDataPacket()
.text._ZN10E131Bridge11HandleDmxInEv
- 0x000000000800f220 0x1f8 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- 0x000000000800f220 E131Bridge::HandleDmxIn()
- .text._ZN19ArtNetRdmControllerD2Ev
- 0x000000000800f418 0x2 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f418 ArtNetRdmController::~ArtNetRdmController()
- 0x000000000800f418 ArtNetRdmController::~ArtNetRdmController()
- *fill* 0x000000000800f41a 0x2
- .text._ZN19ArtNetRdmController11GetUidCountEm
- 0x000000000800f41c 0x10 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f41c ArtNetRdmController::GetUidCount(unsigned long)
- .text._ZN19ArtNetRdmController7TodCopyEmPh
- 0x000000000800f42c 0x2c ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f42c ArtNetRdmController::TodCopy(unsigned long, unsigned char*)
- .text.__tcf_0 0x000000000800f458 0x2 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- *fill* 0x000000000800f45a 0x2
- .text._ZN19ArtNetRdmController4FullEm
- 0x000000000800f45c 0x14 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f45c ArtNetRdmController::Full(unsigned long)
- .text._ZN19ArtNetRdmControllerD0Ev
- 0x000000000800f470 0xc ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f470 ArtNetRdmController::~ArtNetRdmController()
- .text.memcpy 0x000000000800f47c 0x16 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f47c memcpy
- *fill* 0x000000000800f492 0x2
- .text._ZN19ArtNetRdmController7HandlerEmPKh
- 0x000000000800f494 0x48 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f494 ArtNetRdmController::Handler(unsigned long, unsigned char const*)
- .text._ZN19ArtNetRdmController8TodResetEm
- 0x000000000800f4dc 0x48 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f4dc ArtNetRdmController::TodReset(unsigned long)
- .text._ZN6RDMTod5ExistEPKh
- 0x000000000800f524 0x36 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f524 RDMTod::Exist(unsigned char const*)
- *fill* 0x000000000800f55a 0x2
- .text._ZN19ArtNetRdmController9TodAddUidEmPKh
- 0x000000000800f55c 0x48 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f55c ArtNetRdmController::TodAddUid(unsigned long, unsigned char const*)
- .text._ZN19ArtNetRdmControllerC2Ev
- 0x000000000800f5a4 0x34 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f5a4 ArtNetRdmController::ArtNetRdmController()
- 0x000000000800f5a4 ArtNetRdmController::ArtNetRdmController()
- .text._ZN19ArtNetRdmController17RespondMessageAckEmPKhPK11TRdmMessage
- 0x000000000800f5d8 0x80 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f5d8 ArtNetRdmController::RespondMessageAck(unsigned long, unsigned char const*, TRdmMessage const*)
- .text._ZN19ArtNetRdmController10RdmReceiveEmPh
- 0x000000000800f658 0x208 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- 0x000000000800f658 ArtNetRdmController::RdmReceive(unsigned long, unsigned char*)
- .text.startup._GLOBAL__sub_I__ZN19ArtNetRdmController9m_pRDMTodE
- 0x000000000800f860 0x64 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(artnetrdmcontroller.o)
- .text._ZN6artnet8rdm_sendEmPKh
- 0x000000000800f8c4 0x54 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdm_send.o)
- 0x000000000800f8c4 artnet::rdm_send(unsigned long, unsigned char const*)
+ 0x0800fe00 0x1e8 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ 0x0800fe00 E131Bridge::HandleDmxIn()
+ .text._ZN9RDMDeviceC2Ev
+ 0x0800ffe8 0xa0 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x0800ffe8 RDMDevice::RDMDevice()
+ 0x0800ffe8 RDMDevice::RDMDevice()
+ .text._ZN9RDMDevice5PrintEv
+ 0x08010088 0xa4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x08010088 RDMDevice::Print()
+ .text._ZN20RDMDeviceParamsStore4CopyEPN3rdm12deviceparams6ParamsE
+ 0x0801012c 0x24 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x0801012c RDMDeviceParamsStore::Copy(rdm::deviceparams::Params*)
+ .text._ZN15RDMDeviceParamsC2Ev
+ 0x08010150 0x26 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x08010150 RDMDeviceParams::RDMDeviceParams()
+ 0x08010150 RDMDeviceParams::RDMDeviceParams()
+ .text._ZN15RDMDeviceParams4LoadEv
+ 0x08010176 0x8 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x08010176 RDMDeviceParams::Load()
+ *fill* 0x0801017e 0x2
+ .text._ZN15RDMDeviceParams3SetEP9RDMDevice
+ 0x08010180 0xa0 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x08010180 RDMDeviceParams::Set(RDMDevice*)
+ .text._ZN8Hardware6MicrosEv.isra.0
+ 0x08010220 0x40 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
.text.memcpy.isra.0
- 0x000000000800f918 0x14 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
+ 0x08010260 0x12 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
.text._ZN6RDMTod6AddUidEPKh.isra.0
- 0x000000000800f92c 0x4a ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
+ 0x08010272 0x4e ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ .text._ZN3Rdm4SendEmP11TRdmMessage
+ 0x080102c0 0x74 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x080102c0 Rdm::Send(unsigned long, TRdmMessage*)
+ .text._ZN3Rdm7ReceiveEm
+ 0x08010334 0x10 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010334 Rdm::Receive(unsigned long)
.text._ZN10RDMMessage5SetPdEPKhh
- 0x000000000800f976 0x24 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800f976 RDMMessage::SetPd(unsigned char const*, unsigned char)
- *fill* 0x000000000800f99a 0x2
+ 0x08010344 0x24 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010344 RDMMessage::SetPd(unsigned char const*, unsigned char)
.text._ZN12RDMDiscoveryC2EPKh
- 0x000000000800f99c 0x54 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800f99c RDMDiscovery::RDMDiscovery(unsigned char const*)
- 0x000000000800f99c RDMDiscovery::RDMDiscovery(unsigned char const*)
- .text._ZN12RDMDiscovery24IsValidDiscoveryResponseEPKhPh
- 0x000000000800f9f0 0x6c ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800f9f0 RDMDiscovery::IsValidDiscoveryResponse(unsigned char const*, unsigned char*)
- .text._ZN12RDMDiscovery9QuickFindEPKh
- 0x000000000800fa5c 0x104 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800fa5c RDMDiscovery::QuickFind(unsigned char const*)
- .text._ZN12RDMDiscovery11FindDevicesEyy
- 0x000000000800fb60 0x1c0 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800fb60 RDMDiscovery::FindDevices(unsigned long long, unsigned long long)
+ 0x08010368 0x6c ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010368 RDMDiscovery::RDMDiscovery(unsigned char const*)
+ 0x08010368 RDMDiscovery::RDMDiscovery(unsigned char const*)
+ .text._ZN12RDMDiscovery16CopyWorkingQueueEPcm
+ 0x080103d4 0xdc ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x080103d4 RDMDiscovery::CopyWorkingQueue(char*, unsigned long)
+ .text._ZN12RDMDiscovery5StartEmP6RDMTodb
+ 0x080104b0 0x7c ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x080104b0 RDMDiscovery::Start(unsigned long, RDMTod*, bool)
.text._ZN12RDMDiscovery4FullEmP6RDMTod
- 0x000000000800fd20 0xdc ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
- 0x000000000800fd20 RDMDiscovery::Full(unsigned long, RDMTod*)
- .text._ZN9RDMDeviceC2Ev
- 0x000000000800fdfc 0x5c ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
- 0x000000000800fdfc RDMDevice::RDMDevice()
- 0x000000000800fdfc RDMDevice::RDMDevice()
- .text._ZN9RDMDevice5PrintEv
- 0x000000000800fe58 0xa4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
- 0x000000000800fe58 RDMDevice::Print()
- .text._ZN15RDMDeviceParamsC2EP20RDMDeviceParamsStore
- 0x000000000800fefc 0x2a ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800fefc RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*)
- 0x000000000800fefc RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*)
- .text._ZN15RDMDeviceParams4LoadEv
- 0x000000000800ff26 0x16 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800ff26 RDMDeviceParams::Load()
- .text._ZN15RDMDeviceParams3SetEP9RDMDevice
- 0x000000000800ff3c 0x6a ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800ff3c RDMDeviceParams::Set(RDMDevice*)
- .text._ZN15RDMDeviceParams4DumpEv
- 0x000000000800ffa6 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800ffa6 RDMDeviceParams::Dump()
- .text.uuid_unparse_x
- 0x000000000800ffa8 0x7e ../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- *fill* 0x0000000008010026 0x2
- .text.uuid_unparse
- 0x0000000008010028 0xc ../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- 0x0000000008010028 uuid_unparse
- .text._ZN7DmxSendD2Ev
- 0x0000000008010034 0x2 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x0000000008010034 DmxSend::~DmxSend()
- 0x0000000008010034 DmxSend::~DmxSend()
- *fill* 0x0000000008010036 0x2
- .text._ZN7DmxSend4StopEm
- 0x0000000008010038 0x38 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x0000000008010038 DmxSend::Stop(unsigned long)
- .text._ZN7DmxSend5StartEm
- 0x0000000008010070 0x38 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x0000000008010070 DmxSend::Start(unsigned long)
- .text._ZNK7DmxSend14GetOutputStyleEm
- 0x00000000080100a8 0x18 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080100a8 DmxSend::GetOutputStyle(unsigned long) const
- .text._ZN7DmxSend4SyncEm
- 0x00000000080100c0 0x20 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080100c0 DmxSend::Sync(unsigned long)
- .text._ZN7DmxSend4SyncEb
- 0x00000000080100e0 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080100e0 DmxSend::Sync(bool)
- .text._ZN7DmxSend5PrintEv
- 0x0000000008010138 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x0000000008010138 DmxSend::Print()
- .text._ZN7DmxSend6FullOnEv
- 0x0000000008010190 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x0000000008010190 DmxSend::FullOn()
- .text._ZN7DmxSend8BlackoutEb
- 0x000000000801019c 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000801019c DmxSend::Blackout(bool)
- .text._ZN7DmxSend14SetOutputStyleEmN8lightset11OutputStyleE
- 0x00000000080101a8 0x14 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080101a8 DmxSend::SetOutputStyle(unsigned long, lightset::OutputStyle)
- .text._ZN7DmxSendD0Ev
- 0x00000000080101bc 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080101bc DmxSend::~DmxSend()
- .text._ZN7DmxSend7SetDataEmPKhmb
- 0x00000000080101c8 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000080101c8 DmxSend::SetData(unsigned long, unsigned char const*, unsigned long, bool)
- .text._ZN17PropertiesBuilder3AddItEEbPKcT_bm.isra.0
- 0x0000000008010220 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- .text._ZN9DmxParamsC2EP14DmxParamsStore
- 0x0000000008010270 0x18 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x0000000008010270 DmxParams::DmxParams(DmxParamsStore*)
- 0x0000000008010270 DmxParams::DmxParams(DmxParamsStore*)
+ 0x0801052c 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x0801052c RDMDiscovery::Full(unsigned long, RDMTod*)
+ .text._ZN12RDMDiscovery11IncrementalEmP6RDMTod
+ 0x0801057c 0xc ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x0801057c RDMDiscovery::Incremental(unsigned long, RDMTod*)
+ .text._ZN12RDMDiscovery24IsValidDiscoveryResponseEPh
+ 0x08010588 0x88 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010588 RDMDiscovery::IsValidDiscoveryResponse(unsigned char*)
+ .text._ZN12RDMDiscovery8NewStateEN12rdmdiscovery5StateEbm
+ 0x08010610 0x20 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010610 RDMDiscovery::NewState(rdmdiscovery::State, bool, unsigned long)
+ .text._ZN12RDMDiscovery4StopEv
+ 0x08010630 0x1e ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010630 RDMDiscovery::Stop()
+ *fill* 0x0801064e 0x2
+ .text._ZN12RDMDiscovery7ProcessEv
+ 0x08010650 0x6a8 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ 0x08010650 RDMDiscovery::Process()
+ .text._ZN17PropertiesBuilder3AddItEEbPKcT_bi.isra.0
+ 0x08010cf8 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ .text._ZN12StoreDmxSend4CopyEPN13dmxsendparams6ParamsE
+ 0x08010d48 0x20 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010d48 StoreDmxSend::Copy(dmxsendparams::Params*)
+ .text._ZN9DmxParamsC2Ev
+ 0x08010d68 0x22 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010d68 DmxParams::DmxParams()
+ 0x08010d68 DmxParams::DmxParams()
.text._ZN9DmxParams4LoadEv
- 0x0000000008010288 0x18 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x0000000008010288 DmxParams::Load()
+ 0x08010d8a 0x12 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010d8a DmxParams::Load()
.text._ZN9DmxParams4LoadEPKcm
- 0x00000000080102a0 0x3c ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x00000000080102a0 DmxParams::Load(char const*, unsigned long)
+ 0x08010d9c 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010d9c DmxParams::Load(char const*, unsigned long)
.text._ZN9DmxParams16callbackFunctionEPKc
- 0x00000000080102dc 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x00000000080102dc DmxParams::callbackFunction(char const*)
+ 0x08010dec 0xd4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010dec DmxParams::callbackFunction(char const*)
.text._ZN9DmxParams22staticCallbackFunctionEPvPKc
- 0x00000000080103a8 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x00000000080103a8 DmxParams::staticCallbackFunction(void*, char const*)
- .text._ZN9DmxParams7BuilderEPK10TDmxParamsPcmRm
- 0x00000000080103ac 0x104 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x00000000080103ac DmxParams::Builder(TDmxParams const*, char*, unsigned long, unsigned long&)
+ 0x08010ec0 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010ec0 DmxParams::staticCallbackFunction(void*, char const*)
+ .text._ZN9DmxParams7BuilderEPKN13dmxsendparams6ParamsEPcmRm
+ 0x08010ec4 0xf8 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010ec4 DmxParams::Builder(dmxsendparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN9DmxParams3SetEP3Dmx
- 0x00000000080104b0 0x5c ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x00000000080104b0 DmxParams::Set(Dmx*)
- .text._ZN9DmxParams4DumpEv
- 0x000000000801050c 0x2 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000801050c DmxParams::Dump()
- *fill* 0x000000000801050e 0x2
- .text._ZN3Rdm7ReceiveEm
- 0x0000000008010510 0x10 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008010510 Rdm::Receive(unsigned long)
- .text._ZN3Rdm14ReceiveTimeOutEmt
- 0x0000000008010520 0x10 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008010520 Rdm::ReceiveTimeOut(unsigned long, unsigned short)
- .text._ZN3Rdm7SendRawEmPKhm
- 0x0000000008010530 0x40 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008010530 Rdm::SendRaw(unsigned long, unsigned char const*, unsigned long)
- .text._ZN3Dmx8StopDataEmm.part.0
- 0x0000000008010570 0x98 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08010fbc 0x54 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x08010fbc DmxParams::Set(Dmx*)
+ .text._ZN12remoteconfig3dmx14json_get_portsEPcm
+ 0x08011010 0x70 ../lib-dmx/lib_gd32/libdmx.a(json_get_ports.o)
+ 0x08011010 remoteconfig::dmx::json_get_ports(char*, unsigned long)
+ .text._ZN12remoteconfig3dmx19json_get_portstatusEcPcm
+ 0x08011080 0x64 ../lib-dmx/lib_gd32/libdmx.a(json_get_portstatus.o)
+ 0x08011080 remoteconfig::dmx::json_get_portstatus(char, char*, unsigned long)
+ .text._ZN3Dmx8StopDataEm.part.0
+ 0x080110e4 0xa0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
.text.USART2_IRQHandler
- 0x0000000008010608 0x1ec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010608 USART2_IRQHandler
+ 0x08011184 0x17c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011184 USART2_IRQHandler
.text.USART5_IRQHandler
- 0x00000000080107f4 0x20c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x00000000080107f4 USART5_IRQHandler
+ 0x08011300 0x184 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011300 USART5_IRQHandler
.text.TIMER1_IRQHandler
- 0x0000000008010a00 0xe8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010a00 TIMER1_IRQHandler
+ 0x08011484 0x104 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011484 TIMER1_IRQHandler
.text.TIMER4_IRQHandler
- 0x0000000008010ae8 0xec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010ae8 TIMER4_IRQHandler
- .text.TIMER2_IRQHandler
- 0x0000000008010bd4 0x90 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010bd4 TIMER2_IRQHandler
- .text.TIMER3_IRQHandler
- 0x0000000008010c64 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010c64 TIMER3_IRQHandler
+ 0x08011588 0x124 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011588 TIMER4_IRQHandler
.text.TIMER6_IRQHandler
- 0x0000000008010c78 0x30 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010c78 TIMER6_IRQHandler
+ 0x080116ac 0x54 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080116ac TIMER6_IRQHandler
.text.DMA0_Channel3_IRQHandler
- 0x0000000008010ca8 0x58 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010ca8 DMA0_Channel3_IRQHandler
+ 0x08011700 0x70 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011700 DMA0_Channel3_IRQHandler
.text.DMA1_Channel6_IRQHandler
- 0x0000000008010d00 0x64 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010d00 DMA1_Channel6_IRQHandler
+ 0x08011770 0x88 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011770 DMA1_Channel6_IRQHandler
.text._ZN3DmxC2Ev
- 0x0000000008010d64 0x3f4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008010d64 Dmx::Dmx()
- 0x0000000008010d64 Dmx::Dmx()
+ 0x080117f8 0x2e0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080117f8 Dmx::Dmx()
+ 0x080117f8 Dmx::Dmx()
+ .text._ZN3Dmx16SetPortDirectionEmN3dmx13PortDirectionEb
+ 0x08011ad8 0xe4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011ad8 Dmx::SetPortDirection(unsigned long, dmx::PortDirection, bool)
+ .text._ZN3Dmx18GetTotalStatisticsEm
+ 0x08011bbc 0x24 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011bbc Dmx::GetTotalStatistics(unsigned long)
.text._ZN3Dmx14StartDmxOutputEm
- 0x0000000008011158 0xe4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011158 Dmx::StartDmxOutput(unsigned long)
+ 0x08011be0 0xb4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011be0 Dmx::StartDmxOutput(unsigned long)
.text._ZN3Dmx15SetDmxBreakTimeEm
- 0x000000000801123c 0x6c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000801123c Dmx::SetDmxBreakTime(unsigned long)
+ 0x08011c94 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011c94 Dmx::SetDmxBreakTime(unsigned long)
+ .text._ZNK3Dmx15GetDmxBreakTimeEv
+ 0x08011cf4 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011cf4 Dmx::GetDmxBreakTime() const
.text._ZN3Dmx13SetDmxMabTimeEm
- 0x00000000080112a8 0x6c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x00000000080112a8 Dmx::SetDmxMabTime(unsigned long)
+ 0x08011d00 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011d00 Dmx::SetDmxMabTime(unsigned long)
+ .text._ZNK3Dmx13GetDmxMabTimeEv
+ 0x08011d60 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011d60 Dmx::GetDmxMabTime() const
.text._ZN3Dmx16SetDmxPeriodTimeEm
- 0x0000000008011314 0x68 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011314 Dmx::SetDmxPeriodTime(unsigned long)
+ 0x08011d6c 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011d6c Dmx::SetDmxPeriodTime(unsigned long)
.text._ZN3Dmx11SetDmxSlotsEt
- 0x000000000801137c 0x7c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000801137c Dmx::SetDmxSlots(unsigned short)
+ 0x08011dcc 0x70 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011dcc Dmx::SetDmxSlots(unsigned short)
.text._ZN3Dmx14SetOutputStyleEmN3dmx11OutputStyleE
- 0x00000000080113f8 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x00000000080113f8 Dmx::SetOutputStyle(unsigned long, dmx::OutputStyle)
+ 0x08011e3c 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011e3c Dmx::SetOutputStyle(unsigned long, dmx::OutputStyle)
.text._ZNK3Dmx14GetOutputStyleEm
- 0x000000000801140c 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000801140c Dmx::GetOutputStyle(unsigned long) const
+ 0x08011f08 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011f08 Dmx::GetOutputStyle(unsigned long) const
.text._ZN3Dmx20SetSendDataWithoutSCEmPKhm
- 0x0000000008011420 0xc0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011420 Dmx::SetSendDataWithoutSC(unsigned long, unsigned char const*, unsigned long)
- .text._ZN3Dmx11StartOutputEm
- 0x00000000080114e0 0x34 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x00000000080114e0 Dmx::StartOutput(unsigned long)
- .text._ZN3Dmx9SetOutputEb
- 0x0000000008011514 0xf0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011514 Dmx::SetOutput(bool)
- .text._ZN3Dmx9StartDataEmm
- 0x0000000008011604 0x94 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011604 Dmx::StartData(unsigned long, unsigned long)
- .text._ZN3Dmx16SetPortDirectionEmN3dmx13PortDirectionEb
- 0x0000000008011698 0x98 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011698 Dmx::SetPortDirection(unsigned long, dmx::PortDirection, bool)
+ 0x08011f1c 0xa0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011f1c Dmx::SetSendDataWithoutSC(unsigned long, unsigned char const*, unsigned long)
.text._ZN3Dmx8BlackoutEv
- 0x0000000008011730 0xe8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011730 Dmx::Blackout()
+ 0x08011fbc 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08011fbc Dmx::Blackout()
.text._ZN3Dmx6FullOnEv
- 0x0000000008011818 0xec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011818 Dmx::FullOn()
+ 0x08012088 0xd0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08012088 Dmx::FullOn()
+ .text._ZN3Dmx11StartOutputEm
+ 0x08012158 0x34 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08012158 Dmx::StartOutput(unsigned long)
+ .text._ZN3Dmx4SyncEv
+ 0x0801218c 0x68 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0801218c Dmx::Sync()
.text._ZN3Dmx13GetDmxChangedEm
- 0x0000000008011904 0xf8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011904 Dmx::GetDmxChanged(unsigned long)
+ 0x080121f4 0xd0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080121f4 Dmx::GetDmxChanged(unsigned long)
.text._ZN3Dmx17GetDmxCurrentDataEm
- 0x00000000080119fc 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x00000000080119fc Dmx::GetDmxCurrentData(unsigned long)
+ 0x080122c4 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080122c4 Dmx::GetDmxCurrentData(unsigned long)
.text._ZN3Dmx22GetDmxUpdatesPerSecondEm
- 0x0000000008011a0c 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011a0c Dmx::GetDmxUpdatesPerSecond(unsigned long)
+ 0x080122d4 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080122d4 Dmx::GetDmxUpdatesPerSecond(unsigned long)
.text._ZN3Dmx10RdmSendRawEmPKhm
- 0x0000000008011a18 0xfc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011a18 Dmx::RdmSendRaw(unsigned long, unsigned char const*, unsigned long)
+ 0x080122e4 0x19c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x080122e4 Dmx::RdmSendRaw(unsigned long, unsigned char const*, unsigned long)
+ .text._ZN3Dmx30RdmSendDiscoveryRespondMessageEmPKhm
+ 0x08012480 0x194 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08012480 Dmx::RdmSendDiscoveryRespondMessage(unsigned long, unsigned char const*, unsigned long)
.text._ZN3Dmx10RdmReceiveEm
- 0x0000000008011b14 0x24 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011b14 Dmx::RdmReceive(unsigned long)
- .text._ZN3Dmx17RdmReceiveTimeOutEmt
- 0x0000000008011b38 0x40 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000008011b38 Dmx::RdmReceiveTimeOut(unsigned long, unsigned short)
- .text._ZN3Rdm4SendEmP11TRdmMessagem
- 0x0000000008011b78 0x74 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008011b78 Rdm::Send(unsigned long, TRdmMessage*, unsigned long)
- .text._ZN3Rdm21SendRawRespondMessageEmPKhm
- 0x0000000008011bec 0x28 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008011bec Rdm::SendRawRespondMessage(unsigned long, unsigned char const*, unsigned long)
- .text._ZN3Rdm27SendDiscoveryRespondMessageEmPKhm
- 0x0000000008011c14 0x88 ../lib-dmx/lib_gd32/libdmx.a(rdm.o)
- 0x0000000008011c14 Rdm::SendDiscoveryRespondMessage(unsigned long, unsigned char const*, unsigned long)
- .text._ZN11ConfigStoreC2Ev
- 0x0000000008011c9c 0xb8 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011c9c ConfigStore::ConfigStore()
- 0x0000000008011c9c ConfigStore::ConfigStore()
+ 0x08012614 0x1b4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x08012614 Dmx::RdmReceive(unsigned long)
.text._ZN11ConfigStore14GetStoreOffsetEN11configstore5StoreE
- 0x0000000008011d54 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011d54 ConfigStore::GetStoreOffset(configstore::Store)
+ 0x080127c8 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x080127c8 ConfigStore::GetStoreOffset(configstore::Store)
+ .text._ZN11ConfigStoreC2Ev
+ 0x080127e4 0xf8 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x080127e4 ConfigStore::ConfigStore()
+ 0x080127e4 ConfigStore::ConfigStore()
.text._ZN11ConfigStore12ResetSetListEN11configstore5StoreE
- 0x0000000008011d70 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011d70 ConfigStore::ResetSetList(configstore::Store)
+ 0x080128dc 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x080128dc ConfigStore::ResetSetList(configstore::Store)
.text._ZN11ConfigStore6UpdateEN11configstore5StoreEmPKvmmm
- 0x0000000008011d94 0x5c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011d94 ConfigStore::Update(configstore::Store, unsigned long, void const*, unsigned long, unsigned long, unsigned long)
- .text._ZN11ConfigStore4CopyEN11configstore5StoreEPvmm
- 0x0000000008011df0 0x58 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011df0 ConfigStore::Copy(configstore::Store, void*, unsigned long, unsigned long)
+ 0x08012900 0x4c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x08012900 ConfigStore::Update(configstore::Store, unsigned long, void const*, unsigned long, unsigned long, unsigned long)
+ .text._ZN11ConfigStore4CopyEN11configstore5StoreEPvmmb
+ 0x0801294c 0x60 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0801294c ConfigStore::Copy(configstore::Store, void*, unsigned long, unsigned long, bool)
.text._ZN11ConfigStore5FlashEv
- 0x0000000008011e48 0xac ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000008011e48 ConfigStore::Flash()
- .text._ZN15StoreDisplayUdfD2Ev
- 0x0000000008011ef4 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008011ef4 StoreDisplayUdf::~StoreDisplayUdf()
- 0x0000000008011ef4 StoreDisplayUdf::~StoreDisplayUdf()
- *fill* 0x0000000008011ef6 0x2
- .text._ZN15StoreDisplayUdf4CopyEPN16displayudfparams6ParamsE
- 0x0000000008011ef8 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008011ef8 StoreDisplayUdf::Copy(displayudfparams::Params*)
- .text._ZN15StoreDisplayUdf6UpdateEPKN16displayudfparams6ParamsE
- 0x0000000008011f18 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008011f18 StoreDisplayUdf::Update(displayudfparams::Params const*)
- .text._ZN15StoreDisplayUdfD0Ev
- 0x0000000008011f3c 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008011f3c StoreDisplayUdf::~StoreDisplayUdf()
- .text._ZN15StoreDisplayUdfC2Ev
- 0x0000000008011f48 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008011f48 StoreDisplayUdf::StoreDisplayUdf()
- 0x0000000008011f48 StoreDisplayUdf::StoreDisplayUdf()
- .text._ZN12StoreDmxSendD2Ev
- 0x0000000008011f5c 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008011f5c StoreDmxSend::~StoreDmxSend()
- 0x0000000008011f5c StoreDmxSend::~StoreDmxSend()
- *fill* 0x0000000008011f5e 0x2
- .text._ZN12StoreDmxSend4CopyEP10TDmxParams
- 0x0000000008011f60 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008011f60 StoreDmxSend::Copy(TDmxParams*)
- .text._ZN12StoreDmxSend6UpdateEPK10TDmxParams
- 0x0000000008011f80 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008011f80 StoreDmxSend::Update(TDmxParams const*)
- .text._ZN12StoreDmxSendD0Ev
- 0x0000000008011fa4 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008011fa4 StoreDmxSend::~StoreDmxSend()
- .text._ZN12StoreDmxSendC2Ev
- 0x0000000008011fb0 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008011fb0 StoreDmxSend::StoreDmxSend()
- 0x0000000008011fb0 StoreDmxSend::StoreDmxSend()
- .text._ZN12StoreNetworkD2Ev
- 0x0000000008011fc4 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008011fc4 StoreNetwork::~StoreNetwork()
- 0x0000000008011fc4 StoreNetwork::~StoreNetwork()
- 0x0000000008011fc6 non-virtual thunk to StoreNetwork::~StoreNetwork()
- *fill* 0x0000000008011fca 0x2
- .text._ZN12StoreNetwork6UpdateEPKN13networkparams6ParamsE
- 0x0000000008011fcc 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008011fcc StoreNetwork::Update(networkparams::Params const*)
- .text._ZN12StoreNetwork8SaveDhcpEb
- 0x0000000008011ff0 0x30 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008011ff0 StoreNetwork::SaveDhcp(bool)
- 0x0000000008012018 non-virtual thunk to StoreNetwork::SaveDhcp(bool)
- .text._ZN12StoreNetwork13SaveGatewayIpEm
- 0x0000000008012020 0x30 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008012020 StoreNetwork::SaveGatewayIp(unsigned long)
- 0x0000000008012048 non-virtual thunk to StoreNetwork::SaveGatewayIp(unsigned long)
- .text._ZN12StoreNetwork11SaveNetMaskEm
- 0x0000000008012050 0x2c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008012050 StoreNetwork::SaveNetMask(unsigned long)
- 0x0000000008012074 non-virtual thunk to StoreNetwork::SaveNetMask(unsigned long)
- .text._ZN12StoreNetwork6SaveIpEm
- 0x000000000801207c 0x2c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x000000000801207c StoreNetwork::SaveIp(unsigned long)
- 0x00000000080120a0 non-virtual thunk to StoreNetwork::SaveIp(unsigned long)
- .text._ZN12StoreNetwork12SaveHostNameEPKcm
- 0x00000000080120a8 0x34 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080120a8 StoreNetwork::SaveHostName(char const*, unsigned long)
- 0x00000000080120d4 non-virtual thunk to StoreNetwork::SaveHostName(char const*, unsigned long)
- .text._ZN12StoreNetworkD0Ev
- 0x00000000080120dc 0x12 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080120dc StoreNetwork::~StoreNetwork()
- 0x00000000080120e8 non-virtual thunk to StoreNetwork::~StoreNetwork()
- *fill* 0x00000000080120ee 0x2
- .text._ZN12StoreNetwork4CopyEPN13networkparams6ParamsE
- 0x00000000080120f0 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080120f0 StoreNetwork::Copy(networkparams::Params*)
- .text._ZN12StoreNetworkC2Ev
- 0x000000000801210c 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x000000000801210c StoreNetwork::StoreNetwork()
- 0x000000000801210c StoreNetwork::StoreNetwork()
- .text._ZN17StoreRemoteConfigD2Ev
- 0x0000000008012124 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008012124 StoreRemoteConfig::~StoreRemoteConfig()
- 0x0000000008012124 StoreRemoteConfig::~StoreRemoteConfig()
- *fill* 0x0000000008012126 0x2
- .text._ZN17StoreRemoteConfig4CopyEP19TRemoteConfigParams
- 0x0000000008012128 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008012128 StoreRemoteConfig::Copy(TRemoteConfigParams*)
- .text._ZN17StoreRemoteConfig6UpdateEPK19TRemoteConfigParams
- 0x0000000008012148 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008012148 StoreRemoteConfig::Update(TRemoteConfigParams const*)
- .text._ZN17StoreRemoteConfigD0Ev
- 0x000000000801216c 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x000000000801216c StoreRemoteConfig::~StoreRemoteConfig()
- .text._ZN17StoreRemoteConfigC2Ev
- 0x0000000008012178 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008012178 StoreRemoteConfig::StoreRemoteConfig()
- 0x0000000008012178 StoreRemoteConfig::StoreRemoteConfig()
+ 0x080129ac 0xac ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x080129ac ConfigStore::Flash()
+ .text._ZN11ConfigStore15GetEnvUtcOffsetERaRh.isra.0
+ 0x08012a58 0x40 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ .text._ZN9EnvParamsC2Ev
+ 0x08012a98 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x08012a98 EnvParams::EnvParams()
+ 0x08012a98 EnvParams::EnvParams()
+ *fill* 0x08012a9a 0x2
+ .text._ZN9EnvParams10LoadAndSetEPKcm
+ 0x08012a9c 0x28 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x08012a9c EnvParams::LoadAndSet(char const*, unsigned long)
+ .text._ZN9EnvParams16callbackFunctionEPKc
+ 0x08012ac4 0x8c ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x08012ac4 EnvParams::callbackFunction(char const*)
+ .text._ZN9EnvParams22staticCallbackFunctionEPvPKc
+ 0x08012b50 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x08012b50 EnvParams::staticCallbackFunction(void*, char const*)
+ .text._ZN9EnvParams7BuilderEPcmRm
+ 0x08012b54 0x64 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x08012b54 EnvParams::Builder(char*, unsigned long, unsigned long&)
.text._ZN11StoreDeviceC2Ev
- 0x000000000801218c 0x4c ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x000000000801218c StoreDevice::StoreDevice()
- 0x000000000801218c StoreDevice::StoreDevice()
+ 0x08012bb8 0x48 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012bb8 StoreDevice::StoreDevice()
+ 0x08012bb8 StoreDevice::StoreDevice()
.text._ZNK11StoreDevice7GetSizeEv
- 0x00000000080121d8 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x00000000080121d8 StoreDevice::GetSize() const
+ 0x08012c00 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012c00 StoreDevice::GetSize() const
.text._ZNK11StoreDevice13GetSectorSizeEv
- 0x00000000080121dc 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x00000000080121dc StoreDevice::GetSectorSize() const
+ 0x08012c04 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012c04 StoreDevice::GetSectorSize() const
.text._ZN11StoreDevice4ReadEmmPhRN11storedevice6resultE
- 0x00000000080121e0 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x00000000080121e0 StoreDevice::Read(unsigned long, unsigned long, unsigned char*, storedevice::result&)
+ 0x08012c08 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012c08 StoreDevice::Read(unsigned long, unsigned long, unsigned char*, storedevice::result&)
.text._ZN11StoreDevice5EraseEmmRN11storedevice6resultE
- 0x00000000080121f6 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x00000000080121f6 StoreDevice::Erase(unsigned long, unsigned long, storedevice::result&)
+ 0x08012c1e 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012c1e StoreDevice::Erase(unsigned long, unsigned long, storedevice::result&)
.text._ZN11StoreDevice5WriteEmmPKhRN11storedevice6resultE
- 0x000000000801220a 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x000000000801220a StoreDevice::Write(unsigned long, unsigned long, unsigned char const*, storedevice::result&)
- .text._ZN11StoreArtNetD2Ev
- 0x0000000008012220 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012220 StoreArtNet::~StoreArtNet()
- 0x0000000008012220 StoreArtNet::~StoreArtNet()
- 0x0000000008012222 non-virtual thunk to StoreArtNet::~StoreArtNet()
- *fill* 0x0000000008012226 0x2
- .text._ZN11StoreArtNet6UpdateEPKN12artnetparams6ParamsE
- 0x0000000008012228 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012228 StoreArtNet::Update(artnetparams::Params const*)
- .text._ZN11StoreArtNet13SaveShortNameEmPKc
- 0x000000000801224c 0x40 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x000000000801224c StoreArtNet::SaveShortName(unsigned long, char const*)
- .text._ZThn4_N11StoreArtNet13SaveShortNameEmPKc
- 0x000000000801228c 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x000000000801228c non-virtual thunk to StoreArtNet::SaveShortName(unsigned long, char const*)
- .text._ZN11StoreArtNet12SaveFailSafeEh
- 0x0000000008012294 0x34 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012294 StoreArtNet::SaveFailSafe(unsigned char)
- 0x00000000080122c0 non-virtual thunk to StoreArtNet::SaveFailSafe(unsigned char)
- .text._ZN11StoreArtNet12SaveLongNameEPKc
- 0x00000000080122c8 0x2c ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080122c8 StoreArtNet::SaveLongName(char const*)
- 0x00000000080122ec non-virtual thunk to StoreArtNet::SaveLongName(char const*)
- .text._ZN11StoreArtNet13SaveMergeModeEmN8lightset9MergeModeE
- 0x00000000080122f4 0x68 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080122f4 StoreArtNet::SaveMergeMode(unsigned long, lightset::MergeMode)
- .text._ZThn4_N11StoreArtNet13SaveMergeModeEmN8lightset9MergeModeE
- 0x000000000801235c 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x000000000801235c non-virtual thunk to StoreArtNet::SaveMergeMode(unsigned long, lightset::MergeMode)
- .text._ZN11StoreArtNet16SavePortProtocolEmN6artnet12PortProtocolE
- 0x0000000008012364 0x68 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012364 StoreArtNet::SavePortProtocol(unsigned long, artnet::PortProtocol)
- .text._ZThn4_N11StoreArtNet16SavePortProtocolEmN6artnet12PortProtocolE
- 0x00000000080123cc 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080123cc non-virtual thunk to StoreArtNet::SavePortProtocol(unsigned long, artnet::PortProtocol)
- .text._ZN11StoreArtNet15SaveOutputStyleEmN8lightset11OutputStyleE
- 0x00000000080123d4 0x64 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080123d4 StoreArtNet::SaveOutputStyle(unsigned long, lightset::OutputStyle)
- .text._ZThn4_N11StoreArtNet15SaveOutputStyleEmN8lightset11OutputStyleE
- 0x0000000008012438 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012438 non-virtual thunk to StoreArtNet::SaveOutputStyle(unsigned long, lightset::OutputStyle)
- .text._ZN11StoreArtNet14SaveRdmEnabledEmb
- 0x0000000008012440 0x74 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012440 StoreArtNet::SaveRdmEnabled(unsigned long, bool)
- .text._ZThn4_N11StoreArtNet14SaveRdmEnabledEmb
- 0x00000000080124b4 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080124b4 non-virtual thunk to StoreArtNet::SaveRdmEnabled(unsigned long, bool)
- .text._ZN11StoreArtNet4CopyEPN12artnetparams6ParamsE
- 0x00000000080124bc 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080124bc StoreArtNet::Copy(artnetparams::Params*)
- .text._ZN11StoreArtNetD0Ev
- 0x00000000080124dc 0x12 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080124dc StoreArtNet::~StoreArtNet()
- 0x00000000080124e8 non-virtual thunk to StoreArtNet::~StoreArtNet()
- *fill* 0x00000000080124ee 0x2
- .text._ZN11StoreArtNetC2Em
- 0x00000000080124f0 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000080124f0 StoreArtNet::StoreArtNet(unsigned long)
- 0x00000000080124f0 StoreArtNet::StoreArtNet(unsigned long)
- .text._ZN11StoreArtNet12SaveUniverseEm
- 0x0000000008012514 0x5c ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012514 StoreArtNet::SaveUniverse(unsigned long)
- .text._ZN11StoreArtNet16SaveSubnetSwitchEmh
- 0x0000000008012570 0xa ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012570 StoreArtNet::SaveSubnetSwitch(unsigned long, unsigned char)
- 0x0000000008012574 non-virtual thunk to StoreArtNet::SaveSubnetSwitch(unsigned long, unsigned char)
- .text._ZN11StoreArtNet13SaveNetSwitchEmh
- 0x000000000801257a 0xa ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x000000000801257a StoreArtNet::SaveNetSwitch(unsigned long, unsigned char)
- 0x000000000801257e non-virtual thunk to StoreArtNet::SaveNetSwitch(unsigned long, unsigned char)
- .text._ZN11StoreArtNet18SaveUniverseSwitchEmh
- 0x0000000008012584 0xa ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x0000000008012584 StoreArtNet::SaveUniverseSwitch(unsigned long, unsigned char)
- 0x0000000008012588 non-virtual thunk to StoreArtNet::SaveUniverseSwitch(unsigned long, unsigned char)
- .text._ZN14StoreRDMDeviceD2Ev
- 0x000000000801258e 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x000000000801258e StoreRDMDevice::~StoreRDMDevice()
- 0x000000000801258e StoreRDMDevice::~StoreRDMDevice()
- 0x0000000008012590 non-virtual thunk to StoreRDMDevice::~StoreRDMDevice()
- .text._ZN14StoreRDMDevice6UpdateEPKN3rdm12deviceparams6ParamsE
- 0x0000000008012594 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008012594 StoreRDMDevice::Update(rdm::deviceparams::Params const*)
- .text._ZN14StoreRDMDevice9SaveLabelEPKch
- 0x00000000080125b8 0x44 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x00000000080125b8 StoreRDMDevice::SaveLabel(char const*, unsigned char)
- 0x00000000080125f4 non-virtual thunk to StoreRDMDevice::SaveLabel(char const*, unsigned char)
- .text._ZN14StoreRDMDeviceD0Ev
- 0x00000000080125fc 0x12 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x00000000080125fc StoreRDMDevice::~StoreRDMDevice()
- 0x0000000008012608 non-virtual thunk to StoreRDMDevice::~StoreRDMDevice()
- *fill* 0x000000000801260e 0x2
- .text._ZN14StoreRDMDevice4CopyEPN3rdm12deviceparams6ParamsE
- 0x0000000008012610 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008012610 StoreRDMDevice::Copy(rdm::deviceparams::Params*)
- .text._ZN14StoreRDMDeviceC2Ev
- 0x0000000008012630 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008012630 StoreRDMDevice::StoreRDMDevice()
- 0x0000000008012630 StoreRDMDevice::StoreRDMDevice()
+ 0x08012c32 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x08012c32 StoreDevice::Write(unsigned long, unsigned long, unsigned char const*, storedevice::result&)
.text.memcpy.isra.0
- 0x0000000008012648 0x14 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .text.strlen 0x000000000801265c 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x000000000801265c strlen
+ 0x08012c48 0x12 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .text.strlen 0x08012c5a 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012c5a strlen
+ *fill* 0x08012c6a 0x2
.text._ZN4mdns6Domain11AddDotLocalEv
- 0x000000000801266c 0x24 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x000000000801266c mdns::Domain::AddDotLocal()
+ 0x08012c6c 0x24 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012c6c mdns::Domain::AddDotLocal()
.text._ZL18create_host_domainRN4mdns6DomainE
- 0x0000000008012690 0x44 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012c90 0x40 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL21create_service_domainRN4mdns6DomainERKNS_13ServiceRecordEb
- 0x00000000080126d4 0xa4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012cd0 0xa4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZN4mdns6Domain5PrintEb
- 0x0000000008012778 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012778 mdns::Domain::Print(bool)
+ 0x08012d74 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012d74 mdns::Domain::Print(bool)
.text._ZN4mdnseqERKNS_6DomainES2_
- 0x00000000080127c0 0x66 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080127c0 mdns::operator==(mdns::Domain const&, mdns::Domain const&)
+ 0x08012dbc 0x66 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012dbc mdns::operator==(mdns::Domain const&, mdns::Domain const&)
.text._Z24find_compression_pointerPKhS0_S0_
- 0x0000000008012826 0x9c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012826 find_compression_pointer(unsigned char const*, unsigned char const*, unsigned char const*)
- *fill* 0x00000000080128c2 0x2
+ 0x08012e22 0xa0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012e22 find_compression_pointer(unsigned char const*, unsigned char const*, unsigned char const*)
+ *fill* 0x08012ec2 0x2
.text._ZL25put_domain_name_as_labelsPhRKN4mdns6DomainE
- 0x00000000080128c4 0x5c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012ec4 0x5c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL12add_answer_aPhm
- 0x0000000008012920 0x44 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012f20 0x40 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL19add_answer_dnsd_ptrRKN4mdns13ServiceRecordEPhm.constprop.0
- 0x0000000008012964 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012f60 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_srvRKN4mdns13ServiceRecordEPhm
- 0x00000000080129b4 0x58 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08012fb0 0x58 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_ptrRKN4mdns13ServiceRecordEPhm
- 0x0000000008012a0c 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013008 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_txtRKN4mdns13ServiceRecordEPhm
- 0x0000000008012a5c 0x5a ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013058 0x5a ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._Z15get_domain_namePKhS0_S0_Ph
- 0x0000000008012ab6 0x86 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012ab6 get_domain_name(unsigned char const*, unsigned char const*, unsigned char const*, unsigned char*)
- .text._ZN4MDNS6SendToEt
- 0x0000000008012b3c 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012b3c MDNS::SendTo(unsigned short)
+ 0x080130b2 0x8c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x080130b2 get_domain_name(unsigned char const*, unsigned char const*, unsigned char const*, unsigned char*)
+ *fill* 0x0801313e 0x2
+ .text._ZN4MDNS6SendToEm
+ 0x08013140 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013140 MDNS::SendTo(unsigned long)
.text._ZN4MDNS24SendAnswerLocalIpAddressEtm
- 0x0000000008012b84 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012b84 MDNS::SendAnswerLocalIpAddress(unsigned short, unsigned long)
+ 0x08013194 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013194 MDNS::SendAnswerLocalIpAddress(unsigned short, unsigned long)
.text._ZN4MDNS11SendMessageERKN4mdns13ServiceRecordEtm
- 0x0000000008012bd8 0xa8 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012bd8 MDNS::SendMessage(mdns::ServiceRecord const&, unsigned short, unsigned long)
+ 0x080131e8 0xa8 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x080131e8 MDNS::SendMessage(mdns::ServiceRecord const&, unsigned short, unsigned long)
.text._ZN4MDNS16SendAnnouncementEm
- 0x0000000008012c80 0x70 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012c80 MDNS::SendAnnouncement(unsigned long)
+ 0x08013290 0x68 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013290 MDNS::SendAnnouncement(unsigned long)
.text._ZN7network17mdns_announcementEv
- 0x0000000008012cf0 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012cf0 network::mdns_announcement()
+ 0x080132f8 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x080132f8 network::mdns_announcement()
.text._ZN7network13mdns_shutdownEv
- 0x0000000008012d00 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012d00 network::mdns_shutdown()
+ 0x08013308 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013308 network::mdns_shutdown()
.text._ZN4MDNSC2Ev
- 0x0000000008012d10 0x74 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012d10 MDNS::MDNS()
- 0x0000000008012d10 MDNS::MDNS()
- .text._ZN4MDNS16AddServiceRecordEPKcN4mdns8ServicesES1_t
- 0x0000000008012d84 0xc0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012d84 MDNS::AddServiceRecord(char const*, mdns::Services, char const*, unsigned short)
+ 0x08013318 0x74 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013318 MDNS::MDNS()
+ 0x08013318 MDNS::MDNS()
+ .text._ZN4MDNS19ServiceRecordDeleteEN4mdns8ServicesE
+ 0x0801338c 0x38 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801338c MDNS::ServiceRecordDelete(mdns::Services)
+ .text._ZN4MDNS16ServiceRecordAddEPKcN4mdns8ServicesES1_t
+ 0x080133c4 0xc0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x080133c4 MDNS::ServiceRecordAdd(char const*, mdns::Services, char const*, unsigned short)
.text._ZN4MDNS15HandleQuestionsEm
- 0x0000000008012e44 0x198 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012e44 MDNS::HandleQuestions(unsigned long)
+ 0x08013484 0x19c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013484 MDNS::HandleQuestions(unsigned long)
.text._ZN4MDNS5PrintEv
- 0x0000000008012fdc 0x70 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008012fdc MDNS::Print()
+ 0x08013620 0x68 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08013620 MDNS::Print()
.text.strncpy.isra.0
- 0x000000000801304c 0x22 ../lib-network/lib_gd32/libnetwork.a(network.o)
- .text._ZN8Hardware12WatchdogInitEv
- 0x000000000801306e 0x24 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x000000000801306e Hardware::WatchdogInit()
- *fill* 0x0000000008013092 0x2
- .text._ZN7NetworkC2EP18NetworkParamsStore
- 0x0000000008013094 0x2b0 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008013094 Network::Network(NetworkParamsStore*)
- 0x0000000008013094 Network::Network(NetworkParamsStore*)
+ 0x08013688 0x22 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ *fill* 0x080136aa 0x2
+ .text._ZN12NetworkStore8SaveDhcpEb
+ 0x080136ac 0x28 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080136ac NetworkStore::SaveDhcp(bool)
+ .text._ZL18netif_ext_callbacktPKN3net25netif_ext_callback_args_tE
+ 0x080136d4 0xe0 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ .text._ZN7NetworkC2Ev
+ 0x080137b4 0x178 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080137b4 Network::Network()
+ 0x080137b4 Network::Network()
.text._ZN7Network5SetIpEm
- 0x0000000008013344 0x62 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008013344 Network::SetIp(unsigned long)
+ 0x0801392c 0x40 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x0801392c Network::SetIp(unsigned long)
.text._ZN7Network10SetNetmaskEm
- 0x00000000080133a6 0x2e ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x00000000080133a6 Network::SetNetmask(unsigned long)
+ 0x0801396c 0x38 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x0801396c Network::SetNetmask(unsigned long)
.text._ZN7Network12SetGatewayIpEm
- 0x00000000080133d4 0x2a ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x00000000080133d4 Network::SetGatewayIp(unsigned long)
- *fill* 0x00000000080133fe 0x2
+ 0x080139a4 0x3c ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080139a4 Network::SetGatewayIp(unsigned long)
.text._ZN7Network10EnableDhcpEv
- 0x0000000008013400 0x6c ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008013400 Network::EnableDhcp()
- .text._ZN7Network5PrintEv
- 0x000000000801346c 0xdc ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x000000000801346c Network::Print()
- .text._ZN13NetworkParamsC2EP18NetworkParamsStore
- 0x0000000008013548 0x18 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008013548 NetworkParams::NetworkParams(NetworkParamsStore*)
- 0x0000000008013548 NetworkParams::NetworkParams(NetworkParamsStore*)
+ 0x080139e0 0xe ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080139e0 Network::EnableDhcp()
+ *fill* 0x080139ee 0x2
+ .text._ZN3net11autoip_stopEv
+ 0x080139f0 0x24 ../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ 0x080139f0 net::autoip_stop()
+ .text._ZN3netL9dhcp_bindEv
+ 0x08013a14 0xd4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL12message_initEv
+ 0x08013ae8 0x40 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL13dhcp_discoverEv
+ 0x08013b28 0xb0 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net9memcpy_ipEPhm
+ 0x08013bd8 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013bd8 net::memcpy_ip(unsigned char*, unsigned long)
+ .text._ZN3netL12send_requestEv
+ 0x08013bdc 0xd0 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL11dhcp_selectEv
+ 0x08013cac 0x4c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL11dhcp_rebootEv
+ 0x08013cf8 0x50 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net9memcpy_ipEPKh
+ 0x08013d48 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013d48 net::memcpy_ip(unsigned char const*)
+ .text._ZN3netL15dhcp_handle_ackEPKNS_4dhcp7MessageE
+ 0x08013d4c 0x40 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net11dhcp_informEv
+ 0x08013d8c 0x6c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013d8c net::dhcp_inform()
+ .text._ZN3net10dhcp_startEv
+ 0x08013df8 0x98 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013df8 net::dhcp_start()
+ .text._ZN3net21dhcp_release_and_stopEv
+ 0x08013e90 0xa4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013e90 net::dhcp_release_and_stop()
+ .text._ZN3netL13dhcp_fine_tmrEv
+ 0x08013f34 0x8c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net12dhcp_processEPKNS_4dhcp7MessageEm
+ 0x08013fc0 0x15c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08013fc0 net::dhcp_process(net::dhcp::Message const*, unsigned long)
+ .text._ZN3netL16igmp_send_reportEm
+ 0x0801411c 0x78 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ .text._ZN3netL10igmp_timerEv
+ 0x08014194 0x54 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ .text._ZN3net11igmp_set_ipEv
+ 0x080141e8 0x20 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x080141e8 net::igmp_set_ip()
+ .text._ZN3net9igmp_joinEm
+ 0x08014208 0x3c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08014208 net::igmp_join(unsigned long)
+ .text._ZN3net10igmp_leaveEm
+ 0x08014244 0x4c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08014244 net::igmp_leave(unsigned long)
+ .text._ZN3net18igmp_report_groupsEv
+ 0x08014290 0x5c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08014290 net::igmp_report_groups()
+ .text._ZN3netL28primary_ip_conflict_callbackENS_3acd8CallbackE
+ 0x080142ec 0x54 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ .text._ZN3net12net_shutdownEv
+ 0x08014340 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08014340 net::net_shutdown()
+ .text._ZN3net18net_set_primary_ipENS_7ip_addrE
+ 0x08014344 0x38 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08014344 net::net_set_primary_ip(net::ip_addr)
+ .text._ZN3net10net_chksumEPKvm
+ 0x0801437c 0x58 ../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
+ 0x0801437c net::net_chksum(void const*, unsigned long)
+ .text._ZN3netL16default_callbackEtPKNS_25netif_ext_callback_args_tE
+ 0x080143d4 0x2 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ *fill* 0x080143d6 0x2
+ .text._ZN3netL23netif_do_update_globalsEv
+ 0x080143d8 0x30 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3netL19netif_issue_reportsEv
+ 0x08014408 0x18 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3netL19netif_do_set_ipaddrENS_7ip_addrERS0_
+ 0x08014420 0x34 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3net10netif_initEv
+ 0x08014454 0x40 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x08014454 net::netif_init()
+ .text._ZN3net16netif_set_ipaddrENS_7ip_addrE
+ 0x08014494 0x24 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x08014494 net::netif_set_ipaddr(net::ip_addr)
+ .text._ZN3net17netif_set_netmaskENS_7ip_addrE
+ 0x080144b8 0x28 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080144b8 net::netif_set_netmask(net::ip_addr)
+ .text._ZN3net12netif_set_gwENS_7ip_addrE
+ 0x080144e0 0x28 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080144e0 net::netif_set_gw(net::ip_addr)
+ .text._ZN3net14netif_set_addrENS_7ip_addrES0_S0_
+ 0x08014508 0x8c ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x08014508 net::netif_set_addr(net::ip_addr, net::ip_addr, net::ip_addr)
+ .text._ZN3net22netif_add_ext_callbackEPFvtPKNS_25netif_ext_callback_args_tEE
+ 0x08014594 0xc ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x08014594 net::netif_add_ext_callback(void (*)(unsigned short, net::netif_ext_callback_args_t const*))
+ .text._ZN3net19netif_set_link_downEv
+ 0x080145a0 0x40 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080145a0 net::netif_set_link_down()
+ .text._ZN3netL8_bswap32EP5t_tcp
+ 0x080145e0 0x40 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL12send_packageEPKNS_3tcbERKNS_8SendInfoE
+ 0x08014620 0x170 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL10send_resetEP5t_tcpPKNS_3tcbE
+ 0x08014790 0x68 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL12scan_optionsEP5t_tcpPNS_3tcbEl
+ 0x080147f8 0xb4 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3net12tcp_shutdownEv
+ 0x080148ac 0x4 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080148ac net::tcp_shutdown()
+ .text._ZN3net9tcp_beginEt
+ 0x080148b0 0x64 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080148b0 net::tcp_begin(unsigned short)
+ .text._ZN3net8tcp_readElPPKhRm
+ 0x08014914 0x70 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08014914 net::tcp_read(long, unsigned char const**, unsigned long&)
+ .text._ZN3net9tcp_writeElPKhmm
+ 0x08014984 0xa0 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08014984 net::tcp_write(long, unsigned char const*, unsigned long, unsigned long)
+ .text._ZN3net10udp_set_ipEv
+ 0x08014a24 0x14 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08014a24 net::udp_set_ip()
+ .text._ZN3net9udp_beginEt
+ 0x08014a38 0x2c ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08014a38 net::udp_begin(unsigned short)
+ .text._ZN3net7udp_endEt
+ 0x08014a64 0x48 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08014a64 net::udp_end(unsigned short)
+ .text._ZN3net9udp_recv2EiPPKhPmPt
+ 0x08014aac 0x3c ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08014aac net::udp_recv2(int, unsigned char const**, unsigned long*, unsigned short*)
+ .text._ZN3net8udp_sendEiPKhmmt
+ 0x08014ae8 0x110 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08014ae8 net::udp_send(int, unsigned char const*, unsigned long, unsigned long, unsigned short)
+ .text._ZN18NetworkParamsStore4CopyEPN13networkparams6ParamsE
+ 0x08014bf8 0x20 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014bf8 NetworkParamsStore::Copy(networkparams::Params*)
+ .text._ZN13NetworkParamsC2Ev
+ 0x08014c18 0x14 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014c18 NetworkParams::NetworkParams()
+ 0x08014c18 NetworkParams::NetworkParams()
.text._ZN13NetworkParams4LoadEv
- 0x0000000008013560 0x18 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008013560 NetworkParams::Load()
+ 0x08014c2c 0x12 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014c2c NetworkParams::Load()
+ *fill* 0x08014c3e 0x2
.text._ZN13NetworkParams4LoadEPKcm
- 0x0000000008013578 0x3c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008013578 NetworkParams::Load(char const*, unsigned long)
+ 0x08014c40 0x50 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014c40 NetworkParams::Load(char const*, unsigned long)
.text._ZN13NetworkParams16callbackFunctionEPKc
- 0x00000000080135b4 0x12c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080135b4 NetworkParams::callbackFunction(char const*)
+ 0x08014c90 0x15c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014c90 NetworkParams::callbackFunction(char const*)
.text._ZN13NetworkParams22staticCallbackFunctionEPvPKc
- 0x00000000080136e0 0x4 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080136e0 NetworkParams::staticCallbackFunction(void*, char const*)
+ 0x08014dec 0x4 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014dec NetworkParams::staticCallbackFunction(void*, char const*)
.text._ZN13NetworkParams7BuilderEPKN13networkparams6ParamsEPcmRm
- 0x00000000080136e4 0x220 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080136e4 NetworkParams::Builder(networkparams::Params const*, char*, unsigned long, unsigned long&)
- .text._ZN13NetworkParams4DumpEv
- 0x0000000008013904 0x2 ../lib-network/lib_gd32/libnetwork.a(networkparamsdump.o)
- 0x0000000008013904 NetworkParams::Dump()
- .text.memcpy.isra.0
- 0x0000000008013906 0x14 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- *fill* 0x000000000801391a 0x2
- .text._ZL12_send_reportm
- 0x000000000801391c 0x7c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- .text._Z11igmp_set_ipv
- 0x0000000008013998 0x34 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x0000000008013998 igmp_set_ip()
- .text._Z10igmp_timerv
- 0x00000000080139cc 0x30 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x00000000080139cc igmp_timer()
- .text._Z9igmp_joinm
- 0x00000000080139fc 0x48 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x00000000080139fc igmp_join(unsigned long)
- .text._Z10igmp_leavem
- 0x0000000008013a44 0x5c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x0000000008013a44 igmp_leave(unsigned long)
- .text._ZL16refresh_and_initP6IpInfob
- 0x0000000008013aa0 0x48 ../lib-network/lib_gd32/libnetwork.a(net.o)
- .text._Z16set_secondary_ipv
- 0x0000000008013ae8 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013ae8 set_secondary_ip()
- .text._Z10net_set_ipP6IpInfo
- 0x0000000008013afc 0x34 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013afc net_set_ip(IpInfo*)
- .text._Z15net_set_netmaskP6IpInfo
- 0x0000000008013b30 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013b30 net_set_netmask(IpInfo*)
- .text._Z10net_set_gwP6IpInfo
- 0x0000000008013b40 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013b40 net_set_gw(IpInfo*)
- .text._Z12net_set_dhcpP6IpInfoPKcPb
- 0x0000000008013b50 0x48 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013b50 net_set_dhcp(IpInfo*, char const*, bool*)
- .text._Z16net_dhcp_releasev
- 0x0000000008013b98 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008013b98 net_dhcp_release()
- .text._Z10net_chksumPKvm
- 0x0000000008013bac 0x34 ../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
- 0x0000000008013bac net_chksum(void const*, unsigned long)
- .text._Z14net_timers_runv
- 0x0000000008013be0 0x20 ../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- 0x0000000008013be0 net_timers_run()
- .text._Z7rfc3927v
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- 0x0000000008013c00 rfc3927()
- .text.memcpy.isra.0
- 0x0000000008013c74 0x14 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL12scan_optionsP5t_tcpP3tcbl
- 0x0000000008013c88 0xb0 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL8_bswap32P5t_tcp
- 0x0000000008013d38 0x4a ../lib-network/lib_gd32/libnetwork.a(tcp.o)
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- .text._ZL12send_packagePK3tcbRK8SendInfo
- 0x0000000008013d84 0x17c ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL9_init_tcbP3tcbt
- 0x0000000008013f00 0x38 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL10send_resetP5t_tcpPK3tcb
- 0x0000000008013f38 0x60 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._Z12tcp_shutdownv
- 0x0000000008013f98 0x2 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008013f98 tcp_shutdown()
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- .text._Z9tcp_begint
- 0x0000000008013f9c 0x34 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008013f9c tcp_begin(unsigned short)
- .text._Z8tcp_readlPPKhRm
- 0x0000000008013fd0 0x68 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008013fd0 tcp_read(long, unsigned char const**, unsigned long&)
- .text._Z9tcp_writelPKhtm
- 0x0000000008014038 0x64 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008014038 tcp_write(long, unsigned char const*, unsigned short, unsigned long)
- .text._Z10net_memcpyPvPKvj.isra.0
- 0x000000000801409c 0x38 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- .text.memcpy.isra.0
- 0x00000000080140d4 0x14 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- .text._Z10udp_set_ipv
- 0x00000000080140e8 0x24 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x00000000080140e8 udp_set_ip()
- .text._Z9udp_begint
- 0x000000000801410c 0x30 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x000000000801410c udp_begin(unsigned short)
- .text._Z7udp_endt
- 0x000000000801413c 0x4c ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x000000000801413c udp_end(unsigned short)
- .text._Z9udp_recv2iPPKhPmPt
- 0x0000000008014188 0x2c ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x0000000008014188 udp_recv2(int, unsigned char const**, unsigned long*, unsigned short*)
- .text._Z8udp_sendiPKhtmt
- 0x00000000080141b4 0x14c ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x00000000080141b4 udp_send(int, unsigned char const*, unsigned short, unsigned long, unsigned short)
+ 0x08014df0 0x23c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08014df0 NetworkParams::Builder(networkparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN3net18phy_customized_ledEv
- 0x0000000008014300 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008014300 net::phy_customized_led()
+ 0x0801502c 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x0801502c net::phy_customized_led()
.text._ZN3net21phy_customized_timingEv
- 0x0000000008014302 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008014302 net::phy_customized_timing()
- .text.emac_eth_recv
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- 0x0000000008014304 emac_eth_recv
- .text.emac_free_pkt
- 0x000000000801432c 0x8 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x000000000801432c emac_free_pkt
- .text.emac_eth_send
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- 0x0000000008014334 emac_eth_send
+ 0x0801502e 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x0801502e net::phy_customized_timing()
+ .text._Z16emac_adjust_linkN3net9PhyStatusE
+ 0x08015030 0x70 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x08015030 emac_adjust_link(net::PhyStatus)
.text._ZN3net8phy_readEmmRt
- 0x0000000008014338 0x16 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008014338 net::phy_read(unsigned long, unsigned long, unsigned short&)
+ 0x080150a0 0x16 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x080150a0 net::phy_read(unsigned long, unsigned long, unsigned short&)
.text._ZN3net9phy_writeEmmt
- 0x000000000801434e 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x000000000801434e net::phy_write(unsigned long, unsigned long, unsigned short)
- *fill* 0x000000000801436e 0x2
+ 0x080150b6 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x080150b6 net::phy_write(unsigned long, unsigned long, unsigned short)
+ *fill* 0x080150d6 0x2
.text._ZN3net10phy_configEm
- 0x0000000008014370 0xd4 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008014370 net::phy_config(unsigned long)
- .text.memcpy.isra.0
- 0x0000000008014444 0x14 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .text._Z16arp_send_requestm
- 0x0000000008014458 0x30 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008014458 arp_send_request(unsigned long)
- .text._Z14arp_send_probev
- 0x0000000008014488 0x40 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008014488 arp_send_probe()
- .text._Z12arp_do_probev
- 0x00000000080144c8 0x30 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x00000000080144c8 arp_do_probe()
- .text._Z21arp_send_announcementv
- 0x00000000080144f8 0x18 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x00000000080144f8 arp_send_announcement()
- .text._Z18arp_handle_requestP5t_arp
- 0x0000000008014510 0x80 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008014510 arp_handle_request(t_arp*)
- .text._Z16arp_handle_replyP5t_arp
- 0x0000000008014590 0x38 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008014590 arp_handle_reply(t_arp*)
- .text._Z16arp_cache_updatePKhm
- 0x00000000080145c8 0x58 ../lib-network/lib_gd32/libnetwork.a(arp_cache.o)
- 0x00000000080145c8 arp_cache_update(unsigned char const*, unsigned long)
- .text._Z16arp_cache_lookupmPh
- 0x0000000008014620 0x98 ../lib-network/lib_gd32/libnetwork.a(arp_cache.o)
- 0x0000000008014620 arp_cache_lookup(unsigned long, unsigned char*)
- .text._ZL14parse_responseiPKh.constprop.0
- 0x00000000080146b8 0x148 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .text.memcpy.isra.0
- 0x0000000008014800 0x14 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .text._Z11dhcp_clientPKc
- 0x0000000008014814 0x210 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- 0x0000000008014814 dhcp_client(char const*)
- .text._Z19dhcp_client_releasev
- 0x0000000008014a24 0x70 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- 0x0000000008014a24 dhcp_client_release()
- .text._Z9ip_set_ipv
- 0x0000000008014a94 0xe ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x0000000008014a94 ip_set_ip()
- .text._ZN3net16link_status_readEv
- 0x0000000008014aa2 0x26 ../lib-network/lib_gd32/libnetwork.a(net_link_check.o)
- 0x0000000008014aa2 net::link_status_read()
+ 0x080150d8 0xd4 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x080150d8 net::phy_config(unsigned long)
+ .text._Z16enet_gpio_configv
+ 0x080151ac 0x1b4 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x080151ac enet_gpio_config()
+ .text._Z13emac_eth_recvPPh
+ 0x08015360 0x24 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08015360 emac_eth_recv(unsigned char**)
+ .text._Z13emac_free_pktv
+ 0x08015384 0x40 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08015384 emac_free_pkt()
+ .text._Z13emac_eth_sendPvm
+ 0x080153c4 0x8c ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x080153c4 emac_eth_send(void*, unsigned long)
+ .text._ZN3net9acd_startEPNS_3acd3AcdENS_7ip_addrE
+ 0x08015450 0x74 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x08015450 net::acd_start(net::acd::Acd*, net::ip_addr)
+ .text._ZN3net8acd_stopEPNS_3acd3AcdE
+ 0x080154c4 0x58 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080154c4 net::acd_stop(net::acd::Acd*)
+ .text._ZN3netL9acd_timerEv
+ 0x0801551c 0xb4 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ .text._ZN3netL11acd_restartEPNS_3acd3AcdE
+ 0x080155d0 0x32 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ *fill* 0x08015602 0x2
+ .text._ZN3net29acd_network_changed_link_downEv
+ 0x08015604 0xc ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x08015604 net::acd_network_changed_link_down()
+ .text._ZN3net13acd_arp_replyEP5t_arp
+ 0x08015610 0xac ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x08015610 net::acd_arp_reply(t_arp*)
+ .text._ZN3net7acd_addEPNS_3acd3AcdEPFvNS0_8CallbackEE
+ 0x080156bc 0xc ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080156bc net::acd_add(net::acd::Acd*, void (*)(net::acd::Callback))
+ .text._ZN3net25acd_netif_ip_addr_changedENS_7ip_addrES0_
+ 0x080156c8 0x54 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080156c8 net::acd_netif_ip_addr_changed(net::ip_addr, net::ip_addr)
+ .text._ZN3netL15arp_find_recordEmNS_3arp5FlagsE
+ 0x0801571c 0x64 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .text._ZN3netL9arp_timerEv
+ 0x08015780 0xb0 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .text._ZN3net8arp_sendEP5t_udpmm
+ 0x08015830 0xf8 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08015830 net::arp_send(t_udp*, unsigned long, unsigned long)
+ .text._ZN3net13arp_acd_probeENS_7ip_addrE
+ 0x08015928 0x28 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08015928 net::arp_acd_probe(net::ip_addr)
+ .text._ZN3net25arp_acd_send_announcementENS_7ip_addrE
+ 0x08015950 0x18 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08015950 net::arp_acd_send_announcement(net::ip_addr)
+ .text._ZN3net9ip_set_ipEv
+ 0x08015968 0x10 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08015968 net::ip_set_ip()
+ .text._ZN3net12phy_get_linkEm
+ 0x08015978 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08015978 net::phy_get_link(unsigned long)
.text._ZN3net9phy_startEmRNS_9PhyStatusE
- 0x0000000008014ac8 0x15c ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008014ac8 net::phy_start(unsigned long, net::PhyStatus&)
- .text.memcpy.isra.0
- 0x0000000008014c24 0x14 ../lib-network/lib_gd32/libnetwork.a(icmp.o)
- .text._ZN8LightSet18GetDmxStartAddressEv
- 0x0000000008014c38 0x4 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008014c38 LightSet::GetDmxStartAddress()
- .text._ZN8LightSet15GetDmxFootprintEv
- 0x0000000008014c3c 0x6 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008014c3c LightSet::GetDmxFootprint()
- .text._ZN8LightSet18SetDmxStartAddressEt
- 0x0000000008014c42 0x4 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008014c42 LightSet::SetDmxStartAddress(unsigned short)
- .text._ZN8LightSet11GetSlotInfoEtRN8lightset8SlotInfoE
- 0x0000000008014c46 0xa ../lib-lightset/lib_gd32/liblightset.a(lightsetgetslotinfo.o)
- 0x0000000008014c46 LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&)
+ 0x08015998 0x144 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08015998 net::phy_start(unsigned long, net::PhyStatus&)
.text._ZN7Display14ClearEndOfLineEv.isra.0
- 0x0000000008014c50 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015adc 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
.text._ZN7Display5WriteEmPKc.isra.0
- 0x0000000008014c58 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015ae4 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
.text._ZN7Display6PrintfEmPKcz
- 0x0000000008014c7a 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014c7a Display::Printf(unsigned long, char const*, ...)
- *fill* 0x0000000008014cb2 0x2
+ 0x08015b06 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015b06 Display::Printf(unsigned long, char const*, ...)
+ *fill* 0x08015b3e 0x2
.text._ZN10DisplayUdf13ShowIpAddressEv
- 0x0000000008014cb4 0x64 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014cb4 DisplayUdf::ShowIpAddress()
+ 0x08015b40 0x68 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015b40 DisplayUdf::ShowIpAddress()
.text._ZN10DisplayUdfC2Ev
- 0x0000000008014d18 0x30 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014d18 DisplayUdf::DisplayUdf()
- 0x0000000008014d18 DisplayUdf::DisplayUdf()
+ 0x08015ba8 0x2c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015ba8 DisplayUdf::DisplayUdf()
+ 0x08015ba8 DisplayUdf::DisplayUdf()
.text._ZN10DisplayUdf8SetTitleEPKcz
- 0x0000000008014d48 0x28 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014d48 DisplayUdf::SetTitle(char const*, ...)
+ 0x08015bd4 0x26 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015bd4 DisplayUdf::SetTitle(char const*, ...)
.text._ZN10DisplayUdf3SetEmN10displayudf6LabelsE
- 0x0000000008014d70 0x34 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014d70 DisplayUdf::Set(unsigned long, displayudf::Labels)
+ 0x08015bfa 0x34 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015bfa DisplayUdf::Set(unsigned long, displayudf::Labels)
+ *fill* 0x08015c2e 0x2
.text._ZN10DisplayUdf4ShowEv
- 0x0000000008014da4 0xe8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008014da4 DisplayUdf::Show()
- .text._ZN17PropertiesBuilder3AddIhEEbPKcT_bm.isra.0
- 0x0000000008014e8c 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- .text._ZN16DisplayUdfParamsC2EP21DisplayUdfParamsStore
- 0x0000000008014edc 0x1a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008014edc DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*)
- 0x0000000008014edc DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*)
+ 0x08015c30 0xec ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08015c30 DisplayUdf::Show()
+ .text._ZN17PropertiesBuilder3AddIhEEbPKcT_bi.isra.0
+ 0x08015d1c 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ .text._ZN21DisplayUdfParamsStore4CopyEPN16displayudfparams6ParamsE
+ 0x08015d6c 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015d6c DisplayUdfParamsStore::Copy(displayudfparams::Params*)
+ .text._ZN16DisplayUdfParamsC2Ev
+ 0x08015d90 0x1c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015d90 DisplayUdfParams::DisplayUdfParams()
+ 0x08015d90 DisplayUdfParams::DisplayUdfParams()
.text._ZN16DisplayUdfParams4LoadEv
- 0x0000000008014ef6 0x18 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008014ef6 DisplayUdfParams::Load()
- *fill* 0x0000000008014f0e 0x2
+ 0x08015dac 0x12 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015dac DisplayUdfParams::Load()
+ *fill* 0x08015dbe 0x2
.text._ZN16DisplayUdfParams4LoadEPKcm
- 0x0000000008014f10 0x3c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008014f10 DisplayUdfParams::Load(char const*, unsigned long)
+ 0x08015dc0 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015dc0 DisplayUdfParams::Load(char const*, unsigned long)
.text._ZN16DisplayUdfParams16callbackFunctionEPKc
- 0x0000000008014f4c 0xc8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008014f4c DisplayUdfParams::callbackFunction(char const*)
+ 0x08015e10 0xc0 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015e10 DisplayUdfParams::callbackFunction(char const*)
.text._ZN16DisplayUdfParams22staticCallbackFunctionEPvPKc
- 0x0000000008015014 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008015014 DisplayUdfParams::staticCallbackFunction(void*, char const*)
+ 0x08015ed0 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015ed0 DisplayUdfParams::staticCallbackFunction(void*, char const*)
.text._ZN16DisplayUdfParams7BuilderEPKN16displayudfparams6ParamsEPcmRm
- 0x0000000008015018 0x134 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008015018 DisplayUdfParams::Builder(displayudfparams::Params const*, char*, unsigned long, unsigned long&)
+ 0x08015ed4 0x128 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015ed4 DisplayUdfParams::Builder(displayudfparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN16DisplayUdfParams3SetEP10DisplayUdf
- 0x000000000801514c 0x6a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x000000000801514c DisplayUdfParams::Set(DisplayUdf*)
- .text._ZN16DisplayUdfParams4DumpEv
- 0x00000000080151b6 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x00000000080151b6 DisplayUdfParams::Dump()
+ 0x08015ffc 0x6a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08015ffc DisplayUdfParams::Set(DisplayUdf*)
.text._ZN6artnet16display_longnameEPKc
- 0x00000000080151b8 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151b8 artnet::display_longname(char const*)
- *fill* 0x00000000080151ba 0x2
+ 0x08016066 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x08016066 artnet::display_longname(char const*)
.text._ZN6artnet23display_universe_switchEmh
- 0x00000000080151bc 0x14 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151bc artnet::display_universe_switch(unsigned long, unsigned char)
+ 0x08016068 0xc ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x08016068 artnet::display_universe_switch(unsigned long, unsigned char)
.text._ZN6artnet18display_merge_modeEmN8lightset9MergeModeE
- 0x00000000080151d0 0x14 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151d0 artnet::display_merge_mode(unsigned long, lightset::MergeMode)
+ 0x08016074 0xc ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x08016074 artnet::display_merge_mode(unsigned long, lightset::MergeMode)
.text._ZN6artnet19display_outputstyleEmN8lightset11OutputStyleE
- 0x00000000080151e4 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151e4 artnet::display_outputstyle(unsigned long, lightset::OutputStyle)
+ 0x08016080 0xc ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x08016080 artnet::display_outputstyle(unsigned long, lightset::OutputStyle)
.text._ZN6artnet21display_port_protocolEmNS_12PortProtocolE
- 0x00000000080151e8 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151e8 artnet::display_port_protocol(unsigned long, artnet::PortProtocol)
+ 0x0801608c 0xc ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x0801608c artnet::display_port_protocol(unsigned long, artnet::PortProtocol)
.text._ZN6artnet19display_rdm_enabledEmb
- 0x00000000080151ec 0x14 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x00000000080151ec artnet::display_rdm_enabled(unsigned long, bool)
+ 0x08016098 0xc ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x08016098 artnet::display_rdm_enabled(unsigned long, bool)
.text._ZN6artnet16display_failsafeEh
- 0x0000000008015200 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
- 0x0000000008015200 artnet::display_failsafe(unsigned char)
- *fill* 0x0000000008015202 0x2
- .text._ZN10DisplayUdf12ShowUniverseEP10ArtNetNode
- 0x0000000008015204 0xc4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
- 0x0000000008015204 DisplayUdf::ShowUniverse(ArtNetNode*)
- .text._ZN10DisplayUdf17ShowDestinationIpEP10ArtNetNode
- 0x00000000080152c8 0x5c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
- 0x00000000080152c8 DisplayUdf::ShowDestinationIp(ArtNetNode*)
- .text._ZN10DisplayUdf4ShowEP10ArtNetNodem
- 0x0000000008015324 0x78 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
- 0x0000000008015324 DisplayUdf::Show(ArtNetNode*, unsigned long)
+ 0x080160a4 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(artnetdisplay.o)
+ 0x080160a4 artnet::display_failsafe(unsigned char)
+ *fill* 0x080160a6 0x2
+ .text._ZN10DisplayUdf22ShowUniverseArtNetNodeEv
+ 0x080160a8 0xe8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
+ 0x080160a8 DisplayUdf::ShowUniverseArtNetNode()
+ .text._ZN10DisplayUdf27ShowDestinationIpArtNetNodeEv
+ 0x08016190 0x60 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
+ 0x08016190 DisplayUdf::ShowDestinationIpArtNetNode()
+ .text._ZN10DisplayUdf14ShowArtNetNodeEv
+ 0x080161f0 0x70 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowartnet.o)
+ 0x080161f0 DisplayUdf::ShowArtNetNode()
.text._ZN7Display14ClearEndOfLineEv.isra.0
- 0x000000000801539c 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- .text._ZN7Display5WriteEmPKc.isra.0
- 0x00000000080153a4 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- .text._ZN7Display6StatusE22Display7SegmentMessage
- 0x00000000080153c6 0x34 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080153c6 Display::Status(Display7SegmentMessage)
- *fill* 0x00000000080153fa 0x2
- .text._ZN10DisplayUdf14ShowDhcpStatusEN7network4dhcp12ClientStatusE
- 0x00000000080153fc 0x68 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080153fc DisplayUdf::ShowDhcpStatus(network::dhcp::ClientStatus)
- .text._ZN7network19display_emac_configEv
- 0x0000000008015464 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x0000000008015464 network::display_emac_config()
- .text._ZN7network18display_emac_startEv
- 0x0000000008015488 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x0000000008015488 network::display_emac_start()
- .text._ZN7network19display_emac_statusEb
- 0x00000000080154ac 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080154ac network::display_emac_status(bool)
- .text._ZN7network10display_ipEv
- 0x00000000080154e4 0x10 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080154e4 network::display_ip()
- .text._ZN7network15display_netmaskEv
- 0x00000000080154f4 0x48 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080154f4 network::display_netmask()
- .text._ZN7network15display_gatewayEv
- 0x000000000801553c 0x40 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x000000000801553c network::display_gateway()
- .text._ZN7network21display_emac_shutdownEv
- 0x000000000801557c 0x64 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x000000000801557c network::display_emac_shutdown()
- .text._ZN7network19display_dhcp_statusENS_4dhcp12ClientStatusE
- 0x00000000080155e0 0x14 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080155e0 network::display_dhcp_status(network::dhcp::ClientStatus)
- .text._ZL24spi_flash_cmd_wait_readym
- 0x00000000080155f4 0x7c ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x08016260 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ .text._ZN3net19display_emac_configEv
+ 0x08016268 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x08016268 net::display_emac_config()
+ .text._ZN3net18display_emac_startEv
+ 0x0801628c 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x0801628c net::display_emac_start()
+ .text._ZN3net19display_emac_statusEb
+ 0x080162b0 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x080162b0 net::display_emac_status(bool)
+ .text._ZN3net10display_ipEv
+ 0x080162e8 0x10 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x080162e8 net::display_ip()
+ .text._ZN3net15display_netmaskEv
+ 0x080162f8 0x44 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x080162f8 net::display_netmask()
+ .text._ZN3net15display_gatewayEv
+ 0x0801633c 0x40 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x0801633c net::display_gateway()
.text._ZL20spi_flash_read_writePKhjS0_Phj
- 0x0000000008015670 0x34 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x0801637c 0x34 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ .text._ZL24spi_flash_cmd_wait_readym
+ 0x080163b0 0x88 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
.text._ZL22spi_flash_write_commonPKhjS0_jb
- 0x00000000080156a4 0x60 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x08016438 0x64 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
.text._Z18spi_flash_get_sizev
- 0x0000000008015704 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015704 spi_flash_get_size()
+ 0x0801649c 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x0801649c spi_flash_get_size()
.text._Z25spi_flash_get_sector_sizev
- 0x0000000008015710 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015710 spi_flash_get_sector_size()
+ 0x080164a8 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080164a8 spi_flash_get_sector_size()
.text._Z18spi_flash_get_namev
- 0x000000000801571c 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x000000000801571c spi_flash_get_name()
+ 0x080164b4 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080164b4 spi_flash_get_name()
.text._Z25spi_flash_cmd_write_multimjPKh
- 0x0000000008015728 0x74 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015728 spi_flash_cmd_write_multi(unsigned long, unsigned int, unsigned char const*)
+ 0x080164c0 0x74 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080164c0 spi_flash_cmd_write_multi(unsigned long, unsigned int, unsigned char const*)
.text._Z23spi_flash_cmd_read_fastmjPh
- 0x000000000801579c 0x58 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x000000000801579c spi_flash_cmd_read_fast(unsigned long, unsigned int, unsigned char*)
+ 0x08016534 0x58 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x08016534 spi_flash_cmd_read_fast(unsigned long, unsigned int, unsigned char*)
.text._Z19spi_flash_cmd_erasemj
- 0x00000000080157f4 0x70 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x00000000080157f4 spi_flash_cmd_erase(unsigned long, unsigned int)
- .text._Z26spi_flash_cmd_write_statush
- 0x0000000008015864 0x28 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015864 spi_flash_cmd_write_status(unsigned char)
+ 0x0801658c 0x70 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x0801658c spi_flash_cmd_erase(unsigned long, unsigned int)
.text._Z15spi_flash_probejjj
- 0x000000000801588c 0x68 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x000000000801588c spi_flash_probe(unsigned int, unsigned int, unsigned int)
+ 0x080165fc 0x58 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080165fc spi_flash_probe(unsigned int, unsigned int, unsigned int)
.text._Z23spi_flash_probe_winbondP9spi_flashPh
- 0x00000000080158f4 0x54 ../lib-flash/lib_gd32/libflash.a(winbond.o)
- 0x00000000080158f4 spi_flash_probe_winbond(spi_flash*, unsigned char*)
+ 0x08016654 0x50 ../lib-flash/lib_gd32/libflash.a(winbond.o)
+ 0x08016654 spi_flash_probe_winbond(spi_flash*, unsigned char*)
.text._Z8spi_initv
- 0x0000000008015948 0x4c ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015948 spi_init()
+ 0x080166a4 0x50 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080166a4 spi_init()
.text._Z8spi_xfermPKhPhm
- 0x0000000008015994 0x48 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
- 0x0000000008015994 spi_xfer(unsigned long, unsigned char const*, unsigned char*, unsigned long)
- .text._Z9get_timerm
- 0x00000000080159dc 0x18 ../lib-flash/lib_gd32/libflash.a(get_timer.o)
- 0x00000000080159dc get_timer(unsigned long)
- .text._Z26spi_flash_probe_gigadeviceP9spi_flashPh
- 0x00000000080159f4 0x44 ../lib-flash/lib_gd32/libflash.a(gigadevice.o)
- 0x00000000080159f4 spi_flash_probe_gigadevice(spi_flash*, unsigned char*)
- .text._Z24spi_flash_probe_macronixP9spi_flashPh
- 0x0000000008015a38 0x4c ../lib-flash/lib_gd32/libflash.a(macronix.o)
- 0x0000000008015a38 spi_flash_probe_macronix(spi_flash*, unsigned char*)
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.text._ZN10properties17convert_json_fileEPcmb
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- 0x0000000008015a84 properties::convert_json_file(char*, unsigned long, bool)
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.text._ZN17PropertiesBuilderC2EPKcPcm
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.text._ZN17PropertiesBuilder12AddIpAddressEPKcmb
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- 0x0000000008015c78 PropertiesBuilder::AddIpAddress(char const*, unsigned long, bool)
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.text._ZN17PropertiesBuilder10AddCommentEPKc
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.text._ZN14ReadConfigFileC2EPFvPvPKcES0_
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.text._ZN14ReadConfigFileD2Ev
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.text._ZN14ReadConfigFile4ReadEPKcj
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.text._ZN5Sscan4CharEPKcS1_PcRm
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.text._ZN5Sscan9IpAddressEPKcS1_Rm
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- 0x0000000008015ddc Sscan::IpAddress(char const*, char const*, unsigned long&)
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.text._ZN5Sscan6Uint16EPKcS1_Rt
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.text._ZN5Sscan5Uint8EPKcS1_Rh
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+ 0x08016b9e Sscan::Uint8(char const*, char const*, unsigned char&)
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.text._ZN5Sscan9checkNameEPKcS1_
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.text._ZN7Display9PrintInfoEv.isra.0
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+ .text._ZN7display7timeoutL9gpio_initEv
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.text._ZN7Display6DetectEN7display4TypeE
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.text._ZN7DisplayC2Ev
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.text._ZN7Ssd1306D2Ev
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.text._ZN7Ssd13069SetCursorEm
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.text._ZN7Ssd13069PrintInfoEv
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.text._ZN7Ssd1306D0Ev
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.text._ZN7HAL_I2C5SetupEv
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.text._ZN7Ssd13067PutCharEi
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.text._ZN7Ssd13069PutStringEPKc
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.text._ZN7Ssd13064TextEPKcm
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.text._ZN7Ssd130611InitMembersEv
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.text._ZN7Ssd1306C2E10TOledPanel
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.text._ZN7Ssd130611SendCommandEh
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.text._ZN7Ssd130612SetCursorPosEmm
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.text._ZN7Ssd13068TextLineEmPKcm
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.text._ZN7Ssd13069ClearLineEm
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.text._ZN7Ssd13068SetSleepEb
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.text._ZN7Ssd130611SetContrastEh
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.text._ZN7Ssd130617SetFlipVerticallyEb
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.text._ZN7Ssd130611CheckSH1106Ev
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.text._ZN7Ssd13063ClsEv
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.text._ZN7Ssd13065StartEv
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.text._ZN15FirmwareVersionC2EPKcS1_S1_
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+ 0x08017194 FirmwareVersion::FirmwareVersion(char const*, char const*, char const*)
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+ .text._ZN8Hardware8ledblinkEv
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+ .text._ZN8Hardware19SoftwareTimerChangeElm.isra.0
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.text._ZN8Hardware7SetModeEN8hardware8ledblink4ModeE
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.text._ZN8Hardware15SetModeWithLockEN8hardware8ledblink4ModeEb
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+ .text._ZN12remoteconfig8timedateL4atoiEPKcm
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+ .text._ZN8Hardware19SoftwareTimerChangeElm.isra.0
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.text._ZN8HardwareC2Ev
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.text._ZN8Hardware6RebootEv
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+ 0x080177a4 Hardware::Reboot()
+ .text.console_putc
+ 0x080177f4 0x4 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x080177f4 console_putc
+ .text.console_puts
+ 0x080177f8 0x4 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x080177f8 console_puts
+ .text.console_error
+ 0x080177fc 0x24 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x080177fc console_error
+ .text.console_set_fg_color
+ 0x08017820 0x44 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x08017820 console_set_fg_color
+ .text.console_status
+ 0x08017864 0x30 ../lib-hal/lib_gd32/libhal.a(console.o)
+ 0x08017864 console_status
+ .text.stack_debug_init
+ 0x08017894 0x20 ../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ 0x08017894 stack_debug_init
+ .text._Z17stack_debug_printv
+ 0x080178b4 0x88 ../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ 0x080178b4 stack_debug_print()
+ .text._Z15stack_debug_runv
+ 0x0801793c 0x20 ../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ 0x0801793c stack_debug_run()
.text.SystemInit
- 0x0000000008016b80 0x170 ../lib-gd32/lib_gd32/libgd32.a(system_gd32f4xx.o)
- 0x0000000008016b80 SystemInit
+ 0x0801795c 0x17c ../lib-gd32/lib_gd32/libgd32.a(system_gd32f4xx.o)
+ 0x0801795c SystemInit
.text.dma_deinit
- 0x0000000008016cf0 0x56 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016cf0 dma_deinit
+ 0x08017ad8 0x58 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
+ 0x08017ad8 dma_deinit
.text.dma_single_data_mode_init
- 0x0000000008016d46 0x7e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016d46 dma_single_data_mode_init
+ 0x08017b30 0x7e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
+ 0x08017b30 dma_single_data_mode_init
.text.dma_circulation_disable
- 0x0000000008016dc4 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016dc4 dma_circulation_disable
+ 0x08017bae 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
+ 0x08017bae dma_circulation_disable
.text.dma_channel_subperipheral_select
- 0x0000000008016dd4 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016dd4 dma_channel_subperipheral_select
- .text.dma_flag_clear
- 0x0000000008016de8 0x34 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016de8 dma_flag_clear
- .text.dma_interrupt_flag_get
- 0x0000000008016e1c 0x17e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016e1c dma_interrupt_flag_get
- .text.dma_interrupt_flag_clear
- 0x0000000008016f9a 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016f9a dma_interrupt_flag_clear
- .text.dma_interrupt_disable
- 0x0000000008016f9e 0x1e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008016f9e dma_interrupt_disable
+ 0x08017bbe 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
+ 0x08017bbe dma_channel_subperipheral_select
+ *fill* 0x08017bd2 0x2
.text.enet_software_reset
- 0x0000000008016fbc 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008016fbc enet_software_reset
+ 0x08017bd4 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017bd4 enet_software_reset
.text.enet_descriptors_chain_init
- 0x0000000008016fe4 0x90 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008016fe4 enet_descriptors_chain_init
- .text.enet_frame_receive
- 0x0000000008017074 0x98 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017074 enet_frame_receive
- .text.enet_frame_transmit
- 0x000000000801710c 0x84 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000000801710c enet_frame_transmit
+ 0x08017bfc 0x90 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017bfc enet_descriptors_chain_init
.text.enet_transmit_checksum_config
- 0x0000000008017190 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017190 enet_transmit_checksum_config
+ 0x08017c8c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017c8c enet_transmit_checksum_config
.text.enet_mac_address_set
- 0x000000000801719c 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000000801719c enet_mac_address_set
+ 0x08017c98 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017c98 enet_mac_address_set
.text.enet_rx_enable
- 0x00000000080171b0 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080171b0 enet_rx_enable
+ 0x08017cac 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017cac enet_rx_enable
.text.enet_phy_write_read
- 0x00000000080171cc 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080171cc enet_phy_write_read
+ 0x08017cc8 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017cc8 enet_phy_write_read
.text.enet_init
- 0x0000000008017220 0x2a0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017220 enet_init
+ 0x08017d1c 0x2a4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017d1c enet_init
.text.enet_txfifo_flush
- 0x00000000080174c0 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080174c0 enet_txfifo_flush
+ 0x08017fc0 0x2c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017fc0 enet_txfifo_flush
.text.enet_tx_enable
- 0x00000000080174e4 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080174e4 enet_tx_enable
+ 0x08017fec 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08017fec enet_tx_enable
.text.enet_enable
- 0x0000000008017508 0xe ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017508 enet_enable
- *fill* 0x0000000008017516 0x2
+ 0x08018010 0xe ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08018010 enet_enable
+ *fill* 0x0801801e 0x2
.text.enet_desc_information_get
- 0x0000000008017518 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017518 enet_desc_information_get
- .text.enet_rxframe_drop
- 0x000000000801756c 0x64 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000000801756c enet_rxframe_drop
- .text.enet_rxframe_size_get
- 0x00000000080175d0 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080175d0 enet_rxframe_size_get
+ 0x08018020 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08018020 enet_desc_information_get
.text.enet_initpara_reset
- 0x000000000801761c 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000000801761c enet_initpara_reset
+ 0x08018074 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08018074 enet_initpara_reset
.text.enet_deinit
- 0x0000000008017644 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008017644 enet_deinit
- *fill* 0x000000000801765e 0x2
+ 0x0801809c 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x0801809c enet_deinit
+ *fill* 0x080180b6 0x2
.text.fwdgt_enable
- 0x0000000008017660 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008017660 fwdgt_enable
+ 0x080180b8 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x080180b8 fwdgt_enable
.text.fwdgt_counter_reload
- 0x0000000008017670 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008017670 fwdgt_counter_reload
+ 0x080180c8 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x080180c8 fwdgt_counter_reload
.text.fwdgt_config
- 0x0000000008017680 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008017680 fwdgt_config
+ 0x080180d8 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x080180d8 fwdgt_config
.text.gpio_mode_set
- 0x00000000080176d4 0x44 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x00000000080176d4 gpio_mode_set
+ 0x0801812c 0x44 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x0801812c gpio_mode_set
.text.gpio_output_options_set
- 0x0000000008017718 0x38 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008017718 gpio_output_options_set
+ 0x08018170 0x38 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08018170 gpio_output_options_set
.text.gpio_bit_set
- 0x0000000008017750 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008017750 gpio_bit_set
+ 0x080181a8 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x080181a8 gpio_bit_set
.text.gpio_bit_reset
- 0x0000000008017754 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008017754 gpio_bit_reset
+ 0x080181ac 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x080181ac gpio_bit_reset
.text.gpio_af_set
- 0x0000000008017758 0x60 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008017758 gpio_af_set
+ 0x080181b0 0x60 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x080181b0 gpio_af_set
.text.pmu_backup_ldo_config
- 0x00000000080177b8 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
- 0x00000000080177b8 pmu_backup_ldo_config
+ 0x08018210 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
+ 0x08018210 pmu_backup_ldo_config
.text.pmu_backup_write_enable
- 0x00000000080177d0 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
- 0x00000000080177d0 pmu_backup_write_enable
+ 0x08018228 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
+ 0x08018228 pmu_backup_write_enable
.text.rcu_periph_clock_enable
- 0x00000000080177e0 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x00000000080177e0 rcu_periph_clock_enable
+ 0x08018238 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08018238 rcu_periph_clock_enable
.text.rcu_periph_clock_disable
- 0x00000000080177fa 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x00000000080177fa rcu_periph_clock_disable
+ 0x08018252 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08018252 rcu_periph_clock_disable
.text.rcu_periph_reset_enable
- 0x0000000008017816 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008017816 rcu_periph_reset_enable
+ 0x0801826e 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x0801826e rcu_periph_reset_enable
.text.rcu_periph_reset_disable
- 0x000000000801781a 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801781a rcu_periph_reset_disable
- *fill* 0x000000000801781e 0x2
+ 0x08018272 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08018272 rcu_periph_reset_disable
+ *fill* 0x08018276 0x2
.text.rcu_ckout0_config
- 0x0000000008017820 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008017820 rcu_ckout0_config
+ 0x08018278 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08018278 rcu_ckout0_config
.text.rcu_timer_clock_prescaler_config
- 0x0000000008017838 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008017838 rcu_timer_clock_prescaler_config
+ 0x08018290 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08018290 rcu_timer_clock_prescaler_config
.text.rcu_clock_freq_get
- 0x0000000008017858 0xe8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008017858 rcu_clock_freq_get
+ 0x080182b0 0xe8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x080182b0 rcu_clock_freq_get
.text.syscfg_enet_phy_interface_config
- 0x0000000008017940 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
- 0x0000000008017940 syscfg_enet_phy_interface_config
+ 0x08018398 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
+ 0x08018398 syscfg_enet_phy_interface_config
.text.timer_deinit
- 0x0000000008017958 0x14c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017958 timer_deinit
+ 0x080183b0 0x14c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080183b0 timer_deinit
+ .text.timer_struct_para_init
+ 0x080184fc 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080184fc timer_struct_para_init
.text.timer_init
- 0x0000000008017aa4 0x7c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017aa4 timer_init
+ 0x0801850c 0x68 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801850c timer_init
.text.timer_enable
- 0x0000000008017b20 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b20 timer_enable
- .text.timer_interrupt_enable
- 0x0000000008017b2a 0x8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b2a timer_interrupt_enable
- .text.timer_interrupt_flag_clear
- 0x0000000008017b32 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b32 timer_interrupt_flag_clear
- .text.timer_flag_clear
- 0x0000000008017b38 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b38 timer_flag_clear
+ 0x08018574 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08018574 timer_enable
+ .text.timer_counter_value_config
+ 0x0801857e 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801857e timer_counter_value_config
.text.timer_channel_output_mode_config
- 0x0000000008017b3e 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b3e timer_channel_output_mode_config
+ 0x08018582 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08018582 timer_channel_output_mode_config
.text.timer_channel_output_pulse_value_config
- 0x0000000008017b8a 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008017b8a timer_channel_output_pulse_value_config
- *fill* 0x0000000008017ba6 0x2
+ 0x080185ce 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080185ce timer_channel_output_pulse_value_config
+ .text.timer_flag_clear
+ 0x080185ea 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080185ea timer_flag_clear
+ .text.timer_interrupt_enable
+ 0x080185f0 0x8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080185f0 timer_interrupt_enable
+ .text.timer_interrupt_flag_clear
+ 0x080185f8 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080185f8 timer_interrupt_flag_clear
+ *fill* 0x080185fe 0x2
.text.usart_deinit
- 0x0000000008017ba8 0xc4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017ba8 usart_deinit
+ 0x08018600 0xc4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08018600 usart_deinit
.text.usart_baudrate_set
- 0x0000000008017c6c 0x88 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017c6c usart_baudrate_set
+ 0x080186c4 0x88 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080186c4 usart_baudrate_set
.text.usart_parity_config
- 0x0000000008017cf4 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017cf4 usart_parity_config
+ 0x0801874c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x0801874c usart_parity_config
.text.usart_word_length_set
- 0x0000000008017d04 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d04 usart_word_length_set
+ 0x0801875c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x0801875c usart_word_length_set
.text.usart_stop_bit_set
- 0x0000000008017d14 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d14 usart_stop_bit_set
+ 0x0801876c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x0801876c usart_stop_bit_set
.text.usart_transmit_config
- 0x0000000008017d24 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d24 usart_transmit_config
+ 0x0801877c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x0801877c usart_transmit_config
.text.usart_receive_config
- 0x0000000008017d30 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d30 usart_receive_config
+ 0x08018788 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08018788 usart_receive_config
.text.usart_hardware_flow_rts_config
- 0x0000000008017d3c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d3c usart_hardware_flow_rts_config
+ 0x08018794 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08018794 usart_hardware_flow_rts_config
.text.usart_hardware_flow_cts_config
- 0x0000000008017d48 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d48 usart_hardware_flow_cts_config
- .text.usart_dma_transmit_config
- 0x0000000008017d54 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d54 usart_dma_transmit_config
+ 0x080187a8 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080187a8 usart_hardware_flow_cts_config
.text.usart_flag_get
- 0x0000000008017d60 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d60 usart_flag_get
- .text.usart_flag_clear
- 0x0000000008017d70 0x16 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d70 usart_flag_clear
- .text.usart_interrupt_enable
- 0x0000000008017d86 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d86 usart_interrupt_enable
- .text.usart_interrupt_disable
- 0x0000000008017d9a 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d9a usart_interrupt_disable
- .text.usart_interrupt_flag_clear
- 0x0000000008017d9e 0x16 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008017d9e usart_interrupt_flag_clear
- .text.uart0_init
- 0x0000000008017db4 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- 0x0000000008017db4 uart0_init
- .text.uart0_putc
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- 0x0000000008017dd4 uart0_putc
+ 0x080187bc 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080187bc usart_flag_get
.text._Z14bkp_data_write22bkp_data_register_enumt
- 0x0000000008017e08 0x10 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
- 0x0000000008017e08 bkp_data_write(bkp_data_register_enum, unsigned short)
+ 0x080187cc 0x1c ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
+ 0x080187cc bkp_data_write(bkp_data_register_enum, unsigned short)
.text._Z13bkp_data_read22bkp_data_register_enum
- 0x0000000008017e18 0x14 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
- 0x0000000008017e18 bkp_data_read(bkp_data_register_enum)
+ 0x080187e8 0x20 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
+ 0x080187e8 bkp_data_read(bkp_data_register_enum)
+ .text._Z15gd32_uart_beginmmmmm
+ 0x08018808 0x36c ../lib-gd32/lib_gd32/libgd32.a(gd32_uart.o)
+ 0x08018808 gd32_uart_begin(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
+ .text._Z15mac_address_getPh
+ 0x08018b74 0x24 ../lib-gd32/lib_gd32/libgd32.a(mac_address.o)
+ 0x08018b74 mac_address_get(unsigned char*)
+ .text._Z13timer6_configv
+ 0x08018b98 0x74 ../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ 0x08018b98 timer6_config()
+ .text._Z11udelay_initv
+ 0x08018c0c 0x28 ../lib-gd32/lib_gd32/libgd32.a(udelay.o)
+ 0x08018c0c udelay_init()
+ .text._Z6udelaymm
+ 0x08018c34 0x30 ../lib-gd32/lib_gd32/libgd32.a(udelay.o)
+ 0x08018c34 udelay(unsigned long, unsigned long)
+ .text.systick_config
+ 0x08018c64 0x3c ../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ 0x08018c64 systick_config
+ .text.SysTick_Handler
+ 0x08018ca0 0x10 ../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ 0x08018ca0 SysTick_Handler
.text._Z13gd32_adc_initv
- 0x0000000008017e2c 0x9c ../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o)
- 0x0000000008017e2c gd32_adc_init()
- .text._ZL5_stopv.isra.0
- 0x0000000008017ec8 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018cb0 0x9c ../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o)
+ 0x08018cb0 gd32_adc_init()
+ .text._ZL9send_stopv.isra.0
+ 0x08018d4c 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
.text.gd32_i2c_begin
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- 0x0000000008017eec gd32_i2c_begin
+ 0x08018d70 0x98 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018d70 gd32_i2c_begin
.text.gd32_i2c_set_baudrate
- 0x0000000008017f80 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
- 0x0000000008017f80 gd32_i2c_set_baudrate
+ 0x08018e08 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018e08 gd32_i2c_set_baudrate
.text.gd32_i2c_set_address
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- 0x0000000008017f90 gd32_i2c_set_address
+ 0x08018e18 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018e18 gd32_i2c_set_address
.text.gd32_i2c_write
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- 0x0000000008017f9c gd32_i2c_write
+ 0x08018e24 0xcc ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018e24 gd32_i2c_write
.text.gd32_i2c_read
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- 0x0000000008018068 gd32_i2c_read
- .text._ZL8_cs_highv
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- .text._ZL7_cs_lowv
- 0x00000000080181c8 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
- .text._ZL10_send_byteh
- 0x00000000080181e0 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x08018ef0 0x14c ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x08018ef0 gd32_i2c_read
+ .text._ZL7cs_highv
+ 0x0801903c 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ .text._ZL6cs_lowv
+ 0x08019054 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ .text._ZL9send_byteh
+ 0x0801906c 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
.text._Z14gd32_spi_beginv
- 0x0000000008018204 0xa4 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
- 0x0000000008018204 gd32_spi_begin()
+ 0x08019088 0xa4 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x08019088 gd32_spi_begin()
.text._Z21gd32_spi_set_speed_hzm
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- 0x00000000080182a8 gd32_spi_set_speed_hz(unsigned long)
+ 0x0801912c 0x6c ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x0801912c gd32_spi_set_speed_hz(unsigned long)
.text._Z20gd32_spi_setDataModeh
- 0x000000000801831c 0x30 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
- 0x000000000801831c gd32_spi_setDataMode(unsigned char)
+ 0x08019198 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x08019198 gd32_spi_setDataMode(unsigned char)
.text._Z19gd32_spi_chipSelecth
- 0x000000000801834c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
- 0x000000000801834c gd32_spi_chipSelect(unsigned char)
+ 0x080191b8 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x080191b8 gd32_spi_chipSelect(unsigned char)
.text._Z19gd32_spi_transfernbPKcPcm
- 0x0000000008018358 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
- 0x0000000008018358 gd32_spi_transfernb(char const*, char*, unsigned long)
+ 0x080191d4 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x080191d4 gd32_spi_transfernb(char const*, char*, unsigned long)
.text._Z16gd32_spi_writenbPKcm
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- 0x0000000008018380 gd32_spi_writenb(char const*, unsigned long)
- .text._Z10_gpio_initm
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- 0x00000000080183a0 _gpio_init(unsigned long)
- .text.gd32_uart_begin
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- 0x0000000008018600 gd32_uart_begin
- .text._Z15mac_address_getPh
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- 0x0000000008018720 mac_address_get(unsigned char*)
- .text._Z11udelay_initv
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- 0x0000000008018744 udelay_init()
- .text._Z6udelaymm
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- 0x000000000801876c udelay(unsigned long, unsigned long)
+ 0x080191fc 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x080191fc gd32_spi_writenb(char const*, unsigned long)
+ .text.uart0_init
+ 0x0801921c 0x20 ../lib-gd32/lib_gd32/libgd32.a(uart0.o)
+ 0x0801921c uart0_init
+ .text.uart0_putc
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+ 0x0801923c uart0_putc
+ .text.uart0_puts
+ 0x08019270 0x1e ../lib-gd32/lib_gd32/libgd32.a(uart0.o)
+ 0x08019270 uart0_puts
+ *fill* 0x0801928e 0x2
.text.adc_clock_config
- 0x000000000801879c 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x000000000801879c adc_clock_config
+ 0x08019290 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019290 adc_clock_config
.text.adc_special_function_config
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- 0x00000000080187bc adc_special_function_config
+ 0x080192b0 0x50 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x080192b0 adc_special_function_config
.text.adc_data_alignment_config
- 0x000000000801880c 0x12 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x000000000801880c adc_data_alignment_config
+ 0x08019300 0x12 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019300 adc_data_alignment_config
.text.adc_enable
- 0x000000000801881e 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x000000000801881e adc_enable
+ 0x08019312 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019312 adc_enable
.text.adc_calibration_enable
- 0x000000000801882e 0x22 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x000000000801882e adc_calibration_enable
+ 0x08019322 0x22 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019322 adc_calibration_enable
.text.adc_channel_16_to_18
- 0x0000000008018850 0x50 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x0000000008018850 adc_channel_16_to_18
+ 0x08019344 0x50 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019344 adc_channel_16_to_18
.text.adc_channel_length_config
- 0x00000000080188a0 0x3a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x00000000080188a0 adc_channel_length_config
+ 0x08019394 0x3a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x08019394 adc_channel_length_config
.text.adc_inserted_channel_config
- 0x00000000080188da 0x5e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x00000000080188da adc_inserted_channel_config
+ 0x080193ce 0x60 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x080193ce adc_inserted_channel_config
.text.adc_external_trigger_config
- 0x0000000008018938 0x2c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x0000000008018938 adc_external_trigger_config
+ 0x0801942e 0x2c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x0801942e adc_external_trigger_config
.text.adc_software_trigger_enable
- 0x0000000008018964 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
- 0x0000000008018964 adc_software_trigger_enable
+ 0x0801945a 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
+ 0x0801945a adc_software_trigger_enable
+ *fill* 0x08019476 0x2
.text.i2c_clock_config
- 0x0000000008018980 0xb8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018980 i2c_clock_config
+ 0x08019478 0xc4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019478 i2c_clock_config
.text.i2c_ack_config
- 0x0000000008018a38 0x12 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a38 i2c_ack_config
+ 0x0801953c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x0801953c i2c_ack_config
.text.i2c_ackpos_config
- 0x0000000008018a4a 0x12 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a4a i2c_ackpos_config
+ 0x08019548 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019548 i2c_ackpos_config
.text.i2c_master_addressing
- 0x0000000008018a5c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a5c i2c_master_addressing
+ 0x08019554 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019554 i2c_master_addressing
.text.i2c_enable
- 0x0000000008018a6c 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a6c i2c_enable
+ 0x08019564 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019564 i2c_enable
.text.i2c_start_on_bus
- 0x0000000008018a76 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a76 i2c_start_on_bus
+ 0x0801956e 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x0801956e i2c_start_on_bus
.text.i2c_stop_on_bus
- 0x0000000008018a80 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a80 i2c_stop_on_bus
+ 0x08019578 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019578 i2c_stop_on_bus
.text.i2c_data_transmit
- 0x0000000008018a8a 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a8a i2c_data_transmit
+ 0x08019582 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019582 i2c_data_transmit
.text.i2c_data_receive
- 0x0000000008018a8e 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a8e i2c_data_receive
+ 0x08019586 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x08019586 i2c_data_receive
.text.i2c_flag_get
- 0x0000000008018a94 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018a94 i2c_flag_get
+ 0x0801958c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x0801958c i2c_flag_get
.text.i2c_flag_clear
- 0x0000000008018aa4 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
- 0x0000000008018aa4 i2c_flag_clear
+ 0x0801959c 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
+ 0x0801959c i2c_flag_clear
.text.spi_i2s_deinit
- 0x0000000008018ac8 0x94 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
- 0x0000000008018ac8 spi_i2s_deinit
+ 0x080195c0 0x94 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x080195c0 spi_i2s_deinit
.text.spi_init
- 0x0000000008018b5c 0x30 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
- 0x0000000008018b5c spi_init
+ 0x08019654 0x30 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x08019654 spi_init
.text.spi_enable
- 0x0000000008018b8c 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
- 0x0000000008018b8c spi_enable
+ 0x08019684 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x08019684 spi_enable
.text.spi_disable
- 0x0000000008018b96 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
- 0x0000000008018b96 spi_disable
+ 0x0801968e 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x0801968e spi_disable
+ .text.spi_nss_output_enable
+ 0x08019698 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x08019698 spi_nss_output_enable
+ .text.spi_nss_output_disable
+ 0x080196a2 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ 0x080196a2 spi_nss_output_disable
+ .text.__libc_init_array
+ 0x080196ac 0x44 ../lib-clib/lib_gd32/libclib.a(init.o)
+ 0x080196ac __libc_init_array
+ .text.memcpy 0x080196f0 0x16 ../lib-clib/lib_gd32/libclib.a(memcpy.o)
+ 0x080196f0 memcpy
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+ 0x08019706 memmove
+ .text.memset 0x08019734 0x44 ../lib-clib/lib_gd32/libclib.a(memset.o)
+ 0x08019734 memset
+ .text._itostr 0x08019778 0x78 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ .text._xputch 0x080197f0 0x30 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ .text._format_int
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+ .text._format_hex
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+ .text._vprintf
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+ 0x08019cfc printf
+ *fill* 0x08019d1a 0x2
+ .text.sprintf 0x08019d1c 0x30 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ 0x08019d1c sprintf
+ .text.snprintf
+ 0x08019d4c 0x30 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ 0x08019d4c snprintf
+ .text.vsnprintf
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+ 0x08019d7c vsnprintf
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+ 0x08019da6 puts
+ *fill* 0x08019db6 0x2
+ .text.random 0x08019db8 0x20 ../lib-clib/lib_gd32/libclib.a(random.o)
+ 0x08019db8 random
+ .text.strtok 0x08019dd8 0x54 ../lib-clib/lib_gd32/libclib.a(strtok.o)
+ 0x08019dd8 strtok
+ .text.uuid_unparse_x
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+ .text.uuid_unparse
+ 0x08019eb0 0xc ../lib-clib/lib_gd32/libclib.a(uuid_unparse.o)
+ 0x08019eb0 uuid_unparse
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.rodata._ZN10ArtNetNode12SetShortNameEmPKc.str1.1
- 0x000000000801a362 0x8 ../lib-artnet/lib_gd32/libartnet.a(artnetnode.o)
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.rodata._ZN10ArtNetNode18GetLongNameDefaultEPc.str1.1
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- 0x2c (size before relaxing)
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.rodata._ZN6artnetL7NODE_IDE
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+ .rodata._ZN10ArtNetNode9HandleDmxEv.str1.4
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+ .rodata._ZN10ArtNetNode14SendPollRelplyEmmPN6artnet12ArtPollQueueE.str1.1
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.rodata._ZN10ArtNetNode5PrintEv.str1.1
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- 0x000000000801a4be 0x1a ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
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+ .rodata._ZN17PropertiesBuilder3AddIPKcEEbS2_T_bi.isra.0.str1.1
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.rodata._ZN17PropertiesBuilder3AddEPKcb.isra.0.str1.1
- 0x000000000801a4be 0x18 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
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.rodata._ZN12ArtNetParams16callbackFunctionEPKc.str1.1
- 0x000000000801a4be 0x12 ../lib-artnet/lib_gd32/libartnet.a(artnetparams.o)
- 0x1d (size before relaxing)
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.rodata._ZN12ArtNetParams7BuilderEPKN12artnetparams6ParamsEPcmRm.str1.1
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- .rodata.CSWTCH.100
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- 0x000000000801a534 0xb ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
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.rodata._ZN17ArtNetParamsConst13MAP_UNIVERSE0E
- 0x000000000801a53f 0xe ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
- 0x000000000801a53f ArtNetParamsConst::MAP_UNIVERSE0
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.rodata._ZN17ArtNetParamsConst13PROTOCOL_PORTE
- 0x000000000801a54d 0x40 ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
- 0x000000000801a54d ArtNetParamsConst::PROTOCOL_PORT
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.rodata._ZN17ArtNetParamsConst15RDM_ENABLE_PORTE
- 0x000000000801a58d 0x48 ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
- 0x000000000801a58d ArtNetParamsConst::RDM_ENABLE_PORT
+ 0x0801de67 0x48 ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
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.rodata._ZN17ArtNetParamsConst19DESTINATION_IP_PORTE
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- 0x000000000801a5d5 ArtNetParamsConst::DESTINATION_IP_PORT
+ 0x0801deaf 0x60 ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
+ 0x0801deaf ArtNetParamsConst::DESTINATION_IP_PORT
+ .rodata._ZN17ArtNetParamsConst10ENABLE_RDME
+ 0x0801df0f 0xb ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
+ 0x0801df0f ArtNetParamsConst::ENABLE_RDM
.rodata._ZN17ArtNetParamsConst9FILE_NAMEE
- 0x000000000801a635 0xb ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
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- .rodata._ZN6artnetL7NODE_IDE
- 0x000000000801a640 0x8 ../lib-artnet/lib_gd32/libartnet.a(handlerdm.o)
+ 0x0801df1a 0xb ../lib-artnet/lib_gd32/libartnet.a(artnetparamsconst.o)
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+ .rodata._ZL7UID_ALL
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+ .rodata._ZL7UID_ALL
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.rodata._ZN6artnetL7NODE_IDE
- 0x000000000801a648 0x8 ../lib-artnet/lib_gd32/libartnet.a(handlerdmin.o)
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+ .rodata._ZN12remoteconfig3rdm14json_get_queueEPcm.str1.1
+ 0x0801df39 0x9 ../lib-artnet/lib_gd32/libartnet.a(json_get_queue.o)
+ .rodata._ZN12remoteconfig3rdm12json_get_rdmEPcm.str1.1
+ 0x0801df39 0xd ../lib-artnet/lib_gd32/libartnet.a(json_get_rdm.o)
+ .rodata._ZN12remoteconfig3rdm12json_get_todEcPcm.str1.1
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.rodata._ZN11ArtNetConst6OEM_IDE
- 0x000000000801a650 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetconst.o)
- 0x000000000801a650 ArtNetConst::OEM_ID
+ 0x0801df39 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetconst.o)
+ 0x0801df39 ArtNetConst::OEM_ID
.rodata._ZN11ArtNetConst7ESTA_IDE
- 0x000000000801a652 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetconst.o)
- 0x000000000801a652 ArtNetConst::ESTA_ID
+ 0x0801df3b 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetconst.o)
+ 0x0801df3b ArtNetConst::ESTA_ID
.rodata._ZN11ArtNetConst7VERSIONE
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- 0x000000000801a656 0x9 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x14 (size before relaxing)
+ 0x0801df3d 0x2 ../lib-artnet/lib_gd32/libartnet.a(artnetconst.o)
+ 0x0801df3d ArtNetConst::VERSION
+ .rodata._ZN10E131BridgeC2Ev.str1.4
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.rodata._ZN10E131Bridge5PrintEv.str1.1
- 0x000000000801a65f 0x71 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
- 0x8a (size before relaxing)
+ 0x0801df3f 0x82 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
.rodata._ZN9E117Const21ACN_PACKET_IDENTIFIERE
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- .rodata._ZTV9ArtNetRdm
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- .rodata._ZL7UID_ALL
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- .rodata._ZTV19ArtNetRdmController
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- .rodata._ZL7UID_ALL
- 0x000000000801a740 0x6 ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a(rdmdiscovery.o)
+ 0x0801df3f 0xc ../lib-e131/lib_gd32/libe131.a(e117const.o)
+ 0x0801df3f E117Const::ACN_PACKET_IDENTIFIER
+ .rodata._ZN9E131Const7VERSIONE
+ 0x0801df4b 0x2 ../lib-e131/lib_gd32/libe131.a(e131const.o)
+ 0x0801df4b E131Const::VERSION
.rodata._ZN9RDMDevice5PrintEv.str1.1
- 0x000000000801a746 0xd4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x0801df4d 0xd3 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
.rodata._ZL12DEVICE_LABEL
- 0x000000000801a81a 0x16 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x0801df4d 0x16 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ .rodata._ZN12RDMDiscovery16CopyWorkingQueueEPcm.str1.1
+ 0x0801df63 0x37 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ .rodata._ZN12RDMDiscovery7ProcessEv.str1.1
+ 0x0801df63 0x1b ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
+ .rodata._ZL7UID_ALL
+ 0x0801df63 0x6 ../lib-rdm/lib_gd32/librdm.a(rdmdiscovery.o)
.rodata._ZN8RDMConst15MANUFACTURER_IDE
- 0x000000000801a830 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
- 0x000000000801a830 RDMConst::MANUFACTURER_ID
+ 0x0801df69 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
+ 0x0801df69 RDMConst::MANUFACTURER_ID
.rodata._ZN8RDMConst17MANUFACTURER_NAMEE
- 0x000000000801a832 0x1c ../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
- 0x000000000801a832 RDMConst::MANUFACTURER_NAME
- .rodata.uuid_unparse.str1.1
- 0x000000000801a84e 0x31 ../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- .rodata._ZN7DmxSend5PrintEv.str1.1
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- .rodata._ZTV7DmxSend
- 0x000000000801a8dc 0x48 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
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- .rodata._ZN17PropertiesBuilder3AddItEEbPKcT_bm.isra.0.str1.1
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- .rodata._ZN14DmxParamsConst10BREAK_TIMEE
- 0x000000000801a924 0xb ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
- 0x000000000801a924 DmxParamsConst::BREAK_TIME
+ 0x0801df6b 0x1c ../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
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+ .rodata._ZN17PropertiesBuilder3AddItEEbPKcT_bi.isra.0.str1.1
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.rodata._ZN14DmxParamsConst11SLOTS_COUNTE
- 0x000000000801a92f 0xc ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
- 0x000000000801a92f DmxParamsConst::SLOTS_COUNT
+ 0x0801df87 0xc ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
+ 0x0801df87 DmxParamsConst::SLOTS_COUNT
.rodata._ZN14DmxParamsConst12REFRESH_RATEE
- 0x000000000801a93b 0xd ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
- 0x000000000801a93b DmxParamsConst::REFRESH_RATE
+ 0x0801df93 0xd ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
+ 0x0801df93 DmxParamsConst::REFRESH_RATE
.rodata._ZN14DmxParamsConst8MAB_TIMEE
- 0x000000000801a948 0x9 ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
- 0x000000000801a948 DmxParamsConst::MAB_TIME
+ 0x0801dfa0 0x9 ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
+ 0x0801dfa0 DmxParamsConst::MAB_TIME
+ .rodata._ZN14DmxParamsConst10BREAK_TIMEE
+ 0x0801dfa9 0xb ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
+ 0x0801dfa9 DmxParamsConst::BREAK_TIME
.rodata._ZN14DmxParamsConst9FILE_NAMEE
- 0x000000000801a951 0xb ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
- 0x000000000801a951 DmxParamsConst::FILE_NAME
- .rodata.TIMER1_IRQHandler.str1.4
- 0x000000000801a95c 0xf ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- *fill* 0x000000000801a96b 0x1
+ 0x0801dfb4 0xb ../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
+ 0x0801dfb4 DmxParamsConst::FILE_NAME
+ .rodata._ZN12remoteconfig3dmx14json_get_portsEPcm.str1.1
+ 0x0801dfbf 0x2d ../lib-dmx/lib_gd32/libdmx.a(json_get_ports.o)
+ .rodata._ZN12remoteconfig3dmx19json_get_portstatusEcPcm.str1.1
+ 0x0801dfbf 0x96 ../lib-dmx/lib_gd32/libdmx.a(json_get_portstatus.o)
+ *fill* 0x0801dfbf 0x1
.rodata._ZL9s_DirGpio
- 0x000000000801a96c 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
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.rodata._ZL11s_aStorSize
- 0x000000000801a97c 0x68 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0801dfd0 0x6c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
.rodata._ZL12s_aSignature
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- 0x000000000801a9e8 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
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- .rodata._ZTV12StoreDmxSend
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- 0x000000000801aa00 vtable for StoreDmxSend
- .rodata._ZTV12StoreNetwork
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- 0x000000000801aa18 vtable for StoreNetwork
- .rodata._ZTV17StoreRemoteConfig
- 0x000000000801aa68 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x000000000801aa68 vtable for StoreRemoteConfig
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+ 0x0801e040 hal::utc_validate(signed char, unsigned char, long&)::s_ValidOffsets
+ .rodata._ZN14EnvParamsConst10UTC_OFFSETE
+ 0x0801e056 0xb ../lib-configstore/lib_gd32/libconfigstore.a(envparamsconst.o)
+ 0x0801e056 EnvParamsConst::UTC_OFFSET
+ .rodata._ZN14EnvParamsConst9FILE_NAMEE
+ 0x0801e061 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(envparamsconst.o)
+ 0x0801e061 EnvParamsConst::FILE_NAME
.rodata._ZN11StoreDeviceC2Ev.str1.1
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- .rodata._ZTV11StoreArtNet
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- 0x000000000801aac8 vtable for StoreArtNet
- .rodata._ZTV14StoreRDMDevice
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- 0x000000000801ab40 vtable for StoreRDMDevice
- .rodata._ZN12NetworkConst15MSG_MDNS_CONFIGE
- 0x000000000801ab70 0x11 ../lib-network/lib_gd32/libnetwork.a(networkconst.o)
- 0x000000000801ab70 NetworkConst::MSG_MDNS_CONFIG
- .rodata._ZN12NetworkConst16MSG_NETWORK_INITE
- 0x000000000801ab81 0xd ../lib-network/lib_gd32/libnetwork.a(networkconst.o)
- 0x000000000801ab81 NetworkConst::MSG_NETWORK_INIT
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.rodata._ZN12NetworkConst19MSG_NETWORK_STARTEDE
- 0x000000000801ab8e 0x10 ../lib-network/lib_gd32/libnetwork.a(networkconst.o)
- 0x000000000801ab8e NetworkConst::MSG_NETWORK_STARTED
+ 0x0801e069 0x10 ../lib-network/lib_gd32/libnetwork.a(networkconst.o)
+ 0x0801e069 NetworkConst::MSG_NETWORK_STARTED
+ .rodata._ZN12NetworkConst16MSG_NETWORK_INITE
+ 0x0801e079 0xd ../lib-network/lib_gd32/libnetwork.a(networkconst.o)
+ 0x0801e079 NetworkConst::MSG_NETWORK_INIT
.rodata._ZN4mdns6Domain5PrintEb.str1.1
- 0x000000000801ab9e 0x6 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
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.rodata._ZN4MDNS5PrintEv.str1.1
- 0x000000000801aba4 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x11 (size before relaxing)
+ 0x0801e086 0x11 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .rodata._ZN4mdnsL12DOMAIN_DNSSDE
+ 0x0801e086 0x102 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .rodata._ZN4mdnsL10s_ServicesE
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+ .rodata._ZN4mdnsL9DOMAIN_PPE
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.rodata._ZN4mdnsL10DOMAIN_DDPE
- 0x000000000801abb4 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL10DOMAIN_NTPE
- 0x000000000801abb9 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801e21c 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.rodata._ZN4mdnsL10DOMAIN_OSCE
- 0x000000000801abbe 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL10DOMAIN_TCPE
- 0x000000000801abc3 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL10DOMAIN_UDPE
- 0x000000000801abc8 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- *fill* 0x000000000801abcd 0x3
- .rodata._ZN4mdnsL10s_ServicesE
- 0x000000000801abd0 0x90 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL11DOMAIN_HTTPE
- 0x000000000801ac60 0x6 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801e221 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.rodata._ZN4mdnsL11DOMAIN_MIDIE
- 0x000000000801ac66 0xc ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801e226 0xc ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .rodata._ZN4mdnsL10DOMAIN_NTPE
+ 0x0801e232 0x5 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .rodata._ZN4mdnsL18DOMAIN_RDMNET_LLRPE
+ 0x0801e237 0xd ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .rodata._ZN4mdnsL11DOMAIN_HTTPE
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.rodata._ZN4mdnsL11DOMAIN_TFTPE
- 0x000000000801ac72 0x6 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL12DOMAIN_DNSSDE
- 0x000000000801ac78 0x102 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .rodata._ZN4mdnsL12DOMAIN_LOCALE
- 0x000000000801ad7a 0x7 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
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.rodata._ZN4mdnsL13DOMAIN_CONFIGE
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.rodata._ZL6pArray
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.rodata._ZN21DisplayUdfParamsConst13DMX_DIRECTIONE
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.rodata._ZN21DisplayUdfParamsConst9INTENSITYE
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+ 0x200036f4 ConfigStore::s_nWaitMillis
.bss._ZN11ConfigStore20s_nSpiFlashStoreSizeE
- 0x00000000200039d8 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x00000000200039d8 ConfigStore::s_nSpiFlashStoreSize
+ 0x200036f8 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x200036f8 ConfigStore::s_nSpiFlashStoreSize
+ .bss._ZN11ConfigStore15s_nStartAddressE
+ 0x200036fc 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x200036fc ConfigStore::s_nStartAddress
.bss._ZN11ConfigStore7s_StateE
- 0x00000000200039dc 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x00000000200039dc ConfigStore::s_State
- .bss._ZN11ConfigStore7s_pThisE
- 0x00000000200039e0 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x00000000200039e0 ConfigStore::s_pThis
- .bss._ZN15StoreDisplayUdf7s_pThisE
- 0x00000000200039e4 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x00000000200039e4 StoreDisplayUdf::s_pThis
- .bss._ZN12StoreDmxSend7s_pThisE
- 0x00000000200039e8 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x00000000200039e8 StoreDmxSend::s_pThis
- .bss._ZN12StoreNetwork7s_pThisE
- 0x00000000200039ec 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000200039ec StoreNetwork::s_pThis
- .bss._ZN17StoreRemoteConfig7s_pThisE
- 0x00000000200039f0 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x00000000200039f0 StoreRemoteConfig::s_pThis
- .bss._ZN11StoreArtNet18s_nPortIndexOffsetE
- 0x00000000200039f4 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000200039f4 StoreArtNet::s_nPortIndexOffset
- .bss._ZN11StoreArtNet7s_pThisE
- 0x00000000200039f8 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storeartnet.o)
- 0x00000000200039f8 StoreArtNet::s_pThis
- .bss._ZN14StoreRDMDevice7s_pThisE
- 0x00000000200039fc 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x00000000200039fc StoreRDMDevice::s_pThis
- .bss._ZN4MDNS11s_nRemoteIpE
- 0x0000000020003a00 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a00 MDNS::s_nRemoteIp
- .bss._ZN4MDNS13s_nRemotePortE
- 0x0000000020003a04 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a04 MDNS::s_nRemotePort
- .bss._ZN4MDNS16s_nBytesReceivedE
- 0x0000000020003a06 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a06 MDNS::s_nBytesReceived
- .bss._ZN4MDNS16s_pReceiveBufferE
- 0x0000000020003a08 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a08 MDNS::s_pReceiveBuffer
+ 0x20003700 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20003700 ConfigStore::s_State
+ .bss._ZN11ConfigStore16s_bHaveFlashChipE
+ 0x20003704 0x1 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20003704 ConfigStore::s_bHaveFlashChip
+ *fill* 0x20003705 0x3
.bss._ZN4MDNS7s_pThisE
- 0x0000000020003a0c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a0c MDNS::s_pThis
+ 0x20003708 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003708 MDNS::s_pThis
+ .bss._ZN4MDNS16s_pReceiveBufferE
+ 0x2000370c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x2000370c MDNS::s_pReceiveBuffer
+ .bss._ZN4MDNS16s_nBytesReceivedE
+ 0x20003710 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003710 MDNS::s_nBytesReceived
+ .bss._ZN4MDNS13s_nRemotePortE
+ 0x20003714 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003714 MDNS::s_nRemotePort
+ *fill* 0x20003716 0x2
+ .bss._ZN4MDNS11s_nRemoteIpE
+ 0x20003718 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003718 MDNS::s_nRemoteIp
.bss._ZN4MDNS9s_nHandleE
- 0x0000000020003a10 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020003a10 MDNS::s_nHandle
+ 0x2000371c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x2000371c MDNS::s_nHandle
.bss._ZN4mdnsL11s_isUnicastE
- 0x0000000020003a14 0x1 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- *fill* 0x0000000020003a15 0x3
- .bss._ZN4mdnsL13s_HostRepliesE
- 0x0000000020003a18 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003720 0x1 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.bss._ZN4mdnsL13s_RecordsDataE
- 0x0000000020003a1c 0x200 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .bss._ZN4mdnsL16s_ServiceRecordsE
- 0x0000000020003c1c 0x20 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003721 0x200 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ *fill* 0x20003921 0x3
.bss._ZN4mdnsL16s_ServiceRepliesE
- 0x0000000020003c3c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20003924 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .bss._ZN4mdnsL13s_HostRepliesE
+ 0x20003928 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .bss._ZN4mdnsL16s_ServiceRecordsE
+ 0x2000392c 0x20 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.bss._ZN7Network7s_pThisE
- 0x0000000020003c40 0x4 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000020003c40 Network::s_pThis
- .bss._ZL3s_p 0x0000000020003c44 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- .bss._ZL8s_isDhcp
- 0x0000000020003c48 0x1 ../lib-network/lib_gd32/libnetwork.a(net.o)
- *fill* 0x0000000020003c49 0x3
- .bss._ZN3net7globals10macAddressE
- 0x0000000020003c4c 0x6 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020003c4c net::globals::macAddress
- *fill* 0x0000000020003c52 0x2
- .bss._ZN3net7globals14nBroadcastMaskE
- 0x0000000020003c54 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020003c54 net::globals::nBroadcastMask
+ 0x2000394c 0x4 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x2000394c Network::s_pThis
.bss._ZN3net7globals14nOnNetworkMaskE
- 0x0000000020003c58 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020003c58 net::globals::nOnNetworkMask
- .bss._ZN3net7globals6ipInfoE
- 0x0000000020003c5c 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020003c5c net::globals::ipInfo
- .bss._ZL8s_ticker
- 0x0000000020003c70 0x4 ../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- .bss._ZL11s_arp_reply
- 0x0000000020003c74 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL13s_arp_request
- 0x0000000020003cb0 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL13s_requestType
- 0x0000000020003cec 0x4 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL22s_isProbeReplyReceived
- 0x0000000020003cf0 0x1 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- *fill* 0x0000000020003cf1 0x3
- .bss._ZL14s_dhcp_message
- 0x0000000020003cf4 0x224 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL16s_dhcp_server_ip
- 0x0000000020003f18 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL19s_dhcp_allocated_gw
- 0x0000000020003f1c 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL19s_dhcp_allocated_ip
- 0x0000000020003f20 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL24s_dhcp_allocated_netmask
- 0x0000000020003f24 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZN3netL11s_phyStatusE
- 0x0000000020003f28 0x10 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x20003950 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x20003950 net::globals::nOnNetworkMask
+ .bss._ZN3net7globals14nBroadcastMaskE
+ 0x20003954 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x20003954 net::globals::nBroadcastMask
+ .bss._ZL5s_acd
+ 0x20003958 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ .bss._ZN3netL11callback_fnE
+ 0x20003968 0x4 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .bss._ZN3net7globals13netif_defaultE
+ 0x2000396c 0x2c ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x2000396c net::globals::netif_default
+ .bss._ZN3netL8nTimerIdE
+ 0x20003998 0x4 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ .bss._ZN3netL11s_arp_replyE
+ 0x2000399c 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .bss._ZN3netL13s_arp_requestE
+ 0x200039d8 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
.bss._ZN10DisplayUdf7s_pThisE
- 0x0000000020003f38 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000020003f38 DisplayUdf::s_pThis
+ 0x20003a14 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x20003a14 DisplayUdf::s_pThis
.bss._ZN16PropertiesConfig8s_ConfigE
- 0x0000000020003f3c 0x1 ../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
- 0x0000000020003f3c PropertiesConfig::s_Config
- *fill* 0x0000000020003f3d 0x3
+ 0x20003a18 0x1 ../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
+ 0x20003a18 PropertiesConfig::s_Config
+ *fill* 0x20003a19 0x3
.bss._ZN7Display7s_pThisE
- 0x0000000020003f40 0x4 ../lib-display/lib_gd32/libdisplay.a(display.o)
- 0x0000000020003f40 Display::s_pThis
- .bss._ZL12_ClearBuffer
- 0x0000000020003f44 0x86 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
- *fill* 0x0000000020003fca 0x2
+ 0x20003a1c 0x4 ../lib-display/lib_gd32/libdisplay.a(display.o)
+ 0x20003a1c Display::s_pThis
.bss._ZN7Ssd13067s_pThisE
- 0x0000000020003fcc 0x4 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
- 0x0000000020003fcc Ssd1306::s_pThis
- .bss._ZN15FirmwareVersion17s_FirmwareVersionE
- 0x0000000020003fd0 0x16 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x0000000020003fd0 FirmwareVersion::s_FirmwareVersion
- .bss._ZN15FirmwareVersion7s_PrintE
- 0x0000000020003fe6 0x40 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x0000000020003fe6 FirmwareVersion::s_Print
- *fill* 0x0000000020004026 0x2
+ 0x20003a20 0x4 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
+ 0x20003a20 Ssd1306::s_pThis
+ .bss._ZL12_ClearBuffer
+ 0x20003a24 0x86 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
+ *fill* 0x20003aaa 0x2
.bss._ZN15FirmwareVersion7s_pThisE
- 0x0000000020004028 0x4 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x0000000020004028 FirmwareVersion::s_pThis
+ 0x20003aac 0x4 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x20003aac FirmwareVersion::s_pThis
+ .bss._ZN15FirmwareVersion7s_PrintE
+ 0x20003ab0 0x40 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x20003ab0 FirmwareVersion::s_Print
+ .bss._ZN15FirmwareVersion17s_FirmwareVersionE
+ 0x20003af0 0x16 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x20003af0 FirmwareVersion::s_FirmwareVersion
+ *fill* 0x20003b06 0x2
.bss._ZN8Hardware7s_pThisE
- 0x000000002000402c 0x4 ../lib-hal/lib_gd32/libhal.a(hardware.o)
- 0x000000002000402c Hardware::s_pThis
- .bss.__dso_handle
- 0x0000000020004030 0x4 ../lib-c++/lib_gd32/libc++.a(dso_handle.o)
- 0x0000000020004030 __dso_handle
- .bss.last.0 0x0000000020004034 0x4 ../lib-c/lib_gd32/libc.a(strtok.o)
- .bss.s_micros 0x0000000020004038 0x8 ../lib-c/lib_gd32/libc.a(time.o)
- .bss.set_timer
- 0x0000000020004040 0x4 ../lib-c/lib_gd32/libc.a(time.o)
- .bss.s_nSysTickMillis
- 0x0000000020004044 0x4 ../lib-gd32/lib_gd32/libgd32.a(systick.o)
- 0x0000000020004044 s_nSysTickMillis
+ 0x20003b08 0x4 ../lib-hal/lib_gd32/libhal.a(hardware.o)
+ 0x20003b08 Hardware::s_pThis
+ .bss._ZL15s_nTimePrevious
+ 0x20003b0c 0x4 ../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ .bss._ZL20s_nUsedBytesPrevious
+ 0x20003b10 0x4 ../lib-hal/lib_gd32/libhal.a(stack_debug.o)
+ .bss.enet_initpara
+ 0x20003b14 0x3c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
.bss.dma_current_ptp_rxdesc
- 0x0000000020004048 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020004048 dma_current_ptp_rxdesc
+ 0x20003b50 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003b50 dma_current_ptp_rxdesc
.bss.dma_current_ptp_txdesc
- 0x000000002000404c 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000404c dma_current_ptp_txdesc
+ 0x20003b54 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003b54 dma_current_ptp_txdesc
.bss.dma_current_rxdesc
- 0x0000000020004050 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020004050 dma_current_rxdesc
+ 0x20003b58 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003b58 dma_current_rxdesc
.bss.dma_current_txdesc
- 0x0000000020004054 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020004054 dma_current_txdesc
- .bss.enet_initpara
- 0x0000000020004058 0x3c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- .bss.rx_buff 0x0000000020004094 0x5f40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020004094 rx_buff
- .bss.rxdesc_tab
- 0x0000000020009fd4 0x100 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020009fd4 rxdesc_tab
- .bss.tx_buff 0x000000002000a0d4 0x17d0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000a0d4 tx_buff
+ 0x20003b5c 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003b5c dma_current_txdesc
+ .bss.tx_buff 0x20003b60 0x17d0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003b60 tx_buff
+ .bss.rx_buff 0x20005330 0x2fa0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20005330 rx_buff
.bss.txdesc_tab
- 0x000000002000b8a4 0x40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000b8a4 txdesc_tab
+ 0x200082d0 0x40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x200082d0 txdesc_tab
+ .bss.rxdesc_tab
+ 0x20008310 0x80 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20008310 rxdesc_tab
+ .bss.g_Seconds
+ 0x20008390 0x8 ../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ 0x20008390 g_Seconds
+ .bss.gv_nSysTickMillis
+ 0x20008398 0x4 ../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ 0x20008398 gv_nSysTickMillis
.bss._ZL10s_nAddress
- 0x000000002000b8e4 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x2000839c 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
.bss._ZL13s_nChipSelect
- 0x000000002000b8e5 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ 0x2000839d 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ *fill* 0x2000839e 0x2
+ .bss.outptr 0x200083a0 0x4 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ .bss.last.0 0x200083a4 0x4 ../lib-clib/lib_gd32/libclib.a(strtok.o)
+ .bss._ZL2Tm 0x200083a8 0x24 ../lib-clib/lib_gd32/libclib.a(time.o)
+ .bss._ZN6global13gp_nUtcOffsetE
+ 0x200083cc 0x4 ../lib-clib/lib_gd32/libclib.a(time.o)
+ 0x200083cc global::gp_nUtcOffset
+ .bss._ZL4s_tv 0x200083d0 0x8 ../lib-clib/lib_gd32/libclib.a(time.o)
+ .bss._ZL22nPreviousSysTickMillis
+ 0x200083d8 0x4 ../lib-clib/lib_gd32/libclib.a(time.o)
*(COMMON)
- 0x000000002000b8e8 . = ALIGN (0x4)
- *fill* 0x000000002000b8e6 0x2
- 0x000000002000b8e8 _ebss = .
- 0x000000002000b8e8 __bss_end__ = _ebss
- 0x000000002000b8e8 . = ALIGN (0x8)
+ 0x200083dc . = ALIGN (0x4)
+ 0x200083dc _ebss = .
+ 0x200083dc __bss_end__ = _ebss
+ 0x200083e0 . = ALIGN (0x8)
[!provide] PROVIDE (end = _ebss)
[!provide] PROVIDE (_end = _ebss)
-.sram1 0x000000002001c000 0x418
- 0x000000002001c000 . = ALIGN (0x4)
+.sram1 0x2001c000 0x428
+ 0x2001c000 . = ALIGN (0x4)
*(.sram1)
*(.sram1*)
- 0x000000002001c000 . = ALIGN (0x4)
- 0x000000002001c000 _sdmx = .
+ 0x2001c000 . = ALIGN (0x4)
+ 0x2001c000 _sdmx = .
*(.dmx)
- .dmx 0x000000002001c000 0x418 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _edmx = .
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _spixel = .
+ .dmx 0x2001c000 0x428 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _edmx = .
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _spixel = .
*(.pixel)
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _epixel = .
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _epixel = .
-.sram2 0x0000000020020000 0x0
- 0x0000000020020000 . = ALIGN (0x4)
+.sram2 0x20020000 0x0
+ 0x20020000 . = ALIGN (0x4)
*(.sram2)
*(.sram2*)
-.ramadd 0x0000000020030000 0x0
- 0x0000000020030000 _sramadd = .
- 0x0000000020030000 . = ALIGN (0x4)
+.ramadd 0x20030000 0x0
+ 0x20030000 _sramadd = .
+ 0x20030000 . = ALIGN (0x4)
*(.ramadd)
*(.ramadd*)
- 0x0000000020030000 . = ALIGN (0x4)
- 0x0000000020030000 _eramadd = .
+ 0x20030000 . = ALIGN (0x4)
+ 0x20030000 _eramadd = .
-.bkpsram 0x0000000040024000 0x0
- 0x0000000040024000 . = ALIGN (0x4)
+.bkpsram 0x40024000 0x0
+ 0x40024000 . = ALIGN (0x4)
*(.bkpsram)
*(.bkpsram*)
*(.configstore*)
@@ -7210,28 +5401,24 @@ LOAD build_gd32/lib/rdmsoftwareversion.o
*(*.comment)
*(*.debug*)
START GROUP
-LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a
-LOAD ../lib-c/lib_gd32/libc.a
+LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a
END GROUP
LOAD ../lib-remoteconfig/lib_gd32/libremoteconfig.a
LOAD ../lib-artnet/lib_gd32/libartnet.a
LOAD ../lib-e131/lib_gd32/libe131.a
-LOAD ../lib-rdmdiscovery/lib_gd32/librdmdiscovery.a
LOAD ../lib-rdm/lib_gd32/librdm.a
-LOAD ../lib-uuid/lib_gd32/libuuid.a
-LOAD ../lib-dmxsend/lib_gd32/libdmxsend.a
LOAD ../lib-dmx/lib_gd32/libdmx.a
LOAD ../lib-configstore/lib_gd32/libconfigstore.a
LOAD ../lib-network/lib_gd32/libnetwork.a
-LOAD ../lib-lightset/lib_gd32/liblightset.a
LOAD ../lib-displayudf/lib_gd32/libdisplayudf.a
+LOAD ../lib-lightset/lib_gd32/liblightset.a
LOAD ../lib-flash/lib_gd32/libflash.a
LOAD ../lib-properties/lib_gd32/libproperties.a
LOAD ../lib-display/lib_gd32/libdisplay.a
+LOAD ../lib-device/lib_gd32/libdevice.a
LOAD ../lib-hal/lib_gd32/libhal.a
-LOAD ../lib-c++/lib_gd32/libc++.a
-LOAD ../lib-c/lib_gd32/libc.a
LOAD ../lib-gd32/lib_gd32/libgd32.a
-LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a
+LOAD ../lib-clib/lib_gd32/libclib.a
+LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a
OUTPUT(build_gd32/main.elf elf32-littlearm)
LOAD linker stubs
diff --git a/gd32_emac_artnet_dmx_multi/include/display_timeout.h b/gd32_emac_artnet_dmx_multi/include/display_timeout.h
deleted file mode 100644
index c7ab4f3d..00000000
--- a/gd32_emac_artnet_dmx_multi/include/display_timeout.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**
- * @file display_timeout.h
- *
- */
-/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
-
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
-
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef DISPLAY_TIMEOUT_H_
-#define DISPLAY_TIMEOUT_H_
-
-#include "gd32.h"
-
-namespace display {
-namespace timeout {
-
-void gpio_init() {
- gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT);
-}
-
-bool gpio_renew() {
- return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0;
-}
-
-} // namespace timeout
-} // namespace display
-
-#endif /* DISPLAY_TIMEOUT_H_ */
diff --git a/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp
index 5149f9a1..94271597 100644
--- a/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp
+++ b/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp
@@ -29,7 +29,7 @@
#include "rdmsoftwareversion.h"
#include "software_version.h"
-#include "sofware_version_id.h"
+#include "software_version_id.h"
const char *RDMSoftwareVersion::GetVersion() {
return SOFTWARE_VERSION;
diff --git a/gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp b/gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp
new file mode 100644
index 00000000..657929f1
--- /dev/null
+++ b/gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp
@@ -0,0 +1,55 @@
+#if defined (NODE_SHOWFILE)
+/**
+ * @file showfileusb.cpp
+ *
+ */
+/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "showfile.h"
+
+#include "debug.h"
+
+namespace showfile {
+void usb_ready() {
+ DEBUG_ENTRY
+
+ ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent());
+
+ if (ShowFile::Get()->IsAutoStart()) {
+ ShowFile::Get()->Play();
+ } else {
+ ShowFile::Get()->LoadShows();
+ }
+
+ DEBUG_EXIT
+}
+
+void usb_disconnected() {
+ DEBUG_ENTRY
+
+ ShowFile::Get()->Stop();
+ ShowFile::Get()->UnloadShows();
+
+ DEBUG_EXIT
+}
+} // namespace showfile
+#endif
diff --git a/gd32_emac_e131_dmx_multi/.cproject b/gd32_emac_e131_dmx_multi/.cproject
index 484f7774..e1cc01b4 100644
--- a/gd32_emac_e131_dmx_multi/.cproject
+++ b/gd32_emac_e131_dmx_multi/.cproject
@@ -31,14 +31,12 @@
-
-
diff --git a/gd32_emac_e131_dmx_multi/Common.mk b/gd32_emac_e131_dmx_multi/Common.mk
new file mode 100644
index 00000000..a0da208a
--- /dev/null
+++ b/gd32_emac_e131_dmx_multi/Common.mk
@@ -0,0 +1,10 @@
+DEFINES+=CONFIG_STORE_USE_SPI
+
+DEFINES+=RTL8201F_LED1_LINK_ALL
+
+DEFINES+=DISPLAY_UDF
+
+DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
+
+DEFINES+=DISABLE_RTC
+DEFINES+=DISABLE_FS
\ No newline at end of file
diff --git a/gd32_emac_e131_dmx_multi/Makefile.GD32 b/gd32_emac_e131_dmx_multi/Makefile.GD32
index d8925a45..fd30d0d7 100644
--- a/gd32_emac_e131_dmx_multi/Makefile.GD32
+++ b/gd32_emac_e131_dmx_multi/Makefile.GD32
@@ -3,6 +3,8 @@ BOARD=BOARD_GD32F407RE
DEFINES =NODE_E131_MULTI LIGHTSET_PORTS=2
DEFINES+=E131_HAVE_DMXIN
+#DEFINES+=LIGHTSET_HAVE_RUN
+
DEFINES+=NODE_RDMNET_LLRP_ONLY
DEFINES+=OUTPUT_DMX_SEND_MULTI
@@ -17,9 +19,6 @@ DEFINES+=ENABLE_HTTPD ENABLE_CONTENT
DEFINES+=DISABLE_RTC
DEFINES+=DISABLE_FS
-#DEFINES+=CONFIG_STORE_USE_SPI
-DEFINES+=CONFIG_STORE_USE_RAM
-
DEFINES+=NDEBUG
LIBS=
@@ -29,4 +28,4 @@ SRCDIR=firmware lib
include ../firmware-template-gd32/Rules.mk
prerequisites:
- ./generate_sofware_version_id.sh
+ @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h
diff --git a/gd32_emac_e131_dmx_multi/do-tftp.sh b/gd32_emac_e131_dmx_multi/do-tftp.sh
new file mode 100755
index 00000000..66bc49c3
--- /dev/null
+++ b/gd32_emac_e131_dmx_multi/do-tftp.sh
@@ -0,0 +1,104 @@
+#!/bin/bash
+PATH=".:./../scripts:$PATH"
+
+if [ -f $2 ]; then
+echo $2
+else
+exit
+fi
+
+echo '!tftp#1' | udp_send $1
+ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "tftp:Off" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+sleep 1
+echo -e "Rebooting..."
+echo '?reboot##' | udp_send $1
+
+ON_LINE=$(echo '?list#' | udp_send $1 ) || true
+
+while [ "$ON_LINE" == "" ]
+ do
+ ON_LINE=$(echo '?list#' | udp_send $1 ) || true
+done
+
+echo '!tftp#1' | udp_send $1
+ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "tftp:Off" ]
+ do
+ sleep 1
+ echo '!tftp#1' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+tftp $1 << -EOF
+binary
+put $2
+quit
+-EOF
+
+echo '!tftp#0' | udp_send $1
+ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "" ]
+ do
+ sleep 1
+ echo '!tftp#0' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+while [ "$ON_LINE" == "tftp:On" ]
+ do
+ sleep 1
+ echo '!tftp#0' | udp_send $1
+ ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true
+done
+
+echo [$ON_LINE]
+
+echo -e "Rebooting..."
+echo '?reboot##' | udp_send $1
+
+ON_LINE=$(echo '?list#' | udp_send $1 ) || true
+
+while [ "$ON_LINE" == "" ]
+ do
+ ON_LINE=$(echo '?list#' | udp_send $1 ) || true
+done
+
+echo -e "[$ON_LINE]"
+echo -e "$(echo '?version#' | udp_send $1 )"
diff --git a/gd32_emac_e131_dmx_multi/firmware/main.cpp b/gd32_emac_e131_dmx_multi/firmware/main.cpp
index f1e28bb3..56247075 100644
--- a/gd32_emac_e131_dmx_multi/firmware/main.cpp
+++ b/gd32_emac_e131_dmx_multi/firmware/main.cpp
@@ -2,7 +2,7 @@
* @file main.cpp
*
*/
-/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org
+/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,16 +29,15 @@
#include "network.h"
#include "networkconst.h"
-#include "mdns.h"
+#include "net/apps/mdns.h"
-#if defined (ENABLE_HTTPD)
-# include "httpd/httpd.h"
+#if defined (ENABLE_NTP_CLIENT)
+# include "net/apps/ntpclient.h"
#endif
#include "displayudf.h"
#include "displayudfparams.h"
#include "displayhandler.h"
-#include "display_timeout.h"
#include "e131.h"
#include "e131bridge.h"
@@ -57,66 +56,53 @@
# include "rdm_e120.h"
#endif
+#if defined (NODE_SHOWFILE)
+# include "showfile.h"
+# include "showfileparams.h"
+#endif
+
#include "remoteconfig.h"
#include "remoteconfigparams.h"
#include "configstore.h"
-#include "storedisplayudf.h"
-#include "storedmxsend.h"
-#include "storee131.h"
-#include "storenetwork.h"
-#if defined (NODE_RDMNET_LLRP_ONLY)
-# include "storerdmdevice.h"
-#endif
-#include "storeremoteconfig.h"
#include "firmwareversion.h"
#include "software_version.h"
-static constexpr uint32_t DMXPORT_OFFSET = 0;
+namespace e131bridge {
+namespace configstore {
+uint32_t DMXPORT_OFFSET = 0;
+} // namespace configstore
+} // namespace e131bridge
void Hardware::RebootHandler() {
Dmx::Get()->Blackout();
E131Bridge::Get()->Stop();
}
-void main() {
+int main() {
Hardware hw;
DisplayUdf display;
ConfigStore configStore;
- display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW);
- StoreNetwork storeNetwork;
- Network nw(&storeNetwork);
- display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN);
+ display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW);
+ Network nw;
+ MDNS mDns;
+ display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN);
FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__);
fw.Print("sACN E1.31 DMX {" STR(LIGHTSET_PORTS) " Universes}");
- nw.Print();
-
- display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW);
-
- MDNS mDns;
- mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=sACN E1.31 DMX");
-#if defined (ENABLE_HTTPD)
- mDns.AddServiceRecord(nullptr, mdns::Services::HTTP);
-#endif
- mDns.Print();
-#if defined (ENABLE_HTTPD)
- HttpDaemon httpDaemon;
+#if defined (ENABLE_NTP_CLIENT)
+ NtpClient ntpClient;
+ ntpClient.Start();
+ ntpClient.Print();
#endif
- display.TextStatus(E131MsgConst::PARAMS, Display7SegmentMessage::INFO_BRIDGE_PARMAMS, CONSOLE_YELLOW);
-
- StoreE131 storeE131;
- E131Params e131params(&storeE131);
-
E131Bridge bridge;
- if (e131params.Load()) {
- e131params.Dump();
- e131params.Set(DMXPORT_OFFSET);
- }
+ E131Params e131params;
+ e131params.Load();
+ e131params.Set();
for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) {
bool bIsSet;
@@ -124,19 +110,15 @@ void main() {
bridge.SetUniverse(nPortIndex, e131params.GetDirection(nPortIndex), nUniverse);
}
- StoreDmxSend storeDmxSend;
- DmxParams dmxparams(&storeDmxSend);
-
Dmx dmx;
- if (dmxparams.Load()) {
- dmxparams.Dump();
- dmxparams.Set(&dmx);
- }
+ DmxParams dmxparams;
+ dmxparams.Load();
+ dmxparams.Set(&dmx);
- for (uint32_t nPortIndex = DMXPORT_OFFSET; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) {
+ for (uint32_t nPortIndex = e131bridge::configstore::DMXPORT_OFFSET; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) {
uint16_t nUniverse;
- const auto nDmxPortIndex = nPortIndex - DMXPORT_OFFSET;
+ const auto nDmxPortIndex = nPortIndex - e131bridge::configstore::DMXPORT_OFFSET;
if (bridge.GetUniverse(nPortIndex, nUniverse, lightset::PortDir::OUTPUT)) {
dmx.SetPortDirection(nDmxPortIndex, dmx::PortDirection::OUTP, false);
@@ -150,12 +132,10 @@ void main() {
bridge.SetOutput(&dmxSend);
- DmxConfigUdp dmxConfigUdp;
-
const auto nActivePorts = static_cast(bridge.GetActiveInputPorts() + bridge.GetActiveOutputPorts());
#if defined (NODE_RDMNET_LLRP_ONLY)
- display.TextStatus(RDMNetConst::MSG_CONFIG, Display7SegmentMessage::INFO_RDMNET_CONFIG, CONSOLE_YELLOW);
+ display.TextStatus(RDMNetConst::MSG_CONFIG, CONSOLE_YELLOW);
char aDescription[rdm::personality::DESCRIPTION_MAX_LENGTH + 1];
snprintf(aDescription, sizeof(aDescription) - 1, "sACN E1.31 DMX %d", nActivePorts);
@@ -170,18 +150,24 @@ void main() {
llrpOnlyDevice.SetProductDetail(E120_PRODUCT_DETAIL_ETHERNET_NODE);
llrpOnlyDevice.Init();
- StoreRDMDevice storeRdmDevice;
- RDMDeviceParams rdmDeviceParams(&storeRdmDevice);
+ RDMDeviceParams rdmDeviceParams;
- if (rdmDeviceParams.Load()) {
- rdmDeviceParams.Dump();
- rdmDeviceParams.Set(&llrpOnlyDevice);
- }
-
- llrpOnlyDevice.SetRDMDeviceStore(&storeRdmDevice);
+ rdmDeviceParams.Load();
+ rdmDeviceParams.Set(&llrpOnlyDevice);
+
llrpOnlyDevice.Print();
#endif
+#if defined (NODE_SHOWFILE)
+ ShowFile showFile;
+
+ ShowFileParams showFileParams;
+ showFileParams.Load();
+ showFileParams.Set();
+
+ showFile.Print();
+#endif
+
bridge.Print();
display.SetTitle("sACN E1.31 DMX %u", nActivePorts);
@@ -191,34 +177,29 @@ void main() {
display.Set(5, displayudf::Labels::UNIVERSE_PORT_B);
display.Set(6, displayudf::Labels::BOARDNAME);
- StoreDisplayUdf storeDisplayUdf;
- DisplayUdfParams displayUdfParams(&storeDisplayUdf);
+ DisplayUdfParams displayUdfParams;
- if(displayUdfParams.Load()) {
- displayUdfParams.Dump();
- displayUdfParams.Set(&display);
- }
+ displayUdfParams.Load();
+ displayUdfParams.Set(&display);
- display.Show(&bridge);
+ display.Show();
RemoteConfig remoteConfig(remoteconfig::Node::E131, remoteconfig::Output::DMX, nActivePorts);
- StoreRemoteConfig storeRemoteConfig;
- RemoteConfigParams remoteConfigParams(&storeRemoteConfig);
-
- if (remoteConfigParams.Load()) {
- remoteConfigParams.Dump();
- remoteConfigParams.Set(&remoteConfig);
- }
+ RemoteConfigParams remoteConfigParams;
+ remoteConfigParams.Load();
+ remoteConfigParams.Set(&remoteConfig);
while (configStore.Flash())
;
- display.TextStatus(E131MsgConst::START, Display7SegmentMessage::INFO_BRIDGE_START, CONSOLE_YELLOW);
+ mDns.Print();
+
+ display.TextStatus(E131MsgConst::START, CONSOLE_YELLOW);
bridge.Start();
- display.TextStatus(E131MsgConst::STARTED, Display7SegmentMessage::INFO_BRIDGE_STARTED, CONSOLE_GREEN);
+ display.TextStatus(E131MsgConst::STARTED, CONSOLE_GREEN);
hw.WatchdogInit();
@@ -226,17 +207,17 @@ void main() {
hw.WatchdogFeed();
nw.Run();
bridge.Run();
+#if defined (NODE_SHOWFILE)
+ showFile.Run();
+#endif
remoteConfig.Run();
configStore.Flash();
- if (bridge.GetActiveOutputPorts() != 0) {
- dmxConfigUdp.Run();
- }
mDns.Run();
+#if defined (ENABLE_NTP_CLIENT)
+ ntpClient.Run();
+#endif
#if defined (NODE_RDMNET_LLRP_ONLY)
llrpOnlyDevice.Run();
-#endif
-#if defined (ENABLE_HTTPD)
- httpDaemon.Run();
#endif
display.Run();
hw.Run();
diff --git a/gd32_emac_e131_dmx_multi/gd32f4xx.map b/gd32_emac_e131_dmx_multi/gd32f4xx.map
index 110ee5ab..48652b82 100644
--- a/gd32_emac_e131_dmx_multi/gd32f4xx.map
+++ b/gd32_emac_e131_dmx_multi/gd32f4xx.map
@@ -1,41 +1,29 @@
Archive member included to satisfy reference by file (symbol)
-../lib-c/lib_gd32/libc.a(printf.o)
- build_gd32/firmware/main.o (printf)
-../lib-c/lib_gd32/libc.a(puts.o)
- build_gd32/firmware/main.o (puts)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (__aeabi_d2f)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (__aeabi_uldivmod)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o)
- /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o)
- /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- build_gd32/firmware/main.o (RemoteConfig::RemoteConfig(remoteconfig::Node, remoteconfig::Output, unsigned long))
+ build_gd32/firmware/main.o (RemoteConfig::s_pUdpBuffer)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigfactory.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::HandleFactory())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
- build_gd32/firmware/main.o (RemoteConfigParams::RemoteConfigParams(RemoteConfigParamsStore*))
-../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparamsdump.o)
- build_gd32/firmware/main.o (RemoteConfigParams::Dump())
+ build_gd32/firmware/main.o (RemoteConfigParams::RemoteConfigParams())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigreboot.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::HandleReboot())
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigstatic.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::GetIndex(void const*, unsigned long&))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (RemoteConfig::PlatformHandleTftpSet())
-../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- build_gd32/firmware/main.o (HttpDaemon::HttpDaemon())
+../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (HttpDaemon::HttpDaemon())
+../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ build_gd32/firmware/main.o (HttpDeamonHandleRequest::HandleRequest(unsigned long, char*))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigconst.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (RemoteConfigConst::PARAMS_DISPLAY_NAME)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (remoteconfig::json_get_list(char*, unsigned short))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::json_get_list(char*, unsigned long))
../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (get_file_content(char const*, char*, http::contentTypes&))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (get_file_content(char const*, unsigned long&, http::contentTypes&))
../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- build_gd32/firmware/main.o (E131Bridge::E131Bridge())
+ build_gd32/firmware/main.o (E131Bridge::s_pThis)
../lib-e131/lib_gd32/libe131.a(e131bridgehandlesynchronization.o)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E131Bridge::HandleSynchronization())
../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
@@ -43,39 +31,19 @@ Archive member included to satisfy reference by file (symbol)
../lib-e131/lib_gd32/libe131.a(e131msgconst.o)
build_gd32/firmware/main.o (E131MsgConst::STARTED)
../lib-e131/lib_gd32/libe131.a(e131params.o)
- build_gd32/firmware/main.o (E131Params::E131Params(E131ParamsStore*))
+ build_gd32/firmware/main.o (E131Params::E131Params())
../lib-e131/lib_gd32/libe131.a(e131paramsconst.o)
../lib-e131/lib_gd32/libe131.a(e131params.o) (E131ParamsConst::PRIORITY)
-../lib-e131/lib_gd32/libe131.a(e131paramsdump.o)
- build_gd32/firmware/main.o (E131Params::Dump())
../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E131Bridge::FillDiscoveryPacket())
../lib-e131/lib_gd32/libe131.a(handledmxin.o)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E131Bridge::FillDataPacket())
../lib-e131/lib_gd32/libe131.a(e117const.o)
../lib-e131/lib_gd32/libe131.a(e131bridge.o) (E117Const::ACN_PACKET_IDENTIFIER)
-../lib-e131/lib_gd32/libe131.a(e131bridgeconst.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (E131BridgeConst::VERSION)
-../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- build_gd32/firmware/main.o (LLRPDevice::HandleRequestMessage())
-../lib-rdmnet/lib_gd32/librdmnet.a(rdmnetconst.o)
- build_gd32/firmware/main.o (RDMNetConst::MSG_CONFIG)
-../lib-rdmnet/lib_gd32/librdmnet.a(rdmnetdevice.o)
- build_gd32/firmware/main.o (RDMNetDevice::Print())
-../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o)
- build_gd32/firmware/main.o (RDMSensors::~RDMSensors())
-../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensorsconst.o)
- ../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o) (RDMSensorsConst::TYPE)
-../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensor.o)
- ../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o) (RDMSensor::GetValues())
-../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- build_gd32/firmware/main.o (RDMSubDevices::~RDMSubDevices())
-../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevicesconst.o)
- ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o) (RDMSubDevicesConst::TYPE)
-../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o) (RDMSubDevice::SetDmxStartAddress(unsigned short))
+../lib-e131/lib_gd32/libe131.a(e131const.o)
+ ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (E131Const::VERSION)
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- build_gd32/firmware/main.o (RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*))
+ build_gd32/firmware/main.o (RDMDeviceParams::RDMDeviceParams())
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparamsconst.o)
../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (RDMDeviceParamsConst::PRODUCT_DETAIL)
../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
@@ -83,111 +51,111 @@ Archive member included to satisfy reference by file (symbol)
../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
build_gd32/firmware/main.o (RDMHandler::RDMHandler(bool))
../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o) (RDMIdentify::RDMIdentify())
+ ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o) (RDMIdentify::s_pThis)
+../lib-rdm/lib_gd32/librdm.a(rdmsensors.o)
+ ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o) (RDMSensors::s_pThis)
+../lib-rdm/lib_gd32/librdm.a(rdmsubdevices.o)
+ ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o) (RDMSubDevices::s_pThis)
+../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ build_gd32/firmware/main.o (LLRPDevice::HandleRequestMessage())
../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
../lib-rdm/lib_gd32/librdm.a(rdmhandler.o) (RDMHandler::GetInterfaceList(unsigned short))
+../lib-rdm/lib_gd32/librdm.a(rdmnetconst.o)
+ build_gd32/firmware/main.o (RDMNetConst::MSG_CONFIG)
../lib-rdm/lib_gd32/librdm.a(rdmconst.o)
../lib-rdm/lib_gd32/librdm.a(rdmhandler.o) (RDMConst::MANUFACTURER_NAME)
../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o) (RDMDevice::RDMDevice())
-../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o) (uuid_unparse)
-../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- build_gd32/firmware/main.o (DmxSend::Print())
../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- build_gd32/firmware/main.o (DmxParams::DmxParams(DmxParamsStore*))
+ build_gd32/firmware/main.o (DmxParams::DmxParams())
../lib-dmx/lib_gd32/libdmx.a(dmxparamsconst.o)
../lib-dmx/lib_gd32/libdmx.a(dmxparams.o) (DmxParamsConst::SLOTS_COUNT)
+../lib-dmx/lib_gd32/libdmx.a(json_get_ports.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::dmx::json_get_ports(char*, unsigned long))
+../lib-dmx/lib_gd32/libdmx.a(json_get_portstatus.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::dmx::json_get_portstatus(char, char*, unsigned long))
../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- build_gd32/firmware/main.o (Dmx::Dmx())
-../lib-dmx/lib_gd32/libdmx.a(dmxconfigudp.o)
- build_gd32/firmware/main.o (DmxConfigUdp::s_pUdpBuffer)
+ build_gd32/firmware/main.o (Dmx::s_pThis)
../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- build_gd32/firmware/main.o (ConfigStore::ConfigStore())
-../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- build_gd32/firmware/main.o (StoreDisplayUdf::StoreDisplayUdf())
-../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- build_gd32/firmware/main.o (StoreDmxSend::StoreDmxSend())
-../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- build_gd32/firmware/main.o (StoreNetwork::StoreNetwork())
-../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- build_gd32/firmware/main.o (StoreRemoteConfig::StoreRemoteConfig())
+ build_gd32/firmware/main.o (ConfigStore::s_pThis)
+../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (EnvParams::EnvParams())
+../lib-configstore/lib_gd32/libconfigstore.a(envparamsconst.o)
+ ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o) (EnvParamsConst::UTC_OFFSET)
../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
../lib-configstore/lib_gd32/libconfigstore.a(configstore.o) (StoreDevice::StoreDevice())
-../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- build_gd32/firmware/main.o (StoreE131::StoreE131())
-../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- build_gd32/firmware/main.o (StoreRDMDevice::StoreRDMDevice())
../lib-network/lib_gd32/libnetwork.a(networkconst.o)
- build_gd32/firmware/main.o (NetworkConst::MSG_MDNS_CONFIG)
+ build_gd32/firmware/main.o (NetworkConst::MSG_NETWORK_STARTED)
../lib-network/lib_gd32/libnetwork.a(mdns.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigreboot.o) (network::mdns_shutdown())
+ build_gd32/firmware/main.o (MDNS::s_nHandle)
../lib-network/lib_gd32/libnetwork.a(network.o)
- build_gd32/firmware/main.o (Network::Network(NetworkParamsStore*))
-../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (NetworkParams::NetworkParams(NetworkParamsStore*))
-../lib-network/lib_gd32/libnetwork.a(networkparamsdump.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (NetworkParams::Dump())
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o) (Network::s_pThis)
+../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::autoip_start())
+../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::dhcp_start())
../lib-network/lib_gd32/libnetwork.a(igmp.o)
- build_gd32/firmware/main.o (igmp_join(unsigned long))
+ build_gd32/firmware/main.o (net::igmp_join(unsigned long))
../lib-network/lib_gd32/libnetwork.a(net.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (net_init(unsigned char const*, IpInfo*, char const*, bool*, bool*))
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::net_set_primary_ip(net::ip_addr))
../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
- ../lib-network/lib_gd32/libnetwork.a(igmp.o) (net_chksum(void const*, unsigned long))
-../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (net_timers_run())
-../lib-network/lib_gd32/libnetwork.a(rfc3927.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (rfc3927())
+ ../lib-network/lib_gd32/libnetwork.a(igmp.o) (net::net_chksum(void const*, unsigned long))
+../lib-network/lib_gd32/libnetwork.a(netif.o)
+ build_gd32/firmware/main.o (net::globals::netif_default)
../lib-network/lib_gd32/libnetwork.a(tcp.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (tcp_begin(unsigned short))
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::tcp_shutdown())
../lib-network/lib_gd32/libnetwork.a(udp.o)
- build_gd32/firmware/main.o (udp_begin(unsigned short))
+ build_gd32/firmware/main.o (net::udp_begin(unsigned short))
+../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (NetworkParams::NetworkParams())
+../lib-network/lib_gd32/libnetwork.a(networkparamsconst.o)
+ ../lib-network/lib_gd32/libnetwork.a(networkparams.o) (NetworkParamsConst::NTP_SERVER)
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
../lib-network/lib_gd32/libnetwork.a(network.o) (net::phy_customized_led())
-../lib-network/lib_gd32/libnetwork.a(net.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (emac_eth_recv)
-../lib-network/lib_gd32/libnetwork.a(networkparamsconst.o)
- ../lib-network/lib_gd32/libnetwork.a(networkparams.o) (NetworkParamsConst::HOSTNAME)
../lib-network/lib_gd32/libnetwork.a(emac.o)
../lib-network/lib_gd32/libnetwork.a(network.o) (emac_config())
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
../lib-network/lib_gd32/libnetwork.a(net_phy.o) (net::phy_read(unsigned long, unsigned long, unsigned short&))
+../lib-network/lib_gd32/libnetwork.a(emac.o)
+ ../lib-network/lib_gd32/libnetwork.a(emac.o) (enet_gpio_config())
+../lib-network/lib_gd32/libnetwork.a(net.o)
+ ../lib-network/lib_gd32/libnetwork.a(net.o) (emac_eth_recv(unsigned char**))
+../lib-network/lib_gd32/libnetwork.a(acd.o)
+ ../lib-network/lib_gd32/libnetwork.a(autoip.o) (net::acd_start(net::acd::Acd*, net::ip_addr))
../lib-network/lib_gd32/libnetwork.a(arp.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (arp_init())
-../lib-network/lib_gd32/libnetwork.a(arp_cache.o)
- ../lib-network/lib_gd32/libnetwork.a(arp.o) (arp_cache_init())
-../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (dhcp_client(char const*))
+ ../lib-network/lib_gd32/libnetwork.a(net.o) (net::arp_init())
../lib-network/lib_gd32/libnetwork.a(ip.o)
- ../lib-network/lib_gd32/libnetwork.a(net.o) (ip_set_ip())
+ ../lib-network/lib_gd32/libnetwork.a(netif.o) (net::ip_set_ip())
../lib-network/lib_gd32/libnetwork.a(net_link_check.o)
../lib-network/lib_gd32/libnetwork.a(net_phy.o) (net::link_status_read())
../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- ../lib-network/lib_gd32/libnetwork.a(emac.o) (net::phy_start(unsigned long, net::PhyStatus&))
+ ../lib-network/lib_gd32/libnetwork.a(net_link_check.o) (net::phy_get_link(unsigned long))
../lib-network/lib_gd32/libnetwork.a(icmp.o)
- ../lib-network/lib_gd32/libnetwork.a(ip.o) (icmp_handle(t_icmp*))
-../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o) (LightSet::GetDmxStartAddress())
-../lib-lightset/lib_gd32/liblightset.a(lightsetgetslotinfo.o)
- ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o) (LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&))
-../lib-lightset/lib_gd32/liblightset.a(lightsetparamsconst.o)
- ../lib-e131/lib_gd32/libe131.a(e131params.o) (LightSetParamsConst::FAILSAFE)
+ ../lib-network/lib_gd32/libnetwork.a(ip.o) (net::icmp_handle(t_icmp*))
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
build_gd32/firmware/main.o (DisplayUdf::DisplayUdf())
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- build_gd32/firmware/main.o (DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*))
+ build_gd32/firmware/main.o (DisplayUdfParams::DisplayUdfParams())
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparamsconst.o)
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o) (DisplayUdfParamsConst::DMX_DIRECTION)
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowe131.o)
- build_gd32/firmware/main.o (DisplayUdf::Show(E131Bridge*, unsigned long))
+ ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o) (DisplayUdf::ShowE131Bridge())
../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- ../lib-network/lib_gd32/libnetwork.a(network.o) (network::display_emac_config())
+ ../lib-network/lib_gd32/libnetwork.a(network.o) (net::display_emac_config())
+../lib-lightset/lib_gd32/liblightset.a(lightsetparamsconst.o)
+ ../lib-e131/lib_gd32/libe131.a(e131params.o) (LightSetParamsConst::FAILSAFE)
+../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o) (spi_flash_get_size())
+../lib-flash/lib_gd32/libflash.a(winbond.o)
+ ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_flash_probe_winbond(spi_flash*, unsigned char*))
+../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (spi_init())
../lib-properties/lib_gd32/libproperties.a(properties.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (properties::convert_json_file(char*, unsigned long, bool))
../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long))
../lib-properties/lib_gd32/libproperties.a(propertiesbuilderaddhex.o)
- ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (PropertiesBuilder::AddHex(char const*, unsigned long, bool, unsigned long))
+ ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o) (PropertiesBuilder::AddHex(char const*, unsigned long, bool, int))
../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (PropertiesConfig::s_Config)
../lib-properties/lib_gd32/libproperties.a(readconfigfile.o)
@@ -202,44 +170,24 @@ Archive member included to satisfy reference by file (symbol)
../lib-e131/lib_gd32/libe131.a(e131params.o) (Sscan::Uint16(char const*, char const*, unsigned short&))
../lib-properties/lib_gd32/libproperties.a(sscanuint8.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o) (Sscan::Uint8(char const*, char const*, unsigned char&))
+../lib-properties/lib_gd32/libproperties.a(sscanutcoffset.o)
+ ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o) (Sscan::UtcOffset(char const*, char const*, signed char&, unsigned char&))
../lib-properties/lib_gd32/libproperties.a(sscan.o)
../lib-properties/lib_gd32/libproperties.a(sscanchar.o) (Sscan::checkName(char const*, char const*))
../lib-display/lib_gd32/libdisplay.a(display.o)
../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o) (Display::Display())
../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
../lib-display/lib_gd32/libdisplay.a(display.o) (Ssd1306::Ssd1306(TOledPanel))
-../lib-hal/lib_gd32/libhal.a(console.o)
- ../lib-c/lib_gd32/libc.a(printf.o) (console_putc)
../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- build_gd32/firmware/main.o (FirmwareVersion::FirmwareVersion(char const*, char const*, char const*))
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o) (FirmwareVersion::s_FirmwareVersion)
../lib-hal/lib_gd32/libhal.a(hardware.o)
build_gd32/firmware/main.o (Hardware::SetMode(hardware::ledblink::Mode))
+../lib-hal/lib_gd32/libhal.a(json_datetime.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (remoteconfig::timedate::json_get_timeofday(char*, unsigned long))
../lib-hal/lib_gd32/libhal.a(hardware.o)
- build_gd32/firmware/main.o (Hardware::Hardware())
-../lib-c++/lib_gd32/libc++.a(delete.o)
- build_gd32/firmware/main.o (operator delete(void*))
-../lib-c++/lib_gd32/libc++.a(new.o)
- build_gd32/firmware/main.o (operator new(unsigned int))
-../lib-c/lib_gd32/libc.a(init.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (__libc_init_array)
-../lib-c/lib_gd32/libc.a(malloc.o)
- ../lib-c++/lib_gd32/libc++.a(new.o) (malloc)
-../lib-c/lib_gd32/libc.a(memmove.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memmove)
-../lib-c/lib_gd32/libc.a(memset.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memset)
-../lib-c/lib_gd32/libc.a(putchar.o)
- ../lib-network/lib_gd32/libnetwork.a(mdns.o) (putchar)
-../lib-c/lib_gd32/libc.a(strtok.o)
- ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o) (strtok)
-../lib-c/lib_gd32/libc.a(time.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (localtime)
-../lib-c/lib_gd32/libc.a(time.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (settimeofday)
-../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_puts)
-../lib-gd32/lib_gd32/libgd32.a(systick.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (systick_config)
+ build_gd32/firmware/main.o (Hardware::s_pThis)
+../lib-hal/lib_gd32/libhal.a(console.o)
+ ../lib-network/lib_gd32/libnetwork.a(dhcp.o) (console_error)
../lib-gd32/lib_gd32/libgd32.a(system_gd32f4xx.o)
build_gd32/startup_gd32f407.o (SystemInit)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
@@ -249,6357 +197,4857 @@ Archive member included to satisfy reference by file (symbol)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
build_gd32/firmware/main.o (fwdgt_enable)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- build_gd32/firmware/main.o (gpio_mode_set)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gpio_mode_set)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
../lib-hal/lib_gd32/libhal.a(hardware.o) (pmu_backup_ldo_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- build_gd32/firmware/main.o (rcu_periph_clock_enable)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (rcu_periph_clock_enable)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
../lib-network/lib_gd32/libnetwork.a(emac.o) (syscfg_enet_phy_interface_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
../lib-dmx/lib_gd32/libdmx.a(dmx.o) (timer_deinit)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (usart_dma_transmit_config)
-../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_init)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (usart_flag_get)
../lib-gd32/lib_gd32/libgd32.a(bkp.o)
../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (bkp_data_write(bkp_data_register_enum, unsigned short))
-../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_adc_init())
-../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
- ../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_i2c_begin)
../lib-gd32/lib_gd32/libgd32.a(gd32_uart.o)
- ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gd32_uart_begin)
+ ../lib-dmx/lib_gd32/libdmx.a(dmx.o) (gd32_uart_begin(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long))
../lib-gd32/lib_gd32/libgd32.a(mac_address.o)
../lib-network/lib_gd32/libnetwork.a(emac.o) (mac_address_get(unsigned char*))
+../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (timer6_config())
../lib-gd32/lib_gd32/libgd32.a(udelay.o)
../lib-hal/lib_gd32/libhal.a(hardware.o) (udelay_init())
+../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (systick_config)
+../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_adc_init())
+../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (gd32_i2c_begin)
+../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ ../lib-flash/lib_gd32/libflash.a(spi_flash.o) (gd32_spi_begin())
+../lib-gd32/lib_gd32/libgd32.a(uart0.o)
+ ../lib-hal/lib_gd32/libhal.a(console.o) (uart0_init)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_adc.o)
../lib-gd32/lib_gd32/libgd32.a(gd32_adc.o) (adc_clock_config)
../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_i2c.o)
../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o) (i2c_clock_config)
-/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
+../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_spi.o)
+ ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o) (spi_i2s_deinit)
+../lib-clib/lib_gd32/libclib.a(init.o)
+ build_gd32/startup_gd32f407.o (__libc_init_array)
+../lib-clib/lib_gd32/libclib.a(memcpy.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memcpy)
+../lib-clib/lib_gd32/libclib.a(memmove.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memmove)
+../lib-clib/lib_gd32/libclib.a(memset.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o) (memset)
+../lib-clib/lib_gd32/libclib.a(printf.o)
+ build_gd32/hardfault_handler.o (printf)
+../lib-clib/lib_gd32/libclib.a(putchar.o)
+ ../lib-network/lib_gd32/libnetwork.a(mdns.o) (putchar)
+../lib-clib/lib_gd32/libclib.a(puts.o)
+ build_gd32/firmware/main.o (puts)
+../lib-clib/lib_gd32/libclib.a(random.o)
+ ../lib-network/lib_gd32/libnetwork.a(igmp.o) (random)
+../lib-clib/lib_gd32/libclib.a(strtok.o)
+ ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o) (strtok)
+../lib-clib/lib_gd32/libclib.a(uuid_unparse.o)
+ build_gd32/firmware/main.o (uuid_unparse)
+../lib-clib/lib_gd32/libclib.a(assert.o)
+ ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o) (__assert_func)
+../lib-clib/lib_gd32/libclib.a(time.o)
+ ../lib-hal/lib_gd32/libhal.a(json_datetime.o) (localtime)
+../lib-clib/lib_gd32/libclib.a(uuid.o)
+ ../lib-hal/lib_gd32/libhal.a(hardware.o) (hal::uuid_init(unsigned char*))
+../lib-clib/lib_gd32/libclib.a(time.o)
+ ../lib-hal/lib_gd32/libhal.a(json_datetime.o) (gettimeofday)
+../lib-clib/lib_gd32/libclib.a(delete.o)
+ build_gd32/firmware/main.o (operator delete[](void*))
+../lib-clib/lib_gd32/libclib.a(new.o)
+ build_gd32/firmware/main.o (operator new(unsigned int))
+../lib-clib/lib_gd32/libclib.a(malloc.o)
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+/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ ../lib-clib/lib_gd32/libclib.a(printf.o) (__aeabi_d2f)
+/Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_popcountsi2.o)
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Memory Configuration
Name Origin Length Attributes
-FLASH 0x0000000008008000 0x000000000001a800 xr
-TCMSRAM 0x0000000010000000 0x0000000000010000 rw
-RAM 0x0000000020000000 0x000000000001c000 xrw
-RAM1 0x000000002001c000 0x0000000000004000 xrw
-RAM2 0x0000000020020000 0x0000000000000000 xrw
-RAMADD 0x0000000020030000 0x0000000000000000 xrw
-BKPSRAM 0x0000000040024000 0x0000000000001000 rw
-*default* 0x0000000000000000 0xffffffffffffffff
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+RAM2 0x20020000 0x00000000 xrw
+RAMADD 0x20030000 0x00000000 xrw
+BKPSRAM 0x40024000 0x00001000 rw
+*default* 0x00000000 0xffffffff
Linker script and memory map
LOAD build_gd32/startup_gd32f407.o
+LOAD build_gd32/hardfault_handler.o
LOAD build_gd32/firmware/main.o
LOAD build_gd32/lib/factorydefaults.o
LOAD build_gd32/lib/rdmsoftwareversion.o
- 0x0000000000001000 __heap_size = DEFINED (__heap_size)?__heap_size:0x1000
- 0x0000000000002800 __stack_size = DEFINED (__stack_size)?__stack_size:0x2800
+LOAD build_gd32/lib/showfileusb.o
+ 0x00001000 __heap_size = DEFINED (__heap_size)?__heap_size:0x1000
+ 0x00002800 __stack_size = DEFINED (__stack_size)?__stack_size:0x2800
-.vectors 0x0000000008008000 0x188
- 0x0000000008008000 . = ALIGN (0x4)
+.vectors 0x08008000 0x188
+ 0x08008000 . = ALIGN (0x4)
*(.vectors)
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- 0x0000000008008000 __gVectors
- 0x0000000008008188 . = ALIGN (0x4)
- 0x0000000008008188 __Vectors_End = .
- 0x0000000008008188 __Vectors_Size = (__Vectors_End - __gVectors)
+ .vectors 0x08008000 0x188 build_gd32/startup_gd32f407.o
+ 0x08008000 __gVectors
+ 0x08008188 . = ALIGN (0x4)
+ 0x08008188 __Vectors_End = .
+ 0x08008188 __Vectors_Size = (__Vectors_End - __gVectors)
-.text 0x0000000008008188 0xe0c0
- 0x0000000008008188 . = ALIGN (0x4)
+.text 0x08008188 0xee3c
+ 0x08008188 . = ALIGN (0x4)
*(.text.unlikely*)
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- 0x0000000008008234 net_init(unsigned char const*, IpInfo*, char const*, bool*, bool*)
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- 0x0000000008008320 udp_init()
+ .text.unlikely._ZN3net9igmp_initEv
+ 0x08008188 0xec ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08008188 net::igmp_init()
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+ 0x08008274 0x1c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
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+ 0x08008290 net::net_init(net::Link, net::ip_addr, net::ip_addr, net::ip_addr, bool&)
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+ 0x08008300 0x34 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08008300 net::tcp_init()
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.text.unlikely._Z11emac_configv
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- 0x000000000800835c emac_config()
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.text.unlikely._Z10emac_startPhRN3net4LinkE
- 0x0000000008008540 0xc4 ../lib-network/lib_gd32/libnetwork.a(emac.o)
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- .text.unlikely._Z8arp_initv
- 0x0000000008008604 0xb4 ../lib-network/lib_gd32/libnetwork.a(arp.o)
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- .text.unlikely._Z14arp_cache_initv
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- .text.unlikely._Z7ip_initv
- 0x00000000080086dc 0x12 ../lib-network/lib_gd32/libnetwork.a(ip.o)
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- .text.unlikely._Z11ip_shutdownv
- 0x00000000080086ee 0xe ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x00000000080086ee ip_shutdown()
- .text.unlikely.console_init
- 0x00000000080086fc 0x20 ../lib-hal/lib_gd32/libhal.a(console.o)
- 0x00000000080086fc console_init
+ 0x080083c4 0x60 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x080083c4 emac_start(unsigned char*, net::Link&)
+ .text.unlikely._ZN3net8arp_initEv
+ 0x08008424 0x13c ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08008424 net::arp_init()
+ .text.unlikely._ZN3net7ip_initEv
+ 0x08008560 0x12 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08008560 net::ip_init()
+ *fill* 0x08008572 0x2
+ .text.unlikely._Z12console_initv
+ 0x08008574 0x20 ../lib-hal/lib_gd32/libhal.a(console.o)
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*(.text.hot*)
- .text.hot._Z11igmp_handleP6t_igmp
- 0x000000000800871c 0x98 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x000000000800871c igmp_handle(t_igmp*)
- .text.hot._Z10net_handlev
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- .text.hot._Z7tcp_runv
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- .text.hot._Z10tcp_handleP5t_tcp
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- .text.hot._Z10udp_handleP5t_udp
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- .text.hot._Z10arp_handleP5t_arp
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- 0x0000000008008d8c arp_handle(t_arp*)
- .text.hot._Z9ip_handleP5t_ip4
- 0x0000000008008da4 0x42 ../lib-network/lib_gd32/libnetwork.a(ip.o)
- 0x0000000008008da4 ip_handle(t_ip4*)
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- .text.hot._Z11icmp_handleP6t_icmp
- 0x0000000008008de8 0x7c ../lib-network/lib_gd32/libnetwork.a(icmp.o)
- 0x0000000008008de8 icmp_handle(t_icmp*)
+ .text.hot._ZN3net11igmp_handleEP6t_igmp
+ 0x08008594 0xac ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08008594 net::igmp_handle(t_igmp*)
+ .text.hot._ZN3net10net_handleEv
+ 0x08008640 0x38 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08008640 net::net_handle()
+ .text.hot._ZN3net7tcp_runEv
+ 0x08008678 0x4c ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x08008678 net::tcp_run()
+ .text.hot._ZN3net10tcp_handleEP5t_tcp
+ 0x080086c4 0x620 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080086c4 net::tcp_handle(t_tcp*)
+ .text.hot._ZN3net10udp_handleEP5t_udp
+ 0x08008ce4 0x84 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08008ce4 net::udp_handle(t_udp*)
+ .text.hot._ZN3net10arp_handleEP5t_arp
+ 0x08008d68 0x114 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08008d68 net::arp_handle(t_arp*)
+ .text.hot._ZN3net9ip_handleEP5t_ip4
+ 0x08008e7c 0x54 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08008e7c net::ip_handle(t_ip4*)
+ .text.hot._ZN3net11icmp_handleEP6t_icmp
+ 0x08008ed0 0x80 ../lib-network/lib_gd32/libnetwork.a(icmp.o)
+ 0x08008ed0 net::icmp_handle(t_icmp*)
*(.text)
- .text 0x0000000008008e64 0xa0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
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- 0x0000000008008f34 __aeabi_ldiv0
- 0x0000000008008f34 __aeabi_idiv0
+ .text 0x08008f50 0xa0 /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o)
+ 0x08008f50 __aeabi_d2f
+ 0x08008f50 __truncdfsf2
*(.text*)
.text.Reset_Handler
- 0x0000000008008f38 0x44 build_gd32/startup_gd32f407.o
- 0x0000000008008f38 Reset_Handler
+ 0x08008ff0 0x50 build_gd32/startup_gd32f407.o
+ 0x08008ff0 Reset_Handler
.text.Default_Handler
- 0x0000000008008f7c 0x2 build_gd32/startup_gd32f407.o
- 0x0000000008008f7c USBHS_EP1_Out_IRQHandler
- 0x0000000008008f7c EXTI2_IRQHandler
- 0x0000000008008f7c DebugMon_Handler
- 0x0000000008008f7c LVD_IRQHandler
- 0x0000000008008f7c CAN1_EWMC_IRQHandler
- 0x0000000008008f7c HardFault_Handler
- 0x0000000008008f7c TIMER7_UP_TIMER12_IRQHandler
- 0x0000000008008f7c SDIO_IRQHandler
- 0x0000000008008f7c PendSV_Handler
- 0x0000000008008f7c NMI_Handler
- 0x0000000008008f7c EXTI3_IRQHandler
- 0x0000000008008f7c DCI_IRQHandler
- 0x0000000008008f7c USBFS_WKUP_IRQHandler
- 0x0000000008008f7c USBHS_IRQHandler
- 0x0000000008008f7c TIMER5_DAC_IRQHandler
- 0x0000000008008f7c TIMER0_TRG_CMT_TIMER10_IRQHandler
- 0x0000000008008f7c USBFS_IRQHandler
- 0x0000000008008f7c DMA0_Channel6_IRQHandler
- 0x0000000008008f7c I2C0_EV_IRQHandler
- 0x0000000008008f7c EXTI0_IRQHandler
- 0x0000000008008f7c I2C2_EV_IRQHandler
- 0x0000000008008f7c CAN1_RX0_IRQHandler
- 0x0000000008008f7c FPU_IRQHandler
- 0x0000000008008f7c TIMER7_TRG_CMT_TIMER13_IRQHandler
- 0x0000000008008f7c UsageFault_Handler
- 0x0000000008008f7c SPI1_IRQHandler
- 0x0000000008008f7c DMA0_Channel0_IRQHandler
- 0x0000000008008f7c TIMER0_BRK_TIMER8_IRQHandler
- 0x0000000008008f7c DMA1_Channel0_IRQHandler
- 0x0000000008008f7c TIMER7_BRK_TIMER11_IRQHandler
- 0x0000000008008f7c DMA1_Channel4_IRQHandler
- 0x0000000008008f7c I2C0_ER_IRQHandler
- 0x0000000008008f7c TIMER0_UP_TIMER9_IRQHandler
- 0x0000000008008f7c DMA1_Channel7_IRQHandler
- 0x0000000008008f7c CAN1_RX1_IRQHandler
- 0x0000000008008f7c DMA0_Channel2_IRQHandler
- 0x0000000008008f7c I2C1_EV_IRQHandler
- 0x0000000008008f7c UART4_IRQHandler
- 0x0000000008008f7c EXTI10_15_IRQHandler
- 0x0000000008008f7c DMA1_Channel1_IRQHandler
- 0x0000000008008f7c Default_Handler
- 0x0000000008008f7c TIMER7_Channel_IRQHandler
- 0x0000000008008f7c DMA0_Channel7_IRQHandler
- 0x0000000008008f7c ADC_IRQHandler
- 0x0000000008008f7c CAN0_TX_IRQHandler
- 0x0000000008008f7c WWDGT_IRQHandler
- 0x0000000008008f7c EXMC_IRQHandler
- 0x0000000008008f7c TAMPER_STAMP_IRQHandler
- 0x0000000008008f7c RTC_WKUP_IRQHandler
- 0x0000000008008f7c SPI2_IRQHandler
- 0x0000000008008f7c MemManage_Handler
- 0x0000000008008f7c CAN1_TX_IRQHandler
- 0x0000000008008f7c SVC_Handler
- 0x0000000008008f7c RCU_CTC_IRQHandler
- 0x0000000008008f7c DMA1_Channel5_IRQHandler
- 0x0000000008008f7c EXTI4_IRQHandler
- 0x0000000008008f7c CAN0_RX1_IRQHandler
- 0x0000000008008f7c DMA0_Channel5_IRQHandler
- 0x0000000008008f7c DMA1_Channel3_IRQHandler
- 0x0000000008008f7c EXTI5_9_IRQHandler
- 0x0000000008008f7c DMA0_Channel1_IRQHandler
- 0x0000000008008f7c TIMER0_Channel_IRQHandler
- 0x0000000008008f7c EXTI1_IRQHandler
- 0x0000000008008f7c ENET_WKUP_IRQHandler
- 0x0000000008008f7c USBHS_EP1_In_IRQHandler
- 0x0000000008008f7c SPI0_IRQHandler
- 0x0000000008008f7c CAN0_EWMC_IRQHandler
- 0x0000000008008f7c CAN0_RX0_IRQHandler
- 0x0000000008008f7c I2C2_ER_IRQHandler
- 0x0000000008008f7c DMA1_Channel2_IRQHandler
- 0x0000000008008f7c BusFault_Handler
- 0x0000000008008f7c USART1_IRQHandler
- 0x0000000008008f7c UART3_IRQHandler
- 0x0000000008008f7c I2C1_ER_IRQHandler
- 0x0000000008008f7c FMC_IRQHandler
- 0x0000000008008f7c USBHS_WKUP_IRQHandler
- 0x0000000008008f7c DMA0_Channel4_IRQHandler
- 0x0000000008008f7c TRNG_IRQHandler
- 0x0000000008008f7c ENET_IRQHandler
- 0x0000000008008f7c RTC_Alarm_IRQHandler
- .text._ZN12dmxconfigudpL4atoiEPKcm
- 0x0000000008008f7e 0x24 build_gd32/firmware/main.o
- .text._ZN10LLRPDevice7CopyUIDEPh
- 0x0000000008008fa2 0x2 build_gd32/firmware/main.o
- 0x0000000008008fa2 LLRPDevice::CopyUID(unsigned char*)
- .text._ZN10LLRPDevice7CopyCIDEPh
- 0x0000000008008fa4 0x2 build_gd32/firmware/main.o
- 0x0000000008008fa4 LLRPDevice::CopyCID(unsigned char*)
- .text._ZN10LLRPDevice20LLRPHandleRdmCommandEPKh
- 0x0000000008008fa6 0x4 build_gd32/firmware/main.o
- 0x0000000008008fa6 LLRPDevice::LLRPHandleRdmCommand(unsigned char const*)
- *fill* 0x0000000008008faa 0x2
- .text._ZN12RDMNetDevice20LLRPHandleRdmCommandEPKh
- 0x0000000008008fac 0x1c build_gd32/firmware/main.o
- 0x0000000008008fac RDMNetDevice::LLRPHandleRdmCommand(unsigned char const*)
- 0x0000000008008fc0 non-virtual thunk to RDMNetDevice::LLRPHandleRdmCommand(unsigned char const*)
- .text._ZN10LLRPDeviceD2Ev
- 0x0000000008008fc8 0x24 build_gd32/firmware/main.o
- 0x0000000008008fc8 LLRPDevice::~LLRPDevice()
- 0x0000000008008fc8 LLRPDevice::~LLRPDevice()
- .text._ZN10LLRPDeviceD0Ev
- 0x0000000008008fec 0x12 build_gd32/firmware/main.o
- 0x0000000008008fec LLRPDevice::~LLRPDevice()
+ 0x08009040 0x2 build_gd32/startup_gd32f407.o
+ 0x08009040 USBHS_EP1_Out_IRQHandler
+ 0x08009040 EXTI2_IRQHandler
+ 0x08009040 TIMER2_IRQHandler
+ 0x08009040 DebugMon_Handler
+ 0x08009040 LVD_IRQHandler
+ 0x08009040 CAN1_EWMC_IRQHandler
+ 0x08009040 TIMER7_UP_TIMER12_IRQHandler
+ 0x08009040 SDIO_IRQHandler
+ 0x08009040 PendSV_Handler
+ 0x08009040 NMI_Handler
+ 0x08009040 EXTI3_IRQHandler
+ 0x08009040 DCI_IRQHandler
+ 0x08009040 USBFS_WKUP_IRQHandler
+ 0x08009040 USBHS_IRQHandler
+ 0x08009040 TIMER5_DAC_IRQHandler
+ 0x08009040 TIMER0_TRG_CMT_TIMER10_IRQHandler
+ 0x08009040 USBFS_IRQHandler
+ 0x08009040 TIMER3_IRQHandler
+ 0x08009040 DMA0_Channel6_IRQHandler
+ 0x08009040 I2C0_EV_IRQHandler
+ 0x08009040 EXTI0_IRQHandler
+ 0x08009040 I2C2_EV_IRQHandler
+ 0x08009040 CAN1_RX0_IRQHandler
+ 0x08009040 FPU_IRQHandler
+ 0x08009040 TIMER7_TRG_CMT_TIMER13_IRQHandler
+ 0x08009040 UsageFault_Handler
+ 0x08009040 SPI1_IRQHandler
+ 0x08009040 DMA0_Channel0_IRQHandler
+ 0x08009040 TIMER0_BRK_TIMER8_IRQHandler
+ 0x08009040 DMA1_Channel0_IRQHandler
+ 0x08009040 TIMER7_BRK_TIMER11_IRQHandler
+ 0x08009040 DMA1_Channel4_IRQHandler
+ 0x08009040 I2C0_ER_IRQHandler
+ 0x08009040 TIMER0_UP_TIMER9_IRQHandler
+ 0x08009040 DMA1_Channel7_IRQHandler
+ 0x08009040 CAN1_RX1_IRQHandler
+ 0x08009040 DMA0_Channel2_IRQHandler
+ 0x08009040 I2C1_EV_IRQHandler
+ 0x08009040 UART4_IRQHandler
+ 0x08009040 EXTI10_15_IRQHandler
+ 0x08009040 DMA1_Channel1_IRQHandler
+ 0x08009040 Default_Handler
+ 0x08009040 TIMER7_Channel_IRQHandler
+ 0x08009040 DMA0_Channel7_IRQHandler
+ 0x08009040 ADC_IRQHandler
+ 0x08009040 CAN0_TX_IRQHandler
+ 0x08009040 WWDGT_IRQHandler
+ 0x08009040 EXMC_IRQHandler
+ 0x08009040 TAMPER_STAMP_IRQHandler
+ 0x08009040 RTC_WKUP_IRQHandler
+ 0x08009040 SPI2_IRQHandler
+ 0x08009040 MemManage_Handler
+ 0x08009040 CAN1_TX_IRQHandler
+ 0x08009040 SVC_Handler
+ 0x08009040 RCU_CTC_IRQHandler
+ 0x08009040 DMA1_Channel5_IRQHandler
+ 0x08009040 EXTI4_IRQHandler
+ 0x08009040 CAN0_RX1_IRQHandler
+ 0x08009040 DMA0_Channel5_IRQHandler
+ 0x08009040 DMA1_Channel3_IRQHandler
+ 0x08009040 EXTI5_9_IRQHandler
+ 0x08009040 DMA0_Channel1_IRQHandler
+ 0x08009040 TIMER0_Channel_IRQHandler
+ 0x08009040 EXTI1_IRQHandler
+ 0x08009040 ENET_WKUP_IRQHandler
+ 0x08009040 USBHS_EP1_In_IRQHandler
+ 0x08009040 SPI0_IRQHandler
+ 0x08009040 CAN0_EWMC_IRQHandler
+ 0x08009040 CAN0_RX0_IRQHandler
+ 0x08009040 I2C2_ER_IRQHandler
+ 0x08009040 DMA1_Channel2_IRQHandler
+ 0x08009040 BusFault_Handler
+ 0x08009040 USART1_IRQHandler
+ 0x08009040 UART3_IRQHandler
+ 0x08009040 I2C1_ER_IRQHandler
+ 0x08009040 FMC_IRQHandler
+ 0x08009040 USBHS_WKUP_IRQHandler
+ 0x08009040 DMA0_Channel4_IRQHandler
+ 0x08009040 TRNG_IRQHandler
+ 0x08009040 ENET_IRQHandler
+ 0x08009040 RTC_Alarm_IRQHandler
+ .text.HardFault_Handler
+ 0x08009042 0x16 build_gd32/hardfault_handler.o
+ 0x08009042 HardFault_Handler
+ .text.hardfault_handler
+ 0x08009058 0x114 build_gd32/hardfault_handler.o
+ 0x08009058 hardfault_handler
+ .text._ZN8LightSet18SetDmxStartAddressEt
+ 0x0800916c 0x4 build_gd32/firmware/main.o
+ 0x0800916c LightSet::SetDmxStartAddress(unsigned short)
+ .text._ZN8LightSet18GetDmxStartAddressEv
+ 0x08009170 0x4 build_gd32/firmware/main.o
+ 0x08009170 LightSet::GetDmxStartAddress()
+ .text._ZN8LightSet15GetDmxFootprintEv
+ 0x08009174 0x6 build_gd32/firmware/main.o
+ 0x08009174 LightSet::GetDmxFootprint()
+ .text._ZN8LightSet11GetSlotInfoEtRN8lightset8SlotInfoE
+ 0x0800917a 0xa build_gd32/firmware/main.o
+ 0x0800917a LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&)
+ .text._ZN7DmxSend14GetRefreshRateEv
+ 0x08009184 0x18 build_gd32/firmware/main.o
+ 0x08009184 DmxSend::GetRefreshRate()
+ .text._ZN7DmxSendD2Ev
+ 0x0800919c 0x2 build_gd32/firmware/main.o
+ 0x0800919c DmxSend::~DmxSend()
+ 0x0800919c DmxSend::~DmxSend()
+ *fill* 0x0800919e 0x2
+ .text._ZN7DmxSend8BlackoutEb
+ 0x080091a0 0xc build_gd32/firmware/main.o
+ 0x080091a0 DmxSend::Blackout(bool)
+ .text._ZN7DmxSend4StopEm
+ 0x080091ac 0x30 build_gd32/firmware/main.o
+ 0x080091ac DmxSend::Stop(unsigned long)
+ .text._ZN7DmxSend6FullOnEv
+ 0x080091dc 0xc build_gd32/firmware/main.o
+ 0x080091dc DmxSend::FullOn()
+ .text._ZNK7DmxSend14GetOutputStyleEm
+ 0x080091e8 0x18 build_gd32/firmware/main.o
+ 0x080091e8 DmxSend::GetOutputStyle(unsigned long) const
+ .text._ZN7DmxSend5StartEm
+ 0x08009200 0x34 build_gd32/firmware/main.o
+ 0x08009200 DmxSend::Start(unsigned long)
+ .text._ZN7DmxSend14SetOutputStyleEmN8lightset11OutputStyleE
+ 0x08009234 0x14 build_gd32/firmware/main.o
+ 0x08009234 DmxSend::SetOutputStyle(unsigned long, lightset::OutputStyle)
+ .text._ZN7DmxSend4SyncEv
+ 0x08009248 0x4c build_gd32/firmware/main.o
+ 0x08009248 DmxSend::Sync()
+ .text._ZN7DmxSend4SyncEm
+ 0x08009294 0x2c build_gd32/firmware/main.o
+ 0x08009294 DmxSend::Sync(unsigned long)
+ .text._ZN7DmxSendD0Ev
+ 0x080092c0 0xe build_gd32/firmware/main.o
+ 0x080092c0 DmxSend::~DmxSend()
+ *fill* 0x080092ce 0x2
+ .text._ZN7DmxSend5PrintEv
+ 0x080092d0 0x60 build_gd32/firmware/main.o
+ 0x080092d0 DmxSend::Print()
+ .text._ZN7DmxSend7SetDataEmPKhmb
+ 0x08009330 0x24 build_gd32/firmware/main.o
+ 0x08009330 DmxSend::SetData(unsigned long, unsigned char const*, unsigned long, bool)
.text._ZN7Display12SetCursorPosEmm.isra.0
- 0x0000000008008ffe 0xa build_gd32/firmware/main.o
+ 0x08009354 0xa build_gd32/firmware/main.o
.text._ZN7Display7PutCharEi.isra.0
- 0x0000000008009008 0xa build_gd32/firmware/main.o
- *fill* 0x0000000008009012 0x2
- .text._ZN12RDMNetDeviceD2Ev
- 0x0000000008009014 0x3c build_gd32/firmware/main.o
- 0x0000000008009014 RDMNetDevice::~RDMNetDevice()
- 0x0000000008009014 RDMNetDevice::~RDMNetDevice()
- 0x0000000008009048 non-virtual thunk to RDMNetDevice::~RDMNetDevice()
- .text._ZN12RDMNetDeviceD0Ev
- 0x0000000008009050 0x18 build_gd32/firmware/main.o
- 0x0000000008009050 RDMNetDevice::~RDMNetDevice()
- 0x0000000008009062 non-virtual thunk to RDMNetDevice::~RDMNetDevice()
- .text.memcmp 0x0000000008009068 0x20 build_gd32/firmware/main.o
- 0x0000000008009068 memcmp
- .text.memcpy 0x0000000008009088 0x16 build_gd32/firmware/main.o
- 0x0000000008009088 memcpy
- *fill* 0x000000000800909e 0x2
- .text._ZN12RDMNetDevice7CopyCIDEPh
- 0x00000000080090a0 0x1c build_gd32/firmware/main.o
- 0x00000000080090a0 RDMNetDevice::CopyCID(unsigned char*)
- 0x00000000080090b4 non-virtual thunk to RDMNetDevice::CopyCID(unsigned char*)
- .text._ZN12RDMNetDevice7CopyUIDEPh
- 0x00000000080090bc 0x18 build_gd32/firmware/main.o
- 0x00000000080090bc RDMNetDevice::CopyUID(unsigned char*)
- 0x00000000080090ce non-virtual thunk to RDMNetDevice::CopyUID(unsigned char*)
- .text._ZN7Display10TextStatusEPKc
- 0x00000000080090d4 0x66 build_gd32/firmware/main.o
- 0x00000000080090d4 Display::TextStatus(char const*)
- .text._ZN7Display10TextStatusEPKc22Display7SegmentMessagem
- 0x000000000800913a 0x50 build_gd32/firmware/main.o
- 0x000000000800913a Display::TextStatus(char const*, Display7SegmentMessage, unsigned long)
- *fill* 0x000000000800918a 0x2
+ 0x0800935e 0xa build_gd32/firmware/main.o
+ .text._ZN3net8dhcp_runEv
+ 0x08009368 0x38 build_gd32/firmware/main.o
+ 0x08009368 net::dhcp_run()
+ .text._ZN7Display10TextStatusEPKcm
+ 0x080093a0 0x70 build_gd32/firmware/main.o
+ 0x080093a0 Display::TextStatus(char const*, unsigned long)
.text._ZN7Display8SetSleepEb
- 0x000000000800918c 0x20 build_gd32/firmware/main.o
- 0x000000000800918c Display::SetSleep(bool)
+ 0x08009410 0x20 build_gd32/firmware/main.o
+ 0x08009410 Display::SetSleep(bool)
.text._ZN10E131Bridge3RunEv
- 0x00000000080091ac 0xb0 build_gd32/firmware/main.o
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.text._ZN8hardware8ledblink7displayEm
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.text._ZN8Hardware13RebootHandlerEv
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.text.startup.main
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.text._ZN3rdm6device9responder15factorydefaultsEv
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.text._ZN18RDMSoftwareVersion10GetVersionEv
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.text._ZN18RDMSoftwareVersion16GetVersionLengthEv
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.text._ZN18RDMSoftwareVersion12GetVersionIdEv
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.text._ZN12RemoteConfig16HandleDisplayGetEv
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.text._ZN12RemoteConfig12HandleUptimeEv
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- 0x000000000800a4d8 RemoteConfig::HandleUptime()
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+ .text._ZN12RemoteConfig13HandleVersionEv
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+ .text._ZN12RemoteConfig13HandleTftpGetEv
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+ .text._ZN12RemoteConfig10HandleListEv
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.text._ZN12RemoteConfig16HandleDisplaySetEv
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.text._ZN12RemoteConfig13HandleTftpSetEv
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.text._ZN12RemoteConfigC2EN12remoteconfig4NodeENS0_6OutputEm
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.text._ZNK12RemoteConfig13GetStringNodeEv
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.text._ZNK12RemoteConfig15GetStringOutputEv
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- 0x000000000800a5f8 RemoteConfig::GetStringOutput() const
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+ 0x08009e20 RemoteConfig::GetStringOutput() const
.text._ZN12RemoteConfig10SetDisableEb
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+ 0x08009e38 0x54 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x08009e38 RemoteConfig::SetDisable(bool)
.text._ZN12RemoteConfig14SetDisplayNameEPKc
- 0x000000000800a644 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a644 RemoteConfig::SetDisplayName(char const*)
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+ 0x08009e8c RemoteConfig::SetDisplayName(char const*)
.text._ZN12RemoteConfig9HandleGetEPvm
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- 0x000000000800a674 RemoteConfig::HandleGet(void*, unsigned long)
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.text._ZN12RemoteConfig17HandleGetNoParamsEv
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- 0x000000000800a72c RemoteConfig::HandleGetNoParams()
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.text._ZN12RemoteConfig19HandleGetRconfigTxtERm
- 0x000000000800a734 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
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+ 0x08009f78 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
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+ .text._ZN12RemoteConfig15HandleGetEnvTxtERm
+ 0x08009fa0 0x24 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x08009fa0 RemoteConfig::HandleGetEnvTxt(unsigned long&)
.text._ZN12RemoteConfig19HandleGetNetworkTxtERm
- 0x000000000800a764 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a764 RemoteConfig::HandleGetNetworkTxt(unsigned long&)
+ 0x08009fc4 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x08009fc4 RemoteConfig::HandleGetNetworkTxt(unsigned long&)
.text._ZN12RemoteConfig16HandleGetE131TxtERm
- 0x000000000800a794 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a794 RemoteConfig::HandleGetE131Txt(unsigned long&)
+ 0x08009fec 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x08009fec RemoteConfig::HandleGetE131Txt(unsigned long&)
.text._ZN12RemoteConfig18HandleGetParamsTxtERm
- 0x000000000800a7c4 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a7c4 RemoteConfig::HandleGetParamsTxt(unsigned long&)
+ 0x0800a014 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a014 RemoteConfig::HandleGetParamsTxt(unsigned long&)
.text._ZN12RemoteConfig19HandleGetDisplayTxtERm
- 0x000000000800a7f4 0x30 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a7f4 RemoteConfig::HandleGetDisplayTxt(unsigned long&)
+ 0x0800a03c 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a03c RemoteConfig::HandleGetDisplayTxt(unsigned long&)
.text._ZN12RemoteConfig9HandleSetEPvm
- 0x000000000800a824 0x84 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a824 RemoteConfig::HandleSet(void*, unsigned long)
+ 0x0800a064 0x84 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a064 RemoteConfig::HandleSet(void*, unsigned long)
.text._ZN12RemoteConfig13HandleRequestEv
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- .text._ZN12RemoteConfig16HandleSetRconfigEv
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- 0x000000000800a9cc RemoteConfig::HandleSetRconfig()
+ 0x0800a0e8 0x120 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a0e8 RemoteConfig::HandleRequest()
+ .text._ZN12RemoteConfig19HandleSetRconfigTxtEv
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+ 0x0800a208 RemoteConfig::HandleSetRconfigTxt()
+ .text._ZN12RemoteConfig15HandleSetEnvTxtEv
+ 0x0800a230 0x20 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a230 RemoteConfig::HandleSetEnvTxt()
.text._ZN12RemoteConfig19HandleSetNetworkTxtEv
- 0x000000000800a9fc 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800a9fc RemoteConfig::HandleSetNetworkTxt()
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.text._ZN12RemoteConfig16HandleSetE131TxtEv
- 0x000000000800aa24 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800aa24 RemoteConfig::HandleSetE131Txt()
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+ 0x0800a270 RemoteConfig::HandleSetE131Txt()
.text._ZN12RemoteConfig18HandleSetParamsTxtEv
- 0x000000000800aa4c 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800aa4c RemoteConfig::HandleSetParamsTxt()
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.text._ZN12RemoteConfig19HandleSetDisplayTxtEv
- 0x000000000800aa74 0x28 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800aa74 RemoteConfig::HandleSetDisplayTxt()
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.text._ZN12RemoteConfig13HandleFactoryEv
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- .text._ZN17PropertiesBuilder3AddEPKcb.isra.0
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- 0x000000000800ab08 RemoteConfigParams::RemoteConfigParams(RemoteConfigParamsStore*)
+ 0x0800a2d0 0x1c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigfactory.o)
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+ .text._ZN18RemoteConfigParamsC2Ev
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.text._ZN18RemoteConfigParams4LoadEv
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- 0x000000000800ab1c RemoteConfigParams::Load()
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.text._ZN18RemoteConfigParams4LoadEPKcm
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.text._ZN18RemoteConfigParams7SetBoolEhm
- 0x000000000800ab70 0x10 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
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.text._ZN18RemoteConfigParams16callbackFunctionEPKc
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- 0x000000000800ab80 RemoteConfigParams::callbackFunction(char const*)
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.text._ZN18RemoteConfigParams22staticCallbackFunctionEPvPKc
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- .text._ZN18RemoteConfigParams7BuilderEPK19TRemoteConfigParamsPcmRm
- 0x000000000800ac30 0x120 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
- 0x000000000800ac30 RemoteConfigParams::Builder(TRemoteConfigParams const*, char*, unsigned long, unsigned long&)
+ 0x0800a3fc 0x4 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
+ 0x0800a3fc RemoteConfigParams::staticCallbackFunction(void*, char const*)
+ .text._ZN18RemoteConfigParams7BuilderEPKN18remoteconfigparams6ParamsEPcmRm
+ 0x0800a400 0x13c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
+ 0x0800a400 RemoteConfigParams::Builder(remoteconfigparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN18RemoteConfigParams3SetEP12RemoteConfig
- 0x000000000800ad50 0x40 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigparams.o)
- 0x000000000800ad50 RemoteConfigParams::Set(RemoteConfig*)
- .text._ZN18RemoteConfigParams4DumpEv
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- 0x000000000800ad90 RemoteConfigParams::Dump()
- *fill* 0x000000000800ad92 0x2
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+ 0x0800a53c RemoteConfigParams::Set(RemoteConfig*)
+ .text._ZN7Display10TextStatusEPKc
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+ 0x0800a57c Display::TextStatus(char const*)
.text._ZN12RemoteConfig12HandleRebootEv
- 0x000000000800ad94 0x98 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigreboot.o)
- 0x000000000800ad94 RemoteConfig::HandleReboot()
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+ 0x0800a5e8 RemoteConfig::HandleReboot()
.text._ZN12RemoteConfig8GetIndexEPKvRm
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- 0x000000000800ae2c RemoteConfig::GetIndex(void const*, unsigned long&)
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.text._ZN12RemoteConfig21PlatformHandleTftpSetEv
- 0x000000000800ae80 0x40 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800ae80 RemoteConfig::PlatformHandleTftpSet()
+ 0x0800a6a0 0x48 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
+ 0x0800a6a0 RemoteConfig::PlatformHandleTftpSet()
.text._ZN12RemoteConfig21PlatformHandleTftpGetEv
- 0x000000000800aec0 0x1a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfig.o)
- 0x000000000800aec0 RemoteConfig::PlatformHandleTftpGet()
- .text.strcmp 0x000000000800aeda 0x1a ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800aeda strcmp
- .text.strcasecmp
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- 0x000000000800aef4 strcasecmp
- .text._ZN16PropertiesConfig10EnableJSONEb
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- 0x000000000800af28 PropertiesConfig::EnableJSON(bool)
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+ 0x0800a6e8 RemoteConfig::PlatformHandleTftpGet()
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.text._ZN10HttpDaemonC2Ev
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- .text._ZN10HttpDaemon11ParseMethodEPc
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- .text._ZN10HttpDaemon12HandleGetTxtEv
- 0x000000000800b104 0x88 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b104 HttpDaemon::HandleGetTxt()
- .text._ZN10HttpDaemon9HandleGetEv
- 0x000000000800b18c 0x110 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b18c HttpDaemon::HandleGet()
- .text._ZN10HttpDaemon10HandlePostEb
- 0x000000000800b29c 0x15c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b29c HttpDaemon::HandlePost(bool)
- .text._ZN10HttpDaemon13HandleRequestEm
- 0x000000000800b3f8 0x140 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httd.o)
- 0x000000000800b3f8 HttpDaemon::HandleRequest(unsigned long)
- .text._ZN12remoteconfig13json_get_listEPct
- 0x000000000800b538 0x60 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b538 remoteconfig::json_get_list(char*, unsigned short)
- .text._ZN12remoteconfig16json_get_versionEPct
- 0x000000000800b598 0x38 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b598 remoteconfig::json_get_version(char*, unsigned short)
- .text._ZN12remoteconfig15json_get_uptimeEPct
- 0x000000000800b5d0 0x20 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b5d0 remoteconfig::json_get_uptime(char*, unsigned short)
- .text._ZN12remoteconfig16json_get_displayEPct
- 0x000000000800b5f0 0x20 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b5f0 remoteconfig::json_get_display(char*, unsigned short)
- .text._ZN12remoteconfig18json_get_directoryEPct
- 0x000000000800b610 0x10 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
- 0x000000000800b610 remoteconfig::json_get_directory(char*, unsigned short)
- .text._Z16get_file_contentPKcPcRN4http12contentTypesE
- 0x000000000800b620 0x4c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
- 0x000000000800b620 get_file_content(char const*, char*, http::contentTypes&)
- .text._ZN8lightset4Data13IMergeSourceAEmPKhmNS_9MergeModeE.part.0
- 0x000000000800b66c 0x28 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- .text.memset.isra.0
- 0x000000000800b694 0xe ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- .text.memcpy.isra.0
- 0x000000000800b6a2 0x14 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- *fill* 0x000000000800b6b6 0x2
- .text._ZN8lightset4Data3GetEv
- 0x000000000800b6b8 0x18 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b6b8 lightset::Data::Get()
- .text._ZN8lightset4Data10SetSourceAEmPKhm
- 0x000000000800b6d0 0x3c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b6d0 lightset::Data::SetSourceA(unsigned long, unsigned char const*, unsigned long)
- .text._ZN8lightset4Data12MergeSourceAEmPKhmNS_9MergeModeE
- 0x000000000800b70c 0x52 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b70c lightset::Data::MergeSourceA(unsigned long, unsigned char const*, unsigned long, lightset::MergeMode)
- .text._ZN8lightset4Data12MergeSourceBEmPKhmNS_9MergeModeE
- 0x000000000800b75e 0x54 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b75e lightset::Data::MergeSourceB(unsigned long, unsigned char const*, unsigned long, lightset::MergeMode)
- *fill* 0x000000000800b7b2 0x2
+ 0x0800a704 0x6c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpd.o)
+ 0x0800a704 HttpDaemon::HttpDaemon()
+ 0x0800a704 HttpDaemon::HttpDaemon()
+ .text._ZN10DisplaySet8SetSleepEb
+ 0x0800a770 0x4 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a770 DisplaySet::SetSleep(bool)
+ .text._ZN23HttpDeamonHandleRequest11ParseMethodEPc
+ 0x0800a774 0xc8 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a774 HttpDeamonHandleRequest::ParseMethod(char*)
+ .text._ZN23HttpDeamonHandleRequest16ParseHeaderFieldEPc
+ 0x0800a83c 0x124 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a83c HttpDeamonHandleRequest::ParseHeaderField(char*)
+ .text._ZN23HttpDeamonHandleRequest12ParseRequestEv
+ 0x0800a960 0x7c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a960 HttpDeamonHandleRequest::ParseRequest()
+ .text._ZN23HttpDeamonHandleRequest12HandleGetTxtEv
+ 0x0800a9dc 0x9c ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800a9dc HttpDeamonHandleRequest::HandleGetTxt()
+ .text._ZN23HttpDeamonHandleRequest9HandleGetEv
+ 0x0800aa78 0x214 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800aa78 HttpDeamonHandleRequest::HandleGet()
+ .text._ZN23HttpDeamonHandleRequest10HandlePostEb
+ 0x0800ac8c 0x1cc ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800ac8c HttpDeamonHandleRequest::HandlePost(bool)
+ .text._ZN23HttpDeamonHandleRequest13HandleRequestEmPc
+ 0x0800ae58 0x170 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(httpdhandlerequest.o)
+ 0x0800ae58 HttpDeamonHandleRequest::HandleRequest(unsigned long, char*)
+ .text._ZN12remoteconfig13json_get_listEPcm
+ 0x0800afc8 0x64 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800afc8 remoteconfig::json_get_list(char*, unsigned long)
+ .text._ZN12remoteconfig16json_get_versionEPcm
+ 0x0800b02c 0x38 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b02c remoteconfig::json_get_version(char*, unsigned long)
+ .text._ZN12remoteconfig15json_get_uptimeEPcm
+ 0x0800b064 0x14 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b064 remoteconfig::json_get_uptime(char*, unsigned long)
+ .text._ZN12remoteconfig16json_get_displayEPcm
+ 0x0800b078 0x18 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b078 remoteconfig::json_get_display(char*, unsigned long)
+ .text._ZN12remoteconfig18json_get_directoryEPcm
+ 0x0800b090 0xc ../lib-remoteconfig/lib_gd32/libremoteconfig.a(remoteconfigjson.o)
+ 0x0800b090 remoteconfig::json_get_directory(char*, unsigned long)
+ .text._Z16get_file_contentPKcRmRN4http12contentTypesE
+ 0x0800b09c 0x40 ../lib-remoteconfig/lib_gd32/libremoteconfig.a(get_file_content.o)
+ 0x0800b09c get_file_content(char const*, unsigned long&, http::contentTypes&)
+ .text._ZN8LightSet8BlackoutEb
+ 0x0800b0dc 0x4 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b0dc LightSet::Blackout(bool)
+ .text._ZN8LightSet6FullOnEv
+ 0x0800b0e0 0x4 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b0e0 LightSet::FullOn()
.text._ZN10E131BridgeC2Ev
- 0x000000000800b7b4 0xe8 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b7b4 E131Bridge::E131Bridge()
- 0x000000000800b7b4 E131Bridge::E131Bridge()
+ 0x0800b0e4 0x124 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b0e4 E131Bridge::E131Bridge()
+ 0x0800b0e4 E131Bridge::E131Bridge()
.text._ZN10E131Bridge4StopEv
- 0x000000000800b89c 0x78 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b89c E131Bridge::Stop()
- .text._ZN10E131Bridge13LeaveUniverseEmt
- 0x000000000800b914 0x2e ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b914 E131Bridge::LeaveUniverse(unsigned long, unsigned short)
+ 0x0800b208 0x84 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b208 E131Bridge::Stop()
.text._ZN10E131Bridge25SetSynchronizationAddressEbbt
- 0x000000000800b942 0x44 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b942 E131Bridge::SetSynchronizationAddress(bool, bool, unsigned short)
- *fill* 0x000000000800b986 0x2
+ 0x0800b28c 0x50 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b28c E131Bridge::SetSynchronizationAddress(bool, bool, unsigned short)
.text._ZN10E131Bridge15SetLocalMergingEv
- 0x000000000800b988 0x78 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800b988 E131Bridge::SetLocalMerging()
+ 0x0800b2dc 0x7c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b2dc E131Bridge::SetLocalMerging()
.text._ZN10E131Bridge5StartEv
- 0x000000000800ba00 0xe8 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800ba00 E131Bridge::Start()
+ 0x0800b358 0xb0 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b358 E131Bridge::Start()
.text._ZN10E131Bridge11SetUniverseEmN8lightset7PortDirEt
- 0x000000000800bae8 0xe6 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bae8 E131Bridge::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
- .text._ZN10E131Bridge17UpdateMergeStatusEm
- 0x000000000800bbce 0x1e ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bbce E131Bridge::UpdateMergeStatus(unsigned long)
+ 0x0800b408 0x108 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b408 E131Bridge::SetUniverse(unsigned long, lightset::PortDir, unsigned short)
.text._ZN10E131Bridge18CheckMergeTimeoutsEm
- 0x000000000800bbec 0x72 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bbec E131Bridge::CheckMergeTimeouts(unsigned long)
+ 0x0800b510 0x7c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b510 E131Bridge::CheckMergeTimeouts(unsigned long)
.text._ZNK10E131Bridge17IsPriorityTimeOutEm
- 0x000000000800bc5e 0x4a ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bc5e E131Bridge::IsPriorityTimeOut(unsigned long) const
- .text._ZNK10E131Bridge12isIpCidMatchEPKN10e131bridge6SourceE
- 0x000000000800bca8 0x30 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bca8 E131Bridge::isIpCidMatch(e131bridge::Source const*) const
+ 0x0800b58c 0x44 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b58c E131Bridge::IsPriorityTimeOut(unsigned long) const
.text._ZN10E131Bridge27SetNetworkDataLossConditionEbb
- 0x000000000800bcd8 0x14c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800bcd8 E131Bridge::SetNetworkDataLossCondition(bool, bool)
+ 0x0800b5d0 0x128 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b5d0 E131Bridge::SetNetworkDataLossCondition(bool, bool)
.text._ZN10E131Bridge9HandleDmxEv
- 0x000000000800be24 0x342 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800be24 E131Bridge::HandleDmx()
- *fill* 0x000000000800c166 0x2
+ 0x0800b6f8 0x63c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800b6f8 E131Bridge::HandleDmx()
.text._ZN10E131Bridge11IsValidRootEv
- 0x000000000800c168 0x40 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800c168 E131Bridge::IsValidRoot()
- .text._ZN10E131Bridge17IsValidDataPacketEv
- 0x000000000800c1a8 0x2c ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800c1a8 E131Bridge::IsValidDataPacket()
+ 0x0800bd34 0x50 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800bd34 E131Bridge::IsValidRoot()
.text._ZN10E131Bridge7ProcessEv
- 0x000000000800c1d4 0x98 ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
- 0x000000000800c1d4 E131Bridge::Process()
+ 0x0800bd84 0xbc ../lib-e131/lib_gd32/libe131.a(e131bridge.o)
+ 0x0800bd84 E131Bridge::Process()
.text._ZN10E131Bridge21HandleSynchronizationEv
- 0x000000000800c26c 0xa8 ../lib-e131/lib_gd32/libe131.a(e131bridgehandlesynchronization.o)
- 0x000000000800c26c E131Bridge::HandleSynchronization()
+ 0x0800be40 0xac ../lib-e131/lib_gd32/libe131.a(e131bridgehandlesynchronization.o)
+ 0x0800be40 E131Bridge::HandleSynchronization()
.text._ZN10E131Bridge5PrintEv
- 0x000000000800c314 0xf0 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
- 0x000000000800c314 E131Bridge::Print()
- .text._ZN17PropertiesBuilder3AddIPKcEEbS2_T_bm.isra.0
- 0x000000000800c404 0x50 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- .text._ZN10E131ParamsC2EP15E131ParamsStore
- 0x000000000800c454 0x3c ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c454 E131Params::E131Params(E131ParamsStore*)
- 0x000000000800c454 E131Params::E131Params(E131ParamsStore*)
+ 0x0800beec 0xd4 ../lib-e131/lib_gd32/libe131.a(e131bridgeprint.o)
+ 0x0800beec E131Bridge::Print()
+ .text._ZN17PropertiesBuilder3AddIPKcEEbS2_T_bi.isra.0
+ 0x0800bfc0 0x50 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ .text.memcmp 0x0800c010 0x28 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c010 memcmp
+ .text._ZN15E131ParamsStore4CopyEPN10e131params6ParamsE
+ 0x0800c038 0x24 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c038 E131ParamsStore::Copy(e131params::Params*)
+ .text._ZN10E131ParamsC2Ev
+ 0x0800c05c 0x38 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c05c E131Params::E131Params()
+ 0x0800c05c E131Params::E131Params()
.text._ZN10E131Params4LoadEv
- 0x000000000800c490 0x18 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c490 E131Params::Load()
+ 0x0800c094 0x14 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c094 E131Params::Load()
.text._ZN10E131Params4LoadEPKcm
- 0x000000000800c4a8 0x3c ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c4a8 E131Params::Load(char const*, unsigned long)
+ 0x0800c0a8 0x50 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c0a8 E131Params::Load(char const*, unsigned long)
.text._ZN10E131Params16callbackFunctionEPKc
- 0x000000000800c4e4 0x364 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c4e4 E131Params::callbackFunction(char const*)
+ 0x0800c0f8 0x368 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c0f8 E131Params::callbackFunction(char const*)
.text._ZN10E131Params22staticCallbackFunctionEPvPKc
- 0x000000000800c848 0x4 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c848 E131Params::staticCallbackFunction(void*, char const*)
+ 0x0800c460 0x4 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c460 E131Params::staticCallbackFunction(void*, char const*)
.text._ZN10E131Params7BuilderEPKN10e131params6ParamsEPcmRm
- 0x000000000800c84c 0x318 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800c84c E131Params::Builder(e131params::Params const*, char*, unsigned long, unsigned long&)
- .text._ZN10E131Params3SetEm
- 0x000000000800cb64 0xa0 ../lib-e131/lib_gd32/libe131.a(e131params.o)
- 0x000000000800cb64 E131Params::Set(unsigned long)
- .text._ZN10E131Params4DumpEv
- 0x000000000800cc04 0x2 ../lib-e131/lib_gd32/libe131.a(e131paramsdump.o)
- 0x000000000800cc04 E131Params::Dump()
- *fill* 0x000000000800cc06 0x2
+ 0x0800c464 0x330 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c464 E131Params::Builder(e131params::Params const*, char*, unsigned long, unsigned long&)
+ .text._ZN10E131Params3SetEv
+ 0x0800c794 0x98 ../lib-e131/lib_gd32/libe131.a(e131params.o)
+ 0x0800c794 E131Params::Set()
.text._ZN10E131Bridge19FillDiscoveryPacketEv
- 0x000000000800cc08 0xd8 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
- 0x000000000800cc08 E131Bridge::FillDiscoveryPacket()
+ 0x0800c82c 0xb4 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
+ 0x0800c82c E131Bridge::FillDiscoveryPacket()
.text._ZN10E131Bridge19SendDiscoveryPacketEv
- 0x000000000800cce0 0x5a ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
- 0x000000000800cce0 E131Bridge::SendDiscoveryPacket()
+ 0x0800c8e0 0x60 ../lib-e131/lib_gd32/libe131.a(discoverypacket.o)
+ 0x0800c8e0 E131Bridge::SendDiscoveryPacket()
.text.memcpy.isra.0
- 0x000000000800cd3a 0x14 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- *fill* 0x000000000800cd4e 0x2
+ 0x0800c940 0x12 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ *fill* 0x0800c952 0x2
.text._ZN10E131Bridge14FillDataPacketEv
- 0x000000000800cd50 0x8c ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- 0x000000000800cd50 E131Bridge::FillDataPacket()
+ 0x0800c954 0x7c ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ 0x0800c954 E131Bridge::FillDataPacket()
.text._ZN10E131Bridge11HandleDmxInEv
- 0x000000000800cddc 0x1f8 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- 0x000000000800cddc E131Bridge::HandleDmxIn()
- .text.memcpy.isra.0
- 0x000000000800cfd4 0x14 ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- .text._ZN10LLRPDevice20HandleRequestMessageEv
- 0x000000000800cfe8 0x118 ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- 0x000000000800cfe8 LLRPDevice::HandleRequestMessage()
- .text._ZN10LLRPDevice16HandleRdmCommandEv
- 0x000000000800d100 0x9c ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- 0x000000000800d100 LLRPDevice::HandleRdmCommand()
- .text._ZN12RDMNetDevice5PrintEv
- 0x000000000800d19c 0x78 ../lib-rdmnet/lib_gd32/librdmnet.a(rdmnetdevice.o)
- 0x000000000800d19c RDMNetDevice::Print()
- .text._ZN10RDMSensorsC2Ev
- 0x000000000800d214 0x10 ../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o)
- 0x000000000800d214 RDMSensors::RDMSensors()
- 0x000000000800d214 RDMSensors::RDMSensors()
- .text._ZN10RDMSensorsD2Ev
- 0x000000000800d224 0x30 ../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o)
- 0x000000000800d224 RDMSensors::~RDMSensors()
- 0x000000000800d224 RDMSensors::~RDMSensors()
- .text._ZN13RDMSubDevicesC2Ev
- 0x000000000800d254 0x10 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d254 RDMSubDevices::RDMSubDevices()
- 0x000000000800d254 RDMSubDevices::RDMSubDevices()
- .text._ZN13RDMSubDevicesD2Ev
- 0x000000000800d264 0x30 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d264 RDMSubDevices::~RDMSubDevices()
- 0x000000000800d264 RDMSubDevices::~RDMSubDevices()
- .text._ZN13RDMSubDevices7GetInfoEt
- 0x000000000800d294 0x10 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d294 RDMSubDevices::GetInfo(unsigned short)
- .text._ZN13RDMSubDevices8GetLabelEtP18TRDMDeviceInfoData
- 0x000000000800d2a4 0x12 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d2a4 RDMSubDevices::GetLabel(unsigned short, TRDMDeviceInfoData*)
- .text._ZN13RDMSubDevices8SetLabelEtPKch
- 0x000000000800d2b6 0x1c ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d2b6 RDMSubDevices::SetLabel(unsigned short, char const*, unsigned char)
- .text._ZN13RDMSubDevices18GetFactoryDefaultsEv
- 0x000000000800d2d2 0x26 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d2d2 RDMSubDevices::GetFactoryDefaults()
- .text._ZN13RDMSubDevices18SetFactoryDefaultsEv
- 0x000000000800d2f8 0x1e ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000000800d2f8 RDMSubDevices::SetFactoryDefaults()
- .text._ZN12RDMSubDevice8GetLabelEP18TRDMDeviceInfoData
- 0x000000000800d316 0xe ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d316 RDMSubDevice::GetLabel(TRDMDeviceInfoData*)
- .text._ZN12RDMSubDevice8SetLabelEPKc
- 0x000000000800d324 0x1c ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d324 RDMSubDevice::SetLabel(char const*)
- .text._ZN12RDMSubDevice8SetLabelEPKch
- 0x000000000800d340 0x1e ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d340 RDMSubDevice::SetLabel(char const*, unsigned char)
- .text._ZN12RDMSubDevice18SetFactoryDefaultsEv
- 0x000000000800d35e 0x1c ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d35e RDMSubDevice::SetFactoryDefaults()
- .text._ZN12RDMSubDevice17CalculateChecksumEv
- 0x000000000800d37a 0x30 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d37a RDMSubDevice::CalculateChecksum()
- .text._ZN12RDMSubDevice18GetFactoryDefaultsEv
- 0x000000000800d3aa 0x1a ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevice.o)
- 0x000000000800d3aa RDMSubDevice::GetFactoryDefaults()
- .text._ZN15RDMDeviceParamsC2EP20RDMDeviceParamsStore
- 0x000000000800d3c4 0x2a ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800d3c4 RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*)
- 0x000000000800d3c4 RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore*)
+ 0x0800c9d0 0x1e8 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
+ 0x0800c9d0 E131Bridge::HandleDmxIn()
+ .text._ZN20RDMDeviceParamsStore4CopyEPN3rdm12deviceparams6ParamsE
+ 0x0800cbb8 0x24 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x0800cbb8 RDMDeviceParamsStore::Copy(rdm::deviceparams::Params*)
+ .text._ZN15RDMDeviceParamsC2Ev
+ 0x0800cbdc 0x26 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x0800cbdc RDMDeviceParams::RDMDeviceParams()
+ 0x0800cbdc RDMDeviceParams::RDMDeviceParams()
.text._ZN15RDMDeviceParams4LoadEv
- 0x000000000800d3ee 0x16 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800d3ee RDMDeviceParams::Load()
+ 0x0800cc02 0x8 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x0800cc02 RDMDeviceParams::Load()
+ *fill* 0x0800cc0a 0x2
.text._ZN15RDMDeviceParams3SetEP9RDMDevice
- 0x000000000800d404 0x6a ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800d404 RDMDeviceParams::Set(RDMDevice*)
- .text._ZN15RDMDeviceParams4DumpEv
- 0x000000000800d46e 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
- 0x000000000800d46e RDMDeviceParams::Dump()
+ 0x0800cc0c 0xa0 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceparams.o)
+ 0x0800cc0c RDMDeviceParams::Set(RDMDevice*)
.text._ZN18RDMDeviceResponder17PersonalityUpdateEP8LightSet
- 0x000000000800d470 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d470 RDMDeviceResponder::PersonalityUpdate(LightSet*)
+ 0x0800ccac 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x0800ccac RDMDeviceResponder::PersonalityUpdate(LightSet*)
.text._ZN18RDMDeviceResponder21DmxStartAddressUpdateEv
- 0x000000000800d472 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d472 RDMDeviceResponder::DmxStartAddressUpdate()
- .text._ZN18RDMDeviceResponderD2Ev
- 0x000000000800d474 0x20 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d474 RDMDeviceResponder::~RDMDeviceResponder()
- 0x000000000800d474 RDMDeviceResponder::~RDMDeviceResponder()
- .text._ZN18RDMDeviceResponderD0Ev
- 0x000000000800d494 0x12 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d494 RDMDeviceResponder::~RDMDeviceResponder()
- *fill* 0x000000000800d4a6 0x2
- .text._ZN18RDMDeviceResponderC2EPP14RDMPersonalitym
- 0x000000000800d4a8 0x98 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d4a8 RDMDeviceResponder::RDMDeviceResponder(RDMPersonality**, unsigned long)
- 0x000000000800d4a8 RDMDeviceResponder::RDMDeviceResponder(RDMPersonality**, unsigned long)
+ 0x0800ccae 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x0800ccae RDMDeviceResponder::DmxStartAddressUpdate()
+ .text._ZN18RDMDeviceResponderC2EPP14RDMPersonalitymm
+ 0x0800ccb0 0xb4 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x0800ccb0 RDMDeviceResponder::RDMDeviceResponder(RDMPersonality**, unsigned long, unsigned long)
+ 0x0800ccb0 RDMDeviceResponder::RDMDeviceResponder(RDMPersonality**, unsigned long, unsigned long)
.text._ZN18RDMDeviceResponder4InitEv
- 0x000000000800d540 0x126 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d540 RDMDeviceResponder::Init()
- *fill* 0x000000000800d666 0x2
+ 0x0800cd64 0x158 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x0800cd64 RDMDeviceResponder::Init()
.text._ZN18RDMDeviceResponder5PrintEv
- 0x000000000800d668 0x9c ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x000000000800d668 RDMDeviceResponder::Print()
+ 0x0800cebc 0x9c ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x0800cebc RDMDeviceResponder::Print()
.text.memcpy.isra.0
- 0x000000000800d704 0x14 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800cf58 0x12 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ *fill* 0x0800cf6a 0x2
.text._ZN9RDMDevice8SetLabelEPK18TRDMDeviceInfoData
- 0x000000000800d718 0x44 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d718 RDMDevice::SetLabel(TRDMDeviceInfoData const*)
+ 0x0800cf6c 0x70 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800cf6c RDMDevice::SetLabel(TRDMDeviceInfoData const*)
.text._ZN18RDMDeviceResponder18SetFactoryDefaultsEv
- 0x000000000800d75c 0xf8 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d75c RDMDeviceResponder::SetFactoryDefaults()
+ 0x0800cfdc 0x12e ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800cfdc RDMDeviceResponder::SetFactoryDefaults()
.text._ZN10RDMHandlerC2Eb
- 0x000000000800d854 0xc ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d854 RDMHandler::RDMHandler(bool)
- 0x000000000800d854 RDMHandler::RDMHandler(bool)
+ 0x0800d10a 0xc ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d10a RDMHandler::RDMHandler(bool)
+ 0x0800d10a RDMHandler::RDMHandler(bool)
.text._ZN10RDMHandler12HandleStringEPKcm
- 0x000000000800d860 0x18 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d860 RDMHandler::HandleString(char const*, unsigned long)
+ 0x0800d116 0x18 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d116 RDMHandler::HandleString(char const*, unsigned long)
+ *fill* 0x0800d12e 0x2
.text._ZN10RDMHandler20CreateRespondMessageEht
- 0x000000000800d878 0x98 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d878 RDMHandler::CreateRespondMessage(unsigned char, unsigned short)
+ 0x0800d130 0x94 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d130 RDMHandler::CreateRespondMessage(unsigned char, unsigned short)
.text._ZN10RDMHandler17RespondMessageAckEv
- 0x000000000800d910 0x12 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d910 RDMHandler::RespondMessageAck()
- *fill* 0x000000000800d922 0x2
+ 0x0800d1c4 0x8 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d1c4 RDMHandler::RespondMessageAck()
.text._ZN10RDMHandler13GetDeviceInfoEt
- 0x000000000800d924 0x68 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d924 RDMHandler::GetDeviceInfo(unsigned short)
+ 0x0800d1cc 0x78 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d1cc RDMHandler::GetDeviceInfo(unsigned short)
.text._ZN10RDMHandler18GetFactoryDefaultsEt
- 0x000000000800d98c 0x80 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800d98c RDMHandler::GetFactoryDefaults(unsigned short)
+ 0x0800d244 0xc0 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d244 RDMHandler::GetFactoryDefaults(unsigned short)
.text._ZN10RDMHandler25GetDeviceModelDescriptionEt
- 0x000000000800da0c 0x1c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800da0c RDMHandler::GetDeviceModelDescription(unsigned short)
+ 0x0800d304 0x1c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d304 RDMHandler::GetDeviceModelDescription(unsigned short)
.text._ZN10RDMHandler14GetDeviceLabelEt
- 0x000000000800da28 0x3c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800da28 RDMHandler::GetDeviceLabel(unsigned short)
+ 0x0800d320 0x3c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d320 RDMHandler::GetDeviceLabel(unsigned short)
.text._ZN10RDMHandler17GetIdentifyDeviceEt
- 0x000000000800da64 0x14 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800da64 RDMHandler::GetIdentifyDevice(unsigned short)
+ 0x0800d35c 0x14 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d35c RDMHandler::GetIdentifyDevice(unsigned short)
.text._ZN10RDMHandler20GetManufacturerLabelEt
- 0x000000000800da78 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800da78 RDMHandler::GetManufacturerLabel(unsigned short)
+ 0x0800d370 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d370 RDMHandler::GetManufacturerLabel(unsigned short)
.text._ZN10RDMHandler18RespondMessageNackEt
- 0x000000000800daa8 0x8 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800daa8 RDMHandler::RespondMessageNack(unsigned short)
+ 0x0800d3a0 0x8 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d3a0 RDMHandler::RespondMessageNack(unsigned short)
.text._ZN10RDMHandler14SetResetDeviceEbt
- 0x000000000800dab0 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800dab0 RDMHandler::SetResetDevice(bool, unsigned short)
+ 0x0800d3a8 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d3a8 RDMHandler::SetResetDevice(bool, unsigned short)
.text._ZN10RDMHandler17SetIdentifyDeviceEbt
- 0x000000000800daf8 0x7c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800daf8 RDMHandler::SetIdentifyDevice(bool, unsigned short)
+ 0x0800d3f0 0x7c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d3f0 RDMHandler::SetIdentifyDevice(bool, unsigned short)
.text._ZN10RDMHandler18SetFactoryDefaultsEbt
- 0x000000000800db74 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800db74 RDMHandler::SetFactoryDefaults(bool, unsigned short)
+ 0x0800d46c 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d46c RDMHandler::SetFactoryDefaults(bool, unsigned short)
.text._ZN10RDMHandler14SetDeviceLabelEbt
- 0x000000000800dba8 0x58 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800dba8 RDMHandler::SetDeviceLabel(bool, unsigned short)
+ 0x0800d4a0 0x7c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d4a0 RDMHandler::SetDeviceLabel(bool, unsigned short)
.text._ZN10RDMHandler8HandlersEbhtht
- 0x000000000800dc00 0xc8 ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800dc00 RDMHandler::Handlers(bool, unsigned char, unsigned short, unsigned char, unsigned short)
+ 0x0800d51c 0xcc ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d51c RDMHandler::Handlers(bool, unsigned char, unsigned short, unsigned char, unsigned short)
.text._ZN10RDMHandler10HandleDataEPKhPh
- 0x000000000800dcc8 0x1bc ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
- 0x000000000800dcc8 RDMHandler::HandleData(unsigned char const*, unsigned char*)
+ 0x0800d5e8 0x18c ../lib-rdm/lib_gd32/librdm.a(rdmhandler.o)
+ 0x0800d5e8 RDMHandler::HandleData(unsigned char const*, unsigned char*)
.text._ZN11RDMIdentifyC2Ev
- 0x000000000800de84 0xc ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x000000000800de84 RDMIdentify::RDMIdentify()
- 0x000000000800de84 RDMIdentify::RDMIdentify()
+ 0x0800d774 0xc ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x0800d774 RDMIdentify::RDMIdentify()
+ 0x0800d774 RDMIdentify::RDMIdentify()
.text._ZN11RDMIdentify2OnEN3rdm8identify4ModeE
- 0x000000000800de90 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x000000000800de90 RDMIdentify::On(rdm::identify::Mode)
+ 0x0800d780 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x0800d780 RDMIdentify::On(rdm::identify::Mode)
.text._ZN11RDMIdentify3OffEN3rdm8identify4ModeE
- 0x000000000800de92 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x000000000800de92 RDMIdentify::Off(rdm::identify::Mode)
+ 0x0800d782 0x2 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x0800d782 RDMIdentify::Off(rdm::identify::Mode)
.text.memcpy.isra.0
- 0x000000000800de94 0x14 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800d784 0x12 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ *fill* 0x0800d796 0x2
+ .text._ZN10LLRPDevice20HandleRequestMessageEv
+ 0x0800d798 0x12c ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x0800d798 LLRPDevice::HandleRequestMessage()
+ .text._ZN10LLRPDevice16HandleRdmCommandEv
+ 0x0800d8c4 0xa4 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x0800d8c4 LLRPDevice::HandleRdmCommand()
+ .text.memcpy.isra.0
+ 0x0800d968 0x12 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
.text._ZN10RDMHandler16GetInterfaceListEt
- 0x000000000800dea8 0x28 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800dea8 RDMHandler::GetInterfaceList(unsigned short)
+ 0x0800d97a 0x1a ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800d97a RDMHandler::GetInterfaceList(unsigned short)
.text._ZN10RDMHandler16GetInterfaceNameEt
- 0x000000000800ded0 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800ded0 RDMHandler::GetInterfaceName(unsigned short)
+ 0x0800d994 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800d994 RDMHandler::GetInterfaceName(unsigned short)
.text._ZN10RDMHandler18GetHardwareAddressEt
- 0x000000000800df20 0x38 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800df20 RDMHandler::GetHardwareAddress(unsigned short)
+ 0x0800d9e4 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800d9e4 RDMHandler::GetHardwareAddress(unsigned short)
.text._ZN10RDMHandler11GetDHCPModeEt
- 0x000000000800df58 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800df58 RDMHandler::GetDHCPMode(unsigned short)
+ 0x0800da18 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800da18 RDMHandler::GetDHCPMode(unsigned short)
.text._ZN10RDMHandler11SetDHCPModeEbt
- 0x000000000800df88 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800df88 RDMHandler::SetDHCPMode(bool, unsigned short)
+ 0x0800da48 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800da48 RDMHandler::SetDHCPMode(bool, unsigned short)
.text._ZN10RDMHandler14GetNameServersEt
- 0x000000000800dfd0 0x22 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800dfd0 RDMHandler::GetNameServers(unsigned short)
- *fill* 0x000000000800dff2 0x2
+ 0x0800da7c 0x4c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800da7c RDMHandler::GetNameServers(unsigned short)
.text._ZN10RDMHandler11GetZeroconfEt
- 0x000000000800dff4 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800dff4 RDMHandler::GetZeroconf(unsigned short)
+ 0x0800dac8 0x3c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dac8 RDMHandler::GetZeroconf(unsigned short)
.text._ZN10RDMHandler11SetZeroconfEbt
- 0x000000000800e028 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e028 RDMHandler::SetZeroconf(bool, unsigned short)
+ 0x0800db04 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800db04 RDMHandler::SetZeroconf(bool, unsigned short)
.text._ZN10RDMHandler9RenewDhcpEbt
- 0x000000000800e070 0x2c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e070 RDMHandler::RenewDhcp(bool, unsigned short)
+ 0x0800db4c 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800db4c RDMHandler::RenewDhcp(bool, unsigned short)
.text._ZN10RDMHandler17GetAddressNetmaskEt
- 0x000000000800e09c 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e09c RDMHandler::GetAddressNetmask(unsigned short)
+ 0x0800db7c 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800db7c RDMHandler::GetAddressNetmask(unsigned short)
.text._ZN10RDMHandler16GetStaticAddressEt
- 0x000000000800e0ec 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e0ec RDMHandler::GetStaticAddress(unsigned short)
+ 0x0800dbcc 0x48 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dbcc RDMHandler::GetStaticAddress(unsigned short)
.text._ZN10RDMHandler16SetStaticAddressEbt
- 0x000000000800e134 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e134 RDMHandler::SetStaticAddress(bool, unsigned short)
+ 0x0800dc14 0x50 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dc14 RDMHandler::SetStaticAddress(bool, unsigned short)
.text._ZN10RDMHandler18ApplyConfigurationEbt
- 0x000000000800e184 0x28 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e184 RDMHandler::ApplyConfiguration(bool, unsigned short)
+ 0x0800dc64 0x28 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dc64 RDMHandler::ApplyConfiguration(bool, unsigned short)
.text._ZN10RDMHandler15GetDefaultRouteEt
- 0x000000000800e1ac 0x3c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e1ac RDMHandler::GetDefaultRoute(unsigned short)
+ 0x0800dc8c 0x3c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dc8c RDMHandler::GetDefaultRoute(unsigned short)
.text._ZN10RDMHandler15SetDefaultRouteEbt
- 0x000000000800e1e8 0x6 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e1e8 RDMHandler::SetDefaultRoute(bool, unsigned short)
- *fill* 0x000000000800e1ee 0x2
+ 0x0800dcc8 0x40 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dcc8 RDMHandler::SetDefaultRoute(bool, unsigned short)
.text._ZN10RDMHandler11GetHostNameEt
- 0x000000000800e1f0 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e1f0 RDMHandler::GetHostName(unsigned short)
+ 0x0800dd08 0x2c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dd08 RDMHandler::GetHostName(unsigned short)
.text._ZN10RDMHandler11SetHostNameEbt
- 0x000000000800e220 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e220 RDMHandler::SetHostName(bool, unsigned short)
+ 0x0800dd34 0x34 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dd34 RDMHandler::SetHostName(bool, unsigned short)
.text._ZN10RDMHandler13GetDomainNameEt
- 0x000000000800e254 0x30 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e254 RDMHandler::GetDomainName(unsigned short)
+ 0x0800dd68 0x2c ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dd68 RDMHandler::GetDomainName(unsigned short)
.text._ZN10RDMHandler13SetDomainNameEbt
- 0x000000000800e284 0x6 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
- 0x000000000800e284 RDMHandler::SetDomainName(bool, unsigned short)
- *fill* 0x000000000800e28a 0x2
+ 0x0800dd94 0x6 ../lib-rdm/lib_gd32/librdm.a(rdmhandlere1372.o)
+ 0x0800dd94 RDMHandler::SetDomainName(bool, unsigned short)
+ *fill* 0x0800dd9a 0x2
.text._ZN9RDMDeviceC2Ev
- 0x000000000800e28c 0x5c ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
- 0x000000000800e28c RDMDevice::RDMDevice()
- 0x000000000800e28c RDMDevice::RDMDevice()
+ 0x0800dd9c 0xa0 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x0800dd9c RDMDevice::RDMDevice()
+ 0x0800dd9c RDMDevice::RDMDevice()
.text._ZN9RDMDevice5PrintEv
- 0x000000000800e2e8 0xa4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
- 0x000000000800e2e8 RDMDevice::Print()
- .text.uuid_unparse_x
- 0x000000000800e38c 0x7e ../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- *fill* 0x000000000800e40a 0x2
- .text.uuid_unparse
- 0x000000000800e40c 0xc ../lib-uuid/lib_gd32/libuuid.a(uuid_unparse.o)
- 0x000000000800e40c uuid_unparse
- .text._ZN7DmxSendD2Ev
- 0x000000000800e418 0x2 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e418 DmxSend::~DmxSend()
- 0x000000000800e418 DmxSend::~DmxSend()
- *fill* 0x000000000800e41a 0x2
- .text._ZN7DmxSend4StopEm
- 0x000000000800e41c 0x38 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e41c DmxSend::Stop(unsigned long)
- .text._ZN7DmxSend5StartEm
- 0x000000000800e454 0x38 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e454 DmxSend::Start(unsigned long)
- .text._ZNK7DmxSend14GetOutputStyleEm
- 0x000000000800e48c 0x18 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e48c DmxSend::GetOutputStyle(unsigned long) const
- .text._ZN7DmxSend4SyncEm
- 0x000000000800e4a4 0x20 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e4a4 DmxSend::Sync(unsigned long)
- .text._ZN7DmxSend4SyncEb
- 0x000000000800e4c4 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e4c4 DmxSend::Sync(bool)
- .text._ZN7DmxSend5PrintEv
- 0x000000000800e51c 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e51c DmxSend::Print()
- .text._ZN7DmxSend6FullOnEv
- 0x000000000800e574 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e574 DmxSend::FullOn()
- .text._ZN7DmxSend8BlackoutEb
- 0x000000000800e580 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e580 DmxSend::Blackout(bool)
- .text._ZN7DmxSend14SetOutputStyleEmN8lightset11OutputStyleE
- 0x000000000800e58c 0x14 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e58c DmxSend::SetOutputStyle(unsigned long, lightset::OutputStyle)
- .text._ZN7DmxSendD0Ev
- 0x000000000800e5a0 0xc ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e5a0 DmxSend::~DmxSend()
- .text._ZN7DmxSend7SetDataEmPKhmb
- 0x000000000800e5ac 0x58 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000000800e5ac DmxSend::SetData(unsigned long, unsigned char const*, unsigned long, bool)
- .text._ZN17PropertiesBuilder3AddItEEbPKcT_bm.isra.0
- 0x000000000800e604 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- .text._ZN9DmxParamsC2EP14DmxParamsStore
- 0x000000000800e654 0x18 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e654 DmxParams::DmxParams(DmxParamsStore*)
- 0x000000000800e654 DmxParams::DmxParams(DmxParamsStore*)
+ 0x0800de3c 0xa4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x0800de3c RDMDevice::Print()
+ .text._ZN17PropertiesBuilder3AddItEEbPKcT_bi.isra.0
+ 0x0800dee0 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ .text._ZN12StoreDmxSend4CopyEPN13dmxsendparams6ParamsE
+ 0x0800df30 0x20 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800df30 StoreDmxSend::Copy(dmxsendparams::Params*)
+ .text._ZN9DmxParamsC2Ev
+ 0x0800df50 0x22 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800df50 DmxParams::DmxParams()
+ 0x0800df50 DmxParams::DmxParams()
.text._ZN9DmxParams4LoadEv
- 0x000000000800e66c 0x18 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e66c DmxParams::Load()
+ 0x0800df72 0x12 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800df72 DmxParams::Load()
.text._ZN9DmxParams4LoadEPKcm
- 0x000000000800e684 0x3c ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e684 DmxParams::Load(char const*, unsigned long)
+ 0x0800df84 0x50 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800df84 DmxParams::Load(char const*, unsigned long)
.text._ZN9DmxParams16callbackFunctionEPKc
- 0x000000000800e6c0 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e6c0 DmxParams::callbackFunction(char const*)
+ 0x0800dfd4 0xd4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800dfd4 DmxParams::callbackFunction(char const*)
.text._ZN9DmxParams22staticCallbackFunctionEPvPKc
- 0x000000000800e78c 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e78c DmxParams::staticCallbackFunction(void*, char const*)
- .text._ZN9DmxParams7BuilderEPK10TDmxParamsPcmRm
- 0x000000000800e790 0x104 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e790 DmxParams::Builder(TDmxParams const*, char*, unsigned long, unsigned long&)
+ 0x0800e0a8 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800e0a8 DmxParams::staticCallbackFunction(void*, char const*)
+ .text._ZN9DmxParams7BuilderEPKN13dmxsendparams6ParamsEPcmRm
+ 0x0800e0ac 0xf8 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800e0ac DmxParams::Builder(dmxsendparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN9DmxParams3SetEP3Dmx
- 0x000000000800e894 0x5c ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e894 DmxParams::Set(Dmx*)
- .text._ZN9DmxParams4DumpEv
- 0x000000000800e8f0 0x2 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
- 0x000000000800e8f0 DmxParams::Dump()
- *fill* 0x000000000800e8f2 0x2
- .text._ZN3Dmx8StopDataEmm.part.0
- 0x000000000800e8f4 0x98 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e1a4 0x54 ../lib-dmx/lib_gd32/libdmx.a(dmxparams.o)
+ 0x0800e1a4 DmxParams::Set(Dmx*)
+ .text._ZN12remoteconfig3dmx14json_get_portsEPcm
+ 0x0800e1f8 0x70 ../lib-dmx/lib_gd32/libdmx.a(json_get_ports.o)
+ 0x0800e1f8 remoteconfig::dmx::json_get_ports(char*, unsigned long)
+ .text._ZN12remoteconfig3dmx19json_get_portstatusEcPcm
+ 0x0800e268 0x64 ../lib-dmx/lib_gd32/libdmx.a(json_get_portstatus.o)
+ 0x0800e268 remoteconfig::dmx::json_get_portstatus(char, char*, unsigned long)
+ .text._ZN3Dmx8StopDataEm.part.0
+ 0x0800e2cc 0xa0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
.text.USART2_IRQHandler
- 0x000000000800e98c 0x1ec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800e98c USART2_IRQHandler
+ 0x0800e36c 0x17c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e36c USART2_IRQHandler
.text.USART5_IRQHandler
- 0x000000000800eb78 0x20c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800eb78 USART5_IRQHandler
+ 0x0800e4e8 0x184 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e4e8 USART5_IRQHandler
.text.TIMER1_IRQHandler
- 0x000000000800ed84 0xe8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800ed84 TIMER1_IRQHandler
+ 0x0800e66c 0x104 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e66c TIMER1_IRQHandler
.text.TIMER4_IRQHandler
- 0x000000000800ee6c 0xec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800ee6c TIMER4_IRQHandler
- .text.TIMER2_IRQHandler
- 0x000000000800ef58 0x90 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800ef58 TIMER2_IRQHandler
- .text.TIMER3_IRQHandler
- 0x000000000800efe8 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800efe8 TIMER3_IRQHandler
+ 0x0800e770 0x124 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e770 TIMER4_IRQHandler
.text.TIMER6_IRQHandler
- 0x000000000800effc 0x30 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800effc TIMER6_IRQHandler
+ 0x0800e894 0x54 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e894 TIMER6_IRQHandler
.text.DMA0_Channel3_IRQHandler
- 0x000000000800f02c 0x58 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f02c DMA0_Channel3_IRQHandler
+ 0x0800e8e8 0x70 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e8e8 DMA0_Channel3_IRQHandler
.text.DMA1_Channel6_IRQHandler
- 0x000000000800f084 0x64 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f084 DMA1_Channel6_IRQHandler
+ 0x0800e958 0x88 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e958 DMA1_Channel6_IRQHandler
.text._ZN3DmxC2Ev
- 0x000000000800f0e8 0x3f4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f0e8 Dmx::Dmx()
- 0x000000000800f0e8 Dmx::Dmx()
+ 0x0800e9e0 0x2e0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800e9e0 Dmx::Dmx()
+ 0x0800e9e0 Dmx::Dmx()
+ .text._ZN3Dmx16SetPortDirectionEmN3dmx13PortDirectionEb
+ 0x0800ecc0 0xe4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800ecc0 Dmx::SetPortDirection(unsigned long, dmx::PortDirection, bool)
+ .text._ZN3Dmx18GetTotalStatisticsEm
+ 0x0800eda4 0x24 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800eda4 Dmx::GetTotalStatistics(unsigned long)
.text._ZN3Dmx14StartDmxOutputEm
- 0x000000000800f4dc 0xe4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f4dc Dmx::StartDmxOutput(unsigned long)
+ 0x0800edc8 0xb4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800edc8 Dmx::StartDmxOutput(unsigned long)
.text._ZN3Dmx15SetDmxBreakTimeEm
- 0x000000000800f5c0 0x6c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f5c0 Dmx::SetDmxBreakTime(unsigned long)
+ 0x0800ee7c 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800ee7c Dmx::SetDmxBreakTime(unsigned long)
+ .text._ZNK3Dmx15GetDmxBreakTimeEv
+ 0x0800eedc 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800eedc Dmx::GetDmxBreakTime() const
.text._ZN3Dmx13SetDmxMabTimeEm
- 0x000000000800f62c 0x6c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f62c Dmx::SetDmxMabTime(unsigned long)
+ 0x0800eee8 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800eee8 Dmx::SetDmxMabTime(unsigned long)
+ .text._ZNK3Dmx13GetDmxMabTimeEv
+ 0x0800ef48 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800ef48 Dmx::GetDmxMabTime() const
.text._ZN3Dmx16SetDmxPeriodTimeEm
- 0x000000000800f698 0x68 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f698 Dmx::SetDmxPeriodTime(unsigned long)
+ 0x0800ef54 0x60 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800ef54 Dmx::SetDmxPeriodTime(unsigned long)
.text._ZN3Dmx11SetDmxSlotsEt
- 0x000000000800f700 0x7c ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f700 Dmx::SetDmxSlots(unsigned short)
+ 0x0800efb4 0x70 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800efb4 Dmx::SetDmxSlots(unsigned short)
.text._ZN3Dmx14SetOutputStyleEmN3dmx11OutputStyleE
- 0x000000000800f77c 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f77c Dmx::SetOutputStyle(unsigned long, dmx::OutputStyle)
+ 0x0800f024 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f024 Dmx::SetOutputStyle(unsigned long, dmx::OutputStyle)
.text._ZNK3Dmx14GetOutputStyleEm
- 0x000000000800f790 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f790 Dmx::GetOutputStyle(unsigned long) const
+ 0x0800f0f0 0x14 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f0f0 Dmx::GetOutputStyle(unsigned long) const
.text._ZN3Dmx20SetSendDataWithoutSCEmPKhm
- 0x000000000800f7a4 0xc0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f7a4 Dmx::SetSendDataWithoutSC(unsigned long, unsigned char const*, unsigned long)
- .text._ZN3Dmx11StartOutputEm
- 0x000000000800f864 0x34 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f864 Dmx::StartOutput(unsigned long)
- .text._ZN3Dmx9SetOutputEb
- 0x000000000800f898 0xf0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f898 Dmx::SetOutput(bool)
- .text._ZN3Dmx9StartDataEmm
- 0x000000000800f988 0x94 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800f988 Dmx::StartData(unsigned long, unsigned long)
- .text._ZN3Dmx16SetPortDirectionEmN3dmx13PortDirectionEb
- 0x000000000800fa1c 0x98 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fa1c Dmx::SetPortDirection(unsigned long, dmx::PortDirection, bool)
+ 0x0800f104 0xa0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f104 Dmx::SetSendDataWithoutSC(unsigned long, unsigned char const*, unsigned long)
.text._ZN3Dmx8BlackoutEv
- 0x000000000800fab4 0xe8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fab4 Dmx::Blackout()
+ 0x0800f1a4 0xcc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f1a4 Dmx::Blackout()
.text._ZN3Dmx6FullOnEv
- 0x000000000800fb9c 0xec ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fb9c Dmx::FullOn()
+ 0x0800f270 0xd0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f270 Dmx::FullOn()
+ .text._ZN3Dmx11StartOutputEm
+ 0x0800f340 0x34 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f340 Dmx::StartOutput(unsigned long)
+ .text._ZN3Dmx4SyncEv
+ 0x0800f374 0x68 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f374 Dmx::Sync()
.text._ZN3Dmx13GetDmxChangedEm
- 0x000000000800fc88 0xf8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fc88 Dmx::GetDmxChanged(unsigned long)
+ 0x0800f3dc 0xd0 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f3dc Dmx::GetDmxChanged(unsigned long)
.text._ZN3Dmx17GetDmxCurrentDataEm
- 0x000000000800fd80 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fd80 Dmx::GetDmxCurrentData(unsigned long)
+ 0x0800f4ac 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f4ac Dmx::GetDmxCurrentData(unsigned long)
.text._ZN3Dmx22GetDmxUpdatesPerSecondEm
- 0x000000000800fd90 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000000800fd90 Dmx::GetDmxUpdatesPerSecond(unsigned long)
- .text._ZN11ConfigStoreC2Ev
- 0x000000000800fd9c 0xb8 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800fd9c ConfigStore::ConfigStore()
- 0x000000000800fd9c ConfigStore::ConfigStore()
+ 0x0800f4bc 0x10 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x0800f4bc Dmx::GetDmxUpdatesPerSecond(unsigned long)
.text._ZN11ConfigStore14GetStoreOffsetEN11configstore5StoreE
- 0x000000000800fe54 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800fe54 ConfigStore::GetStoreOffset(configstore::Store)
+ 0x0800f4cc 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f4cc ConfigStore::GetStoreOffset(configstore::Store)
+ .text._ZN11ConfigStoreC2Ev
+ 0x0800f4e8 0xf8 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f4e8 ConfigStore::ConfigStore()
+ 0x0800f4e8 ConfigStore::ConfigStore()
.text._ZN11ConfigStore12ResetSetListEN11configstore5StoreE
- 0x000000000800fe70 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800fe70 ConfigStore::ResetSetList(configstore::Store)
+ 0x0800f5e0 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f5e0 ConfigStore::ResetSetList(configstore::Store)
.text._ZN11ConfigStore6UpdateEN11configstore5StoreEmPKvmmm
- 0x000000000800fe94 0x5c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800fe94 ConfigStore::Update(configstore::Store, unsigned long, void const*, unsigned long, unsigned long, unsigned long)
- .text._ZN11ConfigStore4CopyEN11configstore5StoreEPvmm
- 0x000000000800fef0 0x58 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800fef0 ConfigStore::Copy(configstore::Store, void*, unsigned long, unsigned long)
+ 0x0800f604 0x4c ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f604 ConfigStore::Update(configstore::Store, unsigned long, void const*, unsigned long, unsigned long, unsigned long)
+ .text._ZN11ConfigStore4CopyEN11configstore5StoreEPvmmb
+ 0x0800f650 0x60 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f650 ConfigStore::Copy(configstore::Store, void*, unsigned long, unsigned long, bool)
.text._ZN11ConfigStore5FlashEv
- 0x000000000800ff48 0xac ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000000800ff48 ConfigStore::Flash()
- .text._ZN15StoreDisplayUdfD2Ev
- 0x000000000800fff4 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x000000000800fff4 StoreDisplayUdf::~StoreDisplayUdf()
- 0x000000000800fff4 StoreDisplayUdf::~StoreDisplayUdf()
- *fill* 0x000000000800fff6 0x2
- .text._ZN15StoreDisplayUdf4CopyEPN16displayudfparams6ParamsE
- 0x000000000800fff8 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x000000000800fff8 StoreDisplayUdf::Copy(displayudfparams::Params*)
- .text._ZN15StoreDisplayUdf6UpdateEPKN16displayudfparams6ParamsE
- 0x0000000008010018 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008010018 StoreDisplayUdf::Update(displayudfparams::Params const*)
- .text._ZN15StoreDisplayUdfD0Ev
- 0x000000000801003c 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x000000000801003c StoreDisplayUdf::~StoreDisplayUdf()
- .text._ZN15StoreDisplayUdfC2Ev
- 0x0000000008010048 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000008010048 StoreDisplayUdf::StoreDisplayUdf()
- 0x0000000008010048 StoreDisplayUdf::StoreDisplayUdf()
- .text._ZN12StoreDmxSendD2Ev
- 0x000000000801005c 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x000000000801005c StoreDmxSend::~StoreDmxSend()
- 0x000000000801005c StoreDmxSend::~StoreDmxSend()
- *fill* 0x000000000801005e 0x2
- .text._ZN12StoreDmxSend4CopyEP10TDmxParams
- 0x0000000008010060 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008010060 StoreDmxSend::Copy(TDmxParams*)
- .text._ZN12StoreDmxSend6UpdateEPK10TDmxParams
- 0x0000000008010080 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000008010080 StoreDmxSend::Update(TDmxParams const*)
- .text._ZN12StoreDmxSendD0Ev
- 0x00000000080100a4 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x00000000080100a4 StoreDmxSend::~StoreDmxSend()
- .text._ZN12StoreDmxSendC2Ev
- 0x00000000080100b0 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x00000000080100b0 StoreDmxSend::StoreDmxSend()
- 0x00000000080100b0 StoreDmxSend::StoreDmxSend()
- .text._ZN12StoreNetworkD2Ev
- 0x00000000080100c4 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080100c4 StoreNetwork::~StoreNetwork()
- 0x00000000080100c4 StoreNetwork::~StoreNetwork()
- 0x00000000080100c6 non-virtual thunk to StoreNetwork::~StoreNetwork()
- *fill* 0x00000000080100ca 0x2
- .text._ZN12StoreNetwork6UpdateEPKN13networkparams6ParamsE
- 0x00000000080100cc 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080100cc StoreNetwork::Update(networkparams::Params const*)
- .text._ZN12StoreNetwork13SaveGatewayIpEm
- 0x00000000080100f0 0x30 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080100f0 StoreNetwork::SaveGatewayIp(unsigned long)
- 0x0000000008010118 non-virtual thunk to StoreNetwork::SaveGatewayIp(unsigned long)
- .text._ZN12StoreNetwork11SaveNetMaskEm
- 0x0000000008010120 0x2c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008010120 StoreNetwork::SaveNetMask(unsigned long)
- 0x0000000008010144 non-virtual thunk to StoreNetwork::SaveNetMask(unsigned long)
- .text._ZN12StoreNetwork6SaveIpEm
- 0x000000000801014c 0x2c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x000000000801014c StoreNetwork::SaveIp(unsigned long)
- 0x0000000008010170 non-virtual thunk to StoreNetwork::SaveIp(unsigned long)
- .text._ZN12StoreNetwork12SaveHostNameEPKcm
- 0x0000000008010178 0x34 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x0000000008010178 StoreNetwork::SaveHostName(char const*, unsigned long)
- 0x00000000080101a4 non-virtual thunk to StoreNetwork::SaveHostName(char const*, unsigned long)
- .text._ZN12StoreNetworkD0Ev
- 0x00000000080101ac 0x12 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080101ac StoreNetwork::~StoreNetwork()
- 0x00000000080101b8 non-virtual thunk to StoreNetwork::~StoreNetwork()
- *fill* 0x00000000080101be 0x2
- .text._ZN12StoreNetwork4CopyEPN13networkparams6ParamsE
- 0x00000000080101c0 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080101c0 StoreNetwork::Copy(networkparams::Params*)
- .text._ZN12StoreNetworkC2Ev
- 0x00000000080101dc 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x00000000080101dc StoreNetwork::StoreNetwork()
- 0x00000000080101dc StoreNetwork::StoreNetwork()
- .text._ZN17StoreRemoteConfigD2Ev
- 0x00000000080101f4 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x00000000080101f4 StoreRemoteConfig::~StoreRemoteConfig()
- 0x00000000080101f4 StoreRemoteConfig::~StoreRemoteConfig()
- *fill* 0x00000000080101f6 0x2
- .text._ZN17StoreRemoteConfig4CopyEP19TRemoteConfigParams
- 0x00000000080101f8 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x00000000080101f8 StoreRemoteConfig::Copy(TRemoteConfigParams*)
- .text._ZN17StoreRemoteConfig6UpdateEPK19TRemoteConfigParams
- 0x0000000008010218 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008010218 StoreRemoteConfig::Update(TRemoteConfigParams const*)
- .text._ZN17StoreRemoteConfigD0Ev
- 0x000000000801023c 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x000000000801023c StoreRemoteConfig::~StoreRemoteConfig()
- .text._ZN17StoreRemoteConfigC2Ev
- 0x0000000008010248 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000008010248 StoreRemoteConfig::StoreRemoteConfig()
- 0x0000000008010248 StoreRemoteConfig::StoreRemoteConfig()
+ 0x0800f6b0 0xac ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x0800f6b0 ConfigStore::Flash()
+ .text._ZN11ConfigStore15GetEnvUtcOffsetERaRh.isra.0
+ 0x0800f75c 0x40 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ .text._ZN9EnvParamsC2Ev
+ 0x0800f79c 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x0800f79c EnvParams::EnvParams()
+ 0x0800f79c EnvParams::EnvParams()
+ *fill* 0x0800f79e 0x2
+ .text._ZN9EnvParams10LoadAndSetEPKcm
+ 0x0800f7a0 0x28 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x0800f7a0 EnvParams::LoadAndSet(char const*, unsigned long)
+ .text._ZN9EnvParams16callbackFunctionEPKc
+ 0x0800f7c8 0x8c ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x0800f7c8 EnvParams::callbackFunction(char const*)
+ .text._ZN9EnvParams22staticCallbackFunctionEPvPKc
+ 0x0800f854 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x0800f854 EnvParams::staticCallbackFunction(void*, char const*)
+ .text._ZN9EnvParams7BuilderEPcmRm
+ 0x0800f858 0x64 ../lib-configstore/lib_gd32/libconfigstore.a(envparams.o)
+ 0x0800f858 EnvParams::Builder(char*, unsigned long, unsigned long&)
.text._ZN11StoreDeviceC2Ev
- 0x000000000801025c 0x1c ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x000000000801025c StoreDevice::StoreDevice()
- 0x000000000801025c StoreDevice::StoreDevice()
+ 0x0800f8bc 0x48 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f8bc StoreDevice::StoreDevice()
+ 0x0800f8bc StoreDevice::StoreDevice()
.text._ZNK11StoreDevice7GetSizeEv
- 0x0000000008010278 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x0000000008010278 StoreDevice::GetSize() const
+ 0x0800f904 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f904 StoreDevice::GetSize() const
.text._ZNK11StoreDevice13GetSectorSizeEv
- 0x000000000801027e 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x000000000801027e StoreDevice::GetSectorSize() const
+ 0x0800f908 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f908 StoreDevice::GetSectorSize() const
.text._ZN11StoreDevice4ReadEmmPhRN11storedevice6resultE
- 0x0000000008010284 0xa ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x0000000008010284 StoreDevice::Read(unsigned long, unsigned long, unsigned char*, storedevice::result&)
+ 0x0800f90c 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f90c StoreDevice::Read(unsigned long, unsigned long, unsigned char*, storedevice::result&)
.text._ZN11StoreDevice5EraseEmmRN11storedevice6resultE
- 0x000000000801028e 0x8 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x000000000801028e StoreDevice::Erase(unsigned long, unsigned long, storedevice::result&)
+ 0x0800f922 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f922 StoreDevice::Erase(unsigned long, unsigned long, storedevice::result&)
.text._ZN11StoreDevice5WriteEmmPKhRN11storedevice6resultE
- 0x0000000008010296 0xa ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
- 0x0000000008010296 StoreDevice::Write(unsigned long, unsigned long, unsigned char const*, storedevice::result&)
- .text._ZN9StoreE131D2Ev
- 0x00000000080102a0 0x2 ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x00000000080102a0 StoreE131::~StoreE131()
- 0x00000000080102a0 StoreE131::~StoreE131()
- *fill* 0x00000000080102a2 0x2
- .text._ZN9StoreE1314CopyEPN10e131params6ParamsE
- 0x00000000080102a4 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x00000000080102a4 StoreE131::Copy(e131params::Params*)
- .text._ZN9StoreE1316UpdateEPKN10e131params6ParamsE
- 0x00000000080102c4 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x00000000080102c4 StoreE131::Update(e131params::Params const*)
- .text._ZN9StoreE131D0Ev
- 0x00000000080102e8 0xc ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x00000000080102e8 StoreE131::~StoreE131()
- .text._ZN9StoreE131C2Ev
- 0x00000000080102f4 0x14 ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x00000000080102f4 StoreE131::StoreE131()
- 0x00000000080102f4 StoreE131::StoreE131()
- .text._ZN14StoreRDMDeviceD2Ev
- 0x0000000008010308 0x6 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008010308 StoreRDMDevice::~StoreRDMDevice()
- 0x0000000008010308 StoreRDMDevice::~StoreRDMDevice()
- 0x000000000801030a non-virtual thunk to StoreRDMDevice::~StoreRDMDevice()
- *fill* 0x000000000801030e 0x2
- .text._ZN14StoreRDMDevice6UpdateEPKN3rdm12deviceparams6ParamsE
- 0x0000000008010310 0x24 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008010310 StoreRDMDevice::Update(rdm::deviceparams::Params const*)
- .text._ZN14StoreRDMDevice9SaveLabelEPKch
- 0x0000000008010334 0x44 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008010334 StoreRDMDevice::SaveLabel(char const*, unsigned char)
- 0x0000000008010370 non-virtual thunk to StoreRDMDevice::SaveLabel(char const*, unsigned char)
- .text._ZN14StoreRDMDeviceD0Ev
- 0x0000000008010378 0x12 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000008010378 StoreRDMDevice::~StoreRDMDevice()
- 0x0000000008010384 non-virtual thunk to StoreRDMDevice::~StoreRDMDevice()
- *fill* 0x000000000801038a 0x2
- .text._ZN14StoreRDMDevice4CopyEPN3rdm12deviceparams6ParamsE
- 0x000000000801038c 0x20 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x000000000801038c StoreRDMDevice::Copy(rdm::deviceparams::Params*)
- .text._ZN14StoreRDMDeviceC2Ev
- 0x00000000080103ac 0x18 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x00000000080103ac StoreRDMDevice::StoreRDMDevice()
- 0x00000000080103ac StoreRDMDevice::StoreRDMDevice()
+ 0x0800f936 0x16 ../lib-configstore/lib_gd32/libconfigstore.a(storedevice.o)
+ 0x0800f936 StoreDevice::Write(unsigned long, unsigned long, unsigned char const*, storedevice::result&)
.text.memcpy.isra.0
- 0x00000000080103c4 0x14 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .text.strlen 0x00000000080103d8 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080103d8 strlen
+ 0x0800f94c 0x12 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .text.strlen 0x0800f95e 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800f95e strlen
+ *fill* 0x0800f96e 0x2
.text._ZN4mdns6Domain11AddDotLocalEv
- 0x00000000080103e8 0x24 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080103e8 mdns::Domain::AddDotLocal()
+ 0x0800f970 0x24 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800f970 mdns::Domain::AddDotLocal()
.text._ZL18create_host_domainRN4mdns6DomainE
- 0x000000000801040c 0x44 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800f994 0x40 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL21create_service_domainRN4mdns6DomainERKNS_13ServiceRecordEb
- 0x0000000008010450 0xa4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800f9d4 0xa4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZN4mdns6Domain5PrintEb
- 0x00000000080104f4 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080104f4 mdns::Domain::Print(bool)
+ 0x0800fa78 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fa78 mdns::Domain::Print(bool)
.text._ZN4mdnseqERKNS_6DomainES2_
- 0x000000000801053c 0x66 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x000000000801053c mdns::operator==(mdns::Domain const&, mdns::Domain const&)
+ 0x0800fac0 0x66 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fac0 mdns::operator==(mdns::Domain const&, mdns::Domain const&)
.text._Z24find_compression_pointerPKhS0_S0_
- 0x00000000080105a2 0x9c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080105a2 find_compression_pointer(unsigned char const*, unsigned char const*, unsigned char const*)
- *fill* 0x000000000801063e 0x2
+ 0x0800fb26 0xa0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fb26 find_compression_pointer(unsigned char const*, unsigned char const*, unsigned char const*)
+ *fill* 0x0800fbc6 0x2
.text._ZL25put_domain_name_as_labelsPhRKN4mdns6DomainE
- 0x0000000008010640 0x5c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fbc8 0x5c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL12add_answer_aPhm
- 0x000000000801069c 0x44 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fc24 0x40 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL19add_answer_dnsd_ptrRKN4mdns13ServiceRecordEPhm.constprop.0
- 0x00000000080106e0 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fc64 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_srvRKN4mdns13ServiceRecordEPhm
- 0x0000000008010730 0x58 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fcb4 0x58 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_ptrRKN4mdns13ServiceRecordEPhm
- 0x0000000008010788 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fd0c 0x50 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._ZL14add_answer_txtRKN4mdns13ServiceRecordEPhm
- 0x00000000080107d8 0x5a ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fd5c 0x5a ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.text._Z15get_domain_namePKhS0_S0_Ph
- 0x0000000008010832 0x86 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010832 get_domain_name(unsigned char const*, unsigned char const*, unsigned char const*, unsigned char*)
- .text._ZN4MDNS6SendToEt
- 0x00000000080108b8 0x48 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080108b8 MDNS::SendTo(unsigned short)
+ 0x0800fdb6 0x8c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fdb6 get_domain_name(unsigned char const*, unsigned char const*, unsigned char const*, unsigned char*)
+ *fill* 0x0800fe42 0x2
+ .text._ZN4MDNS6SendToEm
+ 0x0800fe44 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fe44 MDNS::SendTo(unsigned long)
.text._ZN4MDNS24SendAnswerLocalIpAddressEtm
- 0x0000000008010900 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010900 MDNS::SendAnswerLocalIpAddress(unsigned short, unsigned long)
+ 0x0800fe98 0x54 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fe98 MDNS::SendAnswerLocalIpAddress(unsigned short, unsigned long)
.text._ZN4MDNS11SendMessageERKN4mdns13ServiceRecordEtm
- 0x0000000008010954 0xa8 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010954 MDNS::SendMessage(mdns::ServiceRecord const&, unsigned short, unsigned long)
+ 0x0800feec 0xa8 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800feec MDNS::SendMessage(mdns::ServiceRecord const&, unsigned short, unsigned long)
.text._ZN4MDNS16SendAnnouncementEm
- 0x00000000080109fc 0x70 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x00000000080109fc MDNS::SendAnnouncement(unsigned long)
+ 0x0800ff94 0x68 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800ff94 MDNS::SendAnnouncement(unsigned long)
.text._ZN7network17mdns_announcementEv
- 0x0000000008010a6c 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010a6c network::mdns_announcement()
+ 0x0800fffc 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0800fffc network::mdns_announcement()
.text._ZN7network13mdns_shutdownEv
- 0x0000000008010a7c 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010a7c network::mdns_shutdown()
+ 0x0801000c 0x10 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801000c network::mdns_shutdown()
.text._ZN4MDNSC2Ev
- 0x0000000008010a8c 0x74 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010a8c MDNS::MDNS()
- 0x0000000008010a8c MDNS::MDNS()
- .text._ZN4MDNS16AddServiceRecordEPKcN4mdns8ServicesES1_t
- 0x0000000008010b00 0xc0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010b00 MDNS::AddServiceRecord(char const*, mdns::Services, char const*, unsigned short)
+ 0x0801001c 0x74 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x0801001c MDNS::MDNS()
+ 0x0801001c MDNS::MDNS()
+ .text._ZN4MDNS19ServiceRecordDeleteEN4mdns8ServicesE
+ 0x08010090 0x38 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08010090 MDNS::ServiceRecordDelete(mdns::Services)
+ .text._ZN4MDNS16ServiceRecordAddEPKcN4mdns8ServicesES1_t
+ 0x080100c8 0xc0 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x080100c8 MDNS::ServiceRecordAdd(char const*, mdns::Services, char const*, unsigned short)
.text._ZN4MDNS15HandleQuestionsEm
- 0x0000000008010bc0 0x198 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010bc0 MDNS::HandleQuestions(unsigned long)
+ 0x08010188 0x19c ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08010188 MDNS::HandleQuestions(unsigned long)
.text._ZN4MDNS5PrintEv
- 0x0000000008010d58 0x70 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000008010d58 MDNS::Print()
+ 0x08010324 0x68 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x08010324 MDNS::Print()
.text.strncpy.isra.0
- 0x0000000008010dc8 0x22 ../lib-network/lib_gd32/libnetwork.a(network.o)
- .text._ZN8Hardware12WatchdogInitEv
- 0x0000000008010dea 0x24 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008010dea Hardware::WatchdogInit()
- *fill* 0x0000000008010e0e 0x2
- .text._ZN7NetworkC2EP18NetworkParamsStore
- 0x0000000008010e10 0x2b0 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008010e10 Network::Network(NetworkParamsStore*)
- 0x0000000008010e10 Network::Network(NetworkParamsStore*)
+ 0x0801038c 0x22 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ *fill* 0x080103ae 0x2
+ .text._ZN12NetworkStore8SaveDhcpEb
+ 0x080103b0 0x28 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080103b0 NetworkStore::SaveDhcp(bool)
+ .text._ZL18netif_ext_callbacktPKN3net25netif_ext_callback_args_tE
+ 0x080103d8 0xe0 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ .text._ZN7NetworkC2Ev
+ 0x080104b8 0x178 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080104b8 Network::Network()
+ 0x080104b8 Network::Network()
.text._ZN7Network5SetIpEm
- 0x00000000080110c0 0x62 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x00000000080110c0 Network::SetIp(unsigned long)
+ 0x08010630 0x40 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010630 Network::SetIp(unsigned long)
.text._ZN7Network10SetNetmaskEm
- 0x0000000008011122 0x2e ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008011122 Network::SetNetmask(unsigned long)
+ 0x08010670 0x38 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010670 Network::SetNetmask(unsigned long)
+ .text._ZN7Network12SetGatewayIpEm
+ 0x080106a8 0x3c ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080106a8 Network::SetGatewayIp(unsigned long)
.text._ZN7Network11SetHostNameEPKc
- 0x0000000008011150 0x40 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008011150 Network::SetHostName(char const*)
+ 0x080106e4 0x54 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x080106e4 Network::SetHostName(char const*)
.text._ZN7Network11SetZeroconfEv
- 0x0000000008011190 0x54 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008011190 Network::SetZeroconf()
+ 0x08010738 0xe ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010738 Network::SetZeroconf()
.text._ZN7Network10EnableDhcpEv
- 0x00000000080111e4 0x6c ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x00000000080111e4 Network::EnableDhcp()
+ 0x08010746 0xe ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010746 Network::EnableDhcp()
.text._ZN7Network17SetQueuedStaticIpEmm
- 0x0000000008011250 0x1a ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x0000000008011250 Network::SetQueuedStaticIp(unsigned long, unsigned long)
+ 0x08010754 0x28 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010754 Network::SetQueuedStaticIp(unsigned long, unsigned long)
+ .text._ZN7Network21SetQueuedDefaultRouteEm
+ 0x0801077c 0x1c ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x0801077c Network::SetQueuedDefaultRoute(unsigned long)
.text._ZN7Network17ApplyQueuedConfigEv
- 0x000000000801126a 0x80 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x000000000801126a Network::ApplyQueuedConfig()
- *fill* 0x00000000080112ea 0x2
- .text._ZN7Network5PrintEv
- 0x00000000080112ec 0xdc ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x00000000080112ec Network::Print()
- .text._ZN13NetworkParamsC2EP18NetworkParamsStore
- 0x00000000080113c8 0x18 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080113c8 NetworkParams::NetworkParams(NetworkParamsStore*)
- 0x00000000080113c8 NetworkParams::NetworkParams(NetworkParamsStore*)
+ 0x08010798 0x78 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x08010798 Network::ApplyQueuedConfig()
+ .text._ZN3net12autoip_startEv
+ 0x08010810 0x9c ../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ 0x08010810 net::autoip_start()
+ .text._ZN3net11autoip_stopEv
+ 0x080108ac 0x24 ../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ 0x080108ac net::autoip_stop()
+ .text._ZN3netL24autoip_conflict_callbackENS_3acd8CallbackE
+ 0x080108d0 0x4c ../lib-network/lib_gd32/libnetwork.a(autoip.o)
+ .text._ZN3netL9dhcp_bindEv
+ 0x0801091c 0xd4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL12message_initEv
+ 0x080109f0 0x40 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL13dhcp_discoverEv
+ 0x08010a30 0xb0 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net9memcpy_ipEPhm
+ 0x08010ae0 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010ae0 net::memcpy_ip(unsigned char*, unsigned long)
+ .text._ZN3netL12send_requestEv
+ 0x08010ae4 0xd0 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL11dhcp_selectEv
+ 0x08010bb4 0x4c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3netL11dhcp_rebootEv
+ 0x08010c00 0x50 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net9memcpy_ipEPKh
+ 0x08010c50 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010c50 net::memcpy_ip(unsigned char const*)
+ .text._ZN3netL15dhcp_handle_ackEPKNS_4dhcp7MessageE
+ 0x08010c54 0x40 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net11dhcp_informEv
+ 0x08010c94 0x6c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010c94 net::dhcp_inform()
+ .text._ZN3net10dhcp_startEv
+ 0x08010d00 0x98 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010d00 net::dhcp_start()
+ .text._ZN3net21dhcp_release_and_stopEv
+ 0x08010d98 0xa4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010d98 net::dhcp_release_and_stop()
+ .text._ZN3netL13dhcp_fine_tmrEv
+ 0x08010e3c 0x8c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ .text._ZN3net12dhcp_processEPKNS_4dhcp7MessageEm
+ 0x08010ec8 0x15c ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
+ 0x08010ec8 net::dhcp_process(net::dhcp::Message const*, unsigned long)
+ .text._ZN3netL16igmp_send_reportEm
+ 0x08011024 0x78 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ .text._ZN3netL10igmp_timerEv
+ 0x0801109c 0x54 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ .text._ZN3net11igmp_set_ipEv
+ 0x080110f0 0x20 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x080110f0 net::igmp_set_ip()
+ .text._ZN3net9igmp_joinEm
+ 0x08011110 0x3c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08011110 net::igmp_join(unsigned long)
+ .text._ZN3net10igmp_leaveEm
+ 0x0801114c 0x4c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x0801114c net::igmp_leave(unsigned long)
+ .text._ZN3net18igmp_report_groupsEv
+ 0x08011198 0x5c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
+ 0x08011198 net::igmp_report_groups()
+ .text._ZN3netL28primary_ip_conflict_callbackENS_3acd8CallbackE
+ 0x080111f4 0x54 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ .text._ZN3net12net_shutdownEv
+ 0x08011248 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08011248 net::net_shutdown()
+ .text._ZN3net18net_set_primary_ipENS_7ip_addrE
+ 0x0801124c 0x38 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x0801124c net::net_set_primary_ip(net::ip_addr)
+ .text._ZN3net10net_chksumEPKvm
+ 0x08011284 0x58 ../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
+ 0x08011284 net::net_chksum(void const*, unsigned long)
+ .text._ZN3netL16default_callbackEtPKNS_25netif_ext_callback_args_tE
+ 0x080112dc 0x2 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ *fill* 0x080112de 0x2
+ .text._ZN3netL23netif_do_update_globalsEv
+ 0x080112e0 0x30 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3netL19netif_issue_reportsEv
+ 0x08011310 0x18 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3netL19netif_do_set_ipaddrENS_7ip_addrERS0_
+ 0x08011328 0x34 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .text._ZN3net10netif_initEv
+ 0x0801135c 0x40 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x0801135c net::netif_init()
+ .text._ZN3net16netif_set_ipaddrENS_7ip_addrE
+ 0x0801139c 0x24 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x0801139c net::netif_set_ipaddr(net::ip_addr)
+ .text._ZN3net17netif_set_netmaskENS_7ip_addrE
+ 0x080113c0 0x28 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080113c0 net::netif_set_netmask(net::ip_addr)
+ .text._ZN3net12netif_set_gwENS_7ip_addrE
+ 0x080113e8 0x28 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080113e8 net::netif_set_gw(net::ip_addr)
+ .text._ZN3net14netif_set_addrENS_7ip_addrES0_S0_
+ 0x08011410 0x8c ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x08011410 net::netif_set_addr(net::ip_addr, net::ip_addr, net::ip_addr)
+ .text._ZN3net22netif_add_ext_callbackEPFvtPKNS_25netif_ext_callback_args_tEE
+ 0x0801149c 0xc ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x0801149c net::netif_add_ext_callback(void (*)(unsigned short, net::netif_ext_callback_args_t const*))
+ .text._ZN3net19netif_set_link_downEv
+ 0x080114a8 0x40 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x080114a8 net::netif_set_link_down()
+ .text._ZN3netL8_bswap32EP5t_tcp
+ 0x080114e8 0x40 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL12send_packageEPKNS_3tcbERKNS_8SendInfoE
+ 0x08011528 0x170 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL10send_resetEP5t_tcpPKNS_3tcbE
+ 0x08011698 0x68 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3netL12scan_optionsEP5t_tcpPNS_3tcbEl
+ 0x08011700 0xb4 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ .text._ZN3net12tcp_shutdownEv
+ 0x080117b4 0x4 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080117b4 net::tcp_shutdown()
+ .text._ZN3net9tcp_beginEt
+ 0x080117b8 0x64 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x080117b8 net::tcp_begin(unsigned short)
+ .text._ZN3net8tcp_readElPPKhRm
+ 0x0801181c 0x70 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x0801181c net::tcp_read(long, unsigned char const**, unsigned long&)
+ .text._ZN3net9tcp_writeElPKhmm
+ 0x0801188c 0xa0 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
+ 0x0801188c net::tcp_write(long, unsigned char const*, unsigned long, unsigned long)
+ .text._ZN3net10udp_set_ipEv
+ 0x0801192c 0x14 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x0801192c net::udp_set_ip()
+ .text._ZN3net9udp_beginEt
+ 0x08011940 0x2c ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x08011940 net::udp_begin(unsigned short)
+ .text._ZN3net7udp_endEt
+ 0x0801196c 0x48 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x0801196c net::udp_end(unsigned short)
+ .text._ZN3net9udp_recv2EiPPKhPmPt
+ 0x080119b4 0x3c ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x080119b4 net::udp_recv2(int, unsigned char const**, unsigned long*, unsigned short*)
+ .text._ZN3net8udp_sendEiPKhmmt
+ 0x080119f0 0x110 ../lib-network/lib_gd32/libnetwork.a(udp.o)
+ 0x080119f0 net::udp_send(int, unsigned char const*, unsigned long, unsigned long, unsigned short)
+ .text._ZN18NetworkParamsStore4CopyEPN13networkparams6ParamsE
+ 0x08011b00 0x20 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011b00 NetworkParamsStore::Copy(networkparams::Params*)
+ .text._ZN13NetworkParamsC2Ev
+ 0x08011b20 0x14 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011b20 NetworkParams::NetworkParams()
+ 0x08011b20 NetworkParams::NetworkParams()
.text._ZN13NetworkParams4LoadEv
- 0x00000000080113e0 0x18 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080113e0 NetworkParams::Load()
+ 0x08011b34 0x12 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011b34 NetworkParams::Load()
+ *fill* 0x08011b46 0x2
.text._ZN13NetworkParams4LoadEPKcm
- 0x00000000080113f8 0x3c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x00000000080113f8 NetworkParams::Load(char const*, unsigned long)
+ 0x08011b48 0x50 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011b48 NetworkParams::Load(char const*, unsigned long)
.text._ZN13NetworkParams16callbackFunctionEPKc
- 0x0000000008011434 0x12c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008011434 NetworkParams::callbackFunction(char const*)
+ 0x08011b98 0x15c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011b98 NetworkParams::callbackFunction(char const*)
.text._ZN13NetworkParams22staticCallbackFunctionEPvPKc
- 0x0000000008011560 0x4 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008011560 NetworkParams::staticCallbackFunction(void*, char const*)
+ 0x08011cf4 0x4 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011cf4 NetworkParams::staticCallbackFunction(void*, char const*)
.text._ZN13NetworkParams7BuilderEPKN13networkparams6ParamsEPcmRm
- 0x0000000008011564 0x220 ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
- 0x0000000008011564 NetworkParams::Builder(networkparams::Params const*, char*, unsigned long, unsigned long&)
- .text._ZN13NetworkParams4DumpEv
- 0x0000000008011784 0x2 ../lib-network/lib_gd32/libnetwork.a(networkparamsdump.o)
- 0x0000000008011784 NetworkParams::Dump()
- .text.memcpy.isra.0
- 0x0000000008011786 0x14 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- *fill* 0x000000000801179a 0x2
- .text._ZL12_send_reportm
- 0x000000000801179c 0x7c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- .text._Z11igmp_set_ipv
- 0x0000000008011818 0x34 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x0000000008011818 igmp_set_ip()
- .text._Z10igmp_timerv
- 0x000000000801184c 0x30 ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x000000000801184c igmp_timer()
- .text._Z9igmp_joinm
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- 0x000000000801187c igmp_join(unsigned long)
- .text._Z10igmp_leavem
- 0x00000000080118c4 0x5c ../lib-network/lib_gd32/libnetwork.a(igmp.o)
- 0x00000000080118c4 igmp_leave(unsigned long)
- .text._ZL16refresh_and_initP6IpInfob
- 0x0000000008011920 0x48 ../lib-network/lib_gd32/libnetwork.a(net.o)
- .text._Z16set_secondary_ipv
- 0x0000000008011968 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008011968 set_secondary_ip()
- .text._Z10net_set_ipP6IpInfo
- 0x000000000801197c 0x34 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x000000000801197c net_set_ip(IpInfo*)
- .text._Z15net_set_netmaskP6IpInfo
- 0x00000000080119b0 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080119b0 net_set_netmask(IpInfo*)
- .text._Z10net_set_gwP6IpInfo
- 0x00000000080119c0 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080119c0 net_set_gw(IpInfo*)
- .text._Z12net_set_dhcpP6IpInfoPKcPb
- 0x00000000080119d0 0x48 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080119d0 net_set_dhcp(IpInfo*, char const*, bool*)
- .text._Z16net_dhcp_releasev
- 0x0000000008011a18 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008011a18 net_dhcp_release()
- .text._Z16net_set_zeroconfP6IpInfo
- 0x0000000008011a2c 0x28 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000008011a2c net_set_zeroconf(IpInfo*)
- .text._Z10net_chksumPKvm
- 0x0000000008011a54 0x34 ../lib-network/lib_gd32/libnetwork.a(net_chksum.o)
- 0x0000000008011a54 net_chksum(void const*, unsigned long)
- .text._Z14net_timers_runv
- 0x0000000008011a88 0x20 ../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- 0x0000000008011a88 net_timers_run()
- .text._Z7rfc3927v
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- .text.memcpy.isra.0
- 0x0000000008011b1c 0x14 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL12scan_optionsP5t_tcpP3tcbl
- 0x0000000008011b30 0xb0 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL8_bswap32P5t_tcp
- 0x0000000008011be0 0x4a ../lib-network/lib_gd32/libnetwork.a(tcp.o)
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- .text._ZL12send_packagePK3tcbRK8SendInfo
- 0x0000000008011c2c 0x17c ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL9_init_tcbP3tcbt
- 0x0000000008011da8 0x38 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._ZL10send_resetP5t_tcpPK3tcb
- 0x0000000008011de0 0x60 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- .text._Z12tcp_shutdownv
- 0x0000000008011e40 0x2 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008011e40 tcp_shutdown()
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- .text._Z9tcp_begint
- 0x0000000008011e44 0x34 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008011e44 tcp_begin(unsigned short)
- .text._Z8tcp_readlPPKhRm
- 0x0000000008011e78 0x68 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008011e78 tcp_read(long, unsigned char const**, unsigned long&)
- .text._Z9tcp_writelPKhtm
- 0x0000000008011ee0 0x64 ../lib-network/lib_gd32/libnetwork.a(tcp.o)
- 0x0000000008011ee0 tcp_write(long, unsigned char const*, unsigned short, unsigned long)
- .text._Z10net_memcpyPvPKvj.isra.0
- 0x0000000008011f44 0x38 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- .text.memcpy.isra.0
- 0x0000000008011f7c 0x14 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- .text._Z10udp_set_ipv
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- 0x0000000008011f90 udp_set_ip()
- .text._Z9udp_begint
- 0x0000000008011fb4 0x30 ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x0000000008011fb4 udp_begin(unsigned short)
- .text._Z7udp_endt
- 0x0000000008011fe4 0x4c ../lib-network/lib_gd32/libnetwork.a(udp.o)
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- .text._Z9udp_recv2iPPKhPmPt
- 0x0000000008012030 0x2c ../lib-network/lib_gd32/libnetwork.a(udp.o)
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- .text._Z8udp_sendiPKhtmt
- 0x000000000801205c 0x14c ../lib-network/lib_gd32/libnetwork.a(udp.o)
- 0x000000000801205c udp_send(int, unsigned char const*, unsigned short, unsigned long, unsigned short)
+ 0x08011cf8 0x23c ../lib-network/lib_gd32/libnetwork.a(networkparams.o)
+ 0x08011cf8 NetworkParams::Builder(networkparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN3net18phy_customized_ledEv
- 0x00000000080121a8 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x00000000080121a8 net::phy_customized_led()
+ 0x08011f34 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08011f34 net::phy_customized_led()
.text._ZN3net21phy_customized_timingEv
- 0x00000000080121aa 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x00000000080121aa net::phy_customized_timing()
- .text.emac_eth_recv
- 0x00000000080121ac 0x28 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x00000000080121ac emac_eth_recv
- .text.emac_free_pkt
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- 0x00000000080121d4 emac_free_pkt
- .text.emac_eth_send
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- 0x00000000080121dc emac_eth_send
+ 0x08011f36 0x2 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08011f36 net::phy_customized_timing()
+ .text._Z16emac_adjust_linkN3net9PhyStatusE
+ 0x08011f38 0x70 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x08011f38 emac_adjust_link(net::PhyStatus)
.text._ZN3net8phy_readEmmRt
- 0x00000000080121e0 0x16 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x00000000080121e0 net::phy_read(unsigned long, unsigned long, unsigned short&)
+ 0x08011fa8 0x16 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08011fa8 net::phy_read(unsigned long, unsigned long, unsigned short&)
.text._ZN3net9phy_writeEmmt
- 0x00000000080121f6 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x00000000080121f6 net::phy_write(unsigned long, unsigned long, unsigned short)
- *fill* 0x0000000008012216 0x2
+ 0x08011fbe 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08011fbe net::phy_write(unsigned long, unsigned long, unsigned short)
+ *fill* 0x08011fde 0x2
.text._ZN3net10phy_configEm
- 0x0000000008012218 0xd4 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008012218 net::phy_config(unsigned long)
- .text.memcpy.isra.0
- 0x00000000080122ec 0x14 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .text._Z16arp_send_requestm
- 0x0000000008012300 0x30 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008012300 arp_send_request(unsigned long)
- .text._Z14arp_send_probev
- 0x0000000008012330 0x40 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008012330 arp_send_probe()
- .text._Z12arp_do_probev
- 0x0000000008012370 0x30 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x0000000008012370 arp_do_probe()
- .text._Z21arp_send_announcementv
- 0x00000000080123a0 0x18 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x00000000080123a0 arp_send_announcement()
- .text._Z18arp_handle_requestP5t_arp
- 0x00000000080123b8 0x80 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- 0x00000000080123b8 arp_handle_request(t_arp*)
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- .text._Z16arp_cache_updatePKhm
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- .text._Z16arp_cache_lookupmPh
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- .text._ZL14parse_responseiPKh.constprop.0
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- .text._Z11dhcp_clientPKc
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- .text._Z19dhcp_client_releasev
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- .text._Z9ip_set_ipv
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- .text._ZN3net16link_status_readEv
- 0x000000000801294a 0x26 ../lib-network/lib_gd32/libnetwork.a(net_link_check.o)
- 0x000000000801294a net::link_status_read()
+ 0x08011fe0 0xd4 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08011fe0 net::phy_config(unsigned long)
+ .text._Z16enet_gpio_configv
+ 0x080120b4 0x1b4 ../lib-network/lib_gd32/libnetwork.a(emac.o)
+ 0x080120b4 enet_gpio_config()
+ .text._Z13emac_eth_recvPPh
+ 0x08012268 0x24 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x08012268 emac_eth_recv(unsigned char**)
+ .text._Z13emac_free_pktv
+ 0x0801228c 0x40 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x0801228c emac_free_pkt()
+ .text._Z13emac_eth_sendPvm
+ 0x080122cc 0x8c ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x080122cc emac_eth_send(void*, unsigned long)
+ .text._ZN3net9acd_startEPNS_3acd3AcdENS_7ip_addrE
+ 0x08012358 0x74 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x08012358 net::acd_start(net::acd::Acd*, net::ip_addr)
+ .text._ZN3net8acd_stopEPNS_3acd3AcdE
+ 0x080123cc 0x58 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080123cc net::acd_stop(net::acd::Acd*)
+ .text._ZN3netL9acd_timerEv
+ 0x08012424 0xb4 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ .text._ZN3netL11acd_restartEPNS_3acd3AcdE
+ 0x080124d8 0x32 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ *fill* 0x0801250a 0x2
+ .text._ZN3net29acd_network_changed_link_downEv
+ 0x0801250c 0xc ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x0801250c net::acd_network_changed_link_down()
+ .text._ZN3net13acd_arp_replyEP5t_arp
+ 0x08012518 0xac ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x08012518 net::acd_arp_reply(t_arp*)
+ .text._ZN3net7acd_addEPNS_3acd3AcdEPFvNS0_8CallbackEE
+ 0x080125c4 0xc ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080125c4 net::acd_add(net::acd::Acd*, void (*)(net::acd::Callback))
+ .text._ZN3net25acd_netif_ip_addr_changedENS_7ip_addrES0_
+ 0x080125d0 0x54 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ 0x080125d0 net::acd_netif_ip_addr_changed(net::ip_addr, net::ip_addr)
+ .text._ZN3netL15arp_find_recordEmNS_3arp5FlagsE
+ 0x08012624 0x64 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .text._ZN3netL9arp_timerEv
+ 0x08012688 0xb0 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .text._ZN3net8arp_sendEP5t_udpmm
+ 0x08012738 0xf8 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08012738 net::arp_send(t_udp*, unsigned long, unsigned long)
+ .text._ZN3net13arp_acd_probeENS_7ip_addrE
+ 0x08012830 0x28 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08012830 net::arp_acd_probe(net::ip_addr)
+ .text._ZN3net25arp_acd_send_announcementENS_7ip_addrE
+ 0x08012858 0x18 ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ 0x08012858 net::arp_acd_send_announcement(net::ip_addr)
+ .text._ZN3net9ip_set_ipEv
+ 0x08012870 0x10 ../lib-network/lib_gd32/libnetwork.a(ip.o)
+ 0x08012870 net::ip_set_ip()
+ .text._ZN3net12phy_get_linkEm
+ 0x08012880 0x20 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x08012880 net::phy_get_link(unsigned long)
.text._ZN3net9phy_startEmRNS_9PhyStatusE
- 0x0000000008012970 0x15c ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
- 0x0000000008012970 net::phy_start(unsigned long, net::PhyStatus&)
- .text.memcpy.isra.0
- 0x0000000008012acc 0x14 ../lib-network/lib_gd32/libnetwork.a(icmp.o)
- .text._ZN8LightSet18GetDmxStartAddressEv
- 0x0000000008012ae0 0x4 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008012ae0 LightSet::GetDmxStartAddress()
- .text._ZN8LightSet15GetDmxFootprintEv
- 0x0000000008012ae4 0x6 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008012ae4 LightSet::GetDmxFootprint()
- .text._ZN8LightSet18SetDmxStartAddressEt
- 0x0000000008012aea 0x4 ../lib-lightset/lib_gd32/liblightset.a(lightsetdmx.o)
- 0x0000000008012aea LightSet::SetDmxStartAddress(unsigned short)
- .text._ZN8LightSet11GetSlotInfoEtRN8lightset8SlotInfoE
- 0x0000000008012aee 0xa ../lib-lightset/lib_gd32/liblightset.a(lightsetgetslotinfo.o)
- 0x0000000008012aee LightSet::GetSlotInfo(unsigned short, lightset::SlotInfo&)
+ 0x080128a0 0x144 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x080128a0 net::phy_start(unsigned long, net::PhyStatus&)
.text._ZN7Display14ClearEndOfLineEv.isra.0
- 0x0000000008012af8 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x080129e4 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
.text._ZN7Display5WriteEmPKc.isra.0
- 0x0000000008012b00 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x080129ec 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
.text._ZN7Display6PrintfEmPKcz
- 0x0000000008012b22 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012b22 Display::Printf(unsigned long, char const*, ...)
- *fill* 0x0000000008012b5a 0x2
+ 0x08012a0e 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012a0e Display::Printf(unsigned long, char const*, ...)
+ *fill* 0x08012a46 0x2
.text._ZN10DisplayUdf13ShowIpAddressEv
- 0x0000000008012b5c 0x64 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012b5c DisplayUdf::ShowIpAddress()
+ 0x08012a48 0x68 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012a48 DisplayUdf::ShowIpAddress()
.text._ZN10DisplayUdfC2Ev
- 0x0000000008012bc0 0x30 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012bc0 DisplayUdf::DisplayUdf()
- 0x0000000008012bc0 DisplayUdf::DisplayUdf()
+ 0x08012ab0 0x2c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012ab0 DisplayUdf::DisplayUdf()
+ 0x08012ab0 DisplayUdf::DisplayUdf()
.text._ZN10DisplayUdf8SetTitleEPKcz
- 0x0000000008012bf0 0x28 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012bf0 DisplayUdf::SetTitle(char const*, ...)
+ 0x08012adc 0x26 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012adc DisplayUdf::SetTitle(char const*, ...)
.text._ZN10DisplayUdf3SetEmN10displayudf6LabelsE
- 0x0000000008012c18 0x34 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012c18 DisplayUdf::Set(unsigned long, displayudf::Labels)
+ 0x08012b02 0x34 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012b02 DisplayUdf::Set(unsigned long, displayudf::Labels)
+ *fill* 0x08012b36 0x2
.text._ZN10DisplayUdf4ShowEv
- 0x0000000008012c4c 0xe8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000008012c4c DisplayUdf::Show()
- .text._ZN17PropertiesBuilder3AddIhEEbPKcT_bm.isra.0
- 0x0000000008012d34 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- .text._ZN16DisplayUdfParamsC2EP21DisplayUdfParamsStore
- 0x0000000008012d84 0x1a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012d84 DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*)
- 0x0000000008012d84 DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore*)
+ 0x08012b38 0xec ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x08012b38 DisplayUdf::Show()
+ .text._ZN17PropertiesBuilder3AddIhEEbPKcT_bi.isra.0
+ 0x08012c24 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ .text._ZN21DisplayUdfParamsStore4CopyEPN16displayudfparams6ParamsE
+ 0x08012c74 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012c74 DisplayUdfParamsStore::Copy(displayudfparams::Params*)
+ .text._ZN16DisplayUdfParamsC2Ev
+ 0x08012c98 0x1c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012c98 DisplayUdfParams::DisplayUdfParams()
+ 0x08012c98 DisplayUdfParams::DisplayUdfParams()
.text._ZN16DisplayUdfParams4LoadEv
- 0x0000000008012d9e 0x18 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012d9e DisplayUdfParams::Load()
- *fill* 0x0000000008012db6 0x2
+ 0x08012cb4 0x12 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012cb4 DisplayUdfParams::Load()
+ *fill* 0x08012cc6 0x2
.text._ZN16DisplayUdfParams4LoadEPKcm
- 0x0000000008012db8 0x3c ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012db8 DisplayUdfParams::Load(char const*, unsigned long)
+ 0x08012cc8 0x50 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012cc8 DisplayUdfParams::Load(char const*, unsigned long)
.text._ZN16DisplayUdfParams16callbackFunctionEPKc
- 0x0000000008012df4 0xc8 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012df4 DisplayUdfParams::callbackFunction(char const*)
+ 0x08012d18 0xc0 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012d18 DisplayUdfParams::callbackFunction(char const*)
.text._ZN16DisplayUdfParams22staticCallbackFunctionEPvPKc
- 0x0000000008012ebc 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012ebc DisplayUdfParams::staticCallbackFunction(void*, char const*)
+ 0x08012dd8 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012dd8 DisplayUdfParams::staticCallbackFunction(void*, char const*)
.text._ZN16DisplayUdfParams7BuilderEPKN16displayudfparams6ParamsEPcmRm
- 0x0000000008012ec0 0x134 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012ec0 DisplayUdfParams::Builder(displayudfparams::Params const*, char*, unsigned long, unsigned long&)
+ 0x08012ddc 0x128 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012ddc DisplayUdfParams::Builder(displayudfparams::Params const*, char*, unsigned long, unsigned long&)
.text._ZN16DisplayUdfParams3SetEP10DisplayUdf
- 0x0000000008012ff4 0x6a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x0000000008012ff4 DisplayUdfParams::Set(DisplayUdf*)
- .text._ZN16DisplayUdfParams4DumpEv
- 0x000000000801305e 0x2 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
- 0x000000000801305e DisplayUdfParams::Dump()
- .text._ZN10DisplayUdf4ShowEP10E131Bridgem
- 0x0000000008013060 0xf4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowe131.o)
- 0x0000000008013060 DisplayUdf::Show(E131Bridge*, unsigned long)
+ 0x08012f04 0x6a ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfparams.o)
+ 0x08012f04 DisplayUdfParams::Set(DisplayUdf*)
+ *fill* 0x08012f6e 0x2
+ .text._ZN10DisplayUdf14ShowE131BridgeEv
+ 0x08012f70 0xec ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudfshowe131.o)
+ 0x08012f70 DisplayUdf::ShowE131Bridge()
.text._ZN7Display14ClearEndOfLineEv.isra.0
- 0x0000000008013154 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x0801305c 0x8 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
.text._ZN7Display5WriteEmPKc.isra.0
- 0x000000000801315c 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- .text._ZN7Display6StatusE22Display7SegmentMessage
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- 0x000000000801317e Display::Status(Display7SegmentMessage)
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- .text._ZN10DisplayUdf14ShowDhcpStatusEN7network4dhcp12ClientStatusE
- 0x00000000080131b4 0x68 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080131b4 DisplayUdf::ShowDhcpStatus(network::dhcp::ClientStatus)
- .text._ZN7network19display_emac_configEv
- 0x000000000801321c 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x000000000801321c network::display_emac_config()
- .text._ZN7network18display_emac_startEv
- 0x0000000008013240 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x0000000008013240 network::display_emac_start()
- .text._ZN7network19display_emac_statusEb
- 0x0000000008013264 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x0000000008013264 network::display_emac_status(bool)
- .text._ZN7network10display_ipEv
- 0x000000000801329c 0x10 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x000000000801329c network::display_ip()
- .text._ZN7network15display_netmaskEv
- 0x00000000080132ac 0x48 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080132ac network::display_netmask()
- .text._ZN7network15display_gatewayEv
- 0x00000000080132f4 0x40 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080132f4 network::display_gateway()
- .text._ZN7network16display_hostnameEv
- 0x0000000008013334 0x28 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x0000000008013334 network::display_hostname()
- .text._ZN7network21display_emac_shutdownEv
- 0x000000000801335c 0x64 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x000000000801335c network::display_emac_shutdown()
- .text._ZN7network19display_dhcp_statusENS_4dhcp12ClientStatusE
- 0x00000000080133c0 0x14 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
- 0x00000000080133c0 network::display_dhcp_status(network::dhcp::ClientStatus)
+ 0x08013064 0x22 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ *fill* 0x08013086 0x2
+ .text._ZN3net19display_emac_configEv
+ 0x08013088 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x08013088 net::display_emac_config()
+ .text._ZN3net18display_emac_startEv
+ 0x080130ac 0x24 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x080130ac net::display_emac_start()
+ .text._ZN3net19display_emac_statusEb
+ 0x080130d0 0x38 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x080130d0 net::display_emac_status(bool)
+ .text._ZN3net10display_ipEv
+ 0x08013108 0x10 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x08013108 net::display_ip()
+ .text._ZN3net15display_netmaskEv
+ 0x08013118 0x44 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x08013118 net::display_netmask()
+ .text._ZN3net15display_gatewayEv
+ 0x0801315c 0x40 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x0801315c net::display_gateway()
+ .text._ZN3net16display_hostnameEv
+ 0x0801319c 0x28 ../lib-displayudf/lib_gd32/libdisplayudf.a(network.o)
+ 0x0801319c net::display_hostname()
+ .text._ZL20spi_flash_read_writePKhjS0_Phj
+ 0x080131c4 0x34 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ .text._ZL24spi_flash_cmd_wait_readym
+ 0x080131f8 0x88 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ .text._ZL22spi_flash_write_commonPKhjS0_jb
+ 0x08013280 0x64 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ .text._Z18spi_flash_get_sizev
+ 0x080132e4 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080132e4 spi_flash_get_size()
+ .text._Z25spi_flash_get_sector_sizev
+ 0x080132f0 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080132f0 spi_flash_get_sector_size()
+ .text._Z18spi_flash_get_namev
+ 0x080132fc 0xc ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080132fc spi_flash_get_name()
+ .text._Z25spi_flash_cmd_write_multimjPKh
+ 0x08013308 0x74 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x08013308 spi_flash_cmd_write_multi(unsigned long, unsigned int, unsigned char const*)
+ .text._Z23spi_flash_cmd_read_fastmjPh
+ 0x0801337c 0x58 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x0801337c spi_flash_cmd_read_fast(unsigned long, unsigned int, unsigned char*)
+ .text._Z19spi_flash_cmd_erasemj
+ 0x080133d4 0x70 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080133d4 spi_flash_cmd_erase(unsigned long, unsigned int)
+ .text._Z15spi_flash_probejjj
+ 0x08013444 0x58 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x08013444 spi_flash_probe(unsigned int, unsigned int, unsigned int)
+ .text._Z23spi_flash_probe_winbondP9spi_flashPh
+ 0x0801349c 0x50 ../lib-flash/lib_gd32/libflash.a(winbond.o)
+ 0x0801349c spi_flash_probe_winbond(spi_flash*, unsigned char*)
+ .text._Z8spi_initv
+ 0x080134ec 0x50 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x080134ec spi_init()
+ .text._Z8spi_xfermPKhPhm
+ 0x0801353c 0x48 ../lib-flash/lib_gd32/libflash.a(spi_flash.o)
+ 0x0801353c spi_xfer(unsigned long, unsigned char const*, unsigned char*, unsigned long)
.text._ZN10properties17convert_json_fileEPcmb
- 0x00000000080133d4 0x170 ../lib-properties/lib_gd32/libproperties.a(properties.o)
- 0x00000000080133d4 properties::convert_json_file(char*, unsigned long, bool)
+ 0x08013584 0x158 ../lib-properties/lib_gd32/libproperties.a(properties.o)
+ 0x08013584 properties::convert_json_file(char*, unsigned long, bool)
.text._ZN17PropertiesBuilderC2EPKcPcm
- 0x0000000008013544 0x84 ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
- 0x0000000008013544 PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long)
- 0x0000000008013544 PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long)
+ 0x080136dc 0x84 ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
+ 0x080136dc PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long)
+ 0x080136dc PropertiesBuilder::PropertiesBuilder(char const*, char*, unsigned long)
.text._ZN17PropertiesBuilder12AddIpAddressEPKcmb
- 0x00000000080135c8 0x88 ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
- 0x00000000080135c8 PropertiesBuilder::AddIpAddress(char const*, unsigned long, bool)
+ 0x08013760 0x88 ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
+ 0x08013760 PropertiesBuilder::AddIpAddress(char const*, unsigned long, bool)
+ .text._ZN17PropertiesBuilder12AddUtcOffsetEPKcah
+ 0x080137e8 0x6c ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
+ 0x080137e8 PropertiesBuilder::AddUtcOffset(char const*, signed char, unsigned char)
.text._ZN17PropertiesBuilder10AddCommentEPKc
- 0x0000000008013650 0x34 ../lib-properties/lib_gd32/libproperties.a(propertiesbuilder.o)
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.text._ZN14ReadConfigFileC2EPFvPvPKcES0_
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+ 0x08013888 ReadConfigFile::ReadConfigFile(void (*)(void*, char const*), void*)
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.text._ZN14ReadConfigFileD2Ev
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.text._ZN14ReadConfigFile4ReadEPKcj
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.text._ZN5Sscan4CharEPKcS1_PcRm
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- 0x00000000080136fa Sscan::Char(char const*, char const*, char*, unsigned long&)
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.text._ZN5Sscan9IpAddressEPKcS1_Rm
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- 0x000000000801372c Sscan::IpAddress(char const*, char const*, unsigned long&)
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.text._ZN5Sscan6Uint16EPKcS1_Rt
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.text._ZN5Sscan5Uint8EPKcS1_Rh
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- 0x00000000080137ec Sscan::Uint8(char const*, char const*, unsigned char&)
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+ 0x080139e6 Sscan::Uint8(char const*, char const*, unsigned char&)
+ .text._ZN5Sscan9UtcOffsetEPKcS1_RaRh
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.text._ZN5Sscan9checkNameEPKcS1_
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.text._ZN7Display9PrintInfoEv.isra.0
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- .text._ZN7Display14Detect7SegmentEv
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- 0x00000000080138ce Display::Detect7Segment()
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+ .text._ZN7display7timeoutL9gpio_initEv
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.text._ZN7Display6DetectEN7display4TypeE
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.text._ZN7DisplayC2Ev
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.text._ZN7Ssd1306D2Ev
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.text._ZN7Ssd13069SetCursorEm
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.text._ZN7Ssd13069PrintInfoEv
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.text._ZN7Ssd1306D0Ev
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.text._ZN7HAL_I2C5SetupEv
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.text._ZN7Ssd13067PutCharEi
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.text._ZN7Ssd13069PutStringEPKc
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.text._ZN7Ssd13064TextEPKcm
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.text._ZN7Ssd130611InitMembersEv
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.text._ZN7Ssd1306C2E10TOledPanel
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.text._ZN7Ssd130611SendCommandEh
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.text._ZN7Ssd130612SetCursorPosEmm
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.text._ZN7Ssd13068TextLineEmPKcm
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.text._ZN7Ssd13069ClearLineEm
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.text._ZN7Ssd13068SetSleepEb
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.text._ZN7Ssd130611SetContrastEh
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- 0x0000000008013bc4 Ssd1306::SetContrast(unsigned char)
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.text._ZN7Ssd130617SetFlipVerticallyEb
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.text._ZN7Ssd130611CheckSH1106Ev
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.text._ZN7Ssd13063ClsEv
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.text._ZN7Ssd13065StartEv
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.text._ZN15FirmwareVersionC2EPKcS1_S1_
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+ 0x08013fdc FirmwareVersion::FirmwareVersion(char const*, char const*, char const*)
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+ .text._ZN8Hardware8ledblinkEv
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+ .text._ZN8Hardware19SoftwareTimerChangeElm.isra.0
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+ .text._ZN8Hardware19SoftwareTimerDeleteERl.isra.0
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.text._ZN8Hardware7SetModeEN8hardware8ledblink4ModeE
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.text._ZN8Hardware15SetModeWithLockEN8hardware8ledblink4ModeEb
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+ .text._ZN12remoteconfig8timedateL4atoiEPKcm
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+ .text._ZN8Hardware19SoftwareTimerChangeElm.isra.0
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.text._ZN8HardwareC2Ev
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.text._ZN8Hardware6RebootEv
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+ 0x080145ec Hardware::Reboot()
+ .text.console_putc
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.text.SystemInit
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.text.dma_deinit
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.text.dma_single_data_mode_init
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.text.dma_circulation_disable
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+ 0x0801492e dma_circulation_disable
.text.dma_channel_subperipheral_select
- 0x0000000008014720 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008014720 dma_channel_subperipheral_select
- .text.dma_flag_clear
- 0x0000000008014734 0x34 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008014734 dma_flag_clear
- .text.dma_interrupt_flag_get
- 0x0000000008014768 0x17e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x0000000008014768 dma_interrupt_flag_get
- .text.dma_interrupt_flag_clear
- 0x00000000080148e6 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x00000000080148e6 dma_interrupt_flag_clear
- .text.dma_interrupt_disable
- 0x00000000080148ea 0x1e ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
- 0x00000000080148ea dma_interrupt_disable
+ 0x0801493e 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_dma.o)
+ 0x0801493e dma_channel_subperipheral_select
+ *fill* 0x08014952 0x2
.text.enet_software_reset
- 0x0000000008014908 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014908 enet_software_reset
+ 0x08014954 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014954 enet_software_reset
.text.enet_descriptors_chain_init
- 0x0000000008014930 0x90 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014930 enet_descriptors_chain_init
- .text.enet_frame_receive
- 0x00000000080149c0 0x98 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000080149c0 enet_frame_receive
- .text.enet_frame_transmit
- 0x0000000008014a58 0x84 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014a58 enet_frame_transmit
+ 0x0801497c 0x90 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x0801497c enet_descriptors_chain_init
.text.enet_transmit_checksum_config
- 0x0000000008014adc 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014adc enet_transmit_checksum_config
+ 0x08014a0c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014a0c enet_transmit_checksum_config
.text.enet_mac_address_set
- 0x0000000008014ae8 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014ae8 enet_mac_address_set
+ 0x08014a18 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014a18 enet_mac_address_set
.text.enet_rx_enable
- 0x0000000008014afc 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014afc enet_rx_enable
+ 0x08014a2c 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014a2c enet_rx_enable
.text.enet_phy_write_read
- 0x0000000008014b18 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014b18 enet_phy_write_read
+ 0x08014a48 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014a48 enet_phy_write_read
.text.enet_init
- 0x0000000008014b6c 0x2a0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014b6c enet_init
+ 0x08014a9c 0x2a4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014a9c enet_init
.text.enet_txfifo_flush
- 0x0000000008014e0c 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014e0c enet_txfifo_flush
+ 0x08014d40 0x2c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014d40 enet_txfifo_flush
.text.enet_tx_enable
- 0x0000000008014e30 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014e30 enet_tx_enable
+ 0x08014d6c 0x24 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014d6c enet_tx_enable
.text.enet_enable
- 0x0000000008014e54 0xe ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014e54 enet_enable
- *fill* 0x0000000008014e62 0x2
+ 0x08014d90 0xe ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014d90 enet_enable
+ *fill* 0x08014d9e 0x2
.text.enet_desc_information_get
- 0x0000000008014e64 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014e64 enet_desc_information_get
- .text.enet_rxframe_drop
- 0x0000000008014eb8 0x64 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014eb8 enet_rxframe_drop
- .text.enet_rxframe_size_get
- 0x0000000008014f1c 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014f1c enet_rxframe_size_get
+ 0x08014da0 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014da0 enet_desc_information_get
.text.enet_initpara_reset
- 0x0000000008014f68 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014f68 enet_initpara_reset
+ 0x08014df4 0x28 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014df4 enet_initpara_reset
.text.enet_deinit
- 0x0000000008014f90 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000008014f90 enet_deinit
- *fill* 0x0000000008014faa 0x2
+ 0x08014e1c 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x08014e1c enet_deinit
+ *fill* 0x08014e36 0x2
.text.fwdgt_enable
- 0x0000000008014fac 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008014fac fwdgt_enable
+ 0x08014e38 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x08014e38 fwdgt_enable
.text.fwdgt_counter_reload
- 0x0000000008014fbc 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008014fbc fwdgt_counter_reload
+ 0x08014e48 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x08014e48 fwdgt_counter_reload
.text.fwdgt_config
- 0x0000000008014fcc 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
- 0x0000000008014fcc fwdgt_config
+ 0x08014e58 0x54 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_fwdgt.o)
+ 0x08014e58 fwdgt_config
.text.gpio_mode_set
- 0x0000000008015020 0x44 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008015020 gpio_mode_set
+ 0x08014eac 0x44 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08014eac gpio_mode_set
.text.gpio_output_options_set
- 0x0000000008015064 0x38 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x0000000008015064 gpio_output_options_set
+ 0x08014ef0 0x38 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08014ef0 gpio_output_options_set
+ .text.gpio_bit_set
+ 0x08014f28 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08014f28 gpio_bit_set
+ .text.gpio_bit_reset
+ 0x08014f2c 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08014f2c gpio_bit_reset
.text.gpio_af_set
- 0x000000000801509c 0x60 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
- 0x000000000801509c gpio_af_set
+ 0x08014f30 0x60 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_gpio.o)
+ 0x08014f30 gpio_af_set
.text.pmu_backup_ldo_config
- 0x00000000080150fc 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
- 0x00000000080150fc pmu_backup_ldo_config
+ 0x08014f90 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
+ 0x08014f90 pmu_backup_ldo_config
.text.pmu_backup_write_enable
- 0x0000000008015114 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
- 0x0000000008015114 pmu_backup_write_enable
+ 0x08014fa8 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_pmu.o)
+ 0x08014fa8 pmu_backup_write_enable
.text.rcu_periph_clock_enable
- 0x0000000008015124 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008015124 rcu_periph_clock_enable
+ 0x08014fb8 0x1a ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08014fb8 rcu_periph_clock_enable
.text.rcu_periph_clock_disable
- 0x000000000801513e 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801513e rcu_periph_clock_disable
+ 0x08014fd2 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08014fd2 rcu_periph_clock_disable
.text.rcu_periph_reset_enable
- 0x000000000801515a 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801515a rcu_periph_reset_enable
+ 0x08014fee 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08014fee rcu_periph_reset_enable
.text.rcu_periph_reset_disable
- 0x000000000801515e 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801515e rcu_periph_reset_disable
- *fill* 0x0000000008015162 0x2
+ 0x08014ff2 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08014ff2 rcu_periph_reset_disable
+ *fill* 0x08014ff6 0x2
.text.rcu_ckout0_config
- 0x0000000008015164 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x0000000008015164 rcu_ckout0_config
+ 0x08014ff8 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08014ff8 rcu_ckout0_config
.text.rcu_timer_clock_prescaler_config
- 0x000000000801517c 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801517c rcu_timer_clock_prescaler_config
+ 0x08015010 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08015010 rcu_timer_clock_prescaler_config
.text.rcu_clock_freq_get
- 0x000000000801519c 0xe8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
- 0x000000000801519c rcu_clock_freq_get
+ 0x08015030 0xe8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_rcu.o)
+ 0x08015030 rcu_clock_freq_get
.text.syscfg_enet_phy_interface_config
- 0x0000000008015284 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
- 0x0000000008015284 syscfg_enet_phy_interface_config
+ 0x08015118 0x18 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_syscfg.o)
+ 0x08015118 syscfg_enet_phy_interface_config
.text.timer_deinit
- 0x000000000801529c 0x14c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x000000000801529c timer_deinit
+ 0x08015130 0x14c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08015130 timer_deinit
+ .text.timer_struct_para_init
+ 0x0801527c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801527c timer_struct_para_init
.text.timer_init
- 0x00000000080153e8 0x7c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x00000000080153e8 timer_init
+ 0x0801528c 0x68 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801528c timer_init
.text.timer_enable
- 0x0000000008015464 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008015464 timer_enable
- .text.timer_interrupt_enable
- 0x000000000801546e 0x8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x000000000801546e timer_interrupt_enable
- .text.timer_interrupt_flag_clear
- 0x0000000008015476 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008015476 timer_interrupt_flag_clear
- .text.timer_flag_clear
- 0x000000000801547c 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x000000000801547c timer_flag_clear
+ 0x080152f4 0xa ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080152f4 timer_enable
+ .text.timer_counter_value_config
+ 0x080152fe 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x080152fe timer_counter_value_config
.text.timer_channel_output_mode_config
- 0x0000000008015482 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x0000000008015482 timer_channel_output_mode_config
+ 0x08015302 0x4c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08015302 timer_channel_output_mode_config
.text.timer_channel_output_pulse_value_config
- 0x00000000080154ce 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
- 0x00000000080154ce timer_channel_output_pulse_value_config
- *fill* 0x00000000080154ea 0x2
+ 0x0801534e 0x1c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801534e timer_channel_output_pulse_value_config
+ .text.timer_flag_clear
+ 0x0801536a 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x0801536a timer_flag_clear
+ .text.timer_interrupt_enable
+ 0x08015370 0x8 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08015370 timer_interrupt_enable
+ .text.timer_interrupt_flag_clear
+ 0x08015378 0x6 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_timer.o)
+ 0x08015378 timer_interrupt_flag_clear
+ *fill* 0x0801537e 0x2
.text.usart_deinit
- 0x00000000080154ec 0xc4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080154ec usart_deinit
+ 0x08015380 0xc4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08015380 usart_deinit
.text.usart_baudrate_set
- 0x00000000080155b0 0x88 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080155b0 usart_baudrate_set
+ 0x08015444 0x88 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08015444 usart_baudrate_set
.text.usart_parity_config
- 0x0000000008015638 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015638 usart_parity_config
+ 0x080154cc 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080154cc usart_parity_config
.text.usart_word_length_set
- 0x0000000008015648 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015648 usart_word_length_set
+ 0x080154dc 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080154dc usart_word_length_set
.text.usart_stop_bit_set
- 0x0000000008015658 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015658 usart_stop_bit_set
+ 0x080154ec 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080154ec usart_stop_bit_set
.text.usart_transmit_config
- 0x0000000008015668 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015668 usart_transmit_config
+ 0x080154fc 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x080154fc usart_transmit_config
.text.usart_receive_config
- 0x0000000008015674 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015674 usart_receive_config
+ 0x08015508 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08015508 usart_receive_config
.text.usart_hardware_flow_rts_config
- 0x0000000008015680 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015680 usart_hardware_flow_rts_config
+ 0x08015514 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08015514 usart_hardware_flow_rts_config
.text.usart_hardware_flow_cts_config
- 0x000000000801568c 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x000000000801568c usart_hardware_flow_cts_config
- .text.usart_dma_transmit_config
- 0x0000000008015698 0xc ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x0000000008015698 usart_dma_transmit_config
+ 0x08015528 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x08015528 usart_hardware_flow_cts_config
.text.usart_flag_get
- 0x00000000080156a4 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080156a4 usart_flag_get
- .text.usart_flag_clear
- 0x00000000080156b4 0x16 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080156b4 usart_flag_clear
- .text.usart_interrupt_enable
- 0x00000000080156ca 0x14 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080156ca usart_interrupt_enable
- .text.usart_interrupt_disable
- 0x00000000080156de 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080156de usart_interrupt_disable
- .text.usart_interrupt_flag_clear
- 0x00000000080156e2 0x16 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
- 0x00000000080156e2 usart_interrupt_flag_clear
- .text.uart0_init
- 0x00000000080156f8 0x20 ../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- 0x00000000080156f8 uart0_init
- .text.uart0_putc
- 0x0000000008015718 0x34 ../lib-gd32/lib_gd32/libgd32.a(gd32_uart0.o)
- 0x0000000008015718 uart0_putc
+ 0x0801553c 0x10 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_usart.o)
+ 0x0801553c usart_flag_get
.text._Z14bkp_data_write22bkp_data_register_enumt
- 0x000000000801574c 0x10 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
- 0x000000000801574c bkp_data_write(bkp_data_register_enum, unsigned short)
+ 0x0801554c 0x1c ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
+ 0x0801554c bkp_data_write(bkp_data_register_enum, unsigned short)
.text._Z13bkp_data_read22bkp_data_register_enum
- 0x000000000801575c 0x14 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
- 0x000000000801575c bkp_data_read(bkp_data_register_enum)
+ 0x08015568 0x20 ../lib-gd32/lib_gd32/libgd32.a(bkp.o)
+ 0x08015568 bkp_data_read(bkp_data_register_enum)
+ .text._Z15gd32_uart_beginmmmmm
+ 0x08015588 0x36c ../lib-gd32/lib_gd32/libgd32.a(gd32_uart.o)
+ 0x08015588 gd32_uart_begin(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
+ .text._Z15mac_address_getPh
+ 0x080158f4 0x24 ../lib-gd32/lib_gd32/libgd32.a(mac_address.o)
+ 0x080158f4 mac_address_get(unsigned char*)
+ .text._Z13timer6_configv
+ 0x08015918 0x74 ../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ 0x08015918 timer6_config()
+ .text._Z11udelay_initv
+ 0x0801598c 0x28 ../lib-gd32/lib_gd32/libgd32.a(udelay.o)
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+ .text._Z6udelaymm
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+ 0x20001264 0x4 ../lib-e131/lib_gd32/libe131.a(e131params.o)
.bss._ZL15s_ReceivingMask
- 0x0000000020001264 0x4 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
- .bss._ZN10LLRPDevice13s_nHandleLLRPE
- 0x0000000020001268 0x4 ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- 0x0000000020001268 LLRPDevice::s_nHandleLLRP
- .bss._ZN10LLRPDevice16s_nIpAddressFromE
- 0x000000002000126c 0x4 ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- 0x000000002000126c LLRPDevice::s_nIpAddressFrom
- .bss._ZN10LLRPDevice7s_pLLRPE
- 0x0000000020001270 0x4 ../lib-rdmnet/lib_gd32/librdmnet.a(llrpdevice.o)
- 0x0000000020001270 LLRPDevice::s_pLLRP
- .bss._ZN12RDMNetDevice12s_RdmCommandE
- 0x0000000020001274 0x101 ../lib-rdmnet/lib_gd32/librdmnet.a(rdmnetdevice.o)
- 0x0000000020001274 RDMNetDevice::s_RdmCommand
- .bss._ZN12RDMNetDevice5s_CidE
- 0x0000000020001375 0x10 ../lib-rdmnet/lib_gd32/librdmnet.a(rdmnetdevice.o)
- 0x0000000020001375 RDMNetDevice::s_Cid
- *fill* 0x0000000020001385 0x3
- .bss._ZN10RDMSensors7s_pThisE
- 0x0000000020001388 0x4 ../lib-rdmsensor/lib_gd32/librdmsensor.a(rdmsensors.o)
- 0x0000000020001388 RDMSensors::s_pThis
- .bss._ZN13RDMSubDevices7s_pThisE
- 0x000000002000138c 0x4 ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a(rdmsubdevices.o)
- 0x000000002000138c RDMSubDevices::s_pThis
+ 0x20001268 0x4 ../lib-e131/lib_gd32/libe131.a(handledmxin.o)
.bss._ZN18RDMDeviceResponder7s_pThisE
- 0x0000000020001390 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
- 0x0000000020001390 RDMDeviceResponder::s_pThis
- .bss._ZN11RDMIdentify12m_bIsEnabledE
- 0x0000000020001394 0x1 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x0000000020001394 RDMIdentify::m_bIsEnabled
- .bss._ZN11RDMIdentify7m_nModeE
- 0x0000000020001395 0x1 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x0000000020001395 RDMIdentify::m_nMode
- *fill* 0x0000000020001396 0x2
+ 0x2000126c 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmdeviceresponder.o)
+ 0x2000126c RDMDeviceResponder::s_pThis
.bss._ZN11RDMIdentify7s_pThisE
- 0x0000000020001398 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
- 0x0000000020001398 RDMIdentify::s_pThis
- .bss._ZN7DmxSend10s_nStartedE
- 0x000000002000139c 0x1 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x000000002000139c DmxSend::s_nStarted
- *fill* 0x000000002000139d 0x3
- .bss._ZN7DmxSend8s_TxDataE
- 0x00000000200013a0 0x410 ../lib-dmxsend/lib_gd32/libdmxsend.a(dmxsend.o)
- 0x00000000200013a0 DmxSend::s_TxData
- .bss._ZL10s_RxBuffer
- 0x00000000200017b0 0x420 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- .bss._ZL12sv_PortState
- 0x0000000020001bd0 0x8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- .bss._ZL15s_RxDmxPrevious
- 0x0000000020001bd8 0x404 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- .bss._ZL16sv_nRxDmxPackets
- 0x0000000020001fdc 0x20 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- .bss._ZL9s_doForce
- 0x0000000020001ffc 0x1 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- *fill* 0x0000000020001ffd 0x3
+ 0x20001270 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x20001270 RDMIdentify::s_pThis
+ .bss._ZN11RDMIdentify7m_nModeE
+ 0x20001274 0x1 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x20001274 RDMIdentify::m_nMode
+ .bss._ZN11RDMIdentify12m_bIsEnabledE
+ 0x20001275 0x1 ../lib-rdm/lib_gd32/librdm.a(rdmidentify.o)
+ 0x20001275 RDMIdentify::m_bIsEnabled
+ *fill* 0x20001276 0x2
+ .bss._ZN10RDMSensors7s_pThisE
+ 0x20001278 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmsensors.o)
+ 0x20001278 RDMSensors::s_pThis
+ .bss._ZN13RDMSubDevices7s_pThisE
+ 0x2000127c 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmsubdevices.o)
+ 0x2000127c RDMSubDevices::s_pThis
+ .bss._ZN10LLRPDevice12s_RdmCommandE
+ 0x20001280 0x101 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x20001280 LLRPDevice::s_RdmCommand
+ *fill* 0x20001381 0x3
+ .bss._ZN10LLRPDevice7s_pLLRPE
+ 0x20001384 0x4 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x20001384 LLRPDevice::s_pLLRP
+ .bss._ZN10LLRPDevice16s_nIpAddressFromE
+ 0x20001388 0x4 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x20001388 LLRPDevice::s_nIpAddressFrom
+ .bss._ZN10LLRPDevice13s_nHandleLLRPE
+ 0x2000138c 0x4 ../lib-rdm/lib_gd32/librdm.a(llrpdevice.o)
+ 0x2000138c LLRPDevice::s_nHandleLLRP
+ .bss._ZN9RDMDevice7s_pThisE
+ 0x20001390 0x4 ../lib-rdm/lib_gd32/librdm.a(rdmdevice.o)
+ 0x20001390 RDMDevice::s_pThis
.bss._ZN3Dmx7s_pThisE
- 0x0000000020002000 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000020002000 Dmx::s_pThis
- .bss.gv_RdmDataReceiveEnd
- 0x0000000020002004 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x0000000020002004 gv_RdmDataReceiveEnd
- .bss._ZN12DmxConfigUdp12s_pUdpBufferE
- 0x0000000020002008 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmxconfigudp.o)
- 0x0000000020002008 DmxConfigUdp::s_pUdpBuffer
+ 0x20001394 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x20001394 Dmx::s_pThis
+ .bss._ZL14s_nDmxTransmit
+ 0x20001398 0xc ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ .bss._ZL11sv_RxBuffer
+ 0x200013a4 0xa38 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ .bss.gsv_RdmDataReceiveEnd
+ 0x20001ddc 0x4 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x20001ddc gsv_RdmDataReceiveEnd
+ .bss._ZL16sv_nRxDmxPackets
+ 0x20001de0 0x18 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ .bss._ZL18sv_TotalStatistics
+ 0x20001df8 0x38 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ .bss._ZL12sv_PortState
+ 0x20001e30 0x8 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ .bss._ZN11ConfigStore7s_pThisE
+ 0x20001e38 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20001e38 ConfigStore::s_pThis
+ .bss._ZN11ConfigStore14s_SpiFlashDataE
+ 0x20001e3c 0x1000 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20001e3c ConfigStore::s_SpiFlashData
.bss._ZN11ConfigStore13s_nWaitMillisE
- 0x000000002000200c 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000002000200c ConfigStore::s_nWaitMillis
- .bss._ZN11ConfigStore15s_nStartAddressE
- 0x0000000020002010 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000020002010 ConfigStore::s_nStartAddress
- .bss._ZN11ConfigStore16s_bHaveFlashChipE
- 0x0000000020002014 0x1 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000020002014 ConfigStore::s_bHaveFlashChip
- *fill* 0x0000000020002015 0x3
+ 0x20002e3c 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20002e3c ConfigStore::s_nWaitMillis
.bss._ZN11ConfigStore20s_nSpiFlashStoreSizeE
- 0x0000000020002018 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000020002018 ConfigStore::s_nSpiFlashStoreSize
+ 0x20002e40 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20002e40 ConfigStore::s_nSpiFlashStoreSize
+ .bss._ZN11ConfigStore15s_nStartAddressE
+ 0x20002e44 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20002e44 ConfigStore::s_nStartAddress
.bss._ZN11ConfigStore7s_StateE
- 0x000000002000201c 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x000000002000201c ConfigStore::s_State
- .bss._ZN11ConfigStore7s_pThisE
- 0x0000000020002020 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000020002020 ConfigStore::s_pThis
- .bss._ZN15StoreDisplayUdf7s_pThisE
- 0x0000000020002024 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedisplayudf.o)
- 0x0000000020002024 StoreDisplayUdf::s_pThis
- .bss._ZN12StoreDmxSend7s_pThisE
- 0x0000000020002028 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storedmxsend.o)
- 0x0000000020002028 StoreDmxSend::s_pThis
- .bss._ZN12StoreNetwork7s_pThisE
- 0x000000002000202c 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storenetwork.o)
- 0x000000002000202c StoreNetwork::s_pThis
- .bss._ZN17StoreRemoteConfig7s_pThisE
- 0x0000000020002030 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storeremoteconfig.o)
- 0x0000000020002030 StoreRemoteConfig::s_pThis
- .bss._ZN9StoreE1317s_pThisE
- 0x0000000020002034 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storee131.o)
- 0x0000000020002034 StoreE131::s_pThis
- .bss._ZN14StoreRDMDevice7s_pThisE
- 0x0000000020002038 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(storerdmdevice.o)
- 0x0000000020002038 StoreRDMDevice::s_pThis
- .bss._ZN4MDNS11s_nRemoteIpE
- 0x000000002000203c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x000000002000203c MDNS::s_nRemoteIp
- .bss._ZN4MDNS13s_nRemotePortE
- 0x0000000020002040 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020002040 MDNS::s_nRemotePort
- .bss._ZN4MDNS16s_nBytesReceivedE
- 0x0000000020002042 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020002042 MDNS::s_nBytesReceived
- .bss._ZN4MDNS16s_pReceiveBufferE
- 0x0000000020002044 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020002044 MDNS::s_pReceiveBuffer
+ 0x20002e48 0x4 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20002e48 ConfigStore::s_State
+ .bss._ZN11ConfigStore16s_bHaveFlashChipE
+ 0x20002e4c 0x1 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
+ 0x20002e4c ConfigStore::s_bHaveFlashChip
+ *fill* 0x20002e4d 0x3
.bss._ZN4MDNS7s_pThisE
- 0x0000000020002048 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x0000000020002048 MDNS::s_pThis
+ 0x20002e50 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e50 MDNS::s_pThis
+ .bss._ZN4MDNS16s_pReceiveBufferE
+ 0x20002e54 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e54 MDNS::s_pReceiveBuffer
+ .bss._ZN4MDNS16s_nBytesReceivedE
+ 0x20002e58 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e58 MDNS::s_nBytesReceived
+ .bss._ZN4MDNS13s_nRemotePortE
+ 0x20002e5c 0x2 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e5c MDNS::s_nRemotePort
+ *fill* 0x20002e5e 0x2
+ .bss._ZN4MDNS11s_nRemoteIpE
+ 0x20002e60 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e60 MDNS::s_nRemoteIp
.bss._ZN4MDNS9s_nHandleE
- 0x000000002000204c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- 0x000000002000204c MDNS::s_nHandle
+ 0x20002e64 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e64 MDNS::s_nHandle
.bss._ZN4mdnsL11s_isUnicastE
- 0x0000000020002050 0x1 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- *fill* 0x0000000020002051 0x3
- .bss._ZN4mdnsL13s_HostRepliesE
- 0x0000000020002054 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e68 0x1 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.bss._ZN4mdnsL13s_RecordsDataE
- 0x0000000020002058 0x200 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
- .bss._ZN4mdnsL16s_ServiceRecordsE
- 0x0000000020002258 0x20 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x20002e69 0x200 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ *fill* 0x20003069 0x3
.bss._ZN4mdnsL16s_ServiceRepliesE
- 0x0000000020002278 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ 0x2000306c 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .bss._ZN4mdnsL13s_HostRepliesE
+ 0x20003070 0x4 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
+ .bss._ZN4mdnsL16s_ServiceRecordsE
+ 0x20003074 0x20 ../lib-network/lib_gd32/libnetwork.a(mdns.o)
.bss._ZN7Network7s_pThisE
- 0x000000002000227c 0x4 ../lib-network/lib_gd32/libnetwork.a(network.o)
- 0x000000002000227c Network::s_pThis
- .bss._ZL3s_p 0x0000000020002280 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- .bss._ZL8s_isDhcp
- 0x0000000020002284 0x1 ../lib-network/lib_gd32/libnetwork.a(net.o)
- *fill* 0x0000000020002285 0x3
- .bss._ZN3net7globals10macAddressE
- 0x0000000020002288 0x6 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020002288 net::globals::macAddress
- *fill* 0x000000002000228e 0x2
- .bss._ZN3net7globals14nBroadcastMaskE
- 0x0000000020002290 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020002290 net::globals::nBroadcastMask
+ 0x20003094 0x4 ../lib-network/lib_gd32/libnetwork.a(network.o)
+ 0x20003094 Network::s_pThis
.bss._ZN3net7globals14nOnNetworkMaskE
- 0x0000000020002294 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020002294 net::globals::nOnNetworkMask
- .bss._ZN3net7globals6ipInfoE
- 0x0000000020002298 0x14 ../lib-network/lib_gd32/libnetwork.a(net.o)
- 0x0000000020002298 net::globals::ipInfo
- .bss._ZL8s_ticker
- 0x00000000200022ac 0x4 ../lib-network/lib_gd32/libnetwork.a(net_timers.o)
- .bss._ZL11s_arp_reply
- 0x00000000200022b0 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL13s_arp_request
- 0x00000000200022ec 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL13s_requestType
- 0x0000000020002328 0x4 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- .bss._ZL22s_isProbeReplyReceived
- 0x000000002000232c 0x1 ../lib-network/lib_gd32/libnetwork.a(arp.o)
- *fill* 0x000000002000232d 0x3
- .bss._ZL14s_dhcp_message
- 0x0000000020002330 0x224 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL16s_dhcp_server_ip
- 0x0000000020002554 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL19s_dhcp_allocated_gw
- 0x0000000020002558 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL19s_dhcp_allocated_ip
- 0x000000002000255c 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZL24s_dhcp_allocated_netmask
- 0x0000000020002560 0x4 ../lib-network/lib_gd32/libnetwork.a(dhcp.o)
- .bss._ZN3netL11s_phyStatusE
- 0x0000000020002564 0x10 ../lib-network/lib_gd32/libnetwork.a(net_phy.o)
+ 0x20003098 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x20003098 net::globals::nOnNetworkMask
+ .bss._ZN3net7globals14nBroadcastMaskE
+ 0x2000309c 0x4 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ 0x2000309c net::globals::nBroadcastMask
+ .bss._ZL5s_acd
+ 0x200030a0 0x10 ../lib-network/lib_gd32/libnetwork.a(net.o)
+ .bss._ZN3netL11callback_fnE
+ 0x200030b0 0x4 ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ .bss._ZN3net7globals13netif_defaultE
+ 0x200030b4 0x2c ../lib-network/lib_gd32/libnetwork.a(netif.o)
+ 0x200030b4 net::globals::netif_default
+ .bss._ZN3netL8nTimerIdE
+ 0x200030e0 0x4 ../lib-network/lib_gd32/libnetwork.a(acd.o)
+ .bss._ZN3netL11s_arp_replyE
+ 0x200030e4 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
+ .bss._ZN3netL13s_arp_requestE
+ 0x20003120 0x3c ../lib-network/lib_gd32/libnetwork.a(arp.o)
.bss._ZN10DisplayUdf7s_pThisE
- 0x0000000020002574 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
- 0x0000000020002574 DisplayUdf::s_pThis
+ 0x2000315c 0x4 ../lib-displayudf/lib_gd32/libdisplayudf.a(displayudf.o)
+ 0x2000315c DisplayUdf::s_pThis
.bss._ZN16PropertiesConfig8s_ConfigE
- 0x0000000020002578 0x1 ../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
- 0x0000000020002578 PropertiesConfig::s_Config
- *fill* 0x0000000020002579 0x3
+ 0x20003160 0x1 ../lib-properties/lib_gd32/libproperties.a(propertiesconfig.o)
+ 0x20003160 PropertiesConfig::s_Config
+ *fill* 0x20003161 0x3
.bss._ZN7Display7s_pThisE
- 0x000000002000257c 0x4 ../lib-display/lib_gd32/libdisplay.a(display.o)
- 0x000000002000257c Display::s_pThis
- .bss._ZL12_ClearBuffer
- 0x0000000020002580 0x86 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
- *fill* 0x0000000020002606 0x2
+ 0x20003164 0x4 ../lib-display/lib_gd32/libdisplay.a(display.o)
+ 0x20003164 Display::s_pThis
.bss._ZN7Ssd13067s_pThisE
- 0x0000000020002608 0x4 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
- 0x0000000020002608 Ssd1306::s_pThis
- .bss._ZN15FirmwareVersion17s_FirmwareVersionE
- 0x000000002000260c 0x16 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x000000002000260c FirmwareVersion::s_FirmwareVersion
- .bss._ZN15FirmwareVersion7s_PrintE
- 0x0000000020002622 0x40 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x0000000020002622 FirmwareVersion::s_Print
- *fill* 0x0000000020002662 0x2
+ 0x20003168 0x4 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
+ 0x20003168 Ssd1306::s_pThis
+ .bss._ZL12_ClearBuffer
+ 0x2000316c 0x86 ../lib-display/lib_gd32/libdisplay.a(ssd1306.o)
+ *fill* 0x200031f2 0x2
.bss._ZN15FirmwareVersion7s_pThisE
- 0x0000000020002664 0x4 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
- 0x0000000020002664 FirmwareVersion::s_pThis
+ 0x200031f4 0x4 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x200031f4 FirmwareVersion::s_pThis
+ .bss._ZN15FirmwareVersion7s_PrintE
+ 0x200031f8 0x40 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x200031f8 FirmwareVersion::s_Print
+ .bss._ZN15FirmwareVersion17s_FirmwareVersionE
+ 0x20003238 0x16 ../lib-hal/lib_gd32/libhal.a(firmwareversion.o)
+ 0x20003238 FirmwareVersion::s_FirmwareVersion
+ *fill* 0x2000324e 0x2
.bss._ZN8Hardware7s_pThisE
- 0x0000000020002668 0x4 ../lib-hal/lib_gd32/libhal.a(hardware.o)
- 0x0000000020002668 Hardware::s_pThis
- .bss.last.0 0x000000002000266c 0x4 ../lib-c/lib_gd32/libc.a(strtok.o)
- .bss.s_micros 0x0000000020002670 0x8 ../lib-c/lib_gd32/libc.a(time.o)
- .bss.set_timer
- 0x0000000020002678 0x4 ../lib-c/lib_gd32/libc.a(time.o)
- .bss.s_nSysTickMillis
- 0x000000002000267c 0x4 ../lib-gd32/lib_gd32/libgd32.a(systick.o)
- 0x000000002000267c s_nSysTickMillis
+ 0x20003250 0x4 ../lib-hal/lib_gd32/libhal.a(hardware.o)
+ 0x20003250 Hardware::s_pThis
+ .bss.enet_initpara
+ 0x20003254 0x3c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
.bss.dma_current_ptp_rxdesc
- 0x0000000020002680 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020002680 dma_current_ptp_rxdesc
+ 0x20003290 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003290 dma_current_ptp_rxdesc
.bss.dma_current_ptp_txdesc
- 0x0000000020002684 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020002684 dma_current_ptp_txdesc
+ 0x20003294 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003294 dma_current_ptp_txdesc
.bss.dma_current_rxdesc
- 0x0000000020002688 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020002688 dma_current_rxdesc
+ 0x20003298 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20003298 dma_current_rxdesc
.bss.dma_current_txdesc
- 0x000000002000268c 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000268c dma_current_txdesc
- .bss.enet_initpara
- 0x0000000020002690 0x3c ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- .bss.rx_buff 0x00000000200026cc 0x5f40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x00000000200026cc rx_buff
- .bss.rxdesc_tab
- 0x000000002000860c 0x100 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000860c rxdesc_tab
- .bss.tx_buff 0x000000002000870c 0x17d0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x000000002000870c tx_buff
+ 0x2000329c 0x4 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x2000329c dma_current_txdesc
+ .bss.tx_buff 0x200032a0 0x17d0 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x200032a0 tx_buff
+ .bss.rx_buff 0x20004a70 0x5f40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x20004a70 rx_buff
.bss.txdesc_tab
- 0x0000000020009edc 0x40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
- 0x0000000020009edc txdesc_tab
+ 0x2000a9b0 0x40 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x2000a9b0 txdesc_tab
+ .bss.rxdesc_tab
+ 0x2000a9f0 0x100 ../lib-gd32/lib_gd32/libgd32.a(gd32f4xx_enet.o)
+ 0x2000a9f0 rxdesc_tab
+ .bss.g_Seconds
+ 0x2000aaf0 0x8 ../lib-gd32/lib_gd32/libgd32.a(timer6.o)
+ 0x2000aaf0 g_Seconds
+ .bss.gv_nSysTickMillis
+ 0x2000aaf8 0x4 ../lib-gd32/lib_gd32/libgd32.a(systick.o)
+ 0x2000aaf8 gv_nSysTickMillis
.bss._ZL10s_nAddress
- 0x0000000020009f1c 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ 0x2000aafc 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_i2c.o)
+ .bss._ZL13s_nChipSelect
+ 0x2000aafd 0x1 ../lib-gd32/lib_gd32/libgd32.a(gd32_spi.o)
+ *fill* 0x2000aafe 0x2
+ .bss.outptr 0x2000ab00 0x4 ../lib-clib/lib_gd32/libclib.a(printf.o)
+ .bss.last.0 0x2000ab04 0x4 ../lib-clib/lib_gd32/libclib.a(strtok.o)
+ .bss._ZL2Tm 0x2000ab08 0x24 ../lib-clib/lib_gd32/libclib.a(time.o)
+ .bss._ZN6global13gp_nUtcOffsetE
+ 0x2000ab2c 0x4 ../lib-clib/lib_gd32/libclib.a(time.o)
+ 0x2000ab2c global::gp_nUtcOffset
+ .bss._ZL4s_tv 0x2000ab30 0x8 ../lib-clib/lib_gd32/libclib.a(time.o)
+ .bss._ZL22nPreviousSysTickMillis
+ 0x2000ab38 0x4 ../lib-clib/lib_gd32/libclib.a(time.o)
*(COMMON)
- 0x0000000020009f20 . = ALIGN (0x4)
- *fill* 0x0000000020009f1d 0x3
- 0x0000000020009f20 _ebss = .
- 0x0000000020009f20 __bss_end__ = _ebss
- 0x0000000020009f20 . = ALIGN (0x8)
+ 0x2000ab3c . = ALIGN (0x4)
+ 0x2000ab3c _ebss = .
+ 0x2000ab3c __bss_end__ = _ebss
+ 0x2000ab40 . = ALIGN (0x8)
[!provide] PROVIDE (end = _ebss)
[!provide] PROVIDE (_end = _ebss)
-.sram1 0x000000002001c000 0x418
- 0x000000002001c000 . = ALIGN (0x4)
+.sram1 0x2001c000 0x428
+ 0x2001c000 . = ALIGN (0x4)
*(.sram1)
*(.sram1*)
- 0x000000002001c000 . = ALIGN (0x4)
- 0x000000002001c000 _sdmx = .
+ 0x2001c000 . = ALIGN (0x4)
+ 0x2001c000 _sdmx = .
*(.dmx)
- .dmx 0x000000002001c000 0x418 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _edmx = .
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _spixel = .
+ .dmx 0x2001c000 0x428 ../lib-dmx/lib_gd32/libdmx.a(dmx.o)
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _edmx = .
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _spixel = .
*(.pixel)
- 0x000000002001c418 . = ALIGN (0x4)
- 0x000000002001c418 _epixel = .
+ 0x2001c428 . = ALIGN (0x4)
+ 0x2001c428 _epixel = .
-.sram2 0x0000000020020000 0x0
- 0x0000000020020000 . = ALIGN (0x4)
+.sram2 0x20020000 0x0
+ 0x20020000 . = ALIGN (0x4)
*(.sram2)
*(.sram2*)
-.ramadd 0x0000000020030000 0x0
- 0x0000000020030000 _sramadd = .
- 0x0000000020030000 . = ALIGN (0x4)
+.ramadd 0x20030000 0x0
+ 0x20030000 _sramadd = .
+ 0x20030000 . = ALIGN (0x4)
*(.ramadd)
*(.ramadd*)
- 0x0000000020030000 . = ALIGN (0x4)
- 0x0000000020030000 _eramadd = .
+ 0x20030000 . = ALIGN (0x4)
+ 0x20030000 _eramadd = .
-.bkpsram 0x0000000040024000 0x1000
- 0x0000000040024000 . = ALIGN (0x4)
+.bkpsram 0x40024000 0x0
+ 0x40024000 . = ALIGN (0x4)
*(.bkpsram)
*(.bkpsram*)
*(.configstore*)
- .configstore 0x0000000040024000 0x1000 ../lib-configstore/lib_gd32/libconfigstore.a(configstore.o)
- 0x0000000040024000 ConfigStore::s_SpiFlashData
/DISCARD/
*(*.ARM.*)
*(*.comment)
*(*.debug*)
START GROUP
-LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a
-LOAD ../lib-c/lib_gd32/libc.a
+LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a
END GROUP
LOAD ../lib-remoteconfig/lib_gd32/libremoteconfig.a
LOAD ../lib-e131/lib_gd32/libe131.a
-LOAD ../lib-rdmnet/lib_gd32/librdmnet.a
-LOAD ../lib-rdmsensor/lib_gd32/librdmsensor.a
-LOAD ../lib-rdmsubdevice/lib_gd32/librdmsubdevice.a
LOAD ../lib-rdm/lib_gd32/librdm.a
-LOAD ../lib-uuid/lib_gd32/libuuid.a
-LOAD ../lib-dmxsend/lib_gd32/libdmxsend.a
LOAD ../lib-dmx/lib_gd32/libdmx.a
LOAD ../lib-configstore/lib_gd32/libconfigstore.a
LOAD ../lib-network/lib_gd32/libnetwork.a
-LOAD ../lib-lightset/lib_gd32/liblightset.a
LOAD ../lib-displayudf/lib_gd32/libdisplayudf.a
+LOAD ../lib-lightset/lib_gd32/liblightset.a
LOAD ../lib-flash/lib_gd32/libflash.a
LOAD ../lib-properties/lib_gd32/libproperties.a
LOAD ../lib-display/lib_gd32/libdisplay.a
+LOAD ../lib-device/lib_gd32/libdevice.a
LOAD ../lib-hal/lib_gd32/libhal.a
-LOAD ../lib-c++/lib_gd32/libc++.a
-LOAD ../lib-c/lib_gd32/libc.a
LOAD ../lib-gd32/lib_gd32/libgd32.a
-LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/11.3.1-1.1.2/.content/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/libgcc.a
+LOAD ../lib-clib/lib_gd32/libclib.a
+LOAD /Users/arjanvanvught/Library/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/13.2.1-1.1.1/.content/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a
OUTPUT(build_gd32/main.elf elf32-littlearm)
LOAD linker stubs
diff --git a/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh b/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh
deleted file mode 100755
index 2f453f59..00000000
--- a/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-echo "// Generated "$(date) > ./include/sofware_version_id.h
-var="$(date +%s)"
-echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$var";" >> ./include/sofware_version_id.h
-
diff --git a/gd32_emac_e131_dmx_multi/include/display_timeout.h b/gd32_emac_e131_dmx_multi/include/display_timeout.h
deleted file mode 100644
index a8556629..00000000
--- a/gd32_emac_e131_dmx_multi/include/display_timeout.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**
- * @file display_timeout.h
- *
- */
-/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
-
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
-
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef DISPLAY_TIMEOUT_H_
-#define DISPLAY_TIMEOUT_H_
-
-#include "gd32.h"
-
-namespace display {
-namespace timeout {
-
-void gpio_init() {
- gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT);
-}
-
-bool gpio_renew() {
- return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0;
-}
-
-} // namespace timeout
-} // namespace display
-
-#endif /* DISPLAY_TIMEOUT_H_ */
diff --git a/gd32_emac_e131_dmx_multi/include/software_version_id.h b/gd32_emac_e131_dmx_multi/include/software_version_id.h
new file mode 100644
index 00000000..f779988c
--- /dev/null
+++ b/gd32_emac_e131_dmx_multi/include/software_version_id.h
@@ -0,0 +1 @@
+constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1727116727;
diff --git a/gd32_emac_e131_dmx_multi/include/sofware_version_id.h b/gd32_emac_e131_dmx_multi/include/sofware_version_id.h
deleted file mode 100644
index a1dc23d5..00000000
--- a/gd32_emac_e131_dmx_multi/include/sofware_version_id.h
+++ /dev/null
@@ -1,2 +0,0 @@
-// Generated wo 18 okt 2023 16:04:08 CEST
-constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1697637848;
diff --git a/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp b/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp
index 971fc158..1741e5e2 100644
--- a/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp
+++ b/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp
@@ -28,7 +28,7 @@
#include "remoteconfig.h"
#include "configstore.h"
-#include "storenetwork.h"
+#include "networkstore.h"
namespace rdm {
namespace device {
@@ -37,7 +37,7 @@ namespace responder {
void factorydefaults() {
RemoteConfig::Get()->SetDisable(false);
ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE);
- StoreNetwork::Get()->SaveDhcp(true);
+ NetworkStore::SaveDhcp(true);
}
} // namespace responder
diff --git a/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp
index 5149f9a1..94271597 100644
--- a/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp
+++ b/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp
@@ -29,7 +29,7 @@
#include "rdmsoftwareversion.h"
#include "software_version.h"
-#include "sofware_version_id.h"
+#include "software_version_id.h"
const char *RDMSoftwareVersion::GetVersion() {
return SOFTWARE_VERSION;
diff --git a/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp b/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp
new file mode 100644
index 00000000..657929f1
--- /dev/null
+++ b/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp
@@ -0,0 +1,55 @@
+#if defined (NODE_SHOWFILE)
+/**
+ * @file showfileusb.cpp
+ *
+ */
+/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "showfile.h"
+
+#include "debug.h"
+
+namespace showfile {
+void usb_ready() {
+ DEBUG_ENTRY
+
+ ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent());
+
+ if (ShowFile::Get()->IsAutoStart()) {
+ ShowFile::Get()->Play();
+ } else {
+ ShowFile::Get()->LoadShows();
+ }
+
+ DEBUG_EXIT
+}
+
+void usb_disconnected() {
+ DEBUG_ENTRY
+
+ ShowFile::Get()->Stop();
+ ShowFile::Get()->UnloadShows();
+
+ DEBUG_EXIT
+}
+} // namespace showfile
+#endif
diff --git a/include/cstring b/include/cstring
index 998d93da..b32bea0f 100644
--- a/include/cstring
+++ b/include/cstring
@@ -2,7 +2,7 @@
* @file cstring
*
*/
-/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl
+/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,8 +26,37 @@
#ifndef CSTRING_
#define CSTRING_
-#ifdef __cplusplus
-# include
-#endif
+#include
+
+// Get rid of those macros defined in in lieu of real functions.
+#undef memcmp
+#undef memcpy
+#undef memmove
+#undef memset
+#undef strchr
+#undef strcmp
+#undef strcpy
+#undef strerror
+#undef strlen
+#undef strncmp
+#undef strncpy
+#undef strstr
+#undef strtok
+
+namespace std {
+using ::memcmp;
+using ::memcpy;
+using ::memmove;
+using ::memset;
+using ::strcmp;
+using ::strcpy;
+using ::strerror;
+using ::strlen;
+using ::strncmp;
+using ::strncpy;
+using ::strtok;
+using ::strchr;
+using ::strstr;
+}
#endif /* CSTRING_ */
diff --git a/include/dirent.h b/include/dirent.h
index 70e01606..772c3b96 100644
--- a/include/dirent.h
+++ b/include/dirent.h
@@ -2,7 +2,7 @@
* @file dirent.h
*
*/
-/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl
+/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -28,7 +28,7 @@
#include
-#if !defined (_FATFS)
+#if !defined (FF_DEFINED)
typedef void *DIR;
#endif
diff --git a/include/stdio.h b/include/stdio.h
index 364bf88c..86e47419 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -2,7 +2,7 @@
* @file stdio.h
*
*/
-/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl
+/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -28,10 +28,29 @@
#include
#include
-
-#define EOF -1
-
-typedef void *FILE;
+#include
+
+#define EOF (-1)
+
+typedef struct __sFILE {
+ void *udata;
+#define __SLBF 0x0001 /* line buffered */
+#define __SNBF 0x0002 /* unbuffered */
+#define __SRD 0x0004 /* OK to read */
+#define __SWR 0x0008 /* OK to write */
+ /* RD and WR are never simultaneously asserted */
+#define __SRW 0x0010 /* open for reading & writing */
+#define __SEOF 0x0020 /* found EOF */
+#define __SERR 0x0040 /* found error */
+ uint8_t flags;
+} FILE;
+
+#if defined(CONFIG_POSIX_ENABLE_STDIN)
+#error Not supported
+extern FILE *stdin;
+extern FILE *stdout;
+extern FILE *stderr;
+#endif
#ifndef SEEK_SET
#define SEEK_SET 0 /* set file offset to offset */
@@ -49,36 +68,40 @@ typedef void *FILE;
extern "C" {
#endif
-extern int puts(const char *s);
-extern int putchar(int c);
+int puts(const char *s);
+int putchar(int c);
+
+int fileno(FILE *stream);
-extern FILE *fopen(const char *path, const char *mode);
-extern int fclose(FILE *stream);
+FILE *fopen(const char *path, const char *mode);
+int fclose(FILE *stream);
-extern int fgetc(FILE *stream);
+int fgetc(FILE *stream);
+int fputc(int c, FILE *stream);
-extern char *fgets(char *s, int size, FILE *stream);
-extern int fputs(const char *s, FILE *stream);
+char *fgets(char *s, int size, FILE *stream);
+int fputs(const char *s, FILE *stream);
-extern size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream);
-extern size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream);
+size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream);
+size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream);
-extern int fseek(FILE *stream, long offset, int whence);
+int fseek(FILE *stream, long offset, int whence);
-extern long ftell(FILE *stream);
+long ftell(FILE *stream);
-extern void clearerr(FILE *stream);
-extern int ferror(FILE *stream);
+void clearerr(FILE *stream);
+int ferror(FILE *stream);
+int feof(FILE *stream);
-extern int printf(const char *format, ...);
+int printf(const char *format, ...);
-extern int sprintf(char *str, const char *format, ...);
-extern int snprintf(char *str, size_t size, const char *format, ...);
+int sprintf(char *str, const char *format, ...);
+int snprintf(char *str, size_t size, const char *format, ...);
-extern int vprintf(const char *format, va_list ap);
-extern int vsnprintf(char *str, size_t size, const char *format, va_list);
+int vprintf(const char *format, va_list ap);
+int vsnprintf(char *str, size_t size, const char *format, va_list);
-extern void perror(const char *s);
+void perror(const char *s);
#ifdef __cplusplus
}
diff --git a/include/string.h b/include/string.h
index fdbdbb41..9763a145 100644
--- a/include/string.h
+++ b/include/string.h
@@ -35,6 +35,7 @@ extern "C" {
extern char *strerror(int errnum);
extern char *strtok(char *str, const char *delim);
+extern char *strstr(const char *string, const char *substring);
inline int memcmp(const void *s1, const void *s2, size_t n) {
unsigned char u1, u2;
@@ -193,6 +194,20 @@ inline char *strcat(char *s1, const char *s2) {
return s1;
}
+inline char *strchr(const char *p, int ch) {
+ char c = (char) ch;
+
+ for (;; ++p) {
+ if (*p == c) {
+ return (char *)p;
+ }
+ if (*p == '\0') {
+ return NULL;
+ }
+ }
+ /* NOTREACHED */
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/include/time.h b/include/time.h
index d77b3b67..bee8d350 100644
--- a/include/time.h
+++ b/include/time.h
@@ -2,7 +2,7 @@
* @file time.h
*
*/
-/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl
+/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -61,6 +61,7 @@ extern "C" {
extern time_t time(time_t *t);
extern time_t mktime(struct tm *tm);
+extern struct tm *gmtime(const time_t *timep);
extern struct tm *localtime(const time_t *timep);
extern char *asctime(const struct tm *tm);
diff --git a/lib-artnet/.cproject b/lib-artnet/.cproject
index 874fc167..d4b400e5 100644
--- a/lib-artnet/.cproject
+++ b/lib-artnet/.cproject
@@ -28,7 +28,6 @@