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Adding Custom RR Graph Builder to OpenFPGA #3325

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@amin1377 amin1377 commented Oct 28, 2025

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amin1377 added 30 commits October 14, 2025 12:24
@amin1377
[cli] add crr cli parameters
76d8496
@amin1377
[setup_vpr] add structs for crrOpts
a1b7cc9
@amin1377
[utils] pass CRROpts to alloc_routing_structs
8f30644
@amin1377
[place] padd crropts to relevant funcitons in placement
f18cc17
@amin1377
[vpr][types] add t_crr_opts
81b4cc1
@amin1377
[vpr][base] pass CRROpts to relevant base functions
1500928
@amin1377
[vpr][route] pass crr_opts to relevant routing functions
4bb1fbd
@amin1377
[vpr][route] pass crr_opts to build_tileable_unidir_rr_graph
3b8da60
@amin1377
[libs][external] add openXLSX
5bdab0a
@amin1377
[cli] fix default values for crr params
b9f40e6
@amin1377
[vpr][route][tileable] call crr generator if sb_maps is not empty
664ca84
@amin1377
[libs][external] add OpenXLSX to external libs cmake
3f1518b
@amin1377
[vpr][route][rr_graph] include crr_graph_edge_builder in tileable rr …
c8c964e 
…graph builder
@amin1377
[vpr][route][crr] add df processor
b196045
@amin1377
[vpr][route][crr] add init impl for crr_graph_edge_builder
9a57b25
@amin1377
[vpr][cmake] add openXLSX
7fa8969
@amin1377
[vpr][route][rr_graph] fix warnings
e7bd77e
@amin1377
[libs][external] add yaml-cpp
1d16bf3
@amin1377
[cmake] add yaml-cpp to cmake files
afe9b9c
@amin1377
[crr][switch_block_manager] add header file
2f361fd
@amin1377
[vpr][route][crr] add pattern matcher
7ea7740
@amin1377
[vpr][route][crr][switch_block_manager] add missing libs
d2b81e6
@amin1377
[vpr][route][crr] rename pattern_match to crr_pattern_matcher
6a05626
@amin1377
[vpr][route][crr] add switch block mng impl
7343fce
@amin1377
[vpr][route][crr] add crr.h/cpp
7c03721
@amin1377
[vpr][route][crr] add crr_common.h
835f5e2
@amin1377
[vpr][route][crr] add xml_handler.h/cpp
d2619f8
@amin1377
[vpr][route][crr] fix compile problems with xml_handler
7f32380
@amin1377
[vpr][route][crr] add node_lookup_mng
d38f924
@amin1377
[vpr][route][crr] add crr thread pool
9164048
@amin1377
[vpr][route][crr] pass crr id when making crr connections
0415387
@amin1377
[lib][rr_graph] add crr_id to t_rr_edge_info
94b1a3b
@amin1377
[lib][rr_graph] pass crr_id to create_edge_in_cache
a5fcbc8
@amin1377
[lib][rr_graph] add edge_crr_id_ to rr_graph_storage
a9f1a43
@amin1377
[lib][rr_graph] fix crr_id
a758d0b
@amin1377
[lib][rr_graph] add crr_id to emplace_back_edge
9b8f934
@amin1377
[vpr][route][rr_graph] fix connection issue
4aaeb0f
@amin1377
[lib][rr_graph] add edge_crr_id methos
f35cde6
@amin1377
[lib][rr_graph][storage] add edge_crr_id
b2d8057
@amin1377
[cli] add sb_count_dir cli
915de4a
@amin1377
[lib][rr_graph] fix the bug with find_edges rr_graph_view
6c7365f
@amin1377
[vpr][base] add write_sb_count_stats to vpr analysis
ecec621
@amin1377
[vpr][base] add write_sb_count_stats to stats
4c0f2dd
@amin1377
[vpr][stats] add static funcs to read and trim csv files
6a6eed7
@amin1377
[vpr][base] write csv files in write_sb_count_stats
06a76d9
@amin1377
[temp][lib] revert capnp support
702c6c6
@amin1377
[temp][lib] revert capnp support
52e73fa
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
4b90bd0 
…rilog-to-routing into add_crr
@amin1377
[vpr][base] add static identifier for write_csv
5eedb46
@amin1377
make format
ac5e489
@amin1377
[vpr][base] fix size_t to int cast
1fa6dc2
@amin1377
[doc] add lan_and_tap figures
5f5a764
@amin1377
[doc] add crr doc
0fdc5f0
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
6dbd7cf 
…rilog-to-routing into add_crr
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
40f8216 
…rilog-to-routing into add_crr
@amin1377
[cli] update reg_strong golden
3c8705f
@amin1377
[cli] update odin golden
d7f3183
@amin1377
[vpr][route][crr] fix format
ee938f3
@amin1377 amin1377 changed the title [WIP] Adding Custom RR Graph Builder to OpenFPGA Adding Custom RR Graph Builder to OpenFPGA Dec 1, 2025
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docs Documentation external_libs infra Project Infrastructure lang-cpp C/C++ code lang-make CMake/Make code lang-perl Perl code lang-python Python code lang-shell Shell scripts (bash etc.) libarchfpga Library for handling FPGA Architecture descriptions VPR VPR FPGA Placement & Routing Tool

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@amin1377