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tinebptinebp
committed
xilinx asynchronous bram patch fixes
1 parent 8230b37 commit 320c090

9 files changed

+490
-257
lines changed

‎hw/rtl/VX_platform.vh

+3
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,7 @@ endgenerate
163163
`define USE_BLOCK_BRAM (* ramstyle = "block" *)
164164
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)
165165
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
166+
`define RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams on" *)
166167
`define DISABLE_BRAM (* ramstyle = "logic" *)
167168
`define PRESERVE_NET (* preserve *)
168169
`define BLACKBOX_CELL (* black_box *)
@@ -173,6 +174,7 @@ endgenerate
173174
`define USE_BLOCK_BRAM (* ram_style = "block" *)
174175
`define USE_FAST_BRAM (* ram_style = "distributed" *)
175176
`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
177+
`define RW_RAM_CHECK (* rw_addr_collision = "yes" *)
176178
`define DISABLE_BRAM (* ram_style = "registers" *)
177179
`define PRESERVE_NET (* keep = "true" *)
178180
`define BLACKBOX_CELL (* black_box *)
@@ -183,6 +185,7 @@ endgenerate
183185
`define USE_BLOCK_BRAM
184186
`define USE_FAST_BRAM
185187
`define NO_RW_RAM_CHECK
188+
`define RW_RAM_CHECK
186189
`define DISABLE_BRAM
187190
`define PRESERVE_NET
188191
`define BLACKBOX_CELL

‎hw/rtl/libs/VX_async_ram_patch.sv

+168-68
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,6 @@
1313

1414
`include "VX_platform.vh"
1515

16-
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
17-
if (wren[i]) begin \
18-
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
19-
end \
20-
end
21-
2216
`define RAM_INITIALIZATION \
2317
if (INIT_ENABLE != 0) begin : g_init \
2418
if (INIT_FILE != "") begin : g_file \
@@ -32,21 +26,102 @@
3226
end \
3327
end
3428

35-
`define RAM_BYPASS(__d) \
36-
reg [DATAW-1:0] bypass_data_r; \
37-
reg bypass_valid_r; \
29+
`define SYNC_RAM_WF_BLOCK(__d, __re, __we, __ra, __wa) \
30+
`RAM_ATTRIBUTES `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; \
31+
`RAM_INITIALIZATION \
32+
reg [ADDRW-1:0] raddr_r; \
33+
always @(posedge clk) begin \
34+
if (__re || __we) begin \
35+
if (__we) begin \
36+
ram[__wa] <= wdata; \
37+
end \
38+
raddr_r <= __ra; \
39+
end \
40+
end \
41+
assign __d = ram[raddr_r]
42+
43+
`define SYNC_RAM_WF_WREN_BLOCK(__d, __re, __we, __ra, __wa) \
44+
`RAM_ATTRIBUTES `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; \
45+
`RAM_INITIALIZATION \
46+
reg [ADDRW-1:0] raddr_r; \
3847
always @(posedge clk) begin \
39-
bypass_valid_r <= read_s && write && (raddr_s == waddr); \
40-
bypass_data_r <= wdata; \
48+
if (__re || __we) begin \
49+
if (__we) begin \
50+
for (integer i = 0; i < WRENW; ++i) begin \
51+
if (wren[i]) begin \
52+
ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
53+
end \
54+
end \
55+
end \
56+
raddr_r <= __ra; \
57+
end \
4158
end \
42-
assign __d = bypass_valid_r ? bypass_data_r : rdata_r
59+
assign __d = ram[raddr_r]
60+
61+
`define SYNC_RAM_RF_BLOCK(__d, __re, __we, __ra, __wa) \
62+
`RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \
63+
`RAM_INITIALIZATION \
64+
reg [DATAW-1:0] rdata_r; \
65+
always @(posedge clk) begin \
66+
if (__re || __we) begin \
67+
if (__we) begin \
68+
ram[__wa] <= wdata; \
69+
end \
70+
rdata_r <= ram[__ra]; \
71+
end \
72+
end \
73+
assign __d = rdata_r
74+
75+
`define SYNC_RAM_RF_WREN_BLOCK(__d, __re, __we, __ra, __wa) \
76+
`RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \
77+
`RAM_INITIALIZATION \
78+
reg [DATAW-1:0] rdata_r; \
79+
always @(posedge clk) begin \
80+
if (__re || __we) begin \
81+
if (__we) begin \
82+
for (integer i = 0; i < WRENW; ++i) begin \
83+
if (wren[i]) begin \
84+
ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
85+
end \
86+
end \
87+
end \
88+
rdata_r <= ram[__ra]; \
89+
end \
90+
end \
91+
assign __d = rdata_r
92+
93+
`define ASYNC_RAM_BLOCK(__d, __we, __ra, __wa) \
94+
`RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \
95+
`RAM_INITIALIZATION \
96+
always @(posedge clk) begin \
97+
if (__we) begin \
98+
ram[__wa] <= wdata; \
99+
end \
100+
end \
101+
assign __d = ram[__ra]
102+
103+
`define ASYNC_RAM_BLOCK_WREN(__d, __we, __ra, __wa) \
104+
`RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \
105+
`RAM_INITIALIZATION \
106+
always @(posedge clk) begin \
107+
if (__we) begin \
108+
for (integer i = 0; i < WRENW; ++i) begin \
109+
if (wren[i]) begin \
110+
ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
111+
end \
112+
end \
113+
end \
114+
end \
115+
assign __d = ram[__ra]
43116

44117
`TRACING_OFF
45118
module VX_async_ram_patch #(
46119
parameter DATAW = 1,
47120
parameter SIZE = 1,
48121
parameter WRENW = 1,
49122
parameter DUAL_PORT = 0,
123+
parameter FORCE_BRAM = 0,
124+
parameter WRITE_FIRST = 0,
50125
parameter INIT_ENABLE = 0,
51126
parameter INIT_FILE = "",
52127
parameter [DATAW-1:0] INIT_VALUE = 0,
@@ -79,77 +154,102 @@ module VX_async_ram_patch #(
79154
.out ({raddr_s, read_s, is_raddr_reg})
80155
);
81156

82-
// synchroneous ram
83-
84-
wire [DATAW-1:0] rdata_s;
157+
wire [DATAW-1:0] rdata_s, rdata_a;
85158

86-
if (WRENW != 1) begin : g_wren_sync_ram
87-
`USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
88-
reg [DATAW-1:0] rdata_r;
89-
`RAM_INITIALIZATION
90-
always @(posedge clk) begin
91-
if (read_s || write) begin
92-
if (write) begin
93-
`RAM_WRITE_WREN
159+
if (1) begin : g_sync_ram
160+
if (WRENW != 1) begin : g_wren
161+
if (FORCE_BRAM) begin : g_bram
162+
if (WRITE_FIRST) begin : g_write_first
163+
`define RAM_ATTRIBUTES `USE_BLOCK_BRAM
164+
`SYNC_RAM_WF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
165+
`undef RAM_ATTRIBUTES
166+
end else begin : g_read_first
167+
`define RAM_ATTRIBUTES `USE_BLOCK_BRAM
168+
`SYNC_RAM_RF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
169+
`undef RAM_ATTRIBUTES
170+
end
171+
end else begin : g_lutram
172+
if (WRITE_FIRST) begin : g_write_first
173+
`define RAM_ATTRIBUTES
174+
`SYNC_RAM_WF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
175+
`undef RAM_ATTRIBUTES
176+
end else begin : g_read_first
177+
`define RAM_ATTRIBUTES
178+
`SYNC_RAM_RF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
179+
`undef RAM_ATTRIBUTES
94180
end
95-
rdata_r <= ram[raddr_s];
96181
end
97-
end
98-
`RAM_BYPASS(rdata_s);
99-
end else begin : g_no_wren_sync_ram
100-
`USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
101-
reg [DATAW-1:0] rdata_r;
102-
`RAM_INITIALIZATION
103-
`UNUSED_VAR (wren)
104-
always @(posedge clk) begin
105-
if (read_s || write) begin
106-
if (write) begin
107-
ram[waddr] <= wdata;
182+
end else begin : g_no_wren
183+
if (FORCE_BRAM) begin : g_bram
184+
if (WRITE_FIRST) begin : g_write_first
185+
`define RAM_ATTRIBUTES `USE_BLOCK_BRAM
186+
`SYNC_RAM_WF_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
187+
`undef RAM_ATTRIBUTES
188+
end else begin : g_read_first
189+
`define RAM_ATTRIBUTES `USE_BLOCK_BRAM
190+
`SYNC_RAM_RF_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
191+
`undef RAM_ATTRIBUTES
192+
end
193+
end else begin : g_lutram
194+
if (WRITE_FIRST) begin : g_write_first
195+
`define RAM_ATTRIBUTES
196+
`SYNC_RAM_WF_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
197+
`undef RAM_ATTRIBUTES
198+
end else begin : g_read_first
199+
`define RAM_ATTRIBUTES
200+
`SYNC_RAM_RF_BLOCK(rdata_s, read_s, write, raddr_s, waddr);
201+
`undef RAM_ATTRIBUTES
108202
end
109-
rdata_r <= ram[raddr_s];
110203
end
111204
end
112-
`RAM_BYPASS(rdata_s);
113205
end
114206

115-
// asynchronous ram (fallback)
116-
117-
wire [DATAW-1:0] rdata_a;
118-
119-
if (DUAL_PORT != 0) begin : g_dp_async_ram
120-
reg [DATAW-1:0] ram [0:SIZE-1];
121-
`RAM_INITIALIZATION
122-
if (WRENW != 1) begin : g_wren
123-
always @(posedge clk) begin
124-
if (write) begin
125-
`RAM_WRITE_WREN
207+
if (1) begin : g_async_ram
208+
if (DUAL_PORT != 0) begin : g_dp
209+
if (WRENW != 1) begin : g_wren
210+
if (WRITE_FIRST) begin : g_write_first
211+
`define RAM_ATTRIBUTES `RW_RAM_CHECK
212+
`ASYNC_RAM_BLOCK_WREN(rdata_a, write, raddr, waddr);
213+
`undef RAM_ATTRIBUTES
214+
end else begin : g_read_first
215+
`define RAM_ATTRIBUTES `NO_RW_RAM_CHECK
216+
`ASYNC_RAM_BLOCK_WREN(rdata_a, write, raddr, waddr);
217+
`undef RAM_ATTRIBUTES
126218
end
127-
end
128-
end else begin : g_no_wren
129-
always @(posedge clk) begin
130-
if (write) begin
131-
ram[waddr] <= wdata;
219+
end else begin : g_no_wren
220+
if (WRITE_FIRST) begin : g_write_first
221+
`define RAM_ATTRIBUTES `RW_RAM_CHECK
222+
`ASYNC_RAM_BLOCK(rdata_a, write, raddr, waddr);
223+
`undef RAM_ATTRIBUTES
224+
end else begin : g_read_first
225+
`define RAM_ATTRIBUTES `NO_RW_RAM_CHECK
226+
`ASYNC_RAM_BLOCK(rdata_a, write, raddr, waddr);
227+
`undef RAM_ATTRIBUTES
132228
end
133229
end
134-
end
135-
assign rdata_a = ram[raddr];
136-
end else begin : g_sp_async_ram
137-
reg [DATAW-1:0] ram [0:SIZE-1];
138-
`RAM_INITIALIZATION
139-
if (WRENW != 1) begin : g_wren
140-
always @(posedge clk) begin
141-
if (write) begin
142-
`RAM_WRITE_WREN
230+
end else begin : g_sp
231+
if (WRENW != 1) begin : g_wren
232+
if (WRITE_FIRST) begin : g_write_first
233+
`define RAM_ATTRIBUTES `RW_RAM_CHECK
234+
`ASYNC_RAM_BLOCK_WREN(rdata_a, write, waddr, waddr);
235+
`undef RAM_ATTRIBUTES
236+
end else begin : g_read_first
237+
`define RAM_ATTRIBUTES `NO_RW_RAM_CHECK
238+
`ASYNC_RAM_BLOCK_WREN(rdata_a, write, waddr, waddr);
239+
`undef RAM_ATTRIBUTES
143240
end
144-
end
145-
end else begin : g_no_wren
146-
always @(posedge clk) begin
147-
if (write) begin
148-
ram[waddr] <= wdata;
241+
end else begin : g_no_wren
242+
if (WRITE_FIRST) begin : g_write_first
243+
`define RAM_ATTRIBUTES `RW_RAM_CHECK
244+
`ASYNC_RAM_BLOCK(rdata_a, write, waddr, waddr);
245+
`undef RAM_ATTRIBUTES
246+
end else begin : g_read_first
247+
`define RAM_ATTRIBUTES `NO_RW_RAM_CHECK
248+
`ASYNC_RAM_BLOCK(rdata_a, write, waddr, waddr);
249+
`undef RAM_ATTRIBUTES
149250
end
150251
end
151252
end
152-
assign rdata_a = ram[waddr];
153253
end
154254

155255
assign rdata = is_raddr_reg ? rdata_s : rdata_a;

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