Skip to content

Commit 4947eb5

Browse files
tinebptinebp
committed
bug fixes
1 parent 9f2c5ff commit 4947eb5

File tree

5 files changed

+41
-23
lines changed

5 files changed

+41
-23
lines changed

‎ci/regression.sh.in

+6
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,12 @@ config1()
221221
CONFIGS="-DISSUE_WIDTH=2" ./ci/blackbox.sh --driver=simx --app=diverge
222222
CONFIGS="-DISSUE_WIDTH=4" ./ci/blackbox.sh --driver=simx --app=diverge
223223

224+
# simd width
225+
CONFIGS="-DSIMD_WIDTH=1" ./ci/blackbox.sh --driver=rtlsim --app=dogfood --args="-ttrig"
226+
CONFIGS="-DSIMD_WIDTH=2" ./ci/blackbox.sh --driver=rtlsim --app=dogfood --args="-ttrig"
227+
CONFIGS="-DSIMD_WIDTH=1" ./ci/blackbox.sh --driver=simx --app=dogfood --args="-ttrig"
228+
CONFIGS="-DSIMD_WIDTH=2" ./ci/blackbox.sh --driver=simx --app=dogfood --args="-ttrig"
229+
224230
# ALU scaling
225231
CONFIGS="-DISSUE_WIDTH=2 -DNUM_ALU_BLOCK=1 -DNUM_ALU_LANES=2" ./ci/blackbox.sh --driver=rtlsim --app=diverge
226232
CONFIGS="-DISSUE_WIDTH=4 -DNUM_ALU_BLOCK=4 -DNUM_ALU_LANES=4" ./ci/blackbox.sh --driver=rtlsim --app=diverge

‎hw/rtl/VX_config.vh

+1-1
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,7 @@
332332
// Pipeline Configuration /////////////////////////////////////////////////////
333333

334334
`ifndef SIMD_WIDTH
335-
`define SIMD_WIDTH `MIN(`NUM_THREADS, 2)
335+
`define SIMD_WIDTH `MIN(`NUM_THREADS, 16)
336336
`endif
337337

338338
// Issue width

‎hw/rtl/core/VX_operands.sv

+1
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ module VX_operands import VX_gpu_pkg::*; #(
115115
end
116116

117117
reg [NUM_REGS-1:0] opc_pending_regs;
118+
118119
VX_reduce_tree #(
119120
.DATAW_IN (NUM_REGS),
120121
.N (`NUM_OPCS),

‎hw/rtl/mem/VX_lsu_mem_arb.sv

+16-10
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ module VX_lsu_mem_arb import VX_gpu_pkg::*; #(
3838
localparam REQ_DATAW = 1 + NUM_LANES * (1 + ADDR_WIDTH + DATA_WIDTH + DATA_SIZE + FLAGS_WIDTH) + TAG_WIDTH;
3939
localparam RSP_DATAW = NUM_LANES * (1 + DATA_WIDTH) + TAG_WIDTH;
4040

41-
`STATIC_ASSERT ((NUM_INPUTS >= NUM_OUTPUTS), ("invalid parameter: NUM_INPUTS=%0d, NUM_OUTPUTS=%0d", NUM_INPUTS, NUM_OUTPUTS));
41+
//`STATIC_ASSERT ((NUM_INPUTS >= NUM_OUTPUTS), ("invalid parameter: NUM_INPUTS=%0d, NUM_OUTPUTS=%0d", NUM_INPUTS, NUM_OUTPUTS));
4242

4343
wire [NUM_OUTPUTS-1:0] req_valid_out;
4444
wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out;
@@ -75,15 +75,6 @@ module VX_lsu_mem_arb import VX_gpu_pkg::*; #(
7575

7676
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_bus_out_if
7777
wire [TAG_WIDTH-1:0] req_tag_out;
78-
VX_bits_insert #(
79-
.N (TAG_WIDTH),
80-
.S (LOG_NUM_REQS),
81-
.POS (TAG_SEL_IDX)
82-
) bits_insert (
83-
.data_in (req_tag_out),
84-
.ins_in (req_sel_out[i]),
85-
.data_out (bus_out_if[i].req_data.tag)
86-
);
8778
assign bus_out_if[i].req_valid = req_valid_out[i];
8879
assign {
8980
bus_out_if[i].req_data.mask,
@@ -95,6 +86,21 @@ module VX_lsu_mem_arb import VX_gpu_pkg::*; #(
9586
req_tag_out
9687
} = req_data_out[i];
9788
assign req_ready_out[i] = bus_out_if[i].req_ready;
89+
90+
if (NUM_INPUTS > NUM_OUTPUTS) begin : g_req_tag_sel_out
91+
VX_bits_insert #(
92+
.N (TAG_WIDTH),
93+
.S (LOG_NUM_REQS),
94+
.POS (TAG_SEL_IDX)
95+
) bits_insert (
96+
.data_in (req_tag_out),
97+
.ins_in (req_sel_out[i]),
98+
.data_out (bus_out_if[i].req_data.tag)
99+
);
100+
end else begin : g_req_tag_out
101+
`UNUSED_VAR (req_sel_out)
102+
assign bus_out_if[i].req_data.tag = req_tag_out;
103+
end
98104
end
99105

100106
///////////////////////////////////////////////////////////////////////////

‎hw/rtl/mem/VX_mem_arb.sv

+17-12
Original file line numberDiff line numberDiff line change
@@ -36,16 +36,15 @@ module VX_mem_arb import VX_gpu_pkg::*; #(
3636
localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS);
3737
localparam REQ_DATAW = 1 + ADDR_WIDTH + DATA_WIDTH + DATA_SIZE + FLAGS_WIDTH + TAG_WIDTH;
3838
localparam RSP_DATAW = DATA_WIDTH + TAG_WIDTH;
39-
40-
`STATIC_ASSERT ((NUM_INPUTS >= NUM_OUTPUTS), ("invalid parameter: NUM_INPUTS=%0d, NUM_OUTPUTS=%0d", NUM_INPUTS, NUM_OUTPUTS));
39+
localparam SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS);
4140

4241
wire [NUM_INPUTS-1:0] req_valid_in;
4342
wire [NUM_INPUTS-1:0][REQ_DATAW-1:0] req_data_in;
4443
wire [NUM_INPUTS-1:0] req_ready_in;
4544

4645
wire [NUM_OUTPUTS-1:0] req_valid_out;
4746
wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out;
48-
wire [NUM_OUTPUTS-1:0][`UP(LOG_NUM_REQS)-1:0] req_sel_out;
47+
wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] req_sel_out;
4948
wire [NUM_OUTPUTS-1:0] req_ready_out;
5049

5150
for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_req_data_in
@@ -74,15 +73,6 @@ module VX_mem_arb import VX_gpu_pkg::*; #(
7473

7574
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_bus_out_if
7675
wire [TAG_WIDTH-1:0] req_tag_out;
77-
VX_bits_insert #(
78-
.N (TAG_WIDTH),
79-
.S (LOG_NUM_REQS),
80-
.POS (TAG_SEL_IDX)
81-
) bits_insert (
82-
.data_in (req_tag_out),
83-
.ins_in (req_sel_out[i]),
84-
.data_out (bus_out_if[i].req_data.tag)
85-
);
8676
assign bus_out_if[i].req_valid = req_valid_out[i];
8777
assign {
8878
bus_out_if[i].req_data.rw,
@@ -93,6 +83,21 @@ module VX_mem_arb import VX_gpu_pkg::*; #(
9383
req_tag_out
9484
} = req_data_out[i];
9585
assign req_ready_out[i] = bus_out_if[i].req_ready;
86+
87+
if (NUM_INPUTS > NUM_OUTPUTS) begin : g_req_tag_sel_out
88+
VX_bits_insert #(
89+
.N (TAG_WIDTH),
90+
.S (LOG_NUM_REQS),
91+
.POS (TAG_SEL_IDX)
92+
) bits_insert (
93+
.data_in (req_tag_out),
94+
.ins_in (req_sel_out[i]),
95+
.data_out (bus_out_if[i].req_data.tag)
96+
);
97+
end else begin : g_req_tag_out
98+
`UNUSED_VAR (req_sel_out)
99+
assign bus_out_if[i].req_data.tag = req_tag_out;
100+
end
96101
end
97102

98103
///////////////////////////////////////////////////////////////////////////

0 commit comments

Comments
 (0)