minor update

tinebp · tinebp · commit aa6a47eb1195 · 2024-12-05T23:35:15.000-08:00
diff --git a/sim/simx/execute_v.cpp b/sim/simx/execute_v.cpp
@@ -2438,9 +2438,9 @@ void Emulator::loadVector(const Instr &instr, uint32_t wid, std::vector<reg_data
         std::abort();
       }
       DP(4, "Whole vector register load with nreg: " << nreg);
-      uint32_t vsew_bits = 1 << (3 + instr.getVsew());
+      uint32_t stride = 1 << instr.getVsew();
+      uint32_t vsew_bits = stride * 8;
       uint32_t vl = nreg * VLEN / vsew_bits;
-      WordI stride = instr.getVsew();
       vector_op_vix_load(warp.vreg_file, this, rsdata[0][0].i, rdest, vsew_bits, vl, false, stride, 1, 0, vmask);
       break;
     }

Original file line number	Diff line number	Diff line change
`@@ -2438,9 +2438,9 @@ void Emulator::loadVector(const Instr &instr, uint32_t wid, std::vector<reg_data`
`2438`	`2438`	`std::abort();`
`2439`	`2439`	`}`
`2440`	`2440`	`DP(4, "Whole vector register load with nreg: " << nreg);`
`2441`		`- uint32_t vsew_bits = 1 << (3 + instr.getVsew());`
	`2441`	`+ uint32_t stride = 1 << instr.getVsew();`
	`2442`	`+ uint32_t vsew_bits = stride * 8;`
`2442`	`2443`	`uint32_t vl = nreg * VLEN / vsew_bits;`
`2443`		`- WordI stride = instr.getVsew();`
`2444`	`2444`	`vector_op_vix_load(warp.vreg_file, this, rsdata[0][0].i, rdest, vsew_bits, vl, false, stride, 1, 0, vmask);`
`2445`	`2445`	`break;`
`2446`	`2446`	`}`