Vicuna + Ibex and WFI

[stevobailey]

vicuna/rtl/vproc_top.sv

Line 221 in bda3511

assign vcore_xif.result_ready = 1'b1;

If I issue a WFI instruction while Vicuna has outstanding work, even pending stores, then Ibex will go to sleep and gate its clock (see here). But Vicuna will continue to process its instructions. What happens when it finishes an instruction and tries to send a response to Ibex? Since result_ready is tied to 1, Vicuna will think Ibex has received the result, but since Ibex's clock is off, it won't actually receive the response.

There's a couple issues here, I think:

1. Vicuna has no architectural clock gate, so power can be high when it is idle.
2. Ibex does not wait for all Vicuna instructions to finish when handling a WFI or FENCE instruction.