Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core

[Nikhil-311293]

Hello @michael-platzer and vicuna community,

I am trying to run the demo version of vicuna using cv32e40x as a scalar core. While generating the bitstream (Genesys2 Target) for the same I am getting following errors. I've followed the exact same process as mentioned in the demo/ and sw/ repositories.

Attaching the top module combinations as below

Your feedback will be really appreciated. Thank you.

[1095604926]

Hello, have you solved this problem yet.

[1095604926]

Hello @michael-platzer and vicuna community,

I am trying to run the demo version of vicuna using cv32e40x as a scalar core. While generating the bitstream (Genesys2 Target) for the same I am getting following errors. I've followed the exact same process as mentioned in the demo/ and sw/ repositories.

Attaching the top module combinations as below

Your feedback will be really appreciated. Thank you.

@Nikhil-311293 Hello, have you solved this problem yet.

[Nikhil-311293]

@1095604926 Yes.
You can add the following constraint(s) in the .xdc file:

set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets vproc/core/ex_stage_i/rf_wdata_wb[0]]
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets vproc/core/if_stage_i/dec_buf_valid_q_i_5]

Either one shall work (both constraints are not needed). Mind you this is just a workaround and not the ultimate solution.

[1095604926]

Thanks for the help, this does generate the bitstream.