Applications hang indefinitely on Verilator when size of data cache is different than 0

[maheshejs]

I'm running some applications with these configurations
make -f ../sim/Makefile ICACHE_SZ=16384 ICACHE_LINE_W=128 DCACHE_SZ=16384 DCACHE_LINE_W=128 CORE=cv32e40x TARGET_TECH=fpga VMEM_W=32 VREG_W=1024 VPORT_POLICY=many VPROC_CONFIG=compact
Verilator is running fine when DCACHE_SZ is set 0. However, it's hanging indefinitely when it is set to any other value.

[PhilippvK]

I experience the same kind of issues. As soon as I use non-default configs (especially for the caches) the verilator simulations do not terminate.