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start.S
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/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "../../autoconf.h"
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define SDRAM_CFG0_REG RALINK_MEMCTRL_BASE+ 0x0
#define SDRAM_CFG1_REG RALINK_MEMCTRL_BASE+ 0x4
#else
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define RALINK_DDR_CFG0 (RALINK_MEMCTRL_BASE+0x40)
#define RALINK_DDR_CFG1 (RALINK_MEMCTRL_BASE+0x44)
#define RALINK_DDR_CFG2 (RALINK_MEMCTRL_BASE+0x48)
#define RALINK_DDR_CFG3 (RALINK_MEMCTRL_BASE+0x4c)
#define RALINK_DDR_CFG4 (RALINK_MEMCTRL_BASE+0x50)
#define RALINK_DDR_CFG8 (RALINK_MEMCTRL_BASE+0x60)
#define RALINK_DDR_CFG9 (RALINK_MEMCTRL_BASE+0x64)
#define RALINK_DDR_CFG10 (RALINK_MEMCTRL_BASE+0x68)
#endif
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
#define SDRAM_CFG0_MIPSREG s7
#define SDRAM_CFG1_MIPSREG s8
#define DDR_CFG0_MIPSREG s7
#define DDR_CFG1_MIPSREG s8
#endif
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define DELAY_USEC(us) ((700*(us))/3)
#elif defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD)
#define DELAY_USEC(us) ((60*(us))/4)
#elif defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
#define DELAY_USEC(us) ((58*(us))/3)
#else
#define DELAY_USEC(us) ((500*(us))/3)
#endif
#if defined(MT7628_ASIC_BOARD)
#if defined(ON_BOARD_DDR2)
#define MT7628_LDO_1P8V 1
#elif defined(ON_BOARD_DDR1) && defined(ON_BOARD_64M_DRAM_COMPONENT)
#define MT7628_LDO_1P8V 1
#else
#define MT7628_LDO_2P5V 1
#endif
#endif
#define CPLL_DEFAULT_CFG 0x507
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \
defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \
defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
defined (MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD) || \
defined (MT7628_FPGA_BOARD) || defined (MT7628_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
#if defined (MT7628_ASIC_BOARD)
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
li t0, RALINK_SYSCTL_BASE + 0x34
lw t1, 0(t0)
ori t1, t1, 1<<10
// t1, 0x04000400
sw t1, 0(t0)
#endif
#endif
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#if 0 //MTK: 64K I$->32K I$
mfc0 t0, CP0_CONFIG
or t0,(1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,1
move t1 ,t0
and t0,~(0x7 << 22)
or t0,(2 <<22)
mtc0 t0, CP0_CONFIG,1
nop
mfc0 t0, CP0_CONFIG
and t0,~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
#endif
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
15:
#endif
#if defined(RT3350_ASIC_BOARD)
// force SDRAM_MD_DRV and SDRAM_MA_DRV from 8mA --> 4mA
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (3 << 4)
sw t1, 0(t0)
nop
#endif
#if defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
la t0, RALINK_SYSCTL_BASE + 0x8C
lw t1, 0(t0)
nop
srl t2, t1, 24+1
andi t2, t2, 0x1
bnez t2, 1f
nop
bal rt6855A_cpu_pll
nop
1:
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
ori t1, t1, 1<<8
sw t1, 0(t0)
nop
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
li t2, ~(1<<8)
and t1, t1, t2
sw t1, 0(t0)
nop
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
#if defined(MT7620_ASIC_BOARD) || defined(MT7620_FPGA_BOARD)
/* warm reset will skip CPU PLL CONFIG */
la t0, RALINK_SYSCTL_BASE+0x38
lw t1, 0(t0)
srl t1, t1, 1
andi t1, t1, 0x3
bnez t1, CPLL_DONE
nop
#if defined(CPLL_FROM_480MHZ)
li a0, 1<<11
#elif defined(CPLL_FROM_XTAL)
li a0, 1<<12
#elif defined(CPLL_FROM_CONF)
li a0, CPLL_MULTI_RATIO_CFG
sll a0, a0, 2
ori a0, a0, CPLL_DIV_RATIO_CFG
sll a0, a0, 6
ori a0, a0, CPLL_SSC_CFG
#endif
#if (defined(CPLL_FROM_480MHZ)||defined(CPLL_FROM_XTAL)||defined(CPLL_FROM_CONF))
bal init_cpu_pll
nop
#else
la t0, RALINK_SYSCTL_BASE+0x10
lw t1, 0(t0)
srl t1, t1, 4
andi t1, t1, 0x3
beqz t1, CPLL_DONE
addiu t2, zero, 3
beq t1, t2, CPLL_DONE
li a0, CPLL_DEFAULT_CFG
bal init_cpu_pll
nop
#endif
CPLL_DONE:
#endif
#if defined(MT7628_ASIC_BOARD) || defined(MT7628_FPGA_BOARD)
/* polling CPLL is ready */
li t1, DELAY_USEC(1000000)
la t5, RALINK_SYSCTL_BASE+0x28
1:
lw t2, 0(t5)
andi t2, t2, 0x1
bnez t2, CPLL_READY
subu t1, t1, 1
bgtz t1, 1b
nop
la t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
ori t3, t3, 0x1
sw t3, 0(t0)
j CPLL_DONE
nop
CPLL_READY:
la t0, RALINK_SYSCTL_BASE+0x2c
lw t1, 0(t0)
li t2, ~0x0C
and t1, t1, t2
ori t1, t1, 0xC
sw t1, 0(t0)
#if defined(CPUCLK_FROM_BPLL)
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0x0F<<0))
and t3, t3, t5
li t5, (10<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
la t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xE
sw t3, 0(t0)
lw t3, 0(t0)
ori t3, t3, 0x08
sw t3, 0(t0)
#elif defined(CPUCLK_FROM_XTAL)
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0xF<<0))
and t3, t3, t5
li t5, (1<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
lw t3, 0(t0)
li t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xD
sw t3, 0(t0)
#else
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0x0F<<0))
and t3, t3, t5
li t5, (10<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
la t0, RALINK_SYSCTL_BASE+0x2C
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xC
sw t3, 0(t0)
lw t3, 0(t0)
ori t3, t3, 0x08
sw t3, 0(t0)
#endif
CPLL_DONE:
#endif
/* SDR and DDR initialization: delay 200us
*/
li t0, DELAY_USEC(200+40)
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) || \
defined(MT7620_FPGA_BOARD)||defined(MT7620_ASIC_BOARD)
/* Use default SYSCFG1 setting */
#if defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x0FFF<<16)
or t2, (0x260<<16)
sw t2, 0(t1)
nop
#endif
#elif defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
/* set DRAM IO PAD for DDR2 */
#if defined(ON_BOARD_DDR2)
#if 0
la t0, RALINK_SYSCTL_BASE + 0x4
lw t1, 0(t0)
li t2, 1<<23
or t1, t1, t2
sw t1, 0(t0)
nop
#endif
/*ODT ON*/
#if 1
la t0, RALINK_SYSCTL_BASE + 0x4
lw t1, 0(t0)
li t1, 0x000cc0d4
sw t1, 0(t0)
nop
#endif
#endif /* defined(ON_BOARD_DDR2) */
#elif defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
/* set DRAM IO PAD for MT7628IC */
/* DDR LDO Enable */
li t1, RALINK_RGCTRL_BASE+0x100
lw t4, 0(t1)
li t2, (1<<31)
or t4, t4, t2
sw t4, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x10c
lw t4, 0(t1)
#if defined (MT7628_LDO_1P8V)
j LDO_1P8V
nop
#elif defined (MT7628_LDO_2P5V)
j LDO_2P5V
nop
#else
li t1, RALINK_SYSCTL_BASE+0xC
lw t2, 0(t1)
srl t2, t2, 16
andi t2, t2, 0x1
beqz t2, LDO_1P8V /* KN */
li t1, RALINK_SYSCTL_BASE+0x10
lw t3, 0(t1)
andi t3, t3, 0x1
bnez t3, LDO_2P5V
#endif
LDO_1P8V:
li t2, ~(1<<6)
and t4, t4, t2
li t1, RALINK_RGCTRL_BASE+0x10c
sw t4, 0(t1)
j DDRLDO_SOFT_START
LDO_2P5V:
/* suppose external DDR1 LDO 2.5V */
li t2, 1<<6
or t4, t4, t2
li t1, RALINK_RGCTRL_BASE+0x10c
sw t4, 0(t1)
DDRLDO_SOFT_START:
li t1, RALINK_RGCTRL_BASE+0x10c
lw t2, 0(t1)
li t3, 1<<16
or t2, t2, t3
sw t2, 0(t1)
li t3, DELAY_USEC(250*50)
LDO_DELAY:
subu t3, t3, 1
bnez t3, LDO_DELAY
nop
li t1, RALINK_RGCTRL_BASE+0x10c
lw t2, 0(t1)
li t3, 1<<18
or t2, t2, t3
sw t2, 0(t1)
SET_RG_BUCK_FPWM:
li t1, RALINK_RGCTRL_BASE+0x104
lw t2, 0(t1)
ori t2, t2, 1<<10
sw t2, 0(t1)
DDR_PAD_CFG:
/* clean CLK PAD */
li t1, RALINK_RGCTRL_BASE+0x704
lw t2, 0(t1)
li t8, 0xFFFFF0F0
and t2, t2, t8
/* clean CMD PAD */
li t1, RALINK_RGCTRL_BASE+0x70c
lw t3, 0(t1)
li t8, 0xFFFFF0F0
and t3, t3, t8
/* clean DQ IPAD */
li t1, RALINK_RGCTRL_BASE+0x710
lw t4, 0(t1)
li t8, 0xFFFFF8FF
and t4, t4, t8
/* clean DQ OPAD */
li t1, RALINK_RGCTRL_BASE+0x714
lw t5, 0(t1)
li t8, 0xFFFFF0F0
and t5, t5, t8
/* clean DQS IPAD */
li t1, RALINK_RGCTRL_BASE+0x718
lw t6, 0(t1)
li t8, 0xFFFFF8FF
and t6, t6, t8
/* clean DQS OPAD */
li t1, RALINK_RGCTRL_BASE+0x71c
lw t7, 0(t1)
li t8, 0xFFFFF0F0
and t7, t7, t8
li t1, RALINK_SYSCTL_BASE+0xC
lw t9, 0(t1)
srl t9, t9, 16
andi t9, t9, 0x1
bnez t9, MT7628_AN_DDR1_PAD
MT7628_KN_PAD:
li t8, 0x00000303
or t2, t2, t8
or t3, t3, t8
or t5, t5, t8
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR1_PAD:
li t1, RALINK_SYSCTL_BASE+0x10
lw t1, 0(t1)
andi t1, t1, 0x1
beqz t1, MT7628_AN_DDR2_PAD
li t8, 0x00000C0C
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000707
or t5, t5, t8
li t8, 0x00000C0C
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR2_PAD:
li t8, 0x00000C0C
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000404
or t5, t5, t8
li t8, 0x00000C0C
or t7, t7, t8
//li t8, 0x00000200
li t8, 0x00000000 //ODT off
or t4, t4, t8
or t6, t6, t8
SET_PAD_CFG:
li t1, RALINK_RGCTRL_BASE+0x704
sw t2, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x70c
sw t3, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x710
sw t4, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x714
sw t5, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x718
sw t6, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x71c
sw t7, 0(t1)
#else
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
/* DDR initialization: reset pin to 0
*/
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE + 0x40
#else
li t1, RALINK_SYSCTL_BASE + 0x34
lw t2, 0(t1)
and t2, ~(0x1<<10)
#endif
sw t2, 0(t1)
nop
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, DELAY_USEC(200+40)
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#endif
/* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, RALINK_MEMCTRL_BASE + 0x44 //DDR_CFG1
lw t0, 0(t1)
nop
and t2, t0, (1<<21)
beqz t2, DDR_READY
nop
/* DDR initialization:
*/
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) || \
defined(MT7620_FPGA_BOARD)||defined(MT7620_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD)||defined(MT7628_ASIC_BOARD)
/* fpga/asic: reg DDR_CFG2 -- set bit[30]=0 as DDR1 mode when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[30]=1 as DDR2 mode when DDR2
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b011 when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b100 when DDR2
*/
li t1, RALINK_MEMCTRL_BASE + 0x48 //DDR_CFG2
lw t0, 0(t1)
nop
and t0, ~(1<<30)
#if ON_BOARD_DDR2
and t0, ~(7<<4)
or t0, (4<<4)
or t0, (1<<30)
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
or t0, (1<<11)
#endif
#elif ON_BOARD_DDR1
and t0, ~(7<<4)
or t0, (3<<4)
#endif
#if defined(MT7628_FPGA_BOARD)
li t0, 0x28000033
#endif
sw t0, 0(t1)
nop