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start_1004k.S
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#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#include <sysdefs.h>
#include <ArchDefs.h>
#include <launch.h>
#define CODE_ALIGN .align 2
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_INIT_SP_OFFSET CFG_INIT_SP_OFFSET
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define WAITCODE_IN_RAM 0xA0000D00
#define GIC_SHARED_OFS 0xBFBC0000
#define GIC_SH_WEDGE (GIC_SHARED_OFS | 0x0280)
#define GIC_LOCAL_OFS (GIC_SHARED_OFS | 0x8000)
#define GCR_CONFIG 0xbfbf8000
#define GCR_GIC_BASE 0xbfbf8080
#define GCR_GIC_BASE_VALUE 0x1fbc0000
#define GCR_GIC_STATUS 0xbfbf80d0
#define GCR_CPC_BASE 0xbfbf8088
#define GCR_CPC_STATUS 0xbfbf80f0
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR CONFIG_SYS_SDRAM_BASE + CFG_INIT_SP_OFFSET /* fixme: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
#define CPC_GLOBAL_OFS 0xbfbf0000 /* CPC base address */
#define GCR_CPC_BASE_VALUE 0x1fbf0000 /* CPC base address value */
#define GCR_REG0_BASE_VALUE 0x1c000000 /* CM region 0 base address value */
#define GCR_REG1_BASE_VALUE 0x60000000 /* CM region 1 base address value */
#define GCR_REG2_BASE_VALUE 0x1c000000 /* CM region 2 base address value */
#define GCR_REG3_BASE_VALUE 0x1c000000 /* CM region 3 base address value */
#define GCR_REG0_MASK_VALUE 0x0000fc00 /* CM region 0 mask value 64M */
#define GCR_REG1_MASK_VALUE 0x0000f000 /* CM region 1 mask value 256M */
#define GCR_REG2_MASK_VALUE 0x0000fc00 /* CM region 2 mask value 64M */
#define GCR_REG3_MASK_VALUE 0x0000fc00 /* CM region 3 mask value 64M */
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
RVECENT(romReserved,2)
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/*
* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
b __reset_vector
nop
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
#define r2_has_mt_ase $2 /* Core implements the MT ASE. */
#define r3_is_cps $3 /* Core is part of a Coherent Processing System. */
#define r4_temp_data $4 /* scratch, eventually the 1st param for main (a0.) */
#define r5_temp_addr $5 /* scratch, eventually the 2nd param for main (a1.) */
#define r6_temp_dest $6 /* scratch, eventually the 3rd param for main (a2.) */
#define r7_temp_mark $7 /* scratch, eventually the 4th param for main (a3.) */
#define r16_core_num $16 /* Core number. Only core 0 is active after reset. */
#define r17_vpe_num $17 /* MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r18_tc_num $18 /* MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* Number of cores in CPS addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* Interrupt handler scratch address. */
#define r27_int_data $27 /* Interrupt handler scratch data. */
#define r28_global_addr $28 /* Common Address of shared/coherent globals. GLOBAL! */
#define r29_stack_addr $29 /* Unique per vpe stack pointer. */
#define r30_cpc_addr $30 /* Address of CPC register block after cpc_init. 0 indicates no CPC. */
#define r31_return_addr $31 /* Return address for linked branches. */
.macro set_tag TAG_X
#ifdef USE_PIO_DBG
.set noat
la r5_temp_addr, RALINK_PIO_BASE
lw r4_temp_data, 0x20(r5_temp_addr)
li r7_temp_mark, ~((0x7<<6)|(0x1))
and r4_temp_data, r4_temp_data, r7_temp_mark
li r7_temp_mark, ((((\TAG_X)>>1)<<6)|((\TAG_X)&0x1))
or r4_temp_data, r4_temp_data, r7_temp_mark
sw r4_temp_data, 0x20(r5_temp_addr)
.set at
#endif
.endm
/**************************************************************************************
R E S E T E X C E P T I O N H A N D L E R
**************************************************************************************/
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
LEAF(__reset_vector)
b check_nmi # Note: Real systems might want to save/dump full context.
mtc0 $0, $9 # Clear cp0 Count (Used to measure boot time.)
# Note: adding code here may conflict with Malta board ID register at 0xbfc0010.
END(__reset_vector)
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S
**************************************************************************************/
check_nmi: # Verify we are here due to a reset (and not NMI.)
#if 0 //example code if you need to use LED (GPIO0) to debug some issue.
la t0, 0xbe000600
li t9, 1
sw t9, 0(t0) /* output */
sw t9, 0x40(t0) /* low */
#endif
#ifdef USE_PIO_DBG
la r5_temp_addr, RALINK_PIO_BASE
lw r4_temp_data, 0(r5_temp_addr)
li r7_temp_mark, ~(0x1<<5)
and r4_temp_data, r4_temp_data, r7_temp_mark
li r7_temp_mark, (0x7<<6)|(0x1)
or r4_temp_data, r4_temp_data, r7_temp_mark //output
sw r4_temp_data, 0(r5_temp_addr)
lw r4_temp_data, 0x10(r5_temp_addr)
li r7_temp_mark, ~((0x7<<6)|0x1)
and r4_temp_data, r4_temp_data, r7_temp_mark //not invert
sw r4_temp_data, 0x10(r5_temp_addr)
set_tag 0x0
// USE GPIO0, 6,7,8
la r5_temp_addr, RALINK_GPIOMODE_REG
lw r4_temp_data, 0(r5_temp_addr)
li r7_temp_mark, ~(0x3<<3) //~(0x3<<18)
and r4_temp_data, r4_temp_data, r7_temp_mark
sw r4_temp_data, 0(r5_temp_addr)
#endif
set_tag 0x01
#if 0 // set GPIO19(PERST_N) to output mode and pull low
li t0, 0xbe000600
lw t1, 0(t0)
li t2, 1<<19
or t1, t1, t2
sw t1, 0(t0)
li t0, 0xbe000620
lw t1, 0(t0)
li t2, ~(1<<19)
and t1, t1, t2
sw t1, 0(t0)
#endif
mfc0 r4_temp_data, $12 # Read CP0 Status
srl r4_temp_data, 19 # Shift [NMI] into LSBs.
andi r4_temp_data, r4_temp_data, 1 # Inspect CP0 Config[AT]
beqz r4_temp_data, verify_isa # Branch if this is NOT an NMI exception.
nop
sdbbp # Failed assertion: not NMI.
verify_isa: # Verify device ISA meets code requirements (MIPS32 r2 or later.)
mfc0 r4_temp_data, $16 # Read CP0 Config
srl r4_temp_data, 10 # Shift [AT AR] into LSBs.
andi r7_temp_mark, r4_temp_data, 0x18 # Inspect CP0 Config[AT]
beqz r7_temp_mark, is_mips32 # Branch if executing on MIPS32 ISA.
andi r7_temp_mark, r4_temp_data, 0x07 # Inspect CP0 Config[AR]
sdbbp # Failed assertion: mips32.
is_mips32:
bnez r7_temp_mark, init_vpe_resources # Continue if ISA is MIPS32r2 or later.
nop
sdbbp # Failed assertion mips32r2.
/**************************************************************************************
What is initialized on execution depends on the core/vpe executing it.
(A non-MT device is treated as tc0/vpe0, non-CMP device is treated as core0.)
**************************************************************************************/
init_vpe_resources: # Every "cpu"(vpe) initializes per-vpe resources.
bal init_gpr # Fill register file with dummy value then boot info.
nop
bal init_cp0 # Init CP0 Status, Count, Compare, Watch*, and Cause.
nop
bal init_tlb # Generate unique EntryHi contents per entry pair.
nop
bal init_gic # Configure the global interrupt controller.
nop
bnez r17_vpe_num, init_done # If we are not a vpe0 then we are done.
nop
bnez r16_core_num, init_core_resources # Only core0/vpe0 needs to init systems resources.
nop
set_tag 0x02
init_sys_resources: # We are core0 vpe0.
bal init_cpc # Initialize the CPS CPC (Cluster Power Controller.)
nop
bal init_cm # Initialize the CPS CM (Coherency Manager.)
nop
bal init_mc # Initialize the ROC-it2 MC (Memory Controller.)
nop
bal init_l23u # Initialize the unified L2 and L3 caches (if CCA Override is not available.)
nop
#if 0 //MTK: not used
bal copy_c2_ram # Copy "C" code and data to RAM and zero bss (uncached.)
nop
#endif
bal release_mp # Release other cores to execute this boot code.
nop
set_tag 0x03
init_core_resources: # We are a vpe0.
bal init_icache # Initialize the L1 instruction cache. (Executing using I$ on return.)
nop
set_tag 0x04
bal init_dcache # Initialize the L1 data cache
nop
bal init_l23c # Initialize the unified L2 and L3 caches (if CCA Override is available).
nop
#if 0 // MTK: no thread
bal init_itc # Initialize Inter-Thread Communications unit
nop
#endif
bal join_domain # Join the coherent domain. (OK to use D$ on return.)
nop
#ifdef RALINK_DUAL_VPE_FUN
bal init_vpe1 # Set up MT ASE vpe1 to execute this boot code also.
nop
#endif
init_done:
set_tag 0x05
#if 0 //ignore main
# Prepare for eret to main (sp and gp set up per vpe in init_gpr).
la r31_return_addr, all_done # If main return then go to all_done:.
la r5_temp_addr, main
mtc0 r5_temp_addr, $30 # ErrorEPC
# Prepare arguments for main()
move r4_temp_data, r23_cpu_num # main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
move r5_temp_addr, r16_core_num # main(arg1) is the core number.
move r6_temp_dest, r17_vpe_num # main(arg2) is the vpe number.
addiu r7_temp_mark, r20_more_vpes, 1 # main(arg3) is the number of vpe on this core.
eret # Exit reset exception handler for this vpe and start execution of main().
#endif
/**************************************************************************************
**************************************************************************************/
all_done:
notmtcapable:
/*
* MIPSCMP
* Only Core0 carries on from here
* Everybody else waits...
*/
beqz r23_cpu_num,finish_initialisation
nop
othercores:
/* FIXME any other per-CPU initialisation required? */
li t0,KSEG0(CPULAUNCH)
sll t1,r23_cpu_num, LOG2CPULAUNCH
addu t0,t1
/*
* Set CPU online flag
*/
lw t1,LAUNCH_FLAGS(t0)
andi t1, 0
or t1,LAUNCH_FREADY
sw t1,LAUNCH_FLAGS(t0)
/* enable count interrupt in mask, but don't enable interrupts */
mfc0 t2,C0_Status
li t1,M_StatusIM7 /* FIXME should calculate dynamically from Config3.ippti */
or t1,t2
mtc0 t1,C0_Status
li t9, WAITCODE_IN_RAM
jr t9
nop
CODE_ALIGN
waitcode_start:
/*
* Poll CPU go flag
*/
1:
mfc0 t1,C0_Count
addu t1,LAUNCHPERIOD
mtc0 t1,C0_Compare
swwait: /* Software wait */
mfc0 t4,C0_Count
subu t4,t1
bltz t4,swwait
nop
b checklaunch
nop
checklaunch:
lw t1,LAUNCH_FLAGS(t0)
and t1,LAUNCH_FGO
beqz t1, 1b
nop
/* Reset the counter and interrupts to give naive clients a chance */
mtc0 t2,C0_Status
mfc0 t2,C0_Count
subu t2,1
mtc0 t2,C0_Compare
/* we're off */
lw t2,LAUNCH_PC(t0)
lw gp,LAUNCH_GP(t0)
lw sp,LAUNCH_SP(t0)
lw a0,LAUNCH_A0(t0)
move a1,zero
move a2,zero
move a3,zero
ori t1,LAUNCH_FGONE
jr t2
sw t1,LAUNCH_FLAGS(t0)
CODE_ALIGN
waitcode_end:
finish_initialisation:
/* Set up temporary stack */
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
set_tag 0x06
lui t9, %hi(board_init_f)
addiu t9, %lo(board_init_f)
jr t9
nop
/**************************************************************************************
**************************************************************************************/
init_gpr:
# Initialize the general purpose registers and any shadow register sets.
# Although not necessary, register initialization may be useful during boot,
# debug, and simulation when certain ways of initializing registers may not work
# (xor rN, rN, rN for example.)
# Initialize register sets
li $1, 0x0 # (0x0 stands out, kseg2 mapped, odd.)
# Determine how many shadow sets are implemented (in addition to the base register set.)
mfc0 $29, $12, 2 # C0_SRSCtl
ext $30, $29, 26, 4 # S_SRSCtlHSS, W_SRSCtlHSS
next_shadow_set:
# set PSS to shadow set to be initialized
ins $29, $30, 6, 4 # S_SRSCtlPSS, W_SRSCtlPSS
mtc0 $29, $12, 2 # C0_SRSCtl
wrpgpr $1, $1
wrpgpr $2, $1
wrpgpr $3, $1
wrpgpr $4, $1
wrpgpr $5, $1
wrpgpr $6, $1
wrpgpr $7, $1
wrpgpr $8, $1
wrpgpr $9, $1
wrpgpr $10, $1
wrpgpr $11, $1
wrpgpr $12, $1
wrpgpr $13, $1
wrpgpr $14, $1
wrpgpr $15, $1
wrpgpr $16, $1
wrpgpr $17, $1
wrpgpr $18, $1
wrpgpr $19, $1
wrpgpr $20, $1
wrpgpr $21, $1
wrpgpr $22, $1
wrpgpr $23, $1
wrpgpr $24, $1
wrpgpr $25, $1
wrpgpr $26, $1
wrpgpr $27, $1
wrpgpr $28, $1
wrpgpr $29, $1
beqz $30, set_gpr_boot_values
wrpgpr $30, $1
wrpgpr $31, $1 # Don't clobber $31 in set0. Used as r31_return_addr by bal to this code.
b next_shadow_set
add $30, -1
set_gpr_boot_values:
li r1_all_ones, 0xffffffff # Simplify code and improve clarity
mfc0 r4_temp_data, $15, 1 # Read CP0 EBase
ext r23_cpu_num, r4_temp_data, 0, 4 # Extract CPUNum
li r24_malta_word, MALTA_DISP_ADDR # Need for reporting failed assertions.
lui r28_global_addr, %hi(_gp) # All vpe share globals.
addiu r28_global_addr, %lo(_gp)
li r29_stack_addr, STACK_BASE_ADDR # Each vpe gets it's own stack.
ins r29_stack_addr, r23_cpu_num, STACK_SIZE_LOG2, 3
check_mt_ase:
mfc0 r4_temp_data, $16, 1 # C0_Config1
bgez r4_temp_data, no_mt_ase # No Config2 register
mfc0 r4_temp_data, $16, 2 # C0_Config2
bgez r4_temp_data, no_mt_ase # No Config3 register
mfc0 r4_temp_data, $16, 3 # C0_Config3
and r4_temp_data, (1 << 2) # M_Config3MT
beqz r4_temp_data, no_mt_ase
li r2_has_mt_ase, 0
has_mt_ase:
li r2_has_mt_ase, 1
# Every vpe will set up the following to simplify resource initialization.
mfc0 r4_temp_data, $2, 2 # Read CP0 TCBind
ext r17_vpe_num, r4_temp_data, 0, 4 # Extract CurVPE
ext r18_tc_num, r4_temp_data, 21, 8 # Extract CurTC
mfc0 r4_temp_data, $0, 2 # C0_MVPConf0
ext r21_more_tcs, r4_temp_data, 0, 8 # S_MVPConf0PTC, W_MVPConf0PTC (Not used by all vpe.)
b check_cps
ext r20_more_vpes, r4_temp_data, 10, 4 # S_MVPConf0PVPE, W_MVPConf0PVPE (Not used by all vpe.)
no_mt_ase: # This processor does not implement the MIPS32 MT ASE. Set up defaults.
li r17_vpe_num, 0
li r18_tc_num, 0
li r20_more_vpes, 0
li r21_more_tcs, 0
check_cps: # Determine if there is a coherency manager present. (Implementation Dependent.)
mfc0 r25_coreid, $15, 0 # CP0 PRId.
ext r4_temp_data, r25_coreid, 8, 16 # Extract Manuf and Core.
li r7_temp_mark, 0x0199 # MIPS, 1004K
beq r7_temp_mark, r4_temp_data, is_cps
li r7_temp_mark, 0x019a # MIPS, 1074K
beq r7_temp_mark, r4_temp_data, is_cps
nop
is_not_cps: # This processor is not part of a Coherent Processing System. Set up valid defaults.
li r3_is_cps, 0
li r16_core_num, 0
b done_init_gpr
li r19_more_cores, 0
is_cps:
li r3_is_cps, 1
//MTK: access 1fbf8008 will cause excption??
# Verify that we can find the GCRs.
li r5_temp_addr, GCR_CONFIG # KSEG1(GCRBASE)
lw r4_temp_data, 0x0008(r5_temp_addr) # GCR_BASE
ins r5_temp_addr, $0, 29, 3 # Convert KSEG1 to physical address.
ins r4_temp_data, $0, 0, 15 # Isolate physical base address of GCR.
beq r5_temp_addr, r4_temp_data, gcr_found
nop
sdbbp # Can't find GCR. RTL config override of MIPS default?
gcr_found:
# Every vpe will set up the following to simplify resource initialization.
li r22_gcr_addr, GCR_CONFIG
lw r16_core_num, 0x2028(r22_gcr_addr) # Load GCR_CL_ID
lw r4_temp_data, 0(r22_gcr_addr) # Load GCR_CONFIG
#ifdef RALINK_DUAL_CORE_FUN
li r5_temp_addr, RALINK_SYSCTL_BASE
lw r4_temp_data, 0x000c(r5_temp_addr) #CHIP_REV_ID
ext r19_more_cores, r4_temp_data, 17, 1
#else
li r19_more_cores, 0
#endif
done_init_gpr:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_cp0:
# Initialize Status
li $11, 0x00400404 # (M_StatusIM | M_StatusERL | M_StatusBEV)
mtc0 $11, $12 # C0_Status
# Initialize Watch registers if implemented.
mfc0 $10, $16, 1 # C0_Config1
ext $11, $10, 3, 1 # S_Config1WP, W_Config1WP
beq $11, $0, done_wr
li $11, 0x7 # (M_WatchHiI | M_WatchHiR | M_WatchHiW)
# Clear Watch Status bits and disable watch exceptions
mtc0 $11, $19 # C0_WatchHi0
mfc0 $10, $19 # C0_WatchHi0
bgez $10, done_wr
mtc0 $0, $18 # C0_WatchLo0
mtc0 $11, $19, 1 # C0_WatchHi1
mfc0 $10, $19, 1 # C0_WatchHi1
bgez $10, done_wr
mtc0 $0, $18, 1 # C0_WatchLo1
mtc0 $11, $19, 2 # C0_WatchHi2
mfc0 $10, $19, 2 # C0_WatchHi2
bgez $10, done_wr
mtc0 $0, $18, 2 # C0_WatchLo2
mtc0 $11, $19, 3 # C0_WatchHi3
mfc0 $10, $19, 3 # C0_WatchHi3
bgez $10, done_wr
mtc0 $0, $18, 3 # C0_WatchLo3
mtc0 $11, $19, 4 # C0_WatchHi4
mfc0 $10, $19, 4 # C0_WatchHi4
bgez $10, done_wr
mtc0 $0, $18, 4 # C0_WatchLo4
mtc0 $11, $19, 5 # C0_WatchHi5
mfc0 $10, $19, 5 # C0_WatchHi5
bgez $10, done_wr
mtc0 $0, $18, 5 # C0_WatchLo5
mtc0 $11, $19, 6 # C0_WatchHi6
mfc0 $10, $19, 6 # C0_WatchHi6
bgez $10, done_wr
mtc0 $0, $18, 6 # C0_WatchLo6
mtc0 $11, $19, 7 # C0_WatchHi7
mtc0 $0, $18, 7 # C0_WatchLo7
done_wr:
# Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
mtc0 $0, $13 # C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.
# Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
mtc0 $0, $11 # C0_Compare
# Set CCA for kseg0 to cacheable (Do not access D$ on CPS untill all cores join coherent domain.)
mfc0 $10, $16 # C0_Config
beqz r3_is_cps, set_kseg0_cca
li $11, 3 //3 # K_CacheAttrC
li $11, 5 # K_CacheAttrCCS
# Cacheable, write-back, write-allocate, coherent, read misses request Shared
set_kseg0_cca:
ins $10, $11, 0, 3 # S_ConfigK0, W_ConfigK0
mtc0 $10, $16 # C0_Config
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_tlb: # Initialize the TLB
check_for_tlb:
# Determine if we have a TLB
mfc0 $11, $16 # C0_Config
ext $11, $11, 7, 3 # S_ConfigMT, W_ConfigMT
li $15, 0x1 # K_ConfigMT_TLBMMU
bne $11, $15, done_init_tlb
mfc0 $10, $16, 1 # C0_Config1
# Check for TLB sharing between vpe.
beqz r2_has_mt_ase, start_init_tlb
nop
beqz r17_vpe_num, start_init_tlb
mfc0 r4_temp_data, $0, 1 # MVPEControl
ext r4_temp_data, r4_temp_data, 3, 1 # MVPEControl[STLB]
bnez r4_temp_data, done_init_tlb # has MT ASE, is not vpe0, is sharing tlb so skip.
nop
start_init_tlb:
# Config1MMUSize == Number of TLB entries - 1
ext $11, $10, 25, 6 # S_Config1MMUSize, W_Config1MMUSize
mtc0 $0, $2 # C0_EntryLo0
mtc0 $0, $3 # C0_EntryLo1
mtc0 $0, $5 # C0_PageMask
mtc0 $0, $6 # C0_Wired
li $12, 0x80000000
next_tlb_entry_pair:
ins $12, r23_cpu_num, 20, 4 # test: add "cpu" number to provide cps unique entries.
mtc0 $11, $0 # C0_Index
mtc0 $12, $10 # C0_EntryHi
ehb
tlbwi
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, next_tlb_entry_pair
add $11, -1
done_init_tlb:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_cpc:
beqz r3_is_cps, done_init_cpc # Skip if non-CPS.
nop
lw r4_temp_data, 0x00f0(r22_gcr_addr) # GCR_CPC_STATUS
andi r4_temp_data, 1
beqz r4_temp_data, done_init_cpc # Skip if CPC is not implemented.
move r30_cpc_addr, $0
li r4_temp_data, (GCR_CPC_BASE_VALUE | 0x1) # Locate CPC at same location YAMON does.
sw r4_temp_data, 0x0088(r22_gcr_addr) # GCR_CPC_BASE
li r30_cpc_addr, CPC_GLOBAL_OFS # Maintain address of CPC register block.
done_init_cpc:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_gic:
beqz r3_is_cps, done_gic # Skip if non-CPS.
nop
li r5_temp_addr, GCR_GIC_STATUS # Read GCR_GIC_STATUS
lw r4_temp_data, 0(r5_temp_addr)
ext r4_temp_data, r4_temp_data, 0, 1 # Isolate GCR_GIC_STATUS[GIC_EX].
beqz r4_temp_data, done_gic # If no gic then skip.
nop
bnez r23_cpu_num, init_vpe_gic # Only core0 vpe0 inits shared portion.
nop
li r5_temp_addr, GCR_GIC_BASE # Locate and enable GIC where YAMON does.
li r4_temp_data, (GCR_GIC_BASE_VALUE | 1)
sw r4_temp_data, 0(r5_temp_addr)
nop
# Verify gic is 8 "slices" of 8 interrupts giving 40 interrupts.
li r5_temp_addr, GIC_SHARED_OFS
lw r4_temp_data, 0(r5_temp_addr) # GIC_SH_CONFIG
ext r4_temp_data, 16, 8 # NUMINTERRUPTS (actually slices - 1)
li r7_temp_mark, 7
beq r4_temp_data, r7_temp_mark, configure_slices
nop
sdbbp # Failed assertion that gic implements 64 external interrupts.
configure_slices:
li r4_temp_data, 0x00000000
sw r4_temp_data, 0x180(r5_temp_addr) # GIC_SH_TRIG31_0 (Level trigger 0..5)
li r4_temp_data, 0x0000003F
sw r4_temp_data, 0x300(r5_temp_addr) # GIC_SH_RMASK31_0 (disable 0..5)
sw r4_temp_data, 0x100(r5_temp_addr) # GIC_SH_POL31_0 (Active High 0..5)
sw r4_temp_data, 0x380(r5_temp_addr) # GIC_SH_SMASK31_0 (enable 0..5)
# Hardcoded to set up the last 8 of 64 external interrupts (56..63) for IPI.
li r4_temp_data, 0xFF000000
sw r4_temp_data, 0x184(r5_temp_addr) # GIC_SH_TRIG63_32 (edge trigger 56..63)
sw r4_temp_data, 0x304(r5_temp_addr) # GIC_SH_RMASK63_32 (disable 56..63)
sw r4_temp_data, 0x104(r5_temp_addr) # GIC_SH_POL63_32 (Rising Edge 56..63)
sw r4_temp_data, 0x384(r5_temp_addr) # GIC_SH_SMASK63_32 (enable 56..63)
# Initialize configuration of shared interrupts
# Map interrupt source to particular pin (GIC INT6~INT31 to PIN0)
li r4_temp_data, 0x80000000 //source0 to pin0
sw r4_temp_data, 0x500(r5_temp_addr) # GIC_SH_MAP0_PIN
li r4_temp_data, 0x80000000 //source1 to pin0
sw r4_temp_data, 0x504(r5_temp_addr) # GIC_SH_MAP1_PIN
li r4_temp_data, 0x80000004 //source2 to pin4
sw r4_temp_data, 0x508(r5_temp_addr) # GIC_SH_MAP2_PIN
li r4_temp_data, 0x80000003 //source3 to pin3
sw r4_temp_data, 0x50C(r5_temp_addr) # GIC_SH_MAP3_PIN
li r4_temp_data, 0x80000000 //source4 to pin0
sw r4_temp_data, 0x510(r5_temp_addr) # GIC_SH_MAP4_PIN
li r4_temp_data, 0x80000005 //source5 to pin5
sw r4_temp_data, 0x514(r5_temp_addr) # GIC_SH_MAP5_PIN
li r4_temp_data, 0x80000001 //source56 to pin1
sw r4_temp_data, 0x5E0(r5_temp_addr) # GIC_SH_MAP56_PIN
li r4_temp_data, 0x80000001 //source57 to pin1
sw r4_temp_data, 0x5E4(r5_temp_addr) # GIC_SH_MAP57_PIN
li r4_temp_data, 0x80000001 //source58 to pin1
sw r4_temp_data, 0x5E8(r5_temp_addr) # GIC_SH_MAP58_PIN
li r4_temp_data, 0x80000001 //source59 to pin1
sw r4_temp_data, 0x5EC(r5_temp_addr) # GIC_SH_MAP59_PIN
li r4_temp_data, 0x80000002 //source60 to pin2
sw r4_temp_data, 0x5F0(r5_temp_addr) # GIC_SH_MAP60_PIN
li r4_temp_data, 0x80000002 //source61 to pin2
sw r4_temp_data, 0x5F4(r5_temp_addr) # GIC_SH_MAP61_PIN
li r4_temp_data, 0x80000002 //source62 to pin2
sw r4_temp_data, 0x5F8(r5_temp_addr) # GIC_SH_MAP62_PIN
li r4_temp_data, 0x80000002 //source63 to pin2
sw r4_temp_data, 0x5FC(r5_temp_addr) # GIC_SH_MAP63_PIN
#Interrupt map to VPE (1=vpe0, 2=vpe1, 4=vpe2, 8=vpe3)
li r4_temp_data, 1
sw r4_temp_data, 0x2000(r5_temp_addr) # GIC_SH_MAP0_VPE31_0
sw r4_temp_data, 0x2020(r5_temp_addr) # GIC_SH_MAP1_VPE31_0
sw r4_temp_data, 0x2040(r5_temp_addr) # GIC_SH_MAP2_VPE31_0
sw r4_temp_data, 0x2060(r5_temp_addr) # GIC_SH_MAP3_VPE31_0
sw r4_temp_data, 0x2080(r5_temp_addr) # GIC_SH_MAP4_VPE31_0
sw r4_temp_data, 0x20A0(r5_temp_addr) # GIC_SH_MAP5_VPE31_0
sw r4_temp_data, 0x20C0(r5_temp_addr) # GIC_SH_MAP6_VPE31_0
sw r4_temp_data, 0x20E0(r5_temp_addr) # GIC_SH_MAP7_VPE31_0
sw r4_temp_data, 0x2100(r5_temp_addr) # GIC_SH_MAP8_VPE31_0
sw r4_temp_data, 0x2120(r5_temp_addr) # GIC_SH_MAP9_VPE31_0
sw r4_temp_data, 0x2140(r5_temp_addr) # GIC_SH_MAP10_VPE31_0
sw r4_temp_data, 0x2160(r5_temp_addr) # GIC_SH_MAP11_VPE31_0
sw r4_temp_data, 0x2180(r5_temp_addr) # GIC_SH_MAP12_VPE31_0
sw r4_temp_data, 0x21A0(r5_temp_addr) # GIC_SH_MAP13_VPE31_0
sw r4_temp_data, 0x21C0(r5_temp_addr) # GIC_SH_MAP14_VPE31_0
sw r4_temp_data, 0x21E0(r5_temp_addr) # GIC_SH_MAP15_VPE31_0
sw r4_temp_data, 0x2200(r5_temp_addr) # GIC_SH_MAP16_VPE31_0
sw r4_temp_data, 0x2220(r5_temp_addr) # GIC_SH_MAP17_VPE31_0
sw r4_temp_data, 0x2240(r5_temp_addr) # GIC_SH_MAP18_VPE31_0
sw r4_temp_data, 0x2260(r5_temp_addr) # GIC_SH_MAP19_VPE31_0
sw r4_temp_data, 0x2280(r5_temp_addr) # GIC_SH_MAP20_VPE31_0
sw r4_temp_data, 0x22A0(r5_temp_addr) # GIC_SH_MAP21_VPE31_0
sw r4_temp_data, 0x22C0(r5_temp_addr) # GIC_SH_MAP22_VPE31_0
sw r4_temp_data, 0x22E0(r5_temp_addr) # GIC_SH_MAP23_VPE31_0
sw r4_temp_data, 0x2300(r5_temp_addr) # GIC_SH_MAP24_VPE31_0
sw r4_temp_data, 0x2320(r5_temp_addr) # GIC_SH_MAP25_VPE31_0
sw r4_temp_data, 0x2340(r5_temp_addr) # GIC_SH_MAP26_VPE31_0
sw r4_temp_data, 0x2360(r5_temp_addr) # GIC_SH_MAP27_VPE31_0
sw r4_temp_data, 0x2380(r5_temp_addr) # GIC_SH_MAP28_VPE31_0
sw r4_temp_data, 0x23A0(r5_temp_addr) # GIC_SH_MAP29_VPE31_0
sw r4_temp_data, 0x23C0(r5_temp_addr) # GIC_SH_MAP30_VPE31_0
sw r4_temp_data, 0x23E0(r5_temp_addr) # GIC_SH_MAP31_VPE31_0
# Direct GIC_int 56..63 to vpe 0..3
# MIPS Linux convention that last 16 interrupts implemented be set aside for IPI signaling.
# (The actual interrupts are tied low and software sends interrupts via GIC_SH_WEDGE writes.)
li r4_temp_data, 1 # vpe0 is selected for
sw r4_temp_data, 0x2700(r5_temp_addr) # GIC_SH_MAP56_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe1 is selected for
sw r4_temp_data, 0x2720(r5_temp_addr) # GIC_SH_MAP57_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe2 is selected for
sw r4_temp_data, 0x2740(r5_temp_addr) # GIC_SH_MAP58_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe3 is selected for
sw r4_temp_data, 0x2760(r5_temp_addr) # GIC_SH_MAP59_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe4 is selected for
li r4_temp_data, 1 # vpe0 is selected for
sw r4_temp_data, 0x2780(r5_temp_addr) # GIC_SH_MAP60_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe5 is selected for
sw r4_temp_data, 0x27a0(r5_temp_addr) # GIC_SH_MAP61_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe6 is selected for
sw r4_temp_data, 0x27c0(r5_temp_addr) # GIC_SH_MAP62_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe7 is selected for
sw r4_temp_data, 0x27e0(r5_temp_addr) # GIC_SH_MAP63_VPE31_0 and
init_vpe_gic:
# Initialize configuration of per vpe interrupts
li r5_temp_addr, GIC_LOCAL_OFS
lw r7_temp_mark, 0x0000(r5_temp_addr) # GIC_VPEi_CFG
map_timer_int:
ext r4_temp_data, r7_temp_mark, 1, 1 # TIMER_ROUTABLE
beqz r4_temp_data, map_perfcount_int
nop
map_perfcount_int:
ext r4_temp_data, r7_temp_mark, 2, 1 # PERFCOUNT_ROUTABLE
beqz r4_temp_data, done_gic
nop
done_gic:
jr r31_return_addr
nop
/**************************************************************************************
Hardcoded Denali Databahn DRAM controller initialization.
**************************************************************************************/
init_mc:
#ifdef UBOOT_ROM
//#define USE_PCIE_SRAM 1
#define FE_SRAM_STACK 0xBE108000
#define RALINK_CLKCFG0_REG (RALINK_SYSCTL_BASE+0x2C)
#define RALINK_RSTCTRL_REG (RALINK_SYSCTL_BASE+0x34)
//set SPI clock to system bus /(5+2)
li t0, RALINK_SPI_BASE + 0x3c
//sw zero, 0(t0)
li t1, ~0x0FFF
lw t2, 0(t0)
and t2, t2, t1
ori t2, t2, 0x5
sw t2, 0(t0)
/* change CPU ratio from 1/A to 1/1 */
li t0, RALINK_DYN_CFG0_REG
li t1, ~(0x0F<<8)
lw t2, 0(t0)
and t2, t2, t1
li t1, 1<<8
or t2, t2, t1
sw t2, 0(t0)
/* enter accessible PSE SRAM */
/* RESET PSE SRAM */
li t0, 0xBE100004
li t1 ,0x1
sw t1, 0(t0)
li t2, 0x333333/3
#if 0
DLY:
subu t2, t2, 1
bgtz t2, DLY
nop
#endif
li t0, 0xBE100004
lw t1, 0(t0)
ori t1, 0x6 //FE_RST_GLO[2:1]=2'b11 (bit2=PSE_RAM mode, bit1=enable)
sw t1, 0(t0)
nop
#ifndef BYPASS_MTK_DDR_CAL
#ifdef USE_PCIE_SRAM
/* enable accessible PCIe SRAM */
li t0, RALINK_RSTCTRL_REG
li t1, 0x7<<24
sw t1, 0(t0)
li t0, RALINK_CLKCFG0_REG
lw t1, 0(t0)
li t2, 1<<17
or t1, t1, t2
sw t1, 0(t0)
li t0, RALINK_RSTCTRL_REG
sw zero, 0(t0)
li t0, 0xBE1400B0
ori t1, t3, 1