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Fixes for test-app. Fixes and cleanups for big endian data handling on Renesas RX. Support for build-time switching of endianess (BIG_ENDIAN=1).
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-145
lines changed

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+145
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lines changed

‎Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ DEBUG_UART?=0
2424
LIBS=
2525
SIGN_ALG=
2626
OBJCOPY_FLAGS=
27+
BIG_ENDIAN?=0
2728

2829
OBJS:= \
2930
./hal/$(TARGET).o \

‎arch.mk

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -272,10 +272,19 @@ ifeq ($(ARCH),RENESAS_RX)
272272
endif
273273

274274
ifeq ($(TARGET),rx65n)
275-
CFLAGS+=-misa=v2 -mlittle-endian-data -nofpu
275+
CFLAGS+=-misa=v2 -nofpu
276276
endif
277277
ifeq ($(TARGET),rx72n)
278-
CFLAGS+=-misa=v3 -mlittle-endian-data -nofpu
278+
CFLAGS+=-misa=v3 -nofpu
279+
endif
280+
281+
# RX parts support big or little endian data depending on MDE register
282+
ifeq ($(BIG_ENDIAN),1)
283+
CFLAGS+=-mbig-endian-data
284+
LDFLAGS+=-mbig-endian-data
285+
else
286+
CFLAGS+=-mlittle-endian-data
287+
LDFLAGS+=-mlittle-endian-data
279288
endif
280289

281290
ifeq ($(TSIP),1)

‎config/examples/renesas-rx65n.config

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@ SPMATH?=1
1717
RAM_CODE?=0
1818
DUALBANK_SWAP?=0
1919

20+
# Optionally switch to big endian data if MDE is set
21+
#BIG_ENDIAN=1
22+
2023
# Flash is 2MB with 64KB sector size
2124
WOLFBOOT_SECTOR_SIZE?=0x10000
2225

‎config/examples/renesas-rx72n.config

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@ SPMATH?=1
1717
RAM_CODE?=0
1818
DUALBANK_SWAP?=0
1919

20+
# Optionally switch to big endian data if MDE is set
21+
#BIG_ENDIAN=1
22+
2023
# Flash is 4MB with 64KB sector size
2124
WOLFBOOT_SECTOR_SIZE?=0x10000
2225

‎docs/Targets.md

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1795,6 +1795,12 @@ Default Onboard Flash Memory Layout (2MB) (64KB sector):
17951795
| Swap | 0xFFFE0000 | 0x00010000 ( 64 KB) |
17961796
| wolfBoot | 0xFFFF0000 | 0x00010000 ( 64 KB) |
17971797

1798+
To switch RX parts to big endian data use:
1799+
1800+
```sh
1801+
rfp-cli -if fine -t e2l -device RX65x -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -write32 0xFE7F5D00 0xFFFFFFF8
1802+
```
1803+
17981804
## Building Renesas RX65N
17991805

18001806
Building RX wolfBoot requires the RX-ELF compiler. Please Download and install the Renesas RX GCC toolchain:

‎hal/renesas-rx.h

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -22,22 +22,6 @@
2222
#ifndef _WOLFBOOT_RENESAS_RX_H_
2323
#define _WOLFBOOT_RENESAS_RX_H_
2424

25-
#ifdef BIG_ENDIAN_ORDER
26-
#define ENDIAN_BIT8( n, bits) (1 << (8- (n)))
27-
#define ENDIAN_BIT16(n, bits) (1 << (16-(n)))
28-
#define ENDIAN_BIT32(n, bits) (1 << (32-(n)))
29-
#define ENDIAN_VAL8( val, n, bits) ((val) << (8- (n)))
30-
#define ENDIAN_VAL16(val, n, bits) ((val) << (16-(n)))
31-
#define ENDIAN_VAL32(val, n, bits) ((val) << (32-(n)))
32-
#else
33-
#define ENDIAN_BIT8( n) (1 << (n))
34-
#define ENDIAN_BIT16(n) (1 << (n))
35-
#define ENDIAN_BIT32(n) (1 << (n))
36-
#define ENDIAN_VAL8( val, n) ((val) << (n))
37-
#define ENDIAN_VAL16(val, n) ((val) << (n))
38-
#define ENDIAN_VAL32(val, n) ((val) << (n))
39-
#endif
40-
4125
#if defined(__CCRX__)
4226
#define RX_NOP() nop()
4327
#elif defined(__GNUC__)

‎hal/rx65n.c

Lines changed: 62 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -38,133 +38,133 @@
3838
#define SYSTEM_BASE (0x80000)
3939

4040
#define SYS_SYSCR0 (*(volatile uint16_t *)(SYSTEM_BASE + 0x06))
41-
#define SYS_SYSCR0_EXBE ENDIAN_BIT16(1) /* External Bus Enable */
41+
#define SYS_SYSCR0_EXBE (1 << 1) /* External Bus Enable */
4242

4343
#define SYS_MSTPCRB (*(volatile uint32_t *)(SYSTEM_BASE + 0x14)) /* Module Stop Control 0=release, 1=stop */
4444

4545
#define SYS_SCKCR (*(volatile uint32_t *)(SYSTEM_BASE + 0x20)) /* System Clock Control Register */
46-
#define SYS_SCKCR_FCK(n) ENDIAN_VAL32(n, 28)
47-
#define SYS_SCKCR_ICK(n) ENDIAN_VAL32(n, 24)
48-
#define SYS_SCKCR_PSTOP1 ENDIAN_BIT32(23)
49-
#define SYS_SCKCR_PSTOP0 ENDIAN_BIT32(22)
50-
#define SYS_SCKCR_BCK(n) ENDIAN_VAL32(n, 16)
51-
#define SYS_SCKCR_PCKA(n) ENDIAN_VAL32(n, 12)
52-
#define SYS_SCKCR_PCKB(n) ENDIAN_VAL32(n, 8)
53-
#define SYS_SCKCR_PCKC(n) ENDIAN_VAL32(n, 4)
54-
#define SYS_SCKCR_PCKD(n) ENDIAN_VAL32(n, 0)
46+
#define SYS_SCKCR_FCK(n) ((n) << 28)
47+
#define SYS_SCKCR_ICK(n) ((n) << 24)
48+
#define SYS_SCKCR_PSTOP1 (1 << 23)
49+
#define SYS_SCKCR_PSTOP0 (1 << 22)
50+
#define SYS_SCKCR_BCK(n) ((n) << 16)
51+
#define SYS_SCKCR_PCKA(n) ((n) << 12)
52+
#define SYS_SCKCR_PCKB(n) ((n) << 8)
53+
#define SYS_SCKCR_PCKC(n) ((n) << 4)
54+
#define SYS_SCKCR_PCKD(n) ((n) << 0)
5555

5656
#define SYS_SCKCR2 (*(volatile uint16_t *)(SYSTEM_BASE + 0x24)) /* System Clock Control Register 2 */
57-
#define SYS_SCKCR2_UCK(n) ENDIAN_VAL16(n, 4)
57+
#define SYS_SCKCR2_UCK(n) ((n) << 4)
5858

5959
#define SYS_SCKCR3 (*(volatile uint16_t *)(SYSTEM_BASE + 0x26)) /* System Clock Control Register 3 */
60-
#define SYS_SCKCR3_CKSEL(n) ENDIAN_VAL16(n, 8) /* 0=LOCO, 1=HOCO, 2=Main, 3=Sub, 4=PLL */
60+
#define SYS_SCKCR3_CKSEL(n) ((n) << 8) /* 0=LOCO, 1=HOCO, 2=Main, 3=Sub, 4=PLL */
6161

6262
#define SYS_PLLCR (*(volatile uint16_t *)(SYSTEM_BASE + 0x28))
63-
#define SYS_PLLCR_PLIDIV(n) ENDIAN_VAL16(n, 0) /* 0=x1, 1=x1/2, 2=x1/3 */
64-
#define SYS_PLLCR_PLLSRCSEL ENDIAN_BIT16(4) /* 0=main, 1=HOCO */
65-
#define SYS_PLLCR_STC(n) ENDIAN_VAL16(n, 8) /* Frequency Multiplication Factor */
63+
#define SYS_PLLCR_PLIDIV(n) ((n) << 0) /* 0=x1, 1=x1/2, 2=x1/3 */
64+
#define SYS_PLLCR_PLLSRCSEL (1 << 4) /* 0=main, 1=HOCO */
65+
#define SYS_PLLCR_STC(n) ((n) << 8) /* Frequency Multiplication Factor */
6666

6767
#define SYS_PLLCR2 (*(volatile uint8_t *)(SYSTEM_BASE + 0x2A))
68-
#define SYS_PLLCR2_PLLEN ENDIAN_BIT8(0) /* PLL Stop Control: 0=PLL operating, 1=PLL stopped */
68+
#define SYS_PLLCR2_PLLEN (1 << 0) /* PLL Stop Control: 0=PLL operating, 1=PLL stopped */
6969

7070
#define SYS_BCKCR (*(volatile uint8_t *)(SYSTEM_BASE + 0x30))
71-
#define SYS_BCKCR_BCLKDIV ENDIAN_BIT8(0) /* 0=BCLK, 1= 1/2 BCLK */
71+
#define SYS_BCKCR_BCLKDIV (1 << 0) /* 0=BCLK, 1= 1/2 BCLK */
7272

7373
#define SYS_MOSCCR (*(volatile uint8_t *)(SYSTEM_BASE + 0x32))
74-
#define SYS_MOSCCR_MOSTP ENDIAN_BIT8(0) /* Main-clock osc: 0=operating, 1=stopped */
74+
#define SYS_MOSCCR_MOSTP (1 << 0) /* Main-clock osc: 0=operating, 1=stopped */
7575

7676
#define SYS_SOSCCR (*(volatile uint8_t *)(SYSTEM_BASE + 0x33)) /* Sub-Clock Oscillator Control */
77-
#define SYS_SOSCCR_SOSTP ENDIAN_BIT8(0) /* Sub-clock osc: 0=operating, 1=stopped */
77+
#define SYS_SOSCCR_SOSTP (1 << 0) /* Sub-clock osc: 0=operating, 1=stopped */
7878

7979
#define SYS_LOCOCR (*(volatile uint8_t *)(SYSTEM_BASE + 0x34))
80-
#define SYS_LOCOCR_LCSTP ENDIAN_BIT8(0) /* Low-Speed On-Chip Oscillator Control: 0=On, 1=Off */
80+
#define SYS_LOCOCR_LCSTP (1 << 0) /* Low-Speed On-Chip Oscillator Control: 0=On, 1=Off */
8181

8282
#define SYS_HOCOCR (*(volatile uint8_t *)(SYSTEM_BASE + 0x36))
83-
#define SYS_HOCOCR_HCSTP ENDIAN_BIT8(0) /* High Speed On-Chip Osc - 1=STOPPED */
83+
#define SYS_HOCOCR_HCSTP (1 << 0) /* High Speed On-Chip Osc - 1=STOPPED */
8484
#define SYS_HOCOCR2 (*(volatile uint8_t *)(SYSTEM_BASE + 0x37))
85-
#define SYS_HOCOCR2_HCFRQ(n) ENDIAN_VAL8(n, 0) /* 0=16MHz, 1=18MHz, 2=20MHz */
85+
#define SYS_HOCOCR2_HCFRQ(n) ((n) << 0) /* 0=16MHz, 1=18MHz, 2=20MHz */
8686

8787
#define SYS_OSCOVFSR (*(volatile uint8_t *)(SYSTEM_BASE + 0x3C))
88-
#define SYS_OSCOVFSR_MOOVF ENDIAN_BIT8(0) /* Main clock */
89-
#define SYS_OSCOVFSR_SOOVF ENDIAN_BIT8(1) /* Sub clock */
90-
#define SYS_OSCOVFSR_PLOVF ENDIAN_BIT8(2) /* PLL */
91-
#define SYS_OSCOVFSR_HCOVF ENDIAN_BIT8(3) /* HOCO */
92-
#define SYS_OSCOVFSR_ILCOVF ENDIAN_BIT8(4) /* IWDT */
88+
#define SYS_OSCOVFSR_MOOVF (1 << 0) /* Main clock */
89+
#define SYS_OSCOVFSR_SOOVF (1 << 1) /* Sub clock */
90+
#define SYS_OSCOVFSR_PLOVF (1 << 2) /* PLL */
91+
#define SYS_OSCOVFSR_HCOVF (1 << 3) /* HOCO */
92+
#define SYS_OSCOVFSR_ILCOVF (1 << 4) /* IWDT */
9393

9494
#define SYS_MOSCWTCR (*(volatile uint8_t *)(SYSTEM_BASE + 0xA2))
95-
#define SYS_MOSCWTCR_MSTS(n) ENDIAN_VAL8(n, 0)
95+
#define SYS_MOSCWTCR_MSTS(n) ((n) << 0)
9696

9797
/* Register Write Protection Function */
9898
#define SYS_PRCR (*(volatile uint16_t *)(SYSTEM_BASE + 0x3FE))
99-
#define SYS_PRCR_PRKEY (0xA500)
100-
#define SYS_PRCR_PRC0 ENDIAN_BIT16(0) /* Enables writing to clock generation circuit */
101-
#define SYS_PRCR_PRC1 ENDIAN_BIT16(1) /* Enables writing to operating modes, clock R/W generation circuit, low power consumption, and software reset */
102-
#define SYS_PRCR_PRC3 ENDIAN_BIT16(3) /* Enables writing to LVD */
99+
#define SYS_PRCR_PRKEY (0xA5 << 8)
100+
#define SYS_PRCR_PRC0 (1 << 0) /* Enables writing to clock generation circuit */
101+
#define SYS_PRCR_PRC1 (1 << 1) /* Enables writing to operating modes, clock R/W generation circuit, low power consumption, and software reset */
102+
#define SYS_PRCR_PRC3 (1 << 3) /* Enables writing to LVD */
103103

104104
#define PROTECT_OFF() SYS_PRCR = (SYS_PRCR_PRKEY | SYS_PRCR_PRC0 | SYS_PRCR_PRC1 | SYS_PRCR_PRC3)
105105
#define PROTECT_ON() SYS_PRCR = (SYS_PRCR_PRKEY)
106106

107107
#define SYS_MOFCR (*(volatile uint8_t *)(0x8C293))
108-
#define SYS_MOFCR_MOFXIN ENDIAN_BIT8(0) /* OSC Force Oscillation: 0=not controlled, 1=main clock forced */
109-
#define SYS_MOFCR_MODRV2(n) ENDIAN_VAL8(n, 4) /* OSC MHz: 0=20.1-24, 1=16.1-20, 2=8.1-16, 3=8 */
110-
#define SYS_MOFCR_MOSEL ENDIAN_BIT8(6) /* 0=resonator, 1=external clk in*/
108+
#define SYS_MOFCR_MOFXIN (1 << 0) /* OSC Force Oscillation: 0=not controlled, 1=main clock forced */
109+
#define SYS_MOFCR_MODRV2(n) ((n) << 4) /* OSC MHz: 0=20.1-24, 1=16.1-20, 2=8.1-16, 3=8 */
110+
#define SYS_MOFCR_MOSEL (1 << 6) /* 0=resonator, 1=external clk in*/
111111

112112
#define SYS_HOCOPCR (*(volatile uint8_t *)(0x8C294))
113-
#define SYS_HOCOPCR_HOCOPCNT ENDIAN_BIT8(0) /* High-Speed On-Chip Oscillator Power Supply Control: 0=On, 1=Off */
113+
#define SYS_HOCOPCR_HOCOPCNT (1 << 0) /* High-Speed On-Chip Oscillator Power Supply Control: 0=On, 1=Off */
114114

115115
#define SYS_RSTSR1 (*(volatile uint8_t *)(0x8C291))
116-
#define SYS_RSTSR1_CWSF ENDIAN_BIT8(0) /* 0=Cold Start, 1=Warm Start */
116+
#define SYS_RSTSR1_CWSF (1 << 0) /* 0=Cold Start, 1=Warm Start */
117117

118118
/* RTC */
119119
#define RTC_BASE 0x8C400
120120
#define RTC_RCR3 (*(volatile uint8_t *)(RTC_BASE + 0x26))
121-
#define RTC_RCR3_RTCEN ENDIAN_BIT8(0) /* Sub Clock Osc: 0=stopped, 1=operating */
122-
#define RTC_RCR3_RTCDV(n) ENDIAN_VAL8(n, 1)
121+
#define RTC_RCR3_RTCEN (1 << 0) /* Sub Clock Osc: 0=stopped, 1=operating */
122+
#define RTC_RCR3_RTCDV(n) ((n) << 1)
123123
#define RTC_RCR4 (*(volatile uint8_t *)(RTC_BASE + 0x28))
124-
#define RTC_RCR4_RCKSEL ENDIAN_BIT8(0) /* 0=Sub Clock, 1=Main Clock */
124+
#define RTC_RCR4_RCKSEL (1 << 0) /* 0=Sub Clock, 1=Main Clock */
125125

126126
/* Flash */
127127
#define FLASH_BASE 0x81000
128128
#define FLASH_ROMWT (*(volatile uint8_t *)(FLASH_BASE + 0x1C))
129-
#define FLASH_ROMWT_ROMWT(n) ENDIAN_VAL8(n, 0) /* 0=no wait, 1=one wait cycle, 2=two wait cycles */
129+
#define FLASH_ROMWT_ROMWT(n) ((n) << 0) /* 0=no wait, 1=one wait cycle, 2=two wait cycles */
130130

131131
/* Serial Communication Interface */
132132
#define SCI_BASE(n) (0x8A000 + ((n) * 0x20))
133133
#define SCI_SMR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x00))
134134
#define SCI_SMR_CKS(clk) (clk & 0x3) /* 0=PCLK, 1=PCLK/4, 2=PCLK/16, 3=PCLK/64 */
135-
#define SCI_SMR_STOP ENDIAN_BIT8(3) /* 0=1 stop bit */
136-
#define SCI_SMR_CHR ENDIAN_BIT8(6) /* 0=8-bit */
135+
#define SCI_SMR_STOP (1 << 3) /* 0=1 stop bit */
136+
#define SCI_SMR_CHR (1 << 6) /* 0=8-bit */
137137
#define SCI_BRR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x01)) /* Bit Rate Reg < 255 */
138138
#define SCI_SCR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x02))
139-
#define SCI_SCR_RE ENDIAN_BIT8(4)
140-
#define SCI_SCR_TE ENDIAN_BIT8(5)
139+
#define SCI_SCR_RE (1 << 4)
140+
#define SCI_SCR_TE (1 << 5)
141141
#define SCI_TDR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x03)) /* Transmit Data Register */
142142
#define SCI_SSR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x04))
143-
#define SCI_SSR_TEND ENDIAN_BIT8(2) /* Transmit End Flag */
144-
#define SCI_SSR_RDRF ENDIAN_BIT8(6) /* Receive Data Full Flag */
145-
#define SCI_SSR_TDRE ENDIAN_BIT8(7) /* Transmit Data Empty Flag */
143+
#define SCI_SSR_TEND (1 << 2) /* Transmit End Flag */
144+
#define SCI_SSR_RDRF (1 << 6) /* Receive Data Full Flag */
145+
#define SCI_SSR_TDRE (1 << 7) /* Transmit Data Empty Flag */
146146
#define SCI_RDR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x05)) /* Receive Data Register */
147147
#define SCI_SCMR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x06))
148-
#define SCI_SCMR_CHR1 ENDIAN_BIT8(4) /* 1=8-bit */
148+
#define SCI_SCMR_CHR1 (1 << 4) /* 1=8-bit */
149149
#define SCI_SEMR(n) (*(volatile uint8_t *)(SCI_BASE(n) + 0x08))
150-
#define SCI_SEMR_ASC0 ENDIAN_BIT8(0) /* Asynchronous Mode Clock Source Select 0=external clock input */
151-
#define SCI_SEMR_BRME ENDIAN_BIT8(2) /* Bit Rate Modulation Enable */
152-
#define SCI_SEMR_ABCS ENDIAN_BIT8(4) /* Asynchronous Mode Base Clock Select */
153-
#define SCI_SEMR_NFEN ENDIAN_BIT8(5) /* Digital Noise Filter Function Enable */
154-
#define SCI_SEMR_BGDM ENDIAN_BIT8(6) /* Baud Rate Generator Double-Speed Mode Select */
155-
#define SCI_SEMR_RXDESEL ENDIAN_BIT8(7) /* Asynchronous Start Bit Edge Detection Select */
150+
#define SCI_SEMR_ASC0 (1 << 0) /* Asynchronous Mode Clock Source Select 0=external clock input */
151+
#define SCI_SEMR_BRME (1 << 2) /* Bit Rate Modulation Enable */
152+
#define SCI_SEMR_ABCS (1 << 4) /* Asynchronous Mode Base Clock Select */
153+
#define SCI_SEMR_NFEN (1 << 5) /* Digital Noise Filter Function Enable */
154+
#define SCI_SEMR_BGDM (1 << 6) /* Baud Rate Generator Double-Speed Mode Select */
155+
#define SCI_SEMR_RXDESEL (1 << 7) /* Asynchronous Start Bit Edge Detection Select */
156156

157157
/* MPC (Multi-Function Pin Controller) */
158158
#define MPC_PWPR (*(volatile uint8_t *)(0x8C11F))
159-
#define MPC_PWPR_B0WI ENDIAN_BIT8(7)
160-
#define MPC_PWPR_PFSWE ENDIAN_BIT8(6)
159+
#define MPC_PWPR_B0WI (1 << 7)
160+
#define MPC_PWPR_PFSWE (1 << 6)
161161

162162
#define MPC_PFS(n) (*(volatile uint8_t *)(0x8C0E0 + (n)))
163163

164164
/* Ports */
165-
#define PORT_BASE(n) (0x8C000 + (n))
166-
#define PORT_PDR(n) (*(volatile uint8_t*)(0x8C000 + (n)))
167-
#define PORT_PMR(n) (*(volatile uint8_t*)(0x8C060 + (n))) /* 0=General, 1=Peripheral */
165+
#define PORT_BASE(n) (0x8C000 + (n))
166+
#define PORT_PDR(n) (*(volatile uint8_t*)(0x8C000 + (n)))
167+
#define PORT_PMR(n) (*(volatile uint8_t*)(0x8C060 + (n))) /* 0=General, 1=Peripheral */
168168

169169

170170
static void hal_delay_us(uint32_t us)
@@ -190,14 +190,14 @@ void uart_init(void)
190190
/* Release SCI5 module stop (clear bit) */
191191
/* bit 31=SCI0, 30=SCI1, 29=SCI2, 28=SCI3, 27=SCI4, 26=SCI5, 25=SCI6, 24=SCI7 */
192192
PROTECT_OFF();
193-
SYS_MSTPCRB &= ~ENDIAN_BIT32(26);
193+
SYS_MSTPCRB &= ~(1 << 26);
194194
PROTECT_ON();
195195

196196
/* Disable RX/TX */
197197
SCI_SCR(DEBUG_UART_SCI) = 0;
198198

199199
/* Configure PC3 for UART (TXD5) and PC2 UART (RXD5) */
200-
PORT_PMR(0xC) |= (ENDIAN_BIT32(2) | ENDIAN_BIT32(3));
200+
PORT_PMR(0xC) |= ((1 << 2) | (1 << 3));
201201

202202
/* Disable MPC Write Protect for PFS */
203203
MPC_PWPR &= ~MPC_PWPR_B0WI;

‎include/user_settings.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -39,12 +39,6 @@
3939
#define WOLFCRYPT_ONLY
4040
#define SIZEOF_LONG_LONG 8
4141

42-
/* Endianess */
43-
/* Renesas RX Endianess */
44-
#ifdef __RX_BIG_ENDIAN__ /* or !__RX_LITTLE_ENDIAN__ */
45-
#define BIG_ENDIAN_ORDER
46-
#endif
47-
4842
/* Stdlib Types */
4943
#define CTYPE_USER /* don't let wolfCrypt types.h include ctype.h */
5044
extern int toupper(int c);

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