From 384824ebd30cff756208bcccb41dc6ad0da11e77 Mon Sep 17 00:00:00 2001 From: Ryan Jones Date: Wed, 18 Nov 2020 14:35:58 -0500 Subject: [PATCH] Added advance signal to CU, decreases Fibonacci calculation time by 22% --- rtl/ControlSignals.v | 4 +++- rtl/ControlUnit.v | 31 ++++++++++++++++--------------- rtl/XDN.v | 3 +++ 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/rtl/ControlSignals.v b/rtl/ControlSignals.v index 5b9d38c..cece709 100644 --- a/rtl/ControlSignals.v +++ b/rtl/ControlSignals.v @@ -1,6 +1,7 @@ -localparam CONTROL_WIDTH = 16; +localparam CONTROL_WIDTH = 17; // Definition of signal indices in the control word +localparam CU_ADVANCE_INDEX = 'h10; localparam HALT_INDEX = 'hF; localparam MAR_IN_INDEX = 'hE; localparam RAM_IN_INDEX = 'hD; @@ -18,6 +19,7 @@ localparam PC_INC_INDEX = 'h2; localparam PC_OUT_INDEX = 'h1; localparam JUMP_INDEX = 'h0; +localparam [CONTROL_WIDTH - 1:0] c_CU_ADVANCE = {{CONTROL_WIDTH - 1{1'b0}}, 1'b1} << CU_ADVANCE_INDEX; localparam [CONTROL_WIDTH - 1:0] c_HALT = {{CONTROL_WIDTH - 1{1'b0}}, 1'b1} << HALT_INDEX; localparam [CONTROL_WIDTH - 1:0] c_MAR_IN = {{CONTROL_WIDTH - 1{1'b0}}, 1'b1} << MAR_IN_INDEX; localparam [CONTROL_WIDTH - 1:0] c_RAM_IN = {{CONTROL_WIDTH - 1{1'b0}}, 1'b1} << RAM_IN_INDEX; diff --git a/rtl/ControlUnit.v b/rtl/ControlUnit.v index 097305a..8310bda 100644 --- a/rtl/ControlUnit.v +++ b/rtl/ControlUnit.v @@ -5,6 +5,7 @@ module ControlUnit input [DATA_WIDTH - 1:0] i_IR_DATA, // Instruction register data, contans the opcode of the current instruction input i_ZERO_FLAG, input i_CARRY_FLAG, + input i_ADVANCE, // Instructs the CU to advance to the next instruction output o_CLEAR, output o_CLEAR_n, @@ -22,7 +23,7 @@ module ControlUnit always @(posedge i_CLOCK) begin // Update the clock - if(r_T_CYCLE == 'h6) + if((r_T_CYCLE == 'h6) || (i_ADVANCE)) r_T_CYCLE <= 0; else r_T_CYCLE <= r_T_CYCLE + 1'b1; @@ -38,57 +39,57 @@ module ControlUnit r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_RAM_OUT | c_MAR_IN : r_T_CYCLE == 'h4 ? c_PC_INC | c_RAM_OUT | c_A_IN : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h20) ? // ADD; B = RAM[IMM4], A += B r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_RAM_OUT | c_MAR_IN : r_T_CYCLE == 'h4 ? c_RAM_OUT | c_B_IN : r_T_CYCLE == 'h5 ? c_PC_INC | c_ALU_OUT | c_A_IN | c_FLAGS_UPDATE : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h30) ? // SUB; B = RAM[IMM4], A -= B r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_RAM_OUT | c_MAR_IN : r_T_CYCLE == 'h4 ? c_RAM_OUT | c_B_IN : r_T_CYCLE == 'h5 ? c_PC_INC | c_ALU_OUT | c_A_IN | c_FLAGS_UPDATE | c_ALU_SUB : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h40) ? // LDI; A = IMM4 r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_PC_INC | c_RAM_OUT | c_A_IN : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h50) ? // ADDI; A += IMM4 r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_PC_INC | c_RAM_OUT | c_B_IN : r_T_CYCLE == 'h4 ? c_ALU_OUT | c_A_IN | c_FLAGS_UPDATE : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h60) ? // SUBI; A -= IMM4 r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_PC_INC | c_RAM_OUT | c_B_IN : r_T_CYCLE == 'h4 ? c_ALU_OUT | c_ALU_SUB | c_A_IN | c_FLAGS_UPDATE : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h70) ? // STA; RAM[IMM4] = A r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_RAM_OUT | c_MAR_IN : r_T_CYCLE == 'h4 ? c_PC_INC | c_A_OUT | c_RAM_IN : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h80) ? // JMP; PC = IMM4 r_T_CYCLE == 'h2 ? c_PC_OUT | c_MAR_IN : r_T_CYCLE == 'h3 ? c_PC_INC | c_RAM_OUT | c_JUMP : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'h90) ? // JZ; if(ZERO_FLAG) PC = IMM4 r_T_CYCLE == 'h2 ? i_ZERO_FLAG ? (c_PC_OUT | c_MAR_IN) : 0 : r_T_CYCLE == 'h3 ? i_ZERO_FLAG ? (c_PC_INC | c_RAM_OUT | c_JUMP) : 0 : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'hA0) ? // JC; if(CARRY_FLAG) PC = IMM4 - r_T_CYCLE == 'h2 ? i_CARRY_FLAG ? (c_PC_OUT | c_MAR_IN) : 0 : - r_T_CYCLE == 'h3 ? i_CARRY_FLAG ? (c_PC_INC | c_RAM_OUT | c_JUMP) : c_PC_INC : - 0 : + r_T_CYCLE == 'h2 ? i_CARRY_FLAG ? (c_PC_OUT | c_MAR_IN) : c_PC_INC | c_CU_ADVANCE : + r_T_CYCLE == 'h3 ? i_CARRY_FLAG ? (c_PC_INC | c_RAM_OUT | c_JUMP) : c_PC_INC | c_CU_ADVANCE : + c_CU_ADVANCE : // Instruction 0x0B is unimplemented // Instruction 0x0C is unimplemented // Instruction 0x0D is unimplemented (i_IR_DATA == 'hE0) ? // OUT; Display A r_T_CYCLE == 'h2 ? c_A_OUT | c_OUT_IN : - 0 : + c_CU_ADVANCE : (i_IR_DATA == 'hF0) ? // HLT; Halt the clock c_HALT : - 0; + c_CU_ADVANCE; endmodule \ No newline at end of file diff --git a/rtl/XDN.v b/rtl/XDN.v index e95e4a7..80582e6 100644 --- a/rtl/XDN.v +++ b/rtl/XDN.v @@ -209,6 +209,7 @@ module XDN RAM_WRITE_BUS ); + wire CU_ADVANCE; wire [CONTROL_WIDTH - 1:0] CONTROL_SIGNALS; ControlUnit #(DATA_WIDTH) cu @@ -217,6 +218,7 @@ module XDN IR_DATA, ZERO_FLAG, CARRY_FLAG, + CU_ADVANCE, CLEAR, CLEAR_n, @@ -231,6 +233,7 @@ module XDN assign CLOCK_STEP_TOGGLE = i_BTN_0; assign CLOCK_STEP = i_BTN_1; + assign CU_ADVANCE = CONTROL_SIGNALS[CU_ADVANCE_INDEX]; assign CLOCK_HALT = CONTROL_SIGNALS[HALT_INDEX]; assign MAR_READ_BUS = CONTROL_SIGNALS[MAR_IN_INDEX]; assign MAR_WRITE_BUS = 0;