Better internal opcode table

[x93bd0]

Checklist

• I believe this feature/suggestion would be benefitial and/or necessary to this project.
• I have searched for the same request on the issue tracker.

What's your idea?

The MOS6502 has instructions that can be encoded better by compressing similar ones into "super" instructions. Those instructions can share one arm in the VM's match, making code execution faster and making the final binary more lightweight.

Must do:

• The ADC and SBC instructions only differ by one operation (SBC negates the memory first, then it executes ADC), so they can be compacted as ADDER (not-a-mnemonic, PoC) with a flag that activates SBC.
• All of the branch instructions can be compacted as BRANCH, because they have the same code, only differing in the check of the flag status, and the flag itself.

Why would this be necessary?

I believe this will improve performance.