From f30850d198b03e482692d2c347d7870e3f68a88b Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Mon, 14 May 2012 15:46:18 +0200 Subject: [PATCH 1/6] omap4: tune voltage settings Signed-off-by: Sebastien Jan --- arch/arm/mach-omap2/voltage.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 2996b94e0131ae..c9f24283619be2 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -140,8 +140,8 @@ struct omap_voltage_notifier { #define OMAP3630_VP2_VLIMITTO_VDDMIN 900000 #define OMAP3630_VP2_VLIMITTO_VDDMAX 1200000 -#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 830000 -#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 1410000 +#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 750000 +#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 1380000 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 830000 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 1260000 #define OMAP4_VP_CORE_VLIMITTO_VDDMIN 830000 @@ -149,12 +149,7 @@ struct omap_voltage_notifier { #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 -#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 -#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 - -#define OMAP4_VP_CONFIG_ERROROFFSET 0x00 -#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 -#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 +#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x05 #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 #define OMAP5_VP_MPU_VLIMITTO_VDDMIN 830000 From 1f0e9e4818efc3f41310f22b5a468c706fe17156 Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Mon, 14 May 2012 15:46:59 +0200 Subject: [PATCH 2/6] tps6236x: fix DEF_SET_REG Signed-off-by: Sebastien Jan --- arch/arm/mach-omap2/omap_tps6236x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap_tps6236x.c b/arch/arm/mach-omap2/omap_tps6236x.c index 39f1a7216525c6..0ecb7af2a6e14e 100644 --- a/arch/arm/mach-omap2/omap_tps6236x.c +++ b/arch/arm/mach-omap2/omap_tps6236x.c @@ -42,7 +42,7 @@ /* I2C access parameters */ #define I2C_TPS6236X_SLAVE_ADDR 0x60 -#define DEF_SET_REG(VSEL0, VSEL1) (((VSEL1) << 1) | ((VSEL0) << 0) & 0x3) +#define DEF_SET_REG(VSEL0, VSEL1) (((VSEL1) << 1| (VSEL0) << 0) & 0x3) #define REG_TPS6236X_SET_0 0x00 #define REG_TPS6236X_SET_1 0x01 #define REG_TPS6236X_SET_2 0x02 From 49e1e47815ff024c13aaf06dd64be08885be03cc Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Mon, 21 May 2012 11:06:15 +0200 Subject: [PATCH 3/6] omap4460: fix SR CORE domain offsets On 4460, the CORE domain is powered by SMPS1 instead of SPMS3, so update the PMIC offsets accordingly. (Symptom was: SR never converges on CORE domain and keeps a default high voltage) Signed-off-by: Sebastien Jan --- arch/arm/mach-omap2/omap_twl4030.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-omap2/omap_twl4030.c b/arch/arm/mach-omap2/omap_twl4030.c index a563f67cae4ec5..2fb7fed9ef6d9f 100644 --- a/arch/arm/mach-omap2/omap_twl4030.c +++ b/arch/arm/mach-omap2/omap_twl4030.c @@ -260,6 +260,12 @@ int __init omap_twl4030_init(void) omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; } + if (cpu_is_omap446x()) { + /* use SMPS1 for CORE instead of SMPS3 on 4430 */ + omap_twl_map[1].pmic_data->volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG; + omap_twl_map[1].pmic_data->cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG; + } + if (cpu_is_omap443x()) return omap_pmic_register_data(&omap_twl_map[0]); else if (cpu_is_omap446x()) /* mpu from tps6236x */ From df97a52e8bb3ebe12f21e99832b65d652409ec86 Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Mon, 14 May 2012 15:48:57 +0200 Subject: [PATCH 4/6] omap4: Voltage tunings - get in line with reference settings for SR. - remove remaining references to OPP50 for IVA and CORE Signed-off-by: Sebastien Jan --- arch/arm/mach-omap2/omap_twl4030.c | 3 ++- arch/arm/mach-omap2/opp4xxx_data.c | 17 +++++++---------- arch/arm/mach-omap2/voltage.h | 4 ++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-omap2/omap_twl4030.c b/arch/arm/mach-omap2/omap_twl4030.c index 2fb7fed9ef6d9f..100e94709b0da6 100644 --- a/arch/arm/mach-omap2/omap_twl4030.c +++ b/arch/arm/mach-omap2/omap_twl4030.c @@ -30,6 +30,7 @@ #define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 #define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 +#define OMAP4_VP_CORE_VSTEPMAX_VSTEPMAX 0x04 #define OMAP4_SRI2C_SLAVE_ADDR 0x12 #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 #define OMAP4_VDD_MPU_SR_CMD_REG 0x56 @@ -217,7 +218,7 @@ static struct omap_voltdm_pmic omap443x_core_pmic = { .switch_on_time = 549, .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, - .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, + .vp_vstepmax = OMAP4_VP_CORE_VSTEPMAX_VSTEPMAX, .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index e91aaa1220286d..39823b7a555ffb 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -180,10 +180,10 @@ static struct omap_opp_def __initdata omap443x_opp_def_list[] = { #define OMAP4460_VDD_MPU_OPPNITRO_UV 1380000 struct omap_volt_data omap446x_vdd_mpu_volt_data[] = { - VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP), - VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP), - VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP), - VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27, OMAP_ABB_FAST_OPP), + VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf3, 0x11, OMAP_ABB_NOMINAL_OPP), + VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf8, 0x24, OMAP_ABB_NOMINAL_OPP), + VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x25, OMAP_ABB_NOMINAL_OPP), + VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfb, 0x2f, OMAP_ABB_FAST_OPP), VOLT_DATA_DEFINE(0, 0, 0, 0, 0), }; @@ -194,7 +194,7 @@ struct omap_volt_data omap446x_vdd_mpu_volt_data[] = { struct omap_volt_data omap446x_vdd_iva_volt_data[] = { VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP), - VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP), + VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf8, 0x16, OMAP_ABB_NOMINAL_OPP), VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP), VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP), VOLT_DATA_DEFINE(0, 0, 0, 0, 0), @@ -205,8 +205,7 @@ struct omap_volt_data omap446x_vdd_iva_volt_data[] = { #define OMAP4460_VDD_CORE_OPP100_OV_UV 1250000 struct omap_volt_data omap446x_vdd_core_volt_data[] = { - VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c, OMAP_ABB_NO_LDO), - VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16, OMAP_ABB_NO_LDO), + VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf8, 0x17, OMAP_ABB_NO_LDO), VOLT_DATA_DEFINE(0, 0, 0, 0, 0), }; @@ -224,7 +223,7 @@ struct omap_vc_param omap446x_core_vc_data = { /* OMAP 4460 MPU Core VDD dependency table */ static struct omap_vdd_dep_volt omap446x_vdd_mpu_core_dep_data[] = { - {.main_vdd_volt = OMAP4460_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP50_UV}, + {.main_vdd_volt = OMAP4460_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV}, {.main_vdd_volt = OMAP4460_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV}, {.main_vdd_volt = OMAP4460_VDD_MPU_OPPTURBO_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV}, {.main_vdd_volt = OMAP4460_VDD_MPU_OPPNITRO_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV}, @@ -272,10 +271,8 @@ static struct omap_opp_def __initdata omap446x_opp_def_list[] = { OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV), /* L3 OPP2 - OPP100 */ OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV), -// OPP_INITIALIZER("l3_main_1", "dpll_core_m5x2_ck", "core", true, 400000000, OMAP4460_VDD_CORE_OPP100_UV), /* IVA OPP1 - OPP50 */ - OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV), /* IVA OPP2 - OPP100 */ OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV), /* diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index c9f24283619be2..5989762d1fffac 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -144,8 +144,8 @@ struct omap_voltage_notifier { #define OMAP4_VP_MPU_VLIMITTO_VDDMAX 1380000 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 830000 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 1260000 -#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 830000 -#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 1200000 +#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 750000 +#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 1250000 #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 From 5a0d9ae41efaced71dfbd2e563b6f4b95e6db67a Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Tue, 22 May 2012 11:48:13 +0200 Subject: [PATCH 5/6] UBUNTU: Config: set cpu-freq governors as static Signed-off-by: Sebastien Jan --- debian.ti-omap4/config/config.common.ubuntu | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/debian.ti-omap4/config/config.common.ubuntu b/debian.ti-omap4/config/config.common.ubuntu index 9db891a622705a..232629491ed77d 100644 --- a/debian.ti-omap4/config/config.common.ubuntu +++ b/debian.ti-omap4/config/config.common.ubuntu @@ -603,12 +603,12 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y # CONFIG_CPU_FREQ_STAT_DETAILS is not set CONFIG_CPU_FREQ_TABLE=y From 6c1414dec4afabd90a0e7fc5b2cb6e0f25d0f950 Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Wed, 23 May 2012 14:47:55 +0200 Subject: [PATCH 6/6] aess: hack: disable runtime-pm Runtime PM triggers a hwmod_idle of aess that fails all the time. This leaves SR deactivated for IVA domain. While root cause is not identified and while waiting for a proper fix, use this hack to prevent runtime PM on aess. This 'fixes' SR for IVA domain. Without this hack, we get '_wait_target_disable failed' errors. See below with additional custom trace and stack dump (the point was to trace when SR is disabled): [ 44.294586] omap_hwmod: aess: _wait_target_disable failed [ 44.294586] sebj - clkdm_hwmod_disable - aess [ 44.294616] sebj - omap_sr_disable - iva[] (unwind_backtrace+0x0/0xec) from [] (dump_stack+0x20/0x24) [ 44.294647] [] (dump_stack+0x20/0x24) from [] (omap_sr_disable+0x48/0x88) [ 44.294647] [] (omap_sr_disable+0x48/0x88) from [] (voltdm_pwrdm_disable+0x48/0x98) [ 44.294677] [] (voltdm_pwrdm_disable+0x48/0x98) from [] (pwrdm_clkdm_disable+0x44/0x48) [ 44.294677] [] (pwrdm_clkdm_disable+0x44/0x48) from [] (clkdm_usecount_dec+0x44/0x4c) [ 44.294708] [] (clkdm_usecount_dec+0x44/0x4c) from [] (_clkdm_clk_hwmod_disable+0x5c/0xc8) [ 44.294708] [] (_clkdm_clk_hwmod_disable+0x5c/0xc8) from [] (clkdm_hwmod_disable+0x48/0x5c) [ 44.294738] [] (clkdm_hwmod_disable+0x48/0x5c) from [] (_idle+0x168/0x1ac) [ 44.294738] [] (_idle+0x168/0x1ac) from [] (omap_hwmod_idle+0x34/0x50) [ 44.294769] [] (omap_hwmod_idle+0x34/0x50) from [] (omap_device_idle_hwmods+0x30/0x44) [ 44.294769] [] (omap_device_idle_hwmods+0x30/0x44) from [] (_omap_device_deactivate+0x68/0x130) [ 44.294799] [] (_omap_device_deactivate+0x68/0x130) from [] (omap_device_idle+0x50/0x64) [ 44.294799] [] (omap_device_idle+0x50/0x64) from [] (_od_runtime_suspend+0x2c/0x34) [ 44.294830] [] (_od_runtime_suspend+0x2c/0x34) from [] (__rpm_callback+0x48/0x78) [ 44.294830] [] (__rpm_callback+0x48/0x78) from [] (rpm_suspend+0x3d0/0x668) [ 44.294860] [] (rpm_suspend+0x3d0/0x668) from [] (__pm_runtime_suspend+0x6c/0x84) [ 44.294860] [] (__pm_runtime_suspend+0x6c/0x84) from [] (pm_generic_runtime_idle+0x54/0x5c) [ 44.294891] [] (pm_generic_runtime_idle+0x54/0x5c) from [] (_od_runtime_idle+0x18/0x1c) [ 44.294891] [] (_od_runtime_idle+0x18/0x1c) from [] (__rpm_callback+0x48/0x78) [ 44.294921] [] (__rpm_callback+0x48/0x78) from [] (rpm_idle+0x1f0/0x2c8) [ 44.294921] [] (rpm_idle+0x1f0/0x2c8) from [] (__pm_runtime_idle+0x6c/0x84) [ 44.294952] [] (__pm_runtime_idle+0x6c/0x84) from [] (ul_mux_put_route+0x110/0x120) [ 44.294952] [] (ul_mux_put_route+0x110/0x120) from [] (snd_ctl_ioctl+0x4a4/0x848) [ 44.294982] [] (snd_ctl_ioctl+0x4a4/0x848) from [] (do_vfs_ioctl+0x4f8/0x56c) [ 44.294982] [] (do_vfs_ioctl+0x4f8/0x56c) from [] (sys_ioctl+0x60/0x84) [ 44.295013] [] (sys_ioctl+0x60/0x84) from [] (ret_fast_syscall+0x0/0x30) Signed-off-by: Sebastien Jan --- sound/soc/omap/omap-abe-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/omap/omap-abe-core.c b/sound/soc/omap/omap-abe-core.c index 689c87feac77e6..3a9feacdf7c507 100644 --- a/sound/soc/omap/omap-abe-core.c +++ b/sound/soc/omap/omap-abe-core.c @@ -288,6 +288,7 @@ static int abe_probe(struct snd_soc_platform *platform) /* aess_clk has to be enabled to access hal register. * Disable the clk after it has been used. */ + pm_runtime_disable(abe->dev); pm_runtime_get_sync(abe->dev); abe->aess = omap_abe_port_mgr_get();