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feat: updating from newer svd2rust (#89)
Co-authored-by: lucasbrendel <1765755+lucasbrendel@users.noreply.github.com>
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‎src/can.rs

Lines changed: 33 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,149 +1,139 @@
11
#[repr(C)]
22
#[doc = "Register block"]
33
pub struct RegisterBlock {
4-
clc: Clc,
4+
clc: CLC,
55
_reserved1: [u8; 0x04],
6-
id: Id,
7-
fdr: Fdr,
6+
id: ID,
7+
fdr: FDR,
88
_reserved3: [u8; 0xf0],
9-
list: [List; 8],
9+
list: [LIST; 8],
1010
_reserved4: [u8; 0x20],
11-
mspnd: [Mspnd; 8],
11+
mspnd: [MSPND; 8],
1212
_reserved5: [u8; 0x20],
13-
msid: [Msid; 8],
13+
msid: [MSID; 8],
1414
_reserved6: [u8; 0x20],
15-
msimask: Msimask,
16-
panctr: Panctr,
17-
mcr: Mcr,
18-
mitr: Mitr,
15+
msimask: MSIMASK,
16+
panctr: PANCTR,
17+
mcr: MCR,
18+
mitr: MITR,
1919
}
2020
impl RegisterBlock {
2121
#[doc = "0x00 - CAN Clock Control Register"]
2222
#[inline(always)]
23-
pub const fn clc(&self) -> &Clc {
23+
pub const fn clc(&self) -> &CLC {
2424
&self.clc
2525
}
2626
#[doc = "0x08 - Module Identification Register"]
2727
#[inline(always)]
28-
pub const fn id(&self) -> &Id {
28+
pub const fn id(&self) -> &ID {
2929
&self.id
3030
}
3131
#[doc = "0x0c - CAN Fractional Divider Register"]
3232
#[inline(always)]
33-
pub const fn fdr(&self) -> &Fdr {
33+
pub const fn fdr(&self) -> &FDR {
3434
&self.fdr
3535
}
3636
#[doc = "0x100..0x120 - List Register"]
3737
#[inline(always)]
38-
pub const fn list(&self, n: usize) -> &List {
38+
pub const fn list(&self, n: usize) -> &LIST {
3939
&self.list[n]
4040
}
4141
#[doc = "Iterator for array of:"]
4242
#[doc = "0x100..0x120 - List Register"]
4343
#[inline(always)]
44-
pub fn list_iter(&self) -> impl Iterator<Item = &List> {
44+
pub fn list_iter(&self) -> impl Iterator<Item = &LIST> {
4545
self.list.iter()
4646
}
4747
#[doc = "0x140..0x160 - Message Pending Register"]
4848
#[inline(always)]
49-
pub const fn mspnd(&self, n: usize) -> &Mspnd {
49+
pub const fn mspnd(&self, n: usize) -> &MSPND {
5050
&self.mspnd[n]
5151
}
5252
#[doc = "Iterator for array of:"]
5353
#[doc = "0x140..0x160 - Message Pending Register"]
5454
#[inline(always)]
55-
pub fn mspnd_iter(&self) -> impl Iterator<Item = &Mspnd> {
55+
pub fn mspnd_iter(&self) -> impl Iterator<Item = &MSPND> {
5656
self.mspnd.iter()
5757
}
5858
#[doc = "0x180..0x1a0 - Message Index Register"]
5959
#[inline(always)]
60-
pub const fn msid(&self, n: usize) -> &Msid {
60+
pub const fn msid(&self, n: usize) -> &MSID {
6161
&self.msid[n]
6262
}
6363
#[doc = "Iterator for array of:"]
6464
#[doc = "0x180..0x1a0 - Message Index Register"]
6565
#[inline(always)]
66-
pub fn msid_iter(&self) -> impl Iterator<Item = &Msid> {
66+
pub fn msid_iter(&self) -> impl Iterator<Item = &MSID> {
6767
self.msid.iter()
6868
}
6969
#[doc = "0x1c0 - Message Index Mask Register"]
7070
#[inline(always)]
71-
pub const fn msimask(&self) -> &Msimask {
71+
pub const fn msimask(&self) -> &MSIMASK {
7272
&self.msimask
7373
}
7474
#[doc = "0x1c4 - Panel Control Register"]
7575
#[inline(always)]
76-
pub const fn panctr(&self) -> &Panctr {
76+
pub const fn panctr(&self) -> &PANCTR {
7777
&self.panctr
7878
}
7979
#[doc = "0x1c8 - Module Control Register"]
8080
#[inline(always)]
81-
pub const fn mcr(&self) -> &Mcr {
81+
pub const fn mcr(&self) -> &MCR {
8282
&self.mcr
8383
}
8484
#[doc = "0x1cc - Module Interrupt Trigger Register"]
8585
#[inline(always)]
86-
pub const fn mitr(&self) -> &Mitr {
86+
pub const fn mitr(&self) -> &MITR {
8787
&self.mitr
8888
}
8989
}
9090
#[doc = "CLC (rw) register accessor: CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clc`]
9191
module"]
92-
#[doc(alias = "CLC")]
93-
pub type Clc = crate::Reg<clc::ClcSpec>;
92+
pub type CLC = crate::Reg<clc::CLC_SPEC>;
9493
#[doc = "CAN Clock Control Register"]
9594
pub mod clc;
9695
#[doc = "ID (r) register accessor: Module Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
9796
module"]
98-
#[doc(alias = "ID")]
99-
pub type Id = crate::Reg<id::IdSpec>;
97+
pub type ID = crate::Reg<id::ID_SPEC>;
10098
#[doc = "Module Identification Register"]
10199
pub mod id;
102100
#[doc = "FDR (rw) register accessor: CAN Fractional Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdr`]
103101
module"]
104-
#[doc(alias = "FDR")]
105-
pub type Fdr = crate::Reg<fdr::FdrSpec>;
102+
pub type FDR = crate::Reg<fdr::FDR_SPEC>;
106103
#[doc = "CAN Fractional Divider Register"]
107104
pub mod fdr;
108105
#[doc = "LIST (r) register accessor: List Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`list::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@list`]
109106
module"]
110-
#[doc(alias = "LIST")]
111-
pub type List = crate::Reg<list::ListSpec>;
107+
pub type LIST = crate::Reg<list::LIST_SPEC>;
112108
#[doc = "List Register"]
113109
pub mod list;
114110
#[doc = "MSPND (rw) register accessor: Message Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mspnd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mspnd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mspnd`]
115111
module"]
116-
#[doc(alias = "MSPND")]
117-
pub type Mspnd = crate::Reg<mspnd::MspndSpec>;
112+
pub type MSPND = crate::Reg<mspnd::MSPND_SPEC>;
118113
#[doc = "Message Pending Register"]
119114
pub mod mspnd;
120115
#[doc = "MSID (r) register accessor: Message Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msid`]
121116
module"]
122-
#[doc(alias = "MSID")]
123-
pub type Msid = crate::Reg<msid::MsidSpec>;
117+
pub type MSID = crate::Reg<msid::MSID_SPEC>;
124118
#[doc = "Message Index Register"]
125119
pub mod msid;
126120
#[doc = "MSIMASK (rw) register accessor: Message Index Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msimask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msimask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msimask`]
127121
module"]
128-
#[doc(alias = "MSIMASK")]
129-
pub type Msimask = crate::Reg<msimask::MsimaskSpec>;
122+
pub type MSIMASK = crate::Reg<msimask::MSIMASK_SPEC>;
130123
#[doc = "Message Index Mask Register"]
131124
pub mod msimask;
132125
#[doc = "PANCTR (rw) register accessor: Panel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`panctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`panctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@panctr`]
133126
module"]
134-
#[doc(alias = "PANCTR")]
135-
pub type Panctr = crate::Reg<panctr::PanctrSpec>;
127+
pub type PANCTR = crate::Reg<panctr::PANCTR_SPEC>;
136128
#[doc = "Panel Control Register"]
137129
pub mod panctr;
138130
#[doc = "MCR (rw) register accessor: Module Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
139131
module"]
140-
#[doc(alias = "MCR")]
141-
pub type Mcr = crate::Reg<mcr::McrSpec>;
132+
pub type MCR = crate::Reg<mcr::MCR_SPEC>;
142133
#[doc = "Module Control Register"]
143134
pub mod mcr;
144135
#[doc = "MITR (w) register accessor: Module Interrupt Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mitr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mitr`]
145136
module"]
146-
#[doc(alias = "MITR")]
147-
pub type Mitr = crate::Reg<mitr::MitrSpec>;
137+
pub type MITR = crate::Reg<mitr::MITR_SPEC>;
148138
#[doc = "Module Interrupt Trigger Register"]
149139
pub mod mitr;

‎src/can/clc.rs

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,70 +1,70 @@
11
#[doc = "Register `CLC` reader"]
2-
pub type R = crate::R<ClcSpec>;
2+
pub type R = crate::R<CLC_SPEC>;
33
#[doc = "Register `CLC` writer"]
4-
pub type W = crate::W<ClcSpec>;
4+
pub type W = crate::W<CLC_SPEC>;
55
#[doc = "Field `DISR` reader - Module Disable Request Bit"]
6-
pub type DisrR = crate::BitReader;
6+
pub type DISR_R = crate::BitReader;
77
#[doc = "Field `DISR` writer - Module Disable Request Bit"]
8-
pub type DisrW<'a, REG> = crate::BitWriter<'a, REG>;
8+
pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG>;
99
#[doc = "Field `DISS` reader - Module Disable Status Bit"]
10-
pub type DissR = crate::BitReader;
10+
pub type DISS_R = crate::BitReader;
1111
#[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
12-
pub type EdisR = crate::BitReader;
12+
pub type EDIS_R = crate::BitReader;
1313
#[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
14-
pub type EdisW<'a, REG> = crate::BitWriter<'a, REG>;
14+
pub type EDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
1515
#[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
16-
pub type SbweW<'a, REG> = crate::BitWriter<'a, REG>;
16+
pub type SBWE_W<'a, REG> = crate::BitWriter<'a, REG>;
1717
impl R {
1818
#[doc = "Bit 0 - Module Disable Request Bit"]
1919
#[inline(always)]
20-
pub fn disr(&self) -> DisrR {
21-
DisrR::new((self.bits & 1) != 0)
20+
pub fn disr(&self) -> DISR_R {
21+
DISR_R::new((self.bits & 1) != 0)
2222
}
2323
#[doc = "Bit 1 - Module Disable Status Bit"]
2424
#[inline(always)]
25-
pub fn diss(&self) -> DissR {
26-
DissR::new(((self.bits >> 1) & 1) != 0)
25+
pub fn diss(&self) -> DISS_R {
26+
DISS_R::new(((self.bits >> 1) & 1) != 0)
2727
}
2828
#[doc = "Bit 3 - Sleep Mode Enable Control"]
2929
#[inline(always)]
30-
pub fn edis(&self) -> EdisR {
31-
EdisR::new(((self.bits >> 3) & 1) != 0)
30+
pub fn edis(&self) -> EDIS_R {
31+
EDIS_R::new(((self.bits >> 3) & 1) != 0)
3232
}
3333
}
3434
impl W {
3535
#[doc = "Bit 0 - Module Disable Request Bit"]
3636
#[inline(always)]
3737
#[must_use]
38-
pub fn disr(&mut self) -> DisrW<ClcSpec> {
39-
DisrW::new(self, 0)
38+
pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
39+
DISR_W::new(self, 0)
4040
}
4141
#[doc = "Bit 3 - Sleep Mode Enable Control"]
4242
#[inline(always)]
4343
#[must_use]
44-
pub fn edis(&mut self) -> EdisW<ClcSpec> {
45-
EdisW::new(self, 3)
44+
pub fn edis(&mut self) -> EDIS_W<CLC_SPEC> {
45+
EDIS_W::new(self, 3)
4646
}
4747
#[doc = "Bit 4 - Module Suspend Bit Write Enable for OCDS"]
4848
#[inline(always)]
4949
#[must_use]
50-
pub fn sbwe(&mut self) -> SbweW<ClcSpec> {
51-
SbweW::new(self, 4)
50+
pub fn sbwe(&mut self) -> SBWE_W<CLC_SPEC> {
51+
SBWE_W::new(self, 4)
5252
}
5353
}
5454
#[doc = "CAN Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55-
pub struct ClcSpec;
56-
impl crate::RegisterSpec for ClcSpec {
55+
pub struct CLC_SPEC;
56+
impl crate::RegisterSpec for CLC_SPEC {
5757
type Ux = u32;
5858
}
5959
#[doc = "`read()` method returns [`clc::R`](R) reader structure"]
60-
impl crate::Readable for ClcSpec {}
60+
impl crate::Readable for CLC_SPEC {}
6161
#[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
62-
impl crate::Writable for ClcSpec {
62+
impl crate::Writable for CLC_SPEC {
6363
type Safety = crate::Unsafe;
6464
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
6565
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
6666
}
6767
#[doc = "`reset()` method sets CLC to value 0x03"]
68-
impl crate::Resettable for ClcSpec {
68+
impl crate::Resettable for CLC_SPEC {
6969
const RESET_VALUE: u32 = 0x03;
7070
}

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