From 9307cfd89dfb4de5777c869b59bdbee3bc8ccc65 Mon Sep 17 00:00:00 2001 From: Daniel Pieczko Date: Wed, 6 Oct 2021 08:54:43 +0100 Subject: [PATCH 01/57] Apply skipDefaultCheckout() to the whole Jenkins pipeline --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index c19ede0..be9c99a 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,6 +4,9 @@ getApproval() pipeline { agent none + options { + skipDefaultCheckout() + } parameters { string( name: 'TOOLS_VERSION', @@ -21,9 +24,6 @@ pipeline { REPO = 'lib_spi' VIEW = getViewName(REPO) } - options { - skipDefaultCheckout() - } stages { stage('Get view') { steps { From 321fcb3b4000dd0afe81ae48ec15ea334f999544 Mon Sep 17 00:00:00 2001 From: kieran-kohtz <89012045+kieran-kohtz@users.noreply.github.com> Date: Wed, 6 Oct 2021 10:14:30 +0100 Subject: [PATCH 02/57] Delete LICENSE.rst --- lib_spi/LICENSE.rst | 84 --------------------------------------------- 1 file changed, 84 deletions(-) delete mode 100644 lib_spi/LICENSE.rst diff --git a/lib_spi/LICENSE.rst b/lib_spi/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/lib_spi/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. 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From 06b1304716a0fa02f77289de153cdcff63ccc3b6 Mon Sep 17 00:00:00 2001 From: Daniel Pieczko Date: Fri, 8 Oct 2021 15:19:25 +0100 Subject: [PATCH 03/57] Restructure Jenkinsfile --- Jenkinsfile | 75 +++++++++++++++++++++-------------------------------- 1 file changed, 30 insertions(+), 45 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index be9c99a..9c119c0 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,26 +4,21 @@ getApproval() pipeline { agent none + + environment { + REPO = 'lib_spi' + VIEW = getViewName(REPO) + } + options { skipDefaultCheckout() } - parameters { - string( - name: 'TOOLS_VERSION', - defaultValue: '15.1.1', - description: 'The tools version to build with (check /projects/tools/ReleasesTools/)' - ) - } + stages { stage('Standard build and XS1/2 tests') { agent { label 'x86_64&&brew' } - - environment { - REPO = 'lib_spi' - VIEW = getViewName(REPO) - } stages { stage('Get view') { steps { @@ -56,7 +51,6 @@ pipeline { stash name: path.split("/")[-1], includes: 'bin/*, ' } } - stash name: "reset_xtags", includes: "**/python/reset_xtags.py" // Build Tests dir('legacy_tests/') { @@ -98,10 +92,6 @@ pipeline { agent{ label 'x86_64&&brew&&macOS' } - environment { - REPO = 'lib_spi' - VIEW = getViewName(REPO) - } stages{ stage('Get view') { steps { @@ -122,7 +112,7 @@ pipeline { } post { cleanup { - xcoreCleanSandbox() + cleanWs() } } } @@ -131,42 +121,37 @@ pipeline { agent { label 'xcore.ai-explorer' } - environment { - // '/XMOS/tools' from get_tools.py and rest from tools installers - TOOLS_PATH = "/XMOS/tools/${params.TOOLS_VERSION}/XMOS/XTC/${params.TOOLS_VERSION}" - } stages{ - stage('Install Dependencies') { + stage('Get view') { steps { - sh '/XMOS/get_tools.py ' + params.TOOLS_VERSION - installDependencies() - } - } - stage('Reset XTAGs'){ - steps{ - toolsEnv(TOOLS_PATH) { // load xmos tools - unstash "reset_xtags" - sh 'rm -f ~/.xtag/acquired' //Hacky but ensure it always works even when previous failed run left lock file present - withVenv{ - sh "python -m pip install git+git://github0.xmos.com/xmos-int/xtagctl.git@v1.3.1" - sh "python python/reset_xtags.py 2" //Note 2 xtags to reset on xcore.ai-explorer + xcorePrepareSandbox("${VIEW}", "${REPO}") + dir("${REPO}") { + viewEnv { + withVenv { + sh "pip install -e ${WORKSPACE}/xtagctl" + sh "xtagctl reset_all XCORE-AI-EXPLORER" + } } } } } stage('xrun'){ steps{ - toolsEnv(TOOLS_PATH) { // load xmos tools - forAllMatch("examples", "AN*/") { path -> - unstash path.split("/")[-1] - } - // Run the tests and look for what we expect - sh 'xrun --io --id 0 bin/AN00160_using_SPI_master.xe &> AN00160_using_SPI_master.txt' - // Look for config register 0 value from wifi module - sh 'grep 2005400 AN00160_using_SPI_master.txt' + dir("${REPO}") { + viewEnv { + withVenv { + forAllMatch("examples", "AN*/") { path -> + unstash path.split("/")[-1] + } + // Run the tests and look for what we expect + sh 'xrun --io --id 0 bin/AN00160_using_SPI_master.xe &> AN00160_using_SPI_master.txt' + // Look for config register 0 value from wifi module + sh 'grep 2005400 AN00160_using_SPI_master.txt' - //Just run this and ensure we get no error (like wrong arch). We have no SPI master HW so cannot test it - sh 'xrun --id 0 bin/AN00161_using_SPI_slave.xe' + //Just run this and ensure we get no error (like wrong arch). We have no SPI master HW so cannot test it + sh 'xrun --id 0 bin/AN00161_using_SPI_slave.xe' + } + } } } } From d2d26f11b8dd61152d9dce95551ebfedd8ca9bfb Mon Sep 17 00:00:00 2001 From: Daniel Pieczko Date: Fri, 8 Oct 2021 15:19:53 +0100 Subject: [PATCH 04/57] Delete unused python/reset_xtags.py --- python/reset_xtags.py | 31 ------------------------------- 1 file changed, 31 deletions(-) delete mode 100644 python/reset_xtags.py diff --git a/python/reset_xtags.py b/python/reset_xtags.py deleted file mode 100644 index 62e0f3b..0000000 --- a/python/reset_xtags.py +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright 2020-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -""" This script is used to reset one or more targets using xtagctl -""" -import traceback -import xtagctl -import sys - -if __name__ == "__main__": - if len(sys.argv) > 1: - num_xtags = int(sys.argv[1]) - else: - num_xtags = 1 - - targets = ["XCORE-AI-EXPLORER"] * num_xtags - print(f"XTAGCTL acquiring targets: {targets}") - with xtagctl.acquire(*targets, timeout=10) as adapter_ids: - if type(adapter_ids) is str: - adapter_id_list = [adapter_ids] - else: - adapter_id_list = adapter_ids - print(adapter_id_list) - - for adapter_id in adapter_id_list: - print(f"acquiring adapter_id: {adapter_id}") - try: - xtagctl.reset_adapter(adapter_id) - print("Successfully reset XTAG") - except xtagctl.XtagctlException: - print("WARNING: Could not reset xtag!") - traceback.print_exc() From c5e18716a6096df772f706a2a3634e0c50fb651b Mon Sep 17 00:00:00 2001 From: kieran-kohtz <89012045+kieran-kohtz@users.noreply.github.com> Date: Tue, 8 Mar 2022 16:15:44 +0000 Subject: [PATCH 05/57] Updated jenkins shared library version to v0.18.0 --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 9c119c0..42c4d02 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,4 +1,4 @@ -@Library('xmos_jenkins_shared_library@v0.16.4') _ +@Library('xmos_jenkins_shared_library@v0.18.0') _ getApproval() From 631c4f508d854016506285dca94ca4b5e47b3f98 Mon Sep 17 00:00:00 2001 From: kieran-kohtz <89012045+kieran-kohtz@users.noreply.github.com> Date: Tue, 8 Mar 2022 16:15:45 +0000 Subject: [PATCH 06/57] Removed Brew Labels --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 42c4d02..e997e29 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,7 +17,7 @@ pipeline { stages { stage('Standard build and XS1/2 tests') { agent { - label 'x86_64&&brew' + label 'x86_64' } stages { stage('Get view') { @@ -90,7 +90,7 @@ pipeline { stage('Documentation'){ agent{ - label 'x86_64&&brew&&macOS' + label 'x86_64&&macOS' } stages{ stage('Get view') { @@ -165,7 +165,7 @@ pipeline { stage('Update view files') { agent { - label 'x86_64&&brew' + label 'x86_64' } when { expression { return currentBuild.currentResult == "SUCCESS" } From 88e875872dd8abc7d18565fafa30848a209f9dca Mon Sep 17 00:00:00 2001 From: kieran-kohtz <89012045+kieran-kohtz@users.noreply.github.com> Date: Tue, 8 Mar 2022 16:15:47 +0000 Subject: [PATCH 07/57] Removed Brewfile --- Brewfile | 7 ------- 1 file changed, 7 deletions(-) delete mode 100644 Brewfile diff --git a/Brewfile b/Brewfile deleted file mode 100644 index 2fd6d0b..0000000 --- a/Brewfile +++ /dev/null @@ -1,7 +0,0 @@ -tap 'homebrew/core' - -brew 'perl' -brew 'cpanm' - -brew 'python@2' -brew 'pipenv' From 2b7e4688f29761eac2e29f505e7a886b52235dc7 Mon Sep 17 00:00:00 2001 From: kieran-kohtz <89012045+kieran-kohtz@users.noreply.github.com> Date: Wed, 9 Mar 2022 13:49:03 +0000 Subject: [PATCH 08/57] Update jenkins labels --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index e997e29..8289e4c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,7 +17,7 @@ pipeline { stages { stage('Standard build and XS1/2 tests') { agent { - label 'x86_64' + label 'x86_64 && linux' } stages { stage('Get view') { @@ -165,7 +165,7 @@ pipeline { stage('Update view files') { agent { - label 'x86_64' + label 'x86_64 && linux' } when { expression { return currentBuild.currentResult == "SUCCESS" } From e0d1c1fb0e4886c993529ee426c0eb8f0fca1b68 Mon Sep 17 00:00:00 2001 From: Daniel Pieczko Date: Wed, 10 Aug 2022 13:03:23 +0100 Subject: [PATCH 09/57] Update Python version to 3.10.5 --- legacy_tests/spi_master_checker.py | 26 +++++++++++++------------- legacy_tests/spi_slave_checker.py | 8 ++++---- python/setup.py | 4 ++-- requirements.txt | 4 ++-- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/legacy_tests/spi_master_checker.py b/legacy_tests/spi_master_checker.py index d6f5a96..cb60ad8 100644 --- a/legacy_tests/spi_master_checker.py +++ b/legacy_tests/spi_master_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2022 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest @@ -26,15 +26,15 @@ def run(self): sck_value = xsi.sample_port_pins(self._sck_port) ss_value = [] - for i in range(len(self._ss_ports)): - ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) + for i in range(len(self._ss_ports)): + ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) - print "SPI Master checker started" + print("SPI Master checker started") while True: #first do the setup rx strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) + if strobe_val == 1: + self.wait_for_port_pins_change([self._setup_strobe_port]) expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) @@ -50,8 +50,8 @@ def run(self): all_ss_deserted = True for i in range(len(self._ss_ports)): if (xsi.sample_port_pins(self._ss_ports[i]) == 0): - all_ss_deserted = False - break + all_ss_deserted = False + break while not all_ss_deserted: self.wait_for_port_pins_change(self._ss_ports) @@ -101,7 +101,7 @@ def run(self): for i in range(len(self._ss_ports)): if i != active_slave and xsi.sample_port_pins(self._ss_ports[i]) == 0: error = True - print "Second slave selected during first transaction" + print("Second slave selected during first transaction") if (ss_value == xsi.sample_port_pins(self._ss_ports[active_slave]) and (sck_value == xsi.sample_port_pins(self._sck_port))): continue @@ -146,15 +146,15 @@ def run(self): expected_rx_byte = rx_data[(rx_bit_counter/8) - 1] #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) if expected_rx_byte != rx_byte: - print "ERROR: slave recieved incorrect data Got:%02x Expected:%02x"%(rx_byte, expected_rx_byte) + print("ERROR: slave recieved incorrect data Got:%02x Expected:%02x"%(rx_byte, expected_rx_byte)) error = True rx_byte = 0 else: if clock_edge_number != expected_num_bytes*2*8: error = True - print "ERROR: incorrect number of clock edges at slave {seen}/{expect}".format(seen=clock_edge_number, expect=expected_num_bytes*2*8) + print("ERROR: incorrect number of clock edges at slave {seen}/{expect}".format(seen=clock_edge_number, expect=expected_num_bytes*2*8)) if error: - print "Fail: CPOL:{cpol} CPHA:{cpha} KHz:{freq} MOSI Enabled:{mosi_enabled} MISO Enabled:{miso_enabled}".format( + print("Fail: CPOL:{cpol} CPHA:{cpha} KHz:{freq} MOSI Enabled:{mosi_enabled} MISO Enabled:{miso_enabled}".format( cpol=expected_cpol, cpha=expected_cpha, mosi_enabled = expected_mosi_enabled, miso_enabled = expected_miso_enabled, - freq=expected_frequency_in_khz) + freq=expected_frequency_in_khz)) diff --git a/legacy_tests/spi_slave_checker.py b/legacy_tests/spi_slave_checker.py index 3ee36b2..43c82b6 100644 --- a/legacy_tests/spi_slave_checker.py +++ b/legacy_tests/spi_slave_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2022 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest @@ -28,12 +28,12 @@ def run(self): ss_value = xsi.sample_port_pins(self._ss_port) xsi.drive_port_pins(self._ss_port,1) - print "SPI Slave checker started" + print("SPI Slave checker started") while True: #first do the setup rx strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) + if strobe_val == 1: + self.wait_for_port_pins_change([self._setup_strobe_port]) expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) xsi.drive_port_pins(self._sck_port, expected_cpol) diff --git a/python/setup.py b/python/setup.py index c169625..766b8bb 100644 --- a/python/setup.py +++ b/python/setup.py @@ -1,4 +1,4 @@ -# Copyright 2020-2021 XMOS LIMITED. +# Copyright 2020-2022 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import setuptools @@ -13,7 +13,7 @@ name='lib_spi', packages=setuptools.find_packages(), install_requires=[ - 'flake8~=3.8', + 'flake8~=5.0', ], dependency_links=[ ], diff --git a/requirements.txt b/requirements.txt index 99e7dd7..5b960fd 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,4 +1,4 @@ -# python_version 3.7.6 +# python_version 3.10.5 # # The parse_version_from_requirements() function in the installPipfile.groovy # file of the Jenkins Shared Library uses the python_version comment to set @@ -17,7 +17,7 @@ # pip-install this one as editable using this repository's setup.py file. The # same modules should appear in the setup.py list as given below. -flake8==3.8.3 +flake8==5.0.4 # Development dependencies # From c8e06a16c7585161f6f5984871aa16b72af2f9f2 Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Mon, 23 Sep 2024 17:40:11 +0100 Subject: [PATCH 10/57] Added support for xcommon-cmake --- CHANGELOG.rst | 5 +++++ lib_spi/lib_build_info.cmake | 6 ++++++ 2 files changed, 11 insertions(+) create mode 100644 lib_spi/lib_build_info.cmake diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 4029b95..bcafb1a 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,6 +1,11 @@ SPI library change log ====================== +UNRELEASED +---------- + + * ADDED: Support for XCommon CMake build system + 3.3.0 ----- diff --git a/lib_spi/lib_build_info.cmake b/lib_spi/lib_build_info.cmake new file mode 100644 index 0000000..8b78c21 --- /dev/null +++ b/lib_spi/lib_build_info.cmake @@ -0,0 +1,6 @@ +set(LIB_NAME lib_spi) +set(LIB_VERSION 3.3.0) +set(LIB_INCLUDES api) +set(LIB_DEPENDENT_MODULES "") +set(LIB_COMPILER_FLAGS_spi_async.xc -Wno-reinterpret-alignment) +XMOS_REGISTER_MODULE() From b6caa4050cedd0ca77816896a362aa44045ba4d5 Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Fri, 4 Apr 2025 12:04:08 +0100 Subject: [PATCH 11/57] Remove issue templates --- .../application-note-not-compliant.md | 17 ----------------- .../ISSUE_TEMPLATE/example-not-compliant.md | 18 ------------------ .../ISSUE_TEMPLATE/missing-application-note.md | 10 ---------- .github/ISSUE_TEMPLATE/missing-c-api.md | 10 ---------- .github/ISSUE_TEMPLATE/missing-xcore-test.md | 10 ---------- .github/ISSUE_TEMPLATE/test-not-compliant.md | 16 ---------------- .../top-level-readme-not-compliant.md | 13 ------------- 7 files changed, 94 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/application-note-not-compliant.md delete mode 100644 .github/ISSUE_TEMPLATE/example-not-compliant.md delete mode 100644 .github/ISSUE_TEMPLATE/missing-application-note.md delete mode 100644 .github/ISSUE_TEMPLATE/missing-c-api.md delete mode 100644 .github/ISSUE_TEMPLATE/missing-xcore-test.md delete mode 100644 .github/ISSUE_TEMPLATE/test-not-compliant.md delete mode 100644 .github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md diff --git a/.github/ISSUE_TEMPLATE/application-note-not-compliant.md b/.github/ISSUE_TEMPLATE/application-note-not-compliant.md deleted file mode 100644 index 90723cb..0000000 --- a/.github/ISSUE_TEMPLATE/application-note-not-compliant.md +++ /dev/null @@ -1,17 +0,0 @@ ---- -name: Application Note Issue -about: Template for an Application note issue report -title: examples/ANXXXXX Application Note not compliant -labels: documentation -assignees: '' - ---- - - - - -**Issues:** - - - xdoc-custom RST directives used in the Application Note README - - application note code not compiling for xcore-ai - - application note code not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/example-not-compliant.md b/.github/ISSUE_TEMPLATE/example-not-compliant.md deleted file mode 100644 index 5e68cdb..0000000 --- a/.github/ISSUE_TEMPLATE/example-not-compliant.md +++ /dev/null @@ -1,18 +0,0 @@ ---- -name: Example Issue -about: Template for an example issue report -title: examples/xxx Example not compliant -labels: documentation -assignees: '' - ---- - - - - -**Issues:** - - - convert example to Application Note - - xdoc-custom RST directives used in the README - - example code not compiling for xcore-ai - - example code not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/missing-application-note.md b/.github/ISSUE_TEMPLATE/missing-application-note.md deleted file mode 100644 index 9404dde..0000000 --- a/.github/ISSUE_TEMPLATE/missing-application-note.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing Application Note -about: Template for a Missing Application Note issue report -title: Missing Application Note -labels: documentation -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/missing-c-api.md b/.github/ISSUE_TEMPLATE/missing-c-api.md deleted file mode 100644 index 6230ef7..0000000 --- a/.github/ISSUE_TEMPLATE/missing-c-api.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing C API Issue -about: Template for a Missing C API issue report -title: Missing C API -labels: enhancement -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/missing-xcore-test.md b/.github/ISSUE_TEMPLATE/missing-xcore-test.md deleted file mode 100644 index 866e97c..0000000 --- a/.github/ISSUE_TEMPLATE/missing-xcore-test.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing xCore Test Issue -about: Template for a Missing xCore test issue report -title: Missing xCore test -labels: testing -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/test-not-compliant.md b/.github/ISSUE_TEMPLATE/test-not-compliant.md deleted file mode 100644 index cce3e91..0000000 --- a/.github/ISSUE_TEMPLATE/test-not-compliant.md +++ /dev/null @@ -1,16 +0,0 @@ ---- -name: Test Issue -about: Template for a Test issue report -title: tests/XXX does not build or fails -labels: testing -assignees: '' - ---- - - - - -**Issues:** - - - Test not compiling for xcore-ai - - Test not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md b/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md deleted file mode 100644 index 931414c..0000000 --- a/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md +++ /dev/null @@ -1,13 +0,0 @@ ---- -name: Top-level README Issue -about: Template for the top-level README issue report -title: Top-level README not compliant -labels: documentation -assignees: '' - ---- - - -**Issues:** - - - xdoc-custom RST directives used in the README From a953bc09620436d5c35f74d0d58721e236c701c1 Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Fri, 4 Apr 2025 12:06:50 +0100 Subject: [PATCH 12/57] Removed old project files etc --- lib_spi/.cproject | 970 ---------------------------------------------- lib_spi/.makefile | 8 - lib_spi/.project | 95 ----- lib_spi/wscript | 6 - 4 files changed, 1079 deletions(-) delete mode 100644 lib_spi/.cproject delete mode 100644 lib_spi/.makefile delete mode 100644 lib_spi/.project delete mode 100644 lib_spi/wscript diff --git a/lib_spi/.cproject b/lib_spi/.cproject deleted file mode 100644 index e8f0fb8..0000000 --- a/lib_spi/.cproject +++ /dev/null @@ -1,970 +0,0 @@ - - - - - - - - - - - - - - - - - xmake - -f .makefile - all - true - true - true - - - xmake - -f .makefile - clean - true - true - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib_spi/.makefile b/lib_spi/.makefile deleted file mode 100644 index 87b347b..0000000 --- a/lib_spi/.makefile +++ /dev/null @@ -1,8 +0,0 @@ -all: - @echo "** Module only - only builds as part of application **" - - -clean: - @echo "** Module only - only builds as part of application **" - - diff --git a/lib_spi/.project b/lib_spi/.project deleted file mode 100644 index 31270d3..0000000 --- a/lib_spi/.project +++ /dev/null @@ -1,95 +0,0 @@ - - - lib_spi - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\|\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug - - - org.eclipse.cdt.make.core.buildCommand - xmake - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/lib_spi/wscript b/lib_spi/wscript deleted file mode 100644 index 2177865..0000000 --- a/lib_spi/wscript +++ /dev/null @@ -1,6 +0,0 @@ -def use_module(bld): - bld.env['XCC_FLAGS_spi_async.xc'] = bld.env.XCC_FLAGS + [ - '-Wno-reinterpret-alignment' - ] - source = bld.path.ant_glob('src/*.xc') - bld.module(source=source, includes=['api'], version='3.3.0') From fc7b3d8f2298ba0ff2e4ab1e3ea872ac1464253c Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 2 Jul 2025 15:29:52 +0100 Subject: [PATCH 13/57] Initial changeover of docs (WIP), Jenkins and readme + version bump to 3.4.0 --- CHANGELOG.rst | 11 +- Jenkinsfile | 235 +++++++----------- README.rst | 81 ++++-- doc/Doxyfile.inc | 8 + doc/exclude_patterns.inc | 9 + {lib_spi/doc/rst => doc}/images/Makefile | 0 .../images/spi_master_async_state.dot | 0 .../images/spi_master_async_state.pdf | Bin .../rst => doc}/images/spi_master_connect.odg | Bin .../rst => doc}/images/spi_master_connect.pdf | Bin .../images/spi_master_sync_state.dot | 0 .../images/spi_master_sync_state.pdf | Bin .../images/spi_master_task_diag.odg | Bin .../images/spi_master_task_diag.pdf | Bin .../rst => doc}/images/spi_slave_connect.odg | Bin .../rst => doc}/images/spi_slave_connect.pdf | Bin .../images/spi_slave_task_diag.odg | Bin .../images/spi_slave_task_diag.pdf | Bin .../doc/rst => doc}/images/wavedrom_mode0.js | 0 .../doc/rst => doc}/images/wavedrom_mode0.png | Bin .../doc/rst => doc}/images/wavedrom_mode1.js | 0 .../doc/rst => doc}/images/wavedrom_mode1.png | Bin .../doc/rst => doc}/images/wavedrom_mode2.js | 0 .../doc/rst => doc}/images/wavedrom_mode2.png | Bin .../doc/rst => doc}/images/wavedrom_mode3.js | 0 .../doc/rst => doc}/images/wavedrom_mode3.png | Bin .../doc/rst/index.rst => doc/rst/lib_spi.rst | 233 ++++++++++++----- lib_spi/doc/rst/resource_usage_summary.rst | 37 --- lib_spi/doc/rst/xdoc.conf | 2 - lib_spi/lib_build_info.cmake | 2 +- lib_spi/module_build_info | 2 +- settings.yml | 27 ++ 32 files changed, 364 insertions(+), 283 deletions(-) create mode 100644 doc/Doxyfile.inc create mode 100644 doc/exclude_patterns.inc rename {lib_spi/doc/rst => doc}/images/Makefile (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_async_state.dot (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_async_state.pdf (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_connect.odg (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_connect.pdf (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_sync_state.dot (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_sync_state.pdf (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_task_diag.odg (100%) rename {lib_spi/doc/rst => doc}/images/spi_master_task_diag.pdf (100%) rename {lib_spi/doc/rst => doc}/images/spi_slave_connect.odg (100%) rename {lib_spi/doc/rst => doc}/images/spi_slave_connect.pdf (100%) rename {lib_spi/doc/rst => doc}/images/spi_slave_task_diag.odg (100%) rename {lib_spi/doc/rst => doc}/images/spi_slave_task_diag.pdf (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode0.js (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode0.png (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode1.js (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode1.png (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode2.js (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode2.png (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode3.js (100%) rename {lib_spi/doc/rst => doc}/images/wavedrom_mode3.png (100%) rename lib_spi/doc/rst/index.rst => doc/rst/lib_spi.rst (74%) delete mode 100644 lib_spi/doc/rst/resource_usage_summary.rst delete mode 100644 lib_spi/doc/rst/xdoc.conf create mode 100644 settings.yml diff --git a/CHANGELOG.rst b/CHANGELOG.rst index bcafb1a..9ded6e3 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,10 +1,11 @@ -SPI library change log -====================== +lib_spi change log +================== -UNRELEASED ----------- +3.4.0 +----- - * ADDED: Support for XCommon CMake build system + * CHANGED: Refresh to use latest doc builder and library format + * ADDED: Support for XCommon CMake build system 3.3.0 ----- diff --git a/Jenkinsfile b/Jenkinsfile index 8289e4c..3c7d392 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,178 +1,111 @@ -@Library('xmos_jenkins_shared_library@v0.18.0') _ +// This file relates to internal XMOS infrastructure and should be ignored by external users + +@Library('xmos_jenkins_shared_library@v0.39.0') _ getApproval() pipeline { - agent none - - environment { - REPO = 'lib_spi' - VIEW = getViewName(REPO) + agent { + label 'x86_64 && linux' } - options { + buildDiscarder(xmosDiscardBuildSettings()) skipDefaultCheckout() + timestamps() + } + parameters { + choice(name: 'TEST_LEVEL', choices: ['smoke', 'default', 'extended'], + description: 'The level of test coverage to run' + ) + string( + name: 'TOOLS_VERSION', + defaultValue: '-j -b markp_xsim_expose_signals_from_usb_shim latest', + description: 'The XTC tools version' + ) + string( + name: 'XMOSDOC_VERSION', + defaultValue: 'v7.2.0', + description: 'The xmosdoc version' + ) + string( + name: 'INFR_APPS_VERSION', + defaultValue: 'v2.1.0', + description: 'The infr_apps version' + ) } stages { - stage('Standard build and XS1/2 tests') { - agent { - label 'x86_64 && linux' - } - stages { - stage('Get view') { - steps { - xcorePrepareSandbox("${VIEW}", "${REPO}") - } - } - stage('Library checks') { - steps { - xcoreLibraryChecks("${REPO}") - } - } - stage('Legacy tests') { - steps { - dir("${REPO}/legacy_tests") { - viewEnv() { - // Use Pipfile in legacy_tests, not lib_spi/Pipfile - installPipfile(true) - runPython("./runtests.py --junit-output=${REPO}_tests.xml") - } - } - } + stage('Checkout & build examples') { + steps { + println "Stage running on ${env.NODE_NAME}" + + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo } - stage('Build XCOREAI') { - steps { - dir("${REPO}") { - forAllMatch("examples", "AN*/") { path -> - runXmake(path, '', 'XCOREAI=1') - dir(path) { - stash name: path.split("/")[-1], includes: 'bin/*, ' - } - } + dir("${REPO_NAME}") { + checkoutScmShallow() - // Build Tests - dir('legacy_tests/') { - script { - tests = [ - "spi_master_async_multi_client", - "spi_master_async_multi_device", - "spi_master_async_rx_tx", - "spi_master_async_shutdown", - "spi_master_sync_benchmark", - "spi_master_sync_clock_port_sharing", - "spi_master_sync_multi_client", - "spi_master_sync_multi_device", - "spi_master_sync_rx_tx", - "spi_slave_benchmark", - "spi_slave_rx_tx" - ] - tests.each() { - dir(it) { - //Build all tests tagetting XS3 to check for build errors only - runXmake(".", "", "XCOREAI=1") - stash name: it, includes: 'bin/**/*.xe, ' - } - } - } - } + dir("examples") { + withTools(params.TOOLS_VERSION) { + xcoreBuild() } } } - }//stages - post { - cleanup { - xcoreCleanSandbox() - } } - }//stage - Standard build and XS1/2 tests + } - stage('Documentation'){ - agent{ - label 'x86_64&&macOS' - } - stages{ - stage('Get view') { - steps { - xcorePrepareSandbox("${VIEW}", "${REPO}") - } - } - stage('Builds') { - steps { - forAllMatch("${REPO}/examples", "AN*/") { path -> - runXdoc("${path}/doc") + stage('Library checks') { + steps { + warnError("Library checks failed") + { + runLibraryChecks("${WORKSPACE}/${REPO_NAME}", "${params.INFR_APPS_VERSION}") } - runXdoc("${REPO}/${REPO}/doc") - - // Archive all the generated .pdf docs - archiveArtifacts artifacts: "${REPO}/**/pdf/*.pdf", fingerprint: true, allowEmptyArchive: true - } } - } - post { - cleanup { - cleanWs() + } + + stage('Documentation') { + steps { + dir(REPO_NAME) { + buildDocs() } } } - stage('xcore.ai Verification'){ - agent { - label 'xcore.ai-explorer' - } - stages{ - stage('Get view') { - steps { - xcorePrepareSandbox("${VIEW}", "${REPO}") - dir("${REPO}") { - viewEnv { - withVenv { - sh "pip install -e ${WORKSPACE}/xtagctl" - sh "xtagctl reset_all XCORE-AI-EXPLORER" - } - } - } - } - } - stage('xrun'){ - steps{ - dir("${REPO}") { - viewEnv { - withVenv { - forAllMatch("examples", "AN*/") { path -> - unstash path.split("/")[-1] - } - // Run the tests and look for what we expect - sh 'xrun --io --id 0 bin/AN00160_using_SPI_master.xe &> AN00160_using_SPI_master.txt' - // Look for config register 0 value from wifi module - sh 'grep 2005400 AN00160_using_SPI_master.txt' - //Just run this and ensure we get no error (like wrong arch). We have no SPI master HW so cannot test it - sh 'xrun --id 0 bin/AN00161_using_SPI_slave.xe' - } - } - } - } - } - }//stages - post { - cleanup { - cleanWs() - } - } - }// xcore.ai + //stage('Tests') + //{ + // steps { + // withTools(params.TOOLS_VERSION) { + // dir("${REPO}/tests") { + // createVenv(reqFile: "requirements.txt") + // withVenv{ + // runPytest("--numprocesses=8 --testlevel=${params.TEST_LEVEL}) + // } + // } // dir + // } // withTools + // } // steps + // post + // { + // failure + // { + // //archiveArtifacts artifacts: "${REPO}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true + // } + // } + //} - stage('Update view files') { - agent { - label 'x86_64 && linux' - } - when { - expression { return currentBuild.currentResult == "SUCCESS" } - } - steps { - updateViewfiles() - } + stage("Archive") + { + steps + { + archiveSandbox(REPO_NAME) + } } - }//stages -}//pipeline + } + post { + cleanup { + xcoreCleanSandbox() + } + } +} diff --git a/README.rst b/README.rst index a06322a..0d86554 100644 --- a/README.rst +++ b/README.rst @@ -1,38 +1,69 @@ -SPI Library -=========== +:orphan: -Summary -------- +#################### +lib_spi: SPI library +#################### + +:vendor: XMOS +:version: 3.4.0 +:scope: General Use +:description: SPI Master and Slave components +:category: General Purpose +:keywords: SPI +:devices: xcore-200, xcore.ai -A software defined, industry-standard, SPI (serial peripheral -interface) component -that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. +******* +Summary +******* -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. +SPI is a four-wire hardware bi-directional serial interface. +This library provides a software defined, industry-standard, SPI (serial peripheral +interface) component that allows control a SPI bus via the `xcore` GPIO ports. +******** Features -........ +******** + +* SPI master and SPI slave modes. +* Supports speed of up to 100 Mbit. +* Multiple slave device support +* All clock polarity and phase configurations supported. + +************ +Known issues +************ - * SPI master and SPI slave modes. - * Supports speed of up to 100 Mbit. - * Multiple slave device support - * All clock polarity and phase configurations supported. +* None +**************** +Development repo +**************** -Software version and dependencies -................................. +* `lib_spi `_ -The CHANGELOG contains information about the current and previous versions. -For a list of direct dependencies, look for DEPENDENT_MODULES in lib_spi/module_build_info. +************** +Required tools +************** +* XMOS XTC Tools: 15.3.1 + +********************************* +Required libraries (dependencies) +********************************* + +* None + +************************* Related application notes -......................... +************************* + +* AN00160 - How to communicate as SPI master +* AN00161 - How to communicate as SPI slave + -The following application notes use this library: +******* +Support +******* - * AN00160 - How to communicate as SPI master - * AN00161 - How to communicate as SPI slave +This package is supported by XMOS Ltd. Issues can be raised against the software at +`www.xmos.com/support `_ diff --git a/doc/Doxyfile.inc b/doc/Doxyfile.inc new file mode 100644 index 0000000..0a55ac7 --- /dev/null +++ b/doc/Doxyfile.inc @@ -0,0 +1,8 @@ +# This file provides overrides to the Doxyfile configuration + +PROJECT_NAME = lib_spi +PROJECT_BRIEF = "SPI library" + +INPUT = ../lib_spi/api + +PREDEFINED = C_API= EXTERN_C= slave= __DOXYGEN__=1 diff --git a/doc/exclude_patterns.inc b/doc/exclude_patterns.inc new file mode 100644 index 0000000..0636e6c --- /dev/null +++ b/doc/exclude_patterns.inc @@ -0,0 +1,9 @@ +# The following patterns are to be excluded from the documentation build + +**CHANGELOG* +**LICENSE* +#TODO remove these +**index* +**resource_usage_summary* +**AN00160* +**AN00161* \ No newline at end of file diff --git a/lib_spi/doc/rst/images/Makefile b/doc/images/Makefile similarity index 100% rename from lib_spi/doc/rst/images/Makefile rename to doc/images/Makefile diff --git a/lib_spi/doc/rst/images/spi_master_async_state.dot b/doc/images/spi_master_async_state.dot similarity index 100% rename from lib_spi/doc/rst/images/spi_master_async_state.dot rename to doc/images/spi_master_async_state.dot diff --git a/lib_spi/doc/rst/images/spi_master_async_state.pdf b/doc/images/spi_master_async_state.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_master_async_state.pdf rename to doc/images/spi_master_async_state.pdf diff --git a/lib_spi/doc/rst/images/spi_master_connect.odg b/doc/images/spi_master_connect.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_master_connect.odg rename to doc/images/spi_master_connect.odg diff --git a/lib_spi/doc/rst/images/spi_master_connect.pdf b/doc/images/spi_master_connect.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_master_connect.pdf rename to doc/images/spi_master_connect.pdf diff --git a/lib_spi/doc/rst/images/spi_master_sync_state.dot b/doc/images/spi_master_sync_state.dot similarity index 100% rename from lib_spi/doc/rst/images/spi_master_sync_state.dot rename to doc/images/spi_master_sync_state.dot diff --git a/lib_spi/doc/rst/images/spi_master_sync_state.pdf b/doc/images/spi_master_sync_state.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_master_sync_state.pdf rename to doc/images/spi_master_sync_state.pdf diff --git a/lib_spi/doc/rst/images/spi_master_task_diag.odg b/doc/images/spi_master_task_diag.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_master_task_diag.odg rename to doc/images/spi_master_task_diag.odg diff --git a/lib_spi/doc/rst/images/spi_master_task_diag.pdf b/doc/images/spi_master_task_diag.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_master_task_diag.pdf rename to doc/images/spi_master_task_diag.pdf diff --git a/lib_spi/doc/rst/images/spi_slave_connect.odg b/doc/images/spi_slave_connect.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_connect.odg rename to doc/images/spi_slave_connect.odg diff --git a/lib_spi/doc/rst/images/spi_slave_connect.pdf b/doc/images/spi_slave_connect.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_connect.pdf rename to doc/images/spi_slave_connect.pdf diff --git a/lib_spi/doc/rst/images/spi_slave_task_diag.odg b/doc/images/spi_slave_task_diag.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_task_diag.odg rename to doc/images/spi_slave_task_diag.odg diff --git a/lib_spi/doc/rst/images/spi_slave_task_diag.pdf b/doc/images/spi_slave_task_diag.pdf similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_task_diag.pdf rename to doc/images/spi_slave_task_diag.pdf diff --git a/lib_spi/doc/rst/images/wavedrom_mode0.js b/doc/images/wavedrom_mode0.js similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode0.js rename to doc/images/wavedrom_mode0.js diff --git a/lib_spi/doc/rst/images/wavedrom_mode0.png b/doc/images/wavedrom_mode0.png similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode0.png rename to doc/images/wavedrom_mode0.png diff --git a/lib_spi/doc/rst/images/wavedrom_mode1.js b/doc/images/wavedrom_mode1.js similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode1.js rename to doc/images/wavedrom_mode1.js diff --git a/lib_spi/doc/rst/images/wavedrom_mode1.png b/doc/images/wavedrom_mode1.png similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode1.png rename to doc/images/wavedrom_mode1.png diff --git a/lib_spi/doc/rst/images/wavedrom_mode2.js b/doc/images/wavedrom_mode2.js similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode2.js rename to doc/images/wavedrom_mode2.js diff --git a/lib_spi/doc/rst/images/wavedrom_mode2.png b/doc/images/wavedrom_mode2.png similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode2.png rename to doc/images/wavedrom_mode2.png diff --git a/lib_spi/doc/rst/images/wavedrom_mode3.js b/doc/images/wavedrom_mode3.js similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode3.js rename to doc/images/wavedrom_mode3.js diff --git a/lib_spi/doc/rst/images/wavedrom_mode3.png b/doc/images/wavedrom_mode3.png similarity index 100% rename from lib_spi/doc/rst/images/wavedrom_mode3.png rename to doc/images/wavedrom_mode3.png diff --git a/lib_spi/doc/rst/index.rst b/doc/rst/lib_spi.rst similarity index 74% rename from lib_spi/doc/rst/index.rst rename to doc/rst/lib_spi.rst index e3b2da6..9affc5b 100644 --- a/lib_spi/doc/rst/index.rst +++ b/doc/rst/lib_spi.rst @@ -1,9 +1,24 @@ -.. include:: ../../../README.rst +#################### +lib_spi: SPI library +#################### -.. include:: resource_usage_summary.rst +************ +Introduction +************ +A software defined, industry-standard, SPI (serial peripheral +interface) component +that allows you to control an SPI bus via the +xCORE GPIO hardware-response ports. SPI is a four-wire hardware +bi-directional serial interface. + +The SPI bus can be used by multiple tasks within the xCORE device +and (each addressing the same or different slaves) and +is compatible with other slave devices on the same bus. + +*************************** External signal description ---------------------------- +*************************** The SPI protocol requires a clock, one or more slave selects and either one or two data wires. @@ -31,8 +46,9 @@ the end of the transfer, the *SS* is de-asserted. If the slave select line is not driven high then the slave should ignore any transitions on the other lines. -SPI modes -......... +********* +SPI Modes +********* The data sample points for SPI are defined by the clock polarity (CPOL) and clock phase (CPHA) parameters. SPI clock polarity may be inverted or non-inverted by the CPOL and the CPHA parameter @@ -53,9 +69,9 @@ The setup and hold timings are inherited from the underlying xCORE device. For details on these timing please refer to the device datasheet. Mode 0 - CPOL: 0 CPHA 1 -~~~~~~~~~~~~~~~~~~~~~~~ +======================= -.. figure:: images/wavedrom_mode0.png +.. figure:: ../images/wavedrom_mode0.png :width: 100% Mode 0 @@ -63,54 +79,47 @@ Mode 0 - CPOL: 0 CPHA 1 The master and slave will drive out their first data bit on the first rising edge of the clock and sample on the subsequent falling edge. Mode 1 - CPOL: 0 CPHA 0 -~~~~~~~~~~~~~~~~~~~~~~~ +======================= -.. figure:: images/wavedrom_mode1.png +.. figure:: ../images/wavedrom_mode1.png :width: 100% Mode 1 The master and slave will drive out their first data bit before the first rising edge of the clock then drive on subsequent falling edges. They will sample on rising edges. + Mode 2 - CPOL: 1 CPHA 0 -~~~~~~~~~~~~~~~~~~~~~~~ +======================= -.. figure:: images/wavedrom_mode2.png +.. figure:: ../images/wavedrom_mode2.png :width: 100% Mode 2 The master and slave will drive out their first data bit before the first falling edge of the clock then drive on subsequent rising edges. They will sample on falling edges. + Mode 3 - CPOL: 1 CPHA 1 -~~~~~~~~~~~~~~~~~~~~~~~ +======================= -.. figure:: images/wavedrom_mode3.png +.. figure:: ../images/wavedrom_mode3.png :width: 100% Mode 3 The master and slave will drive out their first data bit on the first falling edge of the clock and sample on the subsequent rising edge. -SPI master timing characteristics -................................. - -The application calls functions to begin a transaction (which asserts -the slave select line) and to transfer data. So the minimum time -between these (*t1*) can be controlled by the application. - -The inter-transmission gap (*t2*) is also controlled by the user -application since the function to specify the end of the transaction -(i.e. the de-assertion of the slave select line) has an argument which -is the minimum amount of time before which another transaction can start. +|newpage| -Synchronous SPI master clock speeds -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +********************************* +SPI master timing characteristics +********************************* The maximum speed that the SPI bus can be driven depends on whether a clock block is used, the speed of the logical core that the SPI code is running on and where both the *MISO* and *MOSI* lines are used. The -timings can be seen in :ref:`spi_master_sync_timings`. +timings can be seen in :numref:`spi_master_sync_timings`. .. _spi_master_sync_timings: @@ -145,7 +154,7 @@ timings can be seen in :ref:`spi_master_sync_timings`. Asynchronous SPI master clock speeds -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +==================================== The asynchronous SPI master is limited only by the clock divider on the clock block. This means that for the 100MHz reference clock, @@ -167,17 +176,19 @@ the asynchronous master can output a clock at up to 100MHz |newpage| + +********************************** Connecting to the xCORE SPI master -.................................. +********************************** The SPI wires need to be connected to the xCORE device as shown in -:ref:`spi_master_xcore_connect`. The signals can be connected to any +:numref:`spi_master_xcore_connect`. The signals can be connected to any one bit ports on the device provide they do not overlap any other used ports and are all on the same tile. .. _spi_master_xcore_connect: -.. figure:: images/spi_master_connect.* +.. figure:: ../images/spi_master_connect.* :width: 40% SPI master connection to the xCORE device @@ -191,7 +202,7 @@ slave select wires. This means that a single slave select assertion cannot be used to communicate with multiple slaves at the same time. SPI slave timings -................. +================= The logical core running the SPI slave task will wait for the slave select line to assert and then begin processing the transaction. At @@ -218,17 +229,19 @@ restrictions on the master. |newpage| + +********************************* Connecting to the xCORE SPI slave -................................. +********************************* The SPI wires need to be connected to the xCORE device as shown in -:ref:`spi_slave_xcore_connect`. The signals can be connected to any +:numref:`spi_slave_xcore_connect`. The signals can be connected to any one bit ports on the device provide they do not overlap any other used ports and are all on the same tile. .. _spi_slave_xcore_connect: -.. figure:: images/spi_slave_connect.* +.. figure:: ../images/spi_slave_connect.* :width: 40% SPI slave connection to the xCORE device @@ -239,11 +252,14 @@ driven high. If the *MISO* line is not required then it need not be connected. The *MOSI* line must always be connected. -Usage ------ +|newpage| + +************ +Master Usage +************ SPI master synchronous operation -................................ +================================ There are two types of interface for SPI master components: synchronous and asynchronous. @@ -259,7 +275,7 @@ SPI master components are instantiated as parallel tasks that run in a ``par`` statement. For synchronous operation, the application can connect via an interface connection using the ``spi_master_if`` interface type: -.. figure:: images/spi_master_task_diag.* +.. figure:: ../images/spi_master_task_diag.* SPI master task diagram @@ -288,7 +304,7 @@ devices via different slave lines. The final parameter of the ``spi_master`` task is an optional clock block. If the clock block is supplied then the maximum transfer rate -of the SPI bus is increased (see :ref:`spi_master_sync_timings`). If +of the SPI bus is increased (see :numref:`spi_master_sync_timings`). If ``null`` is supplied instead then the performance is less but no clock block is used. @@ -319,23 +335,24 @@ function on the logical core of the application task connected to it (provided the application task is on the same tile). Synchronous master usage state machine -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +...................................... The function calls made on the SPI master interface must follow the -sequence shown by the state machine in :ref:`spi_master_usage_state_machine`. +sequence shown by the state machine in :numref:`spi_master_usage_state_machine`. If this sequence is not followed then the behavior is undefined. .. _spi_master_usage_state_machine: -.. figure:: images/spi_master_sync_state.* +.. figure:: ../images/spi_master_sync_state.* :width: 40% SPI master use state machine |newpage| + SPI master asynchronous operation -................................. +================================= The synchronous API will block your application until the bus operation is complete. In cases where the application cannot afford to @@ -411,7 +428,7 @@ core with other tasks (including the application task it is connected to). |newpage| Asynchronous master command buffering -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +..................................... In order to provide asynchronous behaviour for multiple clients the asynchronous master will store up to one ``begin_transaction`` and one ``init_transfer_array_8`` or @@ -423,22 +440,22 @@ asynchronously. Consequently, after client *Y* has issued able to continue operation whilst waiting for the notification. Asynchronous master usage state machine -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +....................................... The function calls made on the SPI master asynchronous interface must follow the sequence shown by the state machine in -:ref:`spi_master_usage_state_machine_async`. +:numref:`spi_master_usage_state_machine_async`. If this sequence is not followed then the behavior is undefined. .. _spi_master_usage_state_machine_async: -.. figure:: images/spi_master_async_state.* +.. figure:: ../images/spi_master_async_state.* :width: 60% SPI master use state machine (asynchronous) Master inter-transaction gap -............................ +============================ For both synchronous and asynchronous modes the ``end_transaction`` requires a slave select deassert time. This parameter will provide a minimum deassert time between @@ -449,14 +466,16 @@ satisfied. |newpage| + +*********** Slave usage -........... +*********** SPI slave components are instantiated as parallel tasks that run in a ``par`` statement. The application can connect via an interface connection. -.. figure:: images/spi_slave_task_diag.pdf +.. figure:: ../images/spi_slave_task_diag.pdf SPI slave task diagram @@ -527,8 +546,11 @@ Note that the time taken to handle the callbacks will determine the timing requirements of the SPI slave. See application note AN00161 for more details on different ways of working with the SPI slave component. +|newpage| + +******************** Disabling data lines -.................... +******************** The *MOSI* and *MISO* parameters of the ``spi_master`` task are optional. So in the top-level ``par`` statement the function can be @@ -542,8 +564,102 @@ optional (but the *MISO* port must be provided). The ``spi_slave`` task has an optional *MISO* parameter (but the *MOSI* port must be supplied). +|newpage| + +******** +Examples +******** + +Building +======== + +The following section assumes that the `XMOS XTC tools `_ has +been downloaded and installed (see `README` for required version). + +Installation instructions can be found `here `_. Particular +attention should be paid to the section `Installation of required third-party tools +`_. + +The application uses the `XMOS` build and dependency system, `xcommon-cmake `_. `xcommon-cmake` +is bundled with the `XMOS` XTC tools. + +To configure the build, run the following from an XTC command prompt: + +.. code-block:: console + + cd examples + cd app_template + cmake -G "Unix Makefiles" -B build + +Any missing dependencies will be downloaded by the build system at this configure step. + +Finally, the application binaries can be built using ``xmake``: + +.. code-block:: console + + xmake -j -C build + +Running +======= + +To run the application return to the ``/examples/app_template`` directory and run the following +command: + +.. code-block:: console + + xrun --xscope bin/app_template.xe + +As application runs and prints "Hello world!" to the console. + +|newpage| + + +************** +Resource Usage +************** + +TODO - Turn me into a table + + * - configuration: Master (synchronous, zero clock blocks) + - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D}; + - locals: interface spi_master_if i[1]; + - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + - pins: 4 + - ports: 4 (1-bit) + * - configuration: Master (synchronous, one clock block) + - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb = XS1_CLKBLK_1; + - locals: interface spi_master_if i[1]; + - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + - pins: 4 + - ports: 4 (1-bit) + * - configuration: Master (asynchronous) + - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb0 = XS1_CLKBLK_1; clock cb1 = XS1_CLKBLK_2; + - locals: interface spi_master_async_if i[1]; + - fn: spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + - pins: 4 + - ports: 4 (1-bit) + * - configuration: Slave (32 bit transfer mode) + - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; + - locals: interface spi_slave_callback_if i; + - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); + - pins: 4 + - ports: 4 (1-bit) + * - configuration: Slave (8 bit transfer mode) + - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; + - locals: interface spi_slave_callback_if i; + - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); + - pins: 4 + - ports: 4 (1-bit) + +The number of pins is reduced if either of the data lines are not required. + + +************* +API Reference +************* + Master API ----------- +========== All SPI master functions can be accessed via the ``spi.h`` header:: @@ -584,8 +700,10 @@ SPI master asynchronous interface .. doxygeninterface:: spi_master_async_if +|newpage| + Slave API ---------- +========= All SPI slave functions can be accessed via the ``spi.h`` header:: @@ -610,13 +728,6 @@ The SPI slave interface API .. doxygeninterface:: spi_slave_callback_if -|newpage| - -|appendix| -Known Issues ------------- -There are no known issues with this library. -.. include:: ../../../CHANGELOG.rst diff --git a/lib_spi/doc/rst/resource_usage_summary.rst b/lib_spi/doc/rst/resource_usage_summary.rst deleted file mode 100644 index 168b99b..0000000 --- a/lib_spi/doc/rst/resource_usage_summary.rst +++ /dev/null @@ -1,37 +0,0 @@ -Typical Resource Usage -...................... - -.. resusage:: - - * - configuration: Master (synchronous, zero clock blocks) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D}; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (synchronous, one clock block) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb = XS1_CLKBLK_1; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (asynchronous) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb0 = XS1_CLKBLK_1; clock cb1 = XS1_CLKBLK_2; - - locals: interface spi_master_async_if i[1]; - - fn: spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (32 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (8 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); - - pins: 4 - - ports: 4 (1-bit) - -The number of pins is reduced if either of the data lines are not required. diff --git a/lib_spi/doc/rst/xdoc.conf b/lib_spi/doc/rst/xdoc.conf deleted file mode 100644 index 2cef5f5..0000000 --- a/lib_spi/doc/rst/xdoc.conf +++ /dev/null @@ -1,2 +0,0 @@ -XMOSNEWSTYLE = 1 -DOXYGEN_DIRS=../../api \ No newline at end of file diff --git a/lib_spi/lib_build_info.cmake b/lib_spi/lib_build_info.cmake index 8b78c21..2074e40 100644 --- a/lib_spi/lib_build_info.cmake +++ b/lib_spi/lib_build_info.cmake @@ -1,5 +1,5 @@ set(LIB_NAME lib_spi) -set(LIB_VERSION 3.3.0) +set(LIB_VERSION 3.4.0) set(LIB_INCLUDES api) set(LIB_DEPENDENT_MODULES "") set(LIB_COMPILER_FLAGS_spi_async.xc -Wno-reinterpret-alignment) diff --git a/lib_spi/module_build_info b/lib_spi/module_build_info index 86a1141..a240d43 100644 --- a/lib_spi/module_build_info +++ b/lib_spi/module_build_info @@ -1,3 +1,3 @@ -VERSION = 3.3.0 +VERSION = 3.4.0 XCC_FLAGS_spi_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment diff --git a/settings.yml b/settings.yml new file mode 100644 index 0000000..83f0a44 --- /dev/null +++ b/settings.yml @@ -0,0 +1,27 @@ +# This file relates to internal XMOS infrastructure and should be ignored by external users +--- +lib_name: lib_spi +project: '{{lib_name}}' +title: '{{lib_name}}: SPI Library' +version: 3.4.0 + +documentation: + exclude_patterns_path: doc/exclude_patterns.inc + root_doc: doc/rst/lib_spi.rst + linkcheck_ignore_regex: [''] + latex_toc_depth: 3 + latex_secnum_depth: 3 + cognidox_part_number: XM-006232-PC + doxygen_projects: + lib_spi: + doxyfile_path: doc/Doxyfile.inc + pdfs: + doc/rst/lib_spi.rst: + pdf_title: '{{title}}' + pdf_filename: '{{lib_name}}_v{{version}}' + README.rst: + pdf_title: '{{title}} (README)' + pdf_filename: '{{lib_name}}_v{{version}}_readme' + pdf_short: yes +software: + cognidox_part_number: XM-012540-SM From aa926e36f084b8e09db4f7f0bf60c74edb338334 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 2 Jul 2025 15:40:18 +0100 Subject: [PATCH 14/57] Update examples to XCCM copyright update Update settings to new CD p/n API doxy and compiler friendly Finish porting doxy and make master example have two build configs --- CHANGELOG.rst | 1 + doc/Doxyfile.inc | 2 +- doc/images/spi_master_async_state.pdf | Bin 16039 -> 0 bytes doc/images/spi_master_async_state.svg | 65 ++ doc/images/spi_master_connect.pdf | Bin 10974 -> 0 bytes doc/images/spi_master_connect.svg | 54 ++ doc/images/spi_master_sync_state.pdf | Bin 14076 -> 0 bytes doc/images/spi_master_sync_state.svg | 40 + doc/images/spi_master_task_diag.pdf | Bin 19955 -> 0 bytes doc/images/spi_master_task_diag.svg | 44 + doc/images/spi_slave_connect.pdf | Bin 10677 -> 0 bytes doc/images/spi_slave_connect.svg | 46 + doc/images/spi_slave_task_diag.pdf | Bin 20214 -> 0 bytes doc/images/spi_slave_task_diag.svg | 44 + doc/rst/lib_spi.rst | 114 ++- examples/AN00160_using_SPI_master/.cproject | 851 ----------------- examples/AN00160_using_SPI_master/.project | 42 - .../AN00160_using_SPI_master.launch | 70 -- .../AN00160_using_SPI_master/CMakeLists.txt | 33 + examples/AN00160_using_SPI_master/Makefile | 36 - examples/AN00160_using_SPI_master/src/main.xc | 57 +- examples/AN00161_using_SPI_slave/.cproject | 869 ------------------ examples/AN00161_using_SPI_slave/.project | 42 - .../AN00161_using_SPI_slave.launch | 71 -- .../AN00161_using_SPI_slave/CMakeLists.txt | 26 + examples/AN00161_using_SPI_slave/Makefile | 35 - examples/AN00161_using_SPI_slave/src/main.xc | 2 +- examples/CMakeLists.txt | 7 + .../lib_spi_master_tester/src/common.h | 2 +- .../src/spi_async_tester.h | 2 +- .../src/spi_sync_tester.h | 2 +- legacy_tests/runtests.py | 2 +- .../src/spi_master_async_multi_client.xc | 2 +- .../src/spi_master_async_multi_device.xc | 2 +- .../src/spi_master_async_rx_tx.xc | 2 +- .../src/spi_master_async_shutdown.xc | 2 +- legacy_tests/spi_master_checker.py | 2 +- .../src/spi_master_sync_benchmark.xc | 2 +- .../spi_master_sync_clock_port_sharing.xc | 2 +- .../src/spi_master_sync_multi_client.xc | 2 +- .../src/spi_master_sync_multi_device.xc | 2 +- .../src/spi_master_sync_rx_tx.xc | 2 +- .../src/spi_slave_benchmark.xc | 2 +- legacy_tests/spi_slave_checker.py | 2 +- .../spi_slave_rx_tx/src/spi_slave_rx_tx.xc | 2 +- .../test_master_async_multi_client.py | 2 +- .../test_master_async_multi_device.py | 2 +- legacy_tests/test_master_async_rx_tx.py | 2 +- legacy_tests/test_master_async_shutdown.py | 2 +- legacy_tests/test_master_sync_benchmark.py | 2 +- .../test_master_sync_clock_port_sharing.py | 2 +- legacy_tests/test_master_sync_multi_client.py | 2 +- legacy_tests/test_master_sync_multi_device.py | 2 +- legacy_tests/test_master_sync_rx_tx.py | 2 +- legacy_tests/test_slave_benchmark.py | 2 +- legacy_tests/test_slave_rx_tx.py | 2 +- lib_spi/api/spi.h | 120 ++- lib_spi/src/spi_async.xc | 2 +- lib_spi/src/spi_slave.xc | 2 +- lib_spi/src/spi_sync.xc | 2 +- python/setup.py | 2 +- settings.yml | 2 +- 62 files changed, 567 insertions(+), 2170 deletions(-) delete mode 100644 doc/images/spi_master_async_state.pdf create mode 100644 doc/images/spi_master_async_state.svg delete mode 100644 doc/images/spi_master_connect.pdf create mode 100644 doc/images/spi_master_connect.svg delete mode 100644 doc/images/spi_master_sync_state.pdf create mode 100644 doc/images/spi_master_sync_state.svg delete mode 100644 doc/images/spi_master_task_diag.pdf create mode 100644 doc/images/spi_master_task_diag.svg delete mode 100644 doc/images/spi_slave_connect.pdf create mode 100644 doc/images/spi_slave_connect.svg delete mode 100644 doc/images/spi_slave_task_diag.pdf create mode 100644 doc/images/spi_slave_task_diag.svg delete mode 100644 examples/AN00160_using_SPI_master/.cproject delete mode 100644 examples/AN00160_using_SPI_master/.project delete mode 100644 examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch create mode 100644 examples/AN00160_using_SPI_master/CMakeLists.txt delete mode 100644 examples/AN00160_using_SPI_master/Makefile delete mode 100644 examples/AN00161_using_SPI_slave/.cproject delete mode 100644 examples/AN00161_using_SPI_slave/.project delete mode 100644 examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch create mode 100644 examples/AN00161_using_SPI_slave/CMakeLists.txt delete mode 100644 examples/AN00161_using_SPI_slave/Makefile create mode 100644 examples/CMakeLists.txt diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 9ded6e3..9a7f751 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -6,6 +6,7 @@ lib_spi change log * CHANGED: Refresh to use latest doc builder and library format * ADDED: Support for XCommon CMake build system + * REMOVED: XCORE-200 targets in examples (now targets xcore.ai explorer) 3.3.0 ----- diff --git a/doc/Doxyfile.inc b/doc/Doxyfile.inc index 0a55ac7..12418ea 100644 --- a/doc/Doxyfile.inc +++ b/doc/Doxyfile.inc @@ -1,7 +1,7 @@ # This file provides overrides to the Doxyfile configuration PROJECT_NAME = lib_spi -PROJECT_BRIEF = "SPI library" +PROJECT_BRIEF = "SPI Library" INPUT = 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zc>sF=!(bD2+GJh`WISmz{P_N!1{|bddH^d>Bt)HN1N#6Z=8Q1k(+qnnGhim5LV%wF zF6}oO+yEQaJ**8MYF%79>JOpTNfXp3s3j4yw8>0u40FAK58{K!fntGx{_96`>93<)fMuIzT^|J|f==G_k>3{nZt~OxCAly#~;qJ^(cufS__2OA&_Ovdf?1$D6b_6AB9O5}U928qb9kUQ!v*!VZx{ne1`rM`%_(1cfF|l( zARV|g3_2=oqc%|w(t|`W&gMi%1T(x5z^B0=fb_EQpojzlj)3w;ZDv?Jm?P1H3fRaX zG8P9Ga!ZB*J%jbwmI0J!TLzIK()PNbJu+DHt#u(R5OcO?_)lcSPh!hh$3z;Q$)3JtIR{umiW2BLkP{ZyAoTyV?q65Sz^M!HW}?=&uRVA%N4Xi{uoN>(bBu+78PS{qwh0Aq r0cIPIC6Gy$1{5O21oi)mxQosvD}){#vc5MUGLb++pwSk#mWclWivZ~m diff --git a/doc/images/spi_slave_task_diag.svg b/doc/images/spi_slave_task_diag.svg new file mode 100644 index 0000000..0e86af1 --- /dev/null +++ b/doc/images/spi_slave_task_diag.svg @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + +SPI +slave + + + + +SPI +slave + + + + +app + + + + +app + + +spi_slave_callback_if + + + + + diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 9affc5b..db2ed6f 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -158,7 +158,7 @@ Asynchronous SPI master clock speeds The asynchronous SPI master is limited only by the clock divider on the clock block. This means that for the 100MHz reference clock, -the asynchronous master can output a clock at up to 100MHz +the asynchronous master can output a clock at up to 100MHz, port timing and hardware permitting. .. list-table:: SPI master timings (asynchronous) :header-rows: 1 @@ -328,7 +328,7 @@ the slave select line. Operations such as ``spi.transfer8`` will block until the operation is completed on the bus. More information on interfaces and tasks can be be found in -the :ref:`XMOS Programming Guide`. By default the +the `XMOS Programming Guide `_. By default the SPI synchronous master mode component does not use any logical cores of its own. It is a *distributed* task which means it will perform its function on the logical core of the application task connected to @@ -475,7 +475,7 @@ SPI slave components are instantiated as parallel tasks that run in a ``par`` statement. The application can connect via an interface connection. -.. figure:: ../images/spi_slave_task_diag.pdf +.. figure:: ../images/spi_slave_task_diag.svg SPI slave task diagram @@ -542,9 +542,11 @@ subsequent transfers either provide or consume data:: } } -Note that the time taken to handle the callbacks will determine the -timing requirements of the SPI slave. See application note AN00161 for -more details on different ways of working with the SPI slave component. +.. note:: + + The time taken to handle the callbacks will determine the + timing requirements of the SPI slave. See application note AN00161 for + more details on different ways of working with the SPI slave component. |newpage| @@ -588,7 +590,7 @@ To configure the build, run the following from an XTC command prompt: .. code-block:: console cd examples - cd app_template + cd AN00160_using_SPI_master cmake -G "Unix Makefiles" -B build Any missing dependencies will be downloaded by the build system at this configure step. @@ -602,14 +604,19 @@ Finally, the application binaries can be built using ``xmake``: Running ======= -To run the application return to the ``/examples/app_template`` directory and run the following +To run the application return to the ``/examples/AN00160_using_SPI_master`` directory and run the following command: .. code-block:: console - xrun --xscope bin/app_template.xe + xrun --xscope bin/SYNC/app_spi_master_SYNC.xe + +As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: + + Sending SPI traffic + 2005400 + Done. -As application runs and prints "Hello world!" to the console. |newpage| @@ -618,38 +625,47 @@ As application runs and prints "Hello world!" to the console. Resource Usage ************** -TODO - Turn me into a table - - * - configuration: Master (synchronous, zero clock blocks) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D}; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (synchronous, one clock block) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb = XS1_CLKBLK_1; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (asynchronous) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb0 = XS1_CLKBLK_1; clock cb1 = XS1_CLKBLK_2; - - locals: interface spi_master_async_if i[1]; - - fn: spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (32 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (8 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); - - pins: 4 - - ports: 4 (1-bit) +Each of the SPI implementations use a number of `xcore` resources which include ports, clock-blocks and may include hardware threads. The table :numref:`res_use_table` + + +.. _res_use_table: + +.. list-table:: `xcore` resource usage for SPI + :widths: 20 30 5 10 5 + :header-rows: 1 + :stub-columns: 1 + + * - configuration + - api + - pins + - ports + - threads + * - Master (synchronous, zero clock blocks) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + - 4 + - 4 (1-bit) + - 0 + * - Master (synchronous, one clock block) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + - 4 + - 4 (1-bit) + - 0 + * - Master (asynchronous) + - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + - 4 + - 4 (1-bit) + - 1 + * - Slave (32 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); + - 4 + - 4 (1-bit) + - 1 + * - Slave (8 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); + - 4 + - 4 (1-bit) + - 1 + The number of pins is reduced if either of the data lines are not required. @@ -663,10 +679,12 @@ Master API All SPI master functions can be accessed via the ``spi.h`` header:: - #include + #include "spi.h" -You will also have to add ``lib_spi`` to the -``USED_MODULES`` field of your application Makefile. +You will also have to add ``lib_spi`` to the application's ``APP_DEPENDENT_MODULES`` list in +`CMakeLists.txt`, for example:: + + set(APP_DEPENDENT_MODULES "lib_spi") Supporting types ................ @@ -691,14 +709,14 @@ Creating an SPI master instance SPI master interface ..................... -.. doxygeninterface:: spi_master_if +.. doxygengroup:: spi_master_if |newpage| SPI master asynchronous interface ................................. -.. doxygeninterface:: spi_master_async_if +.. doxygengroup:: spi_master_async_if |newpage| @@ -726,7 +744,7 @@ Creating an SPI slave instance The SPI slave interface API ........................... -.. doxygeninterface:: spi_slave_callback_if +.. doxygengroup:: spi_slave_callback_if diff --git a/examples/AN00160_using_SPI_master/.cproject b/examples/AN00160_using_SPI_master/.cproject deleted file mode 100644 index 27de2ed..0000000 --- a/examples/AN00160_using_SPI_master/.cproject +++ /dev/null @@ -1,851 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00160_using_SPI_master/.project b/examples/AN00160_using_SPI_master/.project deleted file mode 100644 index b741264..0000000 --- a/examples/AN00160_using_SPI_master/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00160_using_SPI_master - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch b/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch deleted file mode 100644 index 3339834..0000000 --- a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch +++ /dev/null @@ -1,70 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00160_using_SPI_master/CMakeLists.txt b/examples/AN00160_using_SPI_master/CMakeLists.txt new file mode 100644 index 0000000..703ed39 --- /dev/null +++ b/examples/AN00160_using_SPI_master/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_master) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +list(APPEND APP_DEPENDENT_MODULES "lib_spi") + +# Flags +set(COMPILER_FLAGS_COMMON + -Os + -g + -report + -Wall + -Werror +) + +set(APP_COMPILER_FLAGS_SYNC + ${COMPILER_FLAGS_COMMON}) + +set(APP_COMPILER_FLAGS_ASYNC + ${COMPILER_FLAGS_COMMON} + -DSPI_USE_ASYNC=1) + + +XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master/Makefile b/examples/AN00160_using_SPI_master/Makefile deleted file mode 100644 index 3b788af..0000000 --- a/examples/AN00160_using_SPI_master/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -ADDITIONAL_FLAGS = -DXCORE_AI_EXPLORER=1 -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00160_using_SPI_master - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g $(ADDITIONAL_FLAGS) - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 1270725..3acd1b4 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -7,19 +7,12 @@ #include #include -/* These ports are used for the SPI master */ -#ifdef XCORE_AI_EXPLORER + out buffered port:32 p_sclk = WIFI_CLK; out port p_ss[1] = {WIFI_CS_N}; in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; -#else -out buffered port:32 p_sclk = on tile[0]: XS1_PORT_1I; -out port p_ss[1] = on tile[0]: {XS1_PORT_1J}; -in buffered port:32 p_miso = on tile[0]: XS1_PORT_1K; -out buffered port:32 p_mosi = on tile[0]: XS1_PORT_1L; -#endif clock clk0 = on tile[0]: XS1_CLKBLK_1; clock clk1 = on tile[0]: XS1_CLKBLK_2; @@ -33,7 +26,6 @@ void app(client spi_master_if spi) { uint8_t val; printstrln("Sending SPI traffic"); -#if XCORE_AI_EXPLORER p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); @@ -47,18 +39,6 @@ void app(client spi_master_if spi) reg = spi.transfer32(0x00); spi.end_transaction(0); printhexln(reg << 16 | reg >> 16); -#else - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0xab); - val = spi.transfer32(0xcc); - val = spi.transfer8(0xfe); - spi.end_transaction(100); - - delay_microseconds(40); - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0x22); - spi.end_transaction(100); -#endif printstrln("Done."); _exit(0); @@ -127,22 +107,9 @@ void async_app(client spi_master_async_if spi) spi.shutdown(); } -#if 1 -int main(void) { - interface spi_master_if i_spi[1]; - par { - on tile[0]: app(i_spi[0]); - on tile[0]: spi_master(i_spi, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - null); - } - return 0; -} -#endif -/* Uncomment the main below (and comment out the one above) to try the - async version. */ -#if 0 +#if SPI_USE_ASYNC + int main(void) { interface spi_master_async_if i_spi_async[1]; par { @@ -157,4 +124,18 @@ int main(void) { } return 0; } -#endif + +#else + +int main(void) { + interface spi_master_if i_spi[1]; + par { + on tile[0]: app(i_spi[0]); + on tile[0]: spi_master(i_spi, 1, + p_sclk, p_mosi, p_miso, p_ss, 1, + null); + } + return 0; +} + +#endif /*SPI_USE_ASYNC*/ diff --git a/examples/AN00161_using_SPI_slave/.cproject b/examples/AN00161_using_SPI_slave/.cproject deleted file mode 100644 index 6139ffa..0000000 --- a/examples/AN00161_using_SPI_slave/.cproject +++ /dev/null @@ -1,869 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00161_using_SPI_slave/.project b/examples/AN00161_using_SPI_slave/.project deleted file mode 100644 index 5c1ddbb..0000000 --- a/examples/AN00161_using_SPI_slave/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00161_using_SPI_slave - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch b/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch deleted file mode 100644 index 87a5113..0000000 --- a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00161_using_SPI_slave/CMakeLists.txt b/examples/AN00161_using_SPI_slave/CMakeLists.txt new file mode 100644 index 0000000..823970e --- /dev/null +++ b/examples/AN00161_using_SPI_slave/CMakeLists.txt @@ -0,0 +1,26 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_slave) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +list(APPEND APP_DEPENDENT_MODULES "lib_spi") + +# Flags +set( + APP_COMPILER_FLAGS + -Os + -g + -report + -Wall + -Werror +) + +XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00161_using_SPI_slave/Makefile b/examples/AN00161_using_SPI_slave/Makefile deleted file mode 100644 index 7b9a2f5..0000000 --- a/examples/AN00161_using_SPI_slave/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-L16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00161_using_SPI_slave - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g -report -DDEBUG_PRINT_ENABLE=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/AN00161_using_SPI_slave/src/main.xc index 6931682..659263c 100644 --- a/examples/AN00161_using_SPI_slave/src/main.xc +++ b/examples/AN00161_using_SPI_slave/src/main.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt new file mode 100644 index 0000000..2668e58 --- /dev/null +++ b/examples/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +project(lib_camera_examples) + +add_subdirectory(AN00160_using_SPI_master) +add_subdirectory(AN00161_using_SPI_slave) \ No newline at end of file diff --git a/legacy_tests/lib_spi_master_tester/src/common.h b/legacy_tests/lib_spi_master_tester/src/common.h index f002f32..753a74a 100644 --- a/legacy_tests/lib_spi_master_tester/src/common.h +++ b/legacy_tests/lib_spi_master_tester/src/common.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef COMMON_H_ #define COMMON_H_ diff --git a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h b/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h index 7bec60a..226fdad 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h +++ b/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ diff --git a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h b/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h index 0576379..43d0662 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h +++ b/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ diff --git a/legacy_tests/runtests.py b/legacy_tests/runtests.py index 270f4eb..2921a12 100755 --- a/legacy_tests/runtests.py +++ b/legacy_tests/runtests.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index d3c170e..9e5babd 100644 --- a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc b/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc index d5b5d14..82f5ed2 100644 --- a/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc +++ b/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index 64ba336..898a320 100644 --- a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc index e8233b4..38576f3 100644 --- a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc +++ b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc @@ -1,4 +1,4 @@ -// Copyright 2020-2021 XMOS LIMITED. +// Copyright 2020-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_checker.py b/legacy_tests/spi_master_checker.py index cb60ad8..bac4623 100644 --- a/legacy_tests/spi_master_checker.py +++ b/legacy_tests/spi_master_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2022 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest diff --git a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index cf79bfb..9364eb1 100644 --- a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc b/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc index 2e05a57..44c8521 100644 --- a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc +++ b/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc @@ -1,4 +1,4 @@ -// Copyright 2020-2021 XMOS LIMITED. +// Copyright 2020-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 04e71a1..688fdb8 100644 --- a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index f0e5459..b9bc669 100644 --- a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 4b02070..790ed37 100644 --- a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc b/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc index 6e212cd..6708438 100644 --- a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc +++ b/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_slave_checker.py b/legacy_tests/spi_slave_checker.py index 43c82b6..de08d37 100644 --- a/legacy_tests/spi_slave_checker.py +++ b/legacy_tests/spi_slave_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2022 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest diff --git a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc b/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc index 991d283..b10866b 100644 --- a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc +++ b/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/test_master_async_multi_client.py b/legacy_tests/test_master_async_multi_client.py index 8714e2c..d38531c 100644 --- a/legacy_tests/test_master_async_multi_client.py +++ b/legacy_tests/test_master_async_multi_client.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_multi_device.py b/legacy_tests/test_master_async_multi_device.py index d817883..169017e 100644 --- a/legacy_tests/test_master_async_multi_device.py +++ b/legacy_tests/test_master_async_multi_device.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_rx_tx.py b/legacy_tests/test_master_async_rx_tx.py index f3b1099..019fe2b 100644 --- a/legacy_tests/test_master_async_rx_tx.py +++ b/legacy_tests/test_master_async_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_shutdown.py b/legacy_tests/test_master_async_shutdown.py index 090eaef..848176b 100644 --- a/legacy_tests/test_master_async_shutdown.py +++ b/legacy_tests/test_master_async_shutdown.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_benchmark.py b/legacy_tests/test_master_sync_benchmark.py index d64f928..f33e6cd 100644 --- a/legacy_tests/test_master_sync_benchmark.py +++ b/legacy_tests/test_master_sync_benchmark.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_clock_port_sharing.py b/legacy_tests/test_master_sync_clock_port_sharing.py index e14b0bb..6cdaeb6 100644 --- a/legacy_tests/test_master_sync_clock_port_sharing.py +++ b/legacy_tests/test_master_sync_clock_port_sharing.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_multi_client.py b/legacy_tests/test_master_sync_multi_client.py index 4d8b0ec..dafd2d8 100644 --- a/legacy_tests/test_master_sync_multi_client.py +++ b/legacy_tests/test_master_sync_multi_client.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_multi_device.py b/legacy_tests/test_master_sync_multi_device.py index 4f2ae50..556cb09 100644 --- a/legacy_tests/test_master_sync_multi_device.py +++ b/legacy_tests/test_master_sync_multi_device.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_rx_tx.py b/legacy_tests/test_master_sync_rx_tx.py index 80b03e8..e5449cb 100644 --- a/legacy_tests/test_master_sync_rx_tx.py +++ b/legacy_tests/test_master_sync_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_slave_benchmark.py b/legacy_tests/test_slave_benchmark.py index f8fb4bd..8c4ad28 100644 --- a/legacy_tests/test_slave_benchmark.py +++ b/legacy_tests/test_slave_benchmark.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_slave_checker import SPISlaveChecker diff --git a/legacy_tests/test_slave_rx_tx.py b/legacy_tests/test_slave_rx_tx.py index 04c0211..7d92f3f 100644 --- a/legacy_tests/test_slave_rx_tx.py +++ b/legacy_tests/test_slave_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_slave_checker import SPISlaveChecker diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index e3314f9..449105b 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -1,10 +1,29 @@ -// Copyright 2014-2021 XMOS LIMITED. +// Copyright 2014-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef _spi_h_ #define _spi_h_ #include #include #include +#include + +// These are needed for DOXYGEN to render properly +#ifndef __DOXYGEN__ +#define static_const_unsigned static const unsigned +#define static_const_size_t static const size_t +#define out_port out port +#define in_port in port +#define async_master_shutdown shutdown +#define async_master_send_stop_bit send_stop_bit +#define async_master_read read +#define async_master_write write +#define slave_void slave void +#define static_const_spi_mode_t static const spi_mode_t +#define static_const_spi_transfer_type_t static const spi_transfer_type_t +#define static_const_spi_transfer_type_t static const spi_transfer_type_t +#define uint32_t_movable_ptr_t uint32_t * movable +#define uint8_t_movable_ptr_t uint8_t * movable +#endif /** This type indicates what mode an SPI component should use */ typedef enum spi_mode_t { @@ -16,7 +35,14 @@ typedef enum spi_mode_t { /** This interface allows clients to interact with SPI master task. */ +#ifndef __DOXYGEN__ typedef interface spi_master_if { +#endif + + /** + * \addtogroup spi_master_if + * @{ + */ /** Begin a transaction. * @@ -67,7 +93,11 @@ typedef interface spi_master_if { * \returns the data read in from the MISO port. */ uint32_t transfer32(uint32_t data); +#ifndef __DOXYGEN__ } spi_master_if; +#endif + +/**@}*/ // END: addtogroup spi_master_if /** Task that implements the SPI proctocol in master mode that is connected to a multiple slaves on the bus. @@ -92,21 +122,29 @@ typedef interface spi_master_if { \param clk a clock for the component to use. */ [[distributable]] -void spi_master(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock ?clk); +void spi_master( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss[num_slaves], + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); + +/** + * \addtogroup spi_master_async_if + * @{ + */ /** Asynchronous interface to an SPI component. * * This interface allows programs to offload SPI bus transfers to another * task. An asynchronous notification occurs when the transfer is complete. */ +#ifndef __DOXYGEN__ typedef interface spi_master_async_if { +#endif /** Begin a transaction. * * This will start a transaction on the bus. During a transaction, no @@ -149,8 +187,8 @@ typedef interface spi_master_async_if { * transfer will consist of undefined values. * \param nbytes The number of bytes to transfer over the bus. */ - void init_transfer_array_8(uint8_t * movable inbuf, - uint8_t * movable outbuf, + void init_transfer_array_8(uint8_t_movable_ptr_t inbuf, + uint8_t_movable_ptr_t outbuf, size_t nbytes); /** Initialize Transfer an array of bytes over the spi bus. @@ -168,8 +206,8 @@ typedef interface spi_master_async_if { * transfer will consist of undefined values. * \param nwords The number of words to transfer over the bus. */ - void init_transfer_array_32(uint32_t * movable inbuf, - uint32_t * movable outbuf, + void init_transfer_array_32(uint32_t_movable_ptr_t inbuf, + uint32_t_movable_ptr_t outbuf, size_t nwords); @@ -192,8 +230,8 @@ typedef interface spi_master_async_if { * pointer that was transmitted during the transfer. */ [[clears_notification]] - void retrieve_transfer_buffers_8(uint8_t * movable &inbuf, - uint8_t * movable &outbuf); + void retrieve_transfer_buffers_8(REFERENCE_PARAM(uint8_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint8_t_movable_ptr_t, outbuf)); /** Retrieve transfer buffers. @@ -208,14 +246,18 @@ typedef interface spi_master_async_if { * pointer that was transmitted during the transfer. */ [[clears_notification]] - void retrieve_transfer_buffers_32(uint32_t * movable &inbuf, - uint32_t * movable &outbuf); + void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); /** Shut down the interface server. */ void shutdown(void); -} spi_master_async_if; + /**@}*/ // END: addtogroup spi_master_async_if + +#ifndef __DOXYGEN__ +} spi_master_async_if; +#endif /** SPI master component for asynchronous API. * @@ -235,22 +277,30 @@ typedef interface spi_master_async_if { * \param clk1 a clock for the component to use. */ [[combinable]] -void spi_master_async(server interface spi_master_async_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - out port p_ss[num_slaves], - static const size_t num_slaves, +void spi_master_async( + SERVER_INTERFACE(spi_master_async_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + in_buffered_port_32_t miso, + out_port p_ss[num_slaves], + static_const_size_t num_slaves, clock clk0, clock clk1); /**** SLAVE ****/ +/** + * \addtogroup spi_slave_callback_if + * @{ + */ + /** This interface allows clients to interact with SPI slave tasks by * completing callbacks that show how to handle data. */ +#ifndef __DOXYGEN__ typedef interface spi_slave_callback_if { +#endif /** This callback will get called when the master de-asserts on the slave * select line to end a transaction. @@ -280,8 +330,12 @@ typedef interface spi_slave_callback_if { * \param valid_bits the number of valid bits of data received from the master. */ void master_supplied_data(uint32_t datum, uint32_t valid_bits); - +#ifndef __DOXYGEN__ } spi_slave_callback_if; +#endif + + /**@}*/ // END: addtogroup spi_slave_callback_if + /** This type specifies the transfer size from the SPI slave component to the application */ @@ -307,13 +361,13 @@ typedef enum spi_transfer_type_t { * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. */ [[combinable]] - void spi_slave(client spi_slave_callback_if spi_i, - in port p_sclk, - in buffered port:32 p_mosi, - out buffered port:32 ?p_miso, - in port p_ss, + void spi_slave(CLIENT_INTERFACE(spi_slave_callback_if, spi_i), + in_port p_sclk, + in_buffered_port_32_t p_mosi, + NULLABLE_RESOURCE(out_buffered_port_32_t, p_miso), + in_port p_ss, clock clk, - static const spi_mode_t mode, - static const spi_transfer_type_t transfer_type); + static_const_spi_mode_t mode, + static_const_spi_transfer_type_t transfer_type); #endif // _spi_h_ diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc index 14abce2..aa38259 100644 --- a/lib_spi/src/spi_async.xc +++ b/lib_spi/src/spi_async.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 896f468..235453e 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc index e1c7577..e34a93a 100644 --- a/lib_spi/src/spi_sync.xc +++ b/lib_spi/src/spi_sync.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/python/setup.py b/python/setup.py index 766b8bb..8c6864f 100644 --- a/python/setup.py +++ b/python/setup.py @@ -1,4 +1,4 @@ -# Copyright 2020-2022 XMOS LIMITED. +# Copyright 2020-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import setuptools diff --git a/settings.yml b/settings.yml index 83f0a44..cdb68fc 100644 --- a/settings.yml +++ b/settings.yml @@ -11,7 +11,7 @@ documentation: linkcheck_ignore_regex: [''] latex_toc_depth: 3 latex_secnum_depth: 3 - cognidox_part_number: XM-006232-PC + cognidox_part_number: XM-015352-UG doxygen_projects: lib_spi: doxyfile_path: doc/Doxyfile.inc From a4ab9f852d35d8dba3fa30f07b924cf58706fb6f Mon Sep 17 00:00:00 2001 From: Ed Date: Fri, 4 Jul 2025 17:22:11 +0100 Subject: [PATCH 15/57] WIP lib_spi wrapper for fwk_io spi --- .../CMakeLists.txt | 26 ++ .../AN00160_using_SPI_master_fwk/LICENSE.rst | 84 ++++ .../AN00160_using_SPI_master_fwk/README.rst | 46 ++ .../config.xscope | 23 + .../doc/rst/AN00160.rst | 266 ++++++++++++ .../doc/rst/images/Makefile | 19 + .../doc/rst/images/block_diagram.odg | Bin 0 -> 18906 bytes .../doc/rst/images/block_diagram.pdf | Bin 0 -> 26106 bytes .../doc/rst/images/run_config_sim.png | Bin 0 -> 121580 bytes .../doc/rst/images/run_config_trace.png | Bin 0 -> 113567 bytes .../doc/rst/images/task_diag.odg | Bin 0 -> 12566 bytes .../doc/rst/images/task_diag.pdf | Bin 0 -> 19961 bytes .../doc/rst/images/vcd1.png | Bin 0 -> 213200 bytes .../doc/rst/images/vcd2.png | Bin 0 -> 229593 bytes .../doc/rst/xdoc.conf | 2 + .../AN00160_using_SPI_master_fwk/src/main.xc | 61 +++ lib_spi/api/spi.h | 12 + lib_spi/api/spi_fwk.h | 404 ++++++++++++++++++ lib_spi/src/spi_master.c | 317 ++++++++++++++ lib_spi/src/spi_master_fwk.xc | 83 ++++ 20 files changed, 1343 insertions(+) create mode 100644 examples/AN00160_using_SPI_master_fwk/CMakeLists.txt create mode 100644 examples/AN00160_using_SPI_master_fwk/LICENSE.rst create mode 100644 examples/AN00160_using_SPI_master_fwk/README.rst create mode 100644 examples/AN00160_using_SPI_master_fwk/config.xscope create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.odg create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.pdf create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/run_config_sim.png create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/run_config_trace.png create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/task_diag.odg create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/task_diag.pdf create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/vcd1.png create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/vcd2.png create mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/xdoc.conf create mode 100644 examples/AN00160_using_SPI_master_fwk/src/main.xc create mode 100644 lib_spi/api/spi_fwk.h create mode 100644 lib_spi/src/spi_master.c create mode 100644 lib_spi/src/spi_master_fwk.xc diff --git a/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt b/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt new file mode 100644 index 0000000..6a397c5 --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt @@ -0,0 +1,26 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_master) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +list(APPEND APP_DEPENDENT_MODULES "lib_spi") + +# Flags +set(APP_COMPILER_FLAGS + -Os + -g + -report + -Wall + -Werror +) + + +XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master_fwk/LICENSE.rst b/examples/AN00160_using_SPI_master_fwk/LICENSE.rst new file mode 100644 index 0000000..ca48f20 --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/LICENSE.rst @@ -0,0 +1,84 @@ +******************************* +XMOS PUBLIC LICENCE: Version 1 +******************************* + +Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. + +**1. 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The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/examples/AN00160_using_SPI_master_fwk/README.rst b/examples/AN00160_using_SPI_master_fwk/README.rst new file mode 100644 index 0000000..39f206a --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/README.rst @@ -0,0 +1,46 @@ +How to use the SPI library as SPI master +======================================== + +Summary +------- + +This application note shows how to use the SPI library to make the +xCORE drive an SPI bus as SPI master. The application is the simplest +example of setting up the library and performing a couple of +transactions. The code can then be run in simulation to see the +outputted waveforms. + +The note covers both the synchronous and asynchronous use of the SPI +master components provided from the library. + +Required tools and libraries +............................ + +* xTIMEcomposer Tools - Version 14.0 +* XMOS SPI library - Version 3.0.0 + +Required hardware +................. + +This application note is designed to run in simulation so requires no +XMOS hardware. + +Prerequisites +............. + + - This document assumes familiarity with the XMOS xCORE + architecture, the SPI bus protocol, the XMOS tool chain and the xC + language. Documentation related to these aspects which are not + specific to this application note are linked to in the references appendix. + + - For descriptions of XMOS related terms found in this document + please see the XMOS Glossary [#]_. + + - For the full API listing of the XMOS SPI Device Library please see + the library user guide [#]_. + + .. [#] http://www.xmos.com/published/glossary + + .. [#] http://www.xmos.com/support/libraries/lib_spi + + diff --git a/examples/AN00160_using_SPI_master_fwk/config.xscope b/examples/AN00160_using_SPI_master_fwk/config.xscope new file mode 100644 index 0000000..1540288 --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/config.xscope @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst b/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst new file mode 100644 index 0000000..6708d25 --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst @@ -0,0 +1,266 @@ +.. include:: ../../README.rst + +|newpage| + +Overview +-------- + +Introduction +............ + +The XMOS SPI library is a library that provides +software defined, industry-standard, SPI (serial peripheral interface) +components that allows you to control an SPI bus via the +xCORE GPIO hardware-response ports. SPI is a four-wire hardware +bi-directional serial interface. + +The SPI bus can be used by multiple tasks within the xCORE device +and (each addressing the same or different slaves) and +is compatible with other slave devices on the same bus. + +The library includes features such as SPI master and SPI slave modes, +supported speeds of up to 100 Mbit, multiple slave device support and +support for all configurations of clock polarity and phase. + +Block diagram +............. + +.. figure:: images/block_diagram.* + :scale: 100% + :align: center + + Block diagram of SPI master application example + +SPI master example +------------------ + +The example in this application note uses the XMOS SPI library to +perform some bus transactions as SPI master. The binary is then run in +simulation so the user can see the waveform output in the VCD tracing +perspective in the xTIMEcomposer. + +The application consists of two tasks: + + - A task that drives the SPI bus + + - An application task that connects to the SPI task + +These tasks communicate via the use of xC interfaces. + +The following diagram shows the task and communication structure of +the application. + +.. figure:: images/task_diag.* + + Task diagram of SPI master example + +Makefile additions for this example +................................... + +To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: + + USED_MODULES = ... lib_spi + +You can then access the SPI functions in your source code via the +spi.h header file:: + + #include + +Declaring ports +............... + +The SPI library connects to external pins via xCORE ports. In +``main.xc`` these are declared as variables of type ``port`` at the +start of the file: + +.. literalinclude:: main.xc + :start-on: p_sclk + :end-on: p_mosi + +Note that the slave select declaration (``p_ss``) is an array of +ports. This is what the SPI library expects since there may be many +slave select lines for multiple devices. + +How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will +depend on the exact device being used. See the device datasheet for details. + +|newpage| + +The application main() function +............................... + +Below is the source code for the main function of this application, +which is taken from the source file ``main.xc`` + +.. literalinclude:: main.xc + :start-on: int main + :end-before: Uncomment + +Looking at this in more detail you can see the following: + + - The par functionality describes running two separate tasks in parallel + + - The ``spi_master`` task drives the SPI bus and takes the ports it + will use as arguments. + + - The ``app`` task communicates to the ``spi_master`` task via the + shared interface argument ``i_spi``. This is an array since the + SPI master task could connect to many other tasks in parallel. + +The app() function +.................. + +The ``app`` function uses its interface connection to the SPI master +task to perform SPI transactions. It performs two transactions (each +transaction will assert the slave select line, transfer some data and then +de-assert the slave select line). The functions in the SPI master +interface can be found in the SPI library user guide. + +.. literalinclude:: main.xc + :start-on: void app + :end-before: This application function + +Note that when ``begin_transaction`` is called the device is selected +by the first argument. In this case it is ``0``, so the zero-th +element of the ``p_ss`` array will be used for the slave select +line. This is the method that is used to communiate with multiple SPI +slave devices. The speed and mode of the SPI protocol is also set at +in the ``begin_transaction`` call. + +|newpage| + +Setting up the run configuration for the application +.................................................... + +To run the application binary in the simulator, first the application +must be built by pressing the :menuitem:`Build` button in the +xTIMEcomposer. This will create the ``AN00160_using_SPI_master.xe`` +binary in the ``bin`` folder of the project. The xTIMEcomposer may +have to import the SPI library if you do not already have it in your +workspace; this will occur automatically on build. + +Then a *Run Configuration* needs to be set up. This can be done by +selecting the :menuitem:`Run,Run Configurations..` menu. You can +create a new run configuration by right clicking on the +:menuitem:`xCORE application` group in the left hand pane and +:menuitem:`new`. However, in this example a run configuration has +already been created for you. + +Looking at this run configuration, you can see the simulator has been +selected under :menuitem:`Device Options:`: + +.. image:: images/run_config_sim.png + :width: 70% + :align: center + +|newpage| + +In the :menuitem:`Simulator` tab of the run configuration. The +:menuitem:`Enable signal tracing` check box has been enabled and a +:menuitem:`Tile Trace Option` has been added to trace the ports on +tile[0]: + +.. image:: images/run_config_trace.png + :width: 70% + :align: center + +|newpage| + +Running the application +....................... + +By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit +Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` +button in the run configuration dialog, the program +will run. In the console window you will get this output:: + + Sending SPI traffic + Done. + +After this it will immediately swith the the VCD tracing perspective +(since signal tracing was enabled in the run configuration). In this +perspective you can drag ports from within the tree in the +:menuitem:`Signals` pane on the left hand side to the +:menuitem:`Waves` pane on the right: + +.. image:: images/vcd1.png + :width: 70% + :align: center + +By dragging in the four ports used by the application (1I, 1J, 1K and +1L) you can see that the application has driven the correct SPI +signal. Note that you need to expand each port and drag in just the +port value, the other traces (such as ``tile[0]_XS1_PORT_1J_inuse``) +just show the internal port state and are not so interesting here. + +.. image:: images/vcd2.png + :width: 70% + :align: center + +|newpage| + +Using the asynchronous interface +................................ + +There is an alternative ``main()`` function in the program to try: + +.. literalinclude:: main.xc + :start-on: Uncomment + +By uncommenting this main (and commenting out the original main) the +application will use the ``spi_master_async`` task instead of the +synchronous ``spi_master`` task. This task still drives the SPI bus +but runs on a separate logical core and will drive the bus in parallel +to your application. This way your application can overlap processing +with communication. + +The ``async_app()`` function performs the same function as the +``app()`` function using the asynchronous interface. The big +difference is that pointers have to be passed to the SPI task that +point to the buffers to send from/receive into. These need to be +*movable* pointers (see the xC programing guide for more information) +that can be passed to another task: + +.. literalinclude:: main.xc + :start-on: async_app + :end-on: outbuf + +|newpage| + +Once the pointers have been initialized they can be passed and later +retrieved from the SPI master task: + +.. literalinclude:: main.xc + :start-on: traffic (async) + :end-on: end_transaction + +|appendix| +|newpage| + +References +---------- + +.. nopoints:: + + * XMOS Tools User Guide + + http://www.xmos.com/published/xtimecomposer-user-guide + + * XMOS xCORE Programming Guide + + http://www.xmos.com/published/xmos-programming-guide + + * XMOS SPI Library + + http://www.xmos.com/support/libraries/lib_spi + +|newpage| + +Full source code listing +------------------------ + +.. literalinclude:: main.xc + :largelisting: + +|newpage| + diff --git a/examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile b/examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile new file mode 100644 index 0000000..fddcef8 --- /dev/null +++ b/examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile @@ -0,0 +1,19 @@ +ODGS = $(wildcard *.odg) +PDFS = $(ODGS:.odg=.pdf) + +all: $(PDFS) + @echo PDFs created + +_uncropped: + mkdir _uncropped + +_uncropped/%.pdf: %.odg | _uncropped + soffice -env:UserInstallation=file:///home/$(USER)/.libreoffice-alt --headless --convert-to pdf $< --outdir _uncropped + +%.pdf: _uncropped/%.pdf + pdfcrop $< $@ + +clean: + -rm $(PDFS) + -rm _uncropped/*.pdf + -rmdir _uncropped diff --git a/examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.odg b/examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.odg new file mode 100644 index 0000000000000000000000000000000000000000..ffffcf19415a1b2fde36369c7d8edadb08cde226 GIT binary patch literal 18906 zcmeEuW2|URv*zAs+qTZOZQHhO+qP|=ZQHhO+qO05{bs%&Gr4mo_unKlope@rudc3M zl}@VGQ`IFW2?UG`000gEaHJ6?k_$vLNC^M{@K60a1Ym7$ZS3T3XRL2$XJu}v?__Rk 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Since this is run in simulation + * there is no slave, so the incoming data (stored in the 'val' + * variable) will just be zero. + */ +void app(client spi_master_if spi) +{ + uint8_t val; + printstrln("Sending SPI traffic"); + + p_rstn <: 0x2; //Take out of reset and wait + delay_microseconds(1000); + spi.begin_transaction(0, 1000, SPI_MODE_1); + +for(int i=0;i<1000000;i++){ + uint32_t addr = 0; + uint32_t command = 0x8002 | (addr << 12); //Read command + val = spi.transfer8(command >> 8); + val = spi.transfer8(command & 0xff); + uint32_t reg; + reg = spi.transfer32(0x00); + spi.end_transaction(0); + printhexln(reg << 16 | reg >> 16); +} + + printstrln("Done."); + delay_microseconds(100000); + _exit(0); +} + + +int main(void) { + interface spi_master_if i_spi[1]; + par { + on tile[0]: app(i_spi[0]); + on tile[0]: spi_master_fwk(i_spi, 1, + p_sclk, p_mosi, p_miso, p_ss, 1, + clk0); + } + return 0; +} + diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 449105b..6f7ed2f 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -97,6 +97,18 @@ typedef interface spi_master_if { } spi_master_if; #endif + +[[distributable]] +void spi_master_fwk( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss[num_slaves], + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); + /**@}*/ // END: addtogroup spi_master_if /** Task that implements the SPI proctocol in master mode that is diff --git a/lib_spi/api/spi_fwk.h b/lib_spi/api/spi_fwk.h new file mode 100644 index 0000000..3a442fe --- /dev/null +++ b/lib_spi/api/spi_fwk.h @@ -0,0 +1,404 @@ +// Copyright 2021-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#pragma once + +/** \file + * \brief API for SPI I/O + */ + +/** + * The minimum number of clock ticks that should + * be specified for any SPI master delay value. + */ +#define SPI_MASTER_MINIMUM_DELAY 10 + +#include /* for size_t */ +#include +#include /* for byterev() */ +#include +#ifndef __XC__ +#include +#include +#include +#include +#else +#define xclock_t clock +#define port_t port +#define thread_mode_t int +#endif + +/* The SETC constant for pad delay is missing from xs2a_user.h */ +#define SPI_IO_SETC_PAD_DELAY(n) (0x7007 | ((n) << 3)) + +/* These appear to be missing from the public API of lib_xcore */ +#define SPI_IO_RESOURCE_SETCI(res, c) asm volatile( "setc res[%0], %1" :: "r" (res), "n" (c)) +#define SPI_IO_RESOURCE_SETC(res, r) asm volatile( "setc res[%0], %1" :: "r" (res), "r" (r)) + +/* is setpsc available in lib_xcore or anywhere else..??? */ +#ifndef __XC__ +__attribute__((always_inline)) +inline void spi_io_port_outpw( + resource_t __p, + uint32_t __w, + uint32_t __bpw) +{ + asm volatile("outpw res[%0], %1, %2" : : "r" (__p), "r" (__w), "r" (__bpw)); +} +#endif + +/** + * \addtogroup hil_spi_master hil_spi_master + * + * The public API for using the HIL SPI master. + * @{ + */ + +/** + * Enum type representing the different options + * for the SPI master sample delay. + */ +typedef enum { + spi_master_sample_delay_0 = 0, /**< Samples 1/2 clock cycle after output from device */ + spi_master_sample_delay_1 = 1, /**< Samples 3/4 clock cycle after output from device */ + spi_master_sample_delay_2 = 2, /**< Samples 1 clock cycle after output from device */ + spi_master_sample_delay_3 = 3, /**< Samples 1 and 1/4 clock cycle after output from device */ + spi_master_sample_delay_4 = 4, /**< Samples 1 and 1/2 clock cycle after output from device */ +} spi_master_sample_delay_t; + +/** + * Enum type used to set which of the two clock sources SCLK is derived from. + */ +typedef enum { + spi_master_source_clock_ref = 0, /**< SCLK is derived from the 100 MHz reference clock */ + spi_master_source_clock_xcore /**< SCLK is derived from the core clock */ +} spi_master_source_clock_t; + +/** + * Convenience macro that may be used to specify SPI Mode 0 to + * spi_master_device_init() or spi_slave() in place of cpol and cpha. + */ +#define SPI_MODE_0 0,0 + +/** + * Convenience macro that may be used to specify SPI Mode 1 to + * spi_master_device_init() or spi_slave() in place of cpol and cpha. + */ +#define SPI_MODE_1 0,1 + +/** + * Convenience macro that may be used to specify SPI Mode 2 to + * spi_master_device_init() or spi_slave() in place of cpol and cpha. + */ +#define SPI_MODE_2 1,0 + +/** + * Convenience macro that may be used to specify SPI Mode 3 to + * spi_master_device_init() or spi_slave() in place of cpol and cpha. + */ +#define SPI_MODE_3 1,1 + +/** + * Struct to hold a SPI master context. + * + * The members in this struct should not be accessed directly. + */ +typedef struct { + xclock_t clock_block; + port_t cs_port; + port_t sclk_port; + port_t mosi_port; + port_t miso_port; + uint32_t current_device; + int delay_before_transfer; +} spi_master_t; + +/** + * Struct type representing a SPI device connected to a SPI master + * interface. + * + * The members in this struct should not be accessed directly. + */ +typedef struct { + spi_master_t *spi_master_ctx; + spi_master_source_clock_t source_clock; + int clock_divisor; + spi_master_sample_delay_t miso_sample_delay; + uint32_t miso_pad_delay; + uint32_t miso_initial_trigger_delay; + uint32_t cs_assert_val; + uint32_t clock_delay; + uint32_t clock_bits; + uint32_t cs_to_clk_delay_ticks; + uint32_t clk_to_cs_delay_ticks; + uint32_t cs_to_cs_delay_ticks; + thread_mode_t thread_mode; +} spi_master_device_t; + +/** + * Initializes a SPI master I/O interface. + * + * Note: To guarantee timing in all situations, the SPI I/O interface + * implicitly sets the fast mode and high priority status register bits + * for the duration of SPI operations. This may reduce the MIPS of other + * threads based on overall system setup. + * + * \param spi The spi_master_t context to initialize. + * \param clock_block The clock block to use for the SPI master interface. + * \param cs_port The SPI interface's chip select port. This may be a multi-bit port. + * \param sclk_port The SPI interface's SCLK port. Must be a 1-bit port. + * \param mosi_port The SPI interface's MOSI port. Must be a 1-bit port. + * \param miso_port The SPI interface's MISO port. Must be a 1-bit port. + */ +void spi_master_init( + spi_master_t *spi, + xclock_t clock_block, + port_t cs_port, + port_t sclk_port, + port_t mosi_port, + port_t miso_port); + +/** + * Initialize a SPI device. Multiple SPI devices may be initialized per SPI interface. + * Each must be on a unique pin of the interface's chip select port. + * + * \param dev The context representing the device to initialize. + * \param spi The context representing the SPI master interface that the device is connected to. + * \param cs_pin The bit number of the chip select port that is connected to the device's chip select pin. + * \param cpol The clock polarity required by the device. + * \param cpha The clock phase required by the device. + * \param source_clock The source clock to derive SCLK from. See spi_master_source_clock_t. + * \param clock_divisor The value to divide the source clock by. + * The frequency of SCLK will be set to: + * - (F_src) / (4 * clock_divisor) when clock_divisor > 0 + * - (F_src) / (2) when clock_divisor = 0 + * Where F_src is the frequency of the source clock. + * \param miso_sample_delay When to sample MISO. See spi_master_sample_delay_t. + * \param miso_pad_delay The number of core clock cycles to delay sampling the MISO pad during + * a transaction. This allows for more fine grained adjustment + * of sampling time. The value may be between 0 and 5. + * \param cs_to_clk_delay_ticks The minimum number of reference clock ticks between assertion of chip select + * and the first clock edge. + * \param clk_to_cs_delay_ticks The minimum number of reference clock ticks between the last clock edge and + * de-assertion of chip select. + * \param cs_to_cs_delay_ticks The minimum number of reference clock ticks between transactions, which is between + * de-assertion of chip select and the end of one transaction, and its re-assertion at + * the beginning of the next. + */ +void spi_master_device_init( + spi_master_device_t *dev, + spi_master_t *spi, + uint32_t cs_pin, + int cpol, + int cpha, + spi_master_source_clock_t source_clock, + uint32_t clock_divisor, + spi_master_sample_delay_t miso_sample_delay, + uint32_t miso_pad_delay, + uint32_t cs_to_clk_delay_ticks, + uint32_t clk_to_cs_delay_ticks, + uint32_t cs_to_cs_delay_ticks); + +/** + * Starts a SPI transaction with the specified SPI device. This leaves chip select asserted. + * + * \param dev The SPI device with which to start a transaction. + */ +void spi_master_start_transaction( + spi_master_device_t *dev); + +/** + * Transfers data to/from the specified SPI device. This may be called + * multiple times during a single transaction. + * + * \param dev The SPI device with which to transfer data. + * \param data_out Buffer containing the data to send to the device. + * May be NULL if no data needs to be sent. + * \param data_in Buffer to save the data received from the device. + * May be NULL if the data received is not needed. + * \param len The length in bytes of the data to transfer. Both + * buffers must be at least this large if not NULL. + */ +void spi_master_transfer( + spi_master_device_t *dev, + uint8_t *data_out, + uint8_t *data_in, + size_t len); + +#ifndef __XC__ +/** + * Enforces a minimum delay between the time this is called and + * the next transfer. It must be called during a transaction. + * It returns immediately. + * + * \param dev The active SPI device. + * \param delay_ticks The number of reference clock ticks to delay. + */ +inline void spi_master_delay_before_next_transfer( + spi_master_device_t *dev, + uint32_t delay_ticks) +{ + spi_master_t *spi = dev->spi_master_ctx; + + spi->delay_before_transfer = 1; + + port_clear_trigger_time(spi->cs_port); + + /* Assert CS now */ + printstrln("here"); + printhexln(spi->cs_port); + printhexln(dev->cs_assert_val); + port_out(spi->cs_port, dev->cs_assert_val); + port_sync(spi->cs_port); + + /* + * Assert CS again, scheduled for earliest time the + * next transfer is allowed to start. + */ + if (delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + delay_ticks, dev->cs_assert_val); + } +} +#endif +/** + * Ends a SPI transaction with the specified SPI device. This leaves chip select de-asserted. + * + * \param dev The SPI device with which to end a transaction. + */ +void spi_master_end_transaction( + spi_master_device_t *dev); + +/** + * De-initializes the specified SPI master interface. This disables the + * ports and clock block. + * + * \param spi The spi_master_t context to de-initialize. + */ +void spi_master_deinit( + spi_master_t *spi); + +#ifndef __XC__ +/** + * Master has started a transaction + * + * This callback function will be called when the SPI master has asserted + * this slave's chip select. + * + * The input and output buffer may be the same; however, partial byte/incomplete + * reads will result in out_buf bits being masked off due to a partial bit output. + * + * \param app_data A pointer to application specific data provided + * by the application. Used to share data between + * \param out_buf The buffer to send to the master + * \param outbuf_len The length in bytes of out_buf + * \param in_buf The buffer to receive into from the master + * \param inbuf_len The length in bytes of in_buf + */ +typedef void (*slave_transaction_started_t)(void *app_data, uint8_t **out_buf, size_t *outbuf_len, uint8_t **in_buf, size_t *inbuf_len); + +/** + * Master has ended a transaction + * + * This callback function will be called when the SPI master has de-asserted + * this slave's chip select. + * + * The value of bytes_read contains the number of full bytes that are in + * in_buf. When read_bits is greater than 0, the byte after the last full byte + * contains the partial bits read. + * + * \param app_data A pointer to application specific data provided + * by the application. Used to share data between + * \param out_buf The buffer that had been provided to be sent to the master + * \param bytes_written The length in bytes of out_buf that had been written + * \param in_buf The buffer that had been provided to be received into from the master + * \param bytes_read The length in bytes of in_buf that has been read in to + * \param read_bits The length in bits of in_buf + */ +typedef void (*slave_transaction_ended_t)(void *app_data, uint8_t **out_buf, size_t bytes_written, uint8_t **in_buf, size_t bytes_read, size_t read_bits); + +/** + * This attribute must be specified on all SPI callback functions + * provided by the application. + */ +#define SPI_CALLBACK_ATTR __attribute__((fptrgroup("spi_callback"))) + +/**@}*/ // END: addtogroup hil_spi_master + +/** + * \addtogroup hil_spi_slave hil_spi_slave + * + * The public API for using the HIL SPI slave. + * @{ + */ + +/** + * Callback group representing callback events that can occur during the + * operation of the SPI slave task. Must be initialized by the application + * prior to passing it to one of the SPI slaves. + */ +typedef struct { + /** Pointer to the application's slave_transaction_started_t function to be called by the SPI device */ + SPI_CALLBACK_ATTR slave_transaction_started_t slave_transaction_started; + + /** Pointer to the application's slave_transaction_ended_t function to be called by the SPI device + * Note: The time spent in this callback must be less than the minimum CS deassertion to reassertion + * time. If this is violated the first word of the proceeding transaction will be lost. + */ + SPI_CALLBACK_ATTR slave_transaction_ended_t slave_transaction_ended; + + /** Pointer to application specific data which is passed to each callback. */ + void *app_data; +} spi_slave_callback_group_t; +#endif + +#if 0 +/** + * Initializes a SPI slave. + * + * \note Verified at 25000 kbps, with a 2000ns CS assertion to first clock + * in all modes. + * + * The CS to first clock minimum delay, sometimes referred to + * as setup time, will vary based on the duration of the + * slave_transaction_started callback. This parameter will be application + * specific. To determine the typical value, time the duration of the + * slave_transaction_started callback, and add 2000ns as a safety factor. + * If slave_transaction_started has a non-deterministic runtime, perhaps + * due to waiting on an XCORE resource, then the application developer must + * decide an appropriate CS to first SCLK specification. + * + * The minimum delay between consecutive transactions varies based + * on SPI mode, and if MISO is used. + * MISO | CPOL | CPHA | Min Delay (ns) + * --------------------------------------- + * enabled | 0 | 0 | 2270 + * enabled | 0 | 1 | 2240 + * enabled | 1 | 0 | 2240 + * enabled | 1 | 1 | 2270 + * disabled | 0 | 0 | 440 + * disabled | 0 | 1 | 420 + * disabled | 1 | 0 | 430 + * disabled | 1 | 1 | 430 + * + * \param spi_cbg The spi_slave_callback_group_t context to use. + * \param p_sclk The SPI slave's SCLK port. Must be a 1-bit port. + * \param p_mosi The SPI slave's MOSI port. Must be a 1-bit port. + * \param p_miso The SPI slave's MISO port. Must be a 1-bit port. + * \param p_cs The SPI slave's CS port. Must be a 1-bit port. + * \param clock_block The clock block to use for the SPI slave. + * \param cpol The clock polarity to use. + * \param cpha The clock phase to use. + */ +void spi_slave( + const spi_slave_callback_group_t *spi_cbg, + port_t p_sclk, + port_t p_mosi, + port_t p_miso, + port_t p_cs, + xclock_t clk, + int cpol, + int cpha, + uint32_t thread_mode); + +/**@}*/ // END: addtogroup hil_spi_slave + +#endif \ No newline at end of file diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c new file mode 100644 index 0000000..9a2f90a --- /dev/null +++ b/lib_spi/src/spi_master.c @@ -0,0 +1,317 @@ +// Copyright 2021-2022 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include "spi_fwk.h" + +void spi_master_start_transaction( + spi_master_device_t *dev) +{ + spi_master_t *spi = dev->spi_master_ctx; + + /* Save thread bits on entry */ + dev->thread_mode = local_thread_mode_get_bits(); + + /* enable fast mode and high priority */ + local_thread_mode_set_bits(thread_mode_fast | thread_mode_high_priority); + + if (dev->cs_assert_val != spi->current_device) { + spi->current_device = dev->cs_assert_val; + + if (dev->source_clock == spi_master_source_clock_ref) { + clock_set_source_clk_ref(spi->clock_block); + } else { + clock_set_source_clk_xcore(spi->clock_block); + } + clock_set_divide(spi->clock_block, dev->clock_divisor); + + if (spi->miso_port != 0) { + if ((dev->miso_sample_delay & 1) == 0) { + port_set_sample_falling_edge(spi->miso_port); + } else { + port_set_sample_rising_edge(spi->miso_port); + } + SPI_IO_RESOURCE_SETC(spi->miso_port, SPI_IO_SETC_PAD_DELAY(dev->miso_pad_delay)); + } + + /* Output the clock idle value */ + clock_start(spi->clock_block); + spi_io_port_outpw(spi->sclk_port, dev->clock_bits >> 1, 1); + port_sync(spi->sclk_port); + clock_stop(spi->clock_block); + + /* + * This transaction is with a different chip + * than last time, so there is no need to wait + * for the minimum CS to CS time. + */ + port_clear_trigger_time(spi->cs_port); + } else { + /* + * This ensures that the CS_high to CS_low + * minimum time is met. + */ + port_sync(spi->cs_port); + } + + /* + * The first transfer will sync on CS before starting to + * ensure the minimum CS to data time is met. + */ + spi_master_delay_before_next_transfer(dev, dev->cs_to_clk_delay_ticks); +} + +__attribute__((always_inline)) +inline uint32_t load_data_out( + const uint8_t *data_out, + const int len) +{ + uint32_t tmp; + uint32_t word_out; + + tmp = data_out[0] << 8; + if (len > 1) { + tmp |= data_out[1]; + } + word_out = tmp; + asm volatile("zip %0, %1, 0" :"+r"(tmp), "+r"(word_out)); + return bitrev(word_out); +} + +__attribute__((always_inline)) +inline void save_data_in( + uint8_t *data_in, + uint32_t word_in, + size_t bytes) +{ + uint32_t tmp; + + word_in = bitrev(word_in); + asm volatile("unzip %0, %1, 0" :"+r"(tmp), "+r"(word_in)); + if (bytes == 1) { + data_in[0] = word_in; + } else { + data_in[1] = word_in; + data_in[0] = (word_in >> 8) & 0xFF; + } +} + +void spi_master_transfer( + spi_master_device_t *dev, + uint8_t *data_out, + uint8_t *data_in, + size_t len) +{ + const uint32_t start_time = 1; + spi_master_t *spi = dev->spi_master_ctx; + uint32_t word_count; + uint32_t remainder; + uint32_t tw; + uint32_t word; + const int do_output = data_out != NULL && spi->mosi_port != 0; + const int do_input = data_in != NULL && spi->miso_port != 0; + + if (len == 0) { + return; + } + + word_count = len / sizeof(uint16_t); + remainder = len & sizeof(uint16_t) - 1; /* get the byte remainder */ + + if (spi->delay_before_transfer) { + /* Ensure the delay time is met */ + port_sync(spi->cs_port); + spi->delay_before_transfer = 0; + } else { + port_clear_trigger_time(spi->cs_port); + } + + port_set_trigger_time(spi->sclk_port, start_time + dev->clock_delay); + + if (do_output) { + port_set_trigger_time(spi->mosi_port, start_time); + } + + tw = len == 1 ? 16 : 32; + + spi_io_port_outpw(spi->sclk_port, dev->clock_bits, tw); + + if (do_output) { + spi_io_port_outpw(spi->mosi_port, load_data_out(data_out, len), tw); + data_out += 2; + } + if (do_input) { + port_set_trigger_time(spi->miso_port, start_time + (tw - 2) + dev->miso_initial_trigger_delay); /* don't ask. port timing is weird */ + } + + clock_start(spi->clock_block); + + if (word_count > 0) { + while (word_count-- != 1) { + port_out(spi->sclk_port, dev->clock_bits); + + if (do_output) { + word = load_data_out(data_out, 2); + port_out(spi->mosi_port, word); + } + if (do_input) { + word = port_in(spi->miso_port); + save_data_in(data_in, word, 2); + } + data_out += 2; + data_in += 2; + } + + if (remainder > 0) { + spi_io_port_outpw(spi->sclk_port, dev->clock_bits, 16); + + if (do_output) { + word = load_data_out(data_out, 1); + spi_io_port_outpw(spi->mosi_port, word, 16); + } + if (do_input) { + word = port_in(spi->miso_port); + port_set_shift_count(spi->miso_port, 16); + save_data_in(data_in, word, 2); + data_in += 2; + } + } + } + + if (do_input) { + word = port_in(spi->miso_port); + save_data_in(data_in, word, remainder); + } + + port_sync(spi->sclk_port); + clock_stop(spi->clock_block); + + /* Assert CS again now */ + port_out(spi->cs_port, dev->cs_assert_val); + port_sync(spi->cs_port); + + /* + * And assert CS again, scheduled for earliest time CS + * is allowed to deassert. + */ + if (dev->clk_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->clk_to_cs_delay_ticks, dev->cs_assert_val); + } +} + +void spi_master_end_transaction( + spi_master_device_t *dev) +{ + const uint32_t cs_deassert_val = 0xFFFFFFFF; + spi_master_t *spi = dev->spi_master_ctx; + + /* disable fast mode and high priority */ + local_thread_mode_clear_bits(thread_mode_fast | thread_mode_high_priority); + + /* Restore original thread bits on exit */ + local_thread_mode_set_bits(dev->thread_mode); + + port_sync(spi->cs_port); + + printstrln("there"); + port_out(spi->cs_port, cs_deassert_val); + port_sync(spi->cs_port); + + /* + * Deassert CS again, scheduled for earliest time CS + * is allowed to be re-asserted. The next transaction + * will sync on CS before starting to ensure the minimum + * CS to CS time is met. + */ + if (dev->cs_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->cs_to_cs_delay_ticks, cs_deassert_val); + } +} + +void spi_master_deinit( + spi_master_t *spi) +{ + port_disable(spi->cs_port); + if (spi->mosi_port != 0) { + port_disable(spi->mosi_port); + } + if (spi->miso_port != 0) { + port_disable(spi->miso_port); + } + port_disable(spi->sclk_port); + clock_disable(spi->clock_block); +} + +void spi_master_device_init( + spi_master_device_t *dev, + spi_master_t *spi, + uint32_t cs_pin, + int cpol, + int cpha, + spi_master_source_clock_t source_clock, + uint32_t clock_divisor, + spi_master_sample_delay_t miso_sample_delay, + uint32_t miso_pad_delay, + uint32_t cs_to_clk_delay_ticks, + uint32_t clk_to_cs_delay_ticks, + uint32_t cs_to_cs_delay_ticks) +{ + dev->spi_master_ctx = spi; + + dev->source_clock = source_clock; + dev->clock_divisor = clock_divisor; + dev->miso_sample_delay = miso_sample_delay; + + dev->miso_initial_trigger_delay = (miso_sample_delay + 1) >> 1; + dev->miso_pad_delay = miso_pad_delay; + + dev->cs_assert_val = 0xFFFFFFFF & ~(1 << cs_pin); + dev->clock_delay = cpha ? 0 : 1; + dev->clock_bits = cpol ? 0xAAAAAAAA : 0x55555555; + + dev->cs_to_clk_delay_ticks = cs_to_clk_delay_ticks; + dev->clk_to_cs_delay_ticks = clk_to_cs_delay_ticks; + dev->cs_to_cs_delay_ticks = cs_to_cs_delay_ticks; +} + +void spi_master_init( + spi_master_t *spi, + xclock_t clock_block, + port_t cs_port, + port_t sclk_port, + port_t mosi_port, + port_t miso_port) +{ + /* Setup the clock block */ + spi->clock_block = clock_block; + clock_enable(spi->clock_block); + + /* Setup the chip select port */ + spi->cs_port = cs_port; + port_enable(spi->cs_port); + port_set_clock(spi->cs_port, XS1_CLKBLK_REF); + port_out(spi->cs_port, 0xFFFFFFFF); + port_sync(spi->cs_port); + spi->current_device = 0xFFFFFFFF; + + /* Setup the SCLK port */ + spi->sclk_port = sclk_port; + port_start_buffered(spi->sclk_port, 32); + port_set_clock(spi->sclk_port, spi->clock_block); + + /* Setup the MOSI port */ + spi->mosi_port = mosi_port; + if (mosi_port != 0) { + port_start_buffered(spi->mosi_port, 32); + port_set_clock(spi->mosi_port, spi->clock_block); + port_clear_buffer(spi->mosi_port); + } + + /* Setup the MISO port */ + spi->miso_port = miso_port; + if (miso_port != 0) { + port_start_buffered(spi->miso_port, 32); + port_set_clock(spi->miso_port, spi->clock_block); + port_clear_buffer(spi->miso_port); + } +} diff --git a/lib_spi/src/spi_master_fwk.xc b/lib_spi/src/spi_master_fwk.xc new file mode 100644 index 0000000..feb58c1 --- /dev/null +++ b/lib_spi/src/spi_master_fwk.xc @@ -0,0 +1,83 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + +#pragma unsafe arrays +[[distributable]] +void spi_master_fwk(server interface spi_master_if i[num_clients], + static const size_t num_clients, + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + out port p_ss[num_slaves], + static const size_t num_slaves, + clock ?cb){ + + + // Declare the fwk_io_master + // MODE == 1 fixed for now + #define CPOL 0 + #define CPHA 1 + #define DIV 50 + + if(isnull(cb)){ + printstrln("Must supply clockblock"); + } + + spi_master_t spi_ctx; + spi_master_device_t spi_dev; + unsafe{ + spi_master_device_init(&spi_dev, &spi_ctx, + 0, // cs pin in port + CPOL, CPHA, + spi_master_source_clock_xcore, + DIV, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); + spi_master_init(&spi_ctx, cb, (port)p_ss[0], (port)sclk, (port)mosi, (port)miso); + } + + + int accepting_new_transactions = 1; + + while(1){ + select { + case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode):{ + accepting_new_transactions = 0; + spi_master_start_transaction(&spi_dev); + break; + } + case i[int x].end_transaction(unsigned ss_deassert_time):{ + //Unlock the transaction + accepting_new_transactions = 1; + spi_master_end_transaction(&spi_dev); + break; + } + case i[int x].transfer8(uint8_t data)-> uint8_t r :{ + printstrln("transfer8"); + printhexln((int)&data); + printhexln((int)&r); + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 1); + printstrln("transfer8"); + break; + } + case i[int x].transfer32(uint32_t data) -> uint32_t r:{ + printstrln("transfer32"); + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 4); + printstrln("transfer32"); + break; + } + } + } + +} + From c18302ddc61ab0c00e8799d5eab71a4eeca9b830 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 7 Jul 2025 08:35:44 +0100 Subject: [PATCH 16/57] Fromatting --- lib_spi/src/spi_master_fwk.xc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib_spi/src/spi_master_fwk.xc b/lib_spi/src/spi_master_fwk.xc index feb58c1..b4c2a6f 100644 --- a/lib_spi/src/spi_master_fwk.xc +++ b/lib_spi/src/spi_master_fwk.xc @@ -51,9 +51,9 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], while(1){ select { case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode):{ - accepting_new_transactions = 0; - spi_master_start_transaction(&spi_dev); + unsigned speed_in_khz, spi_mode_t mode):{ + accepting_new_transactions = 0; + spi_master_start_transaction(&spi_dev); break; } case i[int x].end_transaction(unsigned ss_deassert_time):{ From 2b79d313ee1a5dca61dcb7cc27b9e0d51e493331 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 2 Jul 2025 15:40:18 +0100 Subject: [PATCH 17/57] Update examples to XCCM copyright update Update settings to new CD p/n API doxy and compiler friendly Finish porting doxy and make master example have two build configs --- CHANGELOG.rst | 1 + Jenkinsfile | 4 +- doc/Doxyfile.inc | 2 +- doc/images/spi_master_async_state.pdf | Bin 16039 -> 0 bytes doc/images/spi_master_async_state.svg | 65 ++ doc/images/spi_master_connect.pdf | Bin 10974 -> 0 bytes doc/images/spi_master_connect.svg | 54 ++ doc/images/spi_master_sync_state.pdf | Bin 14076 -> 0 bytes doc/images/spi_master_sync_state.svg | 40 + doc/images/spi_master_task_diag.pdf | Bin 19955 -> 0 bytes doc/images/spi_master_task_diag.svg | 44 + doc/images/spi_slave_connect.pdf | Bin 10677 -> 0 bytes doc/images/spi_slave_connect.svg | 46 + doc/images/spi_slave_task_diag.pdf | Bin 20214 -> 0 bytes doc/images/spi_slave_task_diag.svg | 44 + doc/rst/lib_spi.rst | 114 ++- examples/AN00160_using_SPI_master/.cproject | 851 ----------------- examples/AN00160_using_SPI_master/.project | 42 - .../AN00160_using_SPI_master.launch | 70 -- .../AN00160_using_SPI_master/CMakeLists.txt | 33 + examples/AN00160_using_SPI_master/Makefile | 36 - examples/AN00160_using_SPI_master/src/main.xc | 57 +- examples/AN00161_using_SPI_slave/.cproject | 869 ------------------ examples/AN00161_using_SPI_slave/.project | 42 - .../AN00161_using_SPI_slave.launch | 71 -- .../AN00161_using_SPI_slave/CMakeLists.txt | 26 + examples/AN00161_using_SPI_slave/Makefile | 35 - examples/AN00161_using_SPI_slave/src/main.xc | 2 +- examples/CMakeLists.txt | 7 + .../lib_spi_master_tester/src/common.h | 2 +- .../src/spi_async_tester.h | 2 +- .../src/spi_sync_tester.h | 2 +- legacy_tests/runtests.py | 2 +- .../src/spi_master_async_multi_client.xc | 2 +- .../src/spi_master_async_multi_device.xc | 2 +- .../src/spi_master_async_rx_tx.xc | 2 +- .../src/spi_master_async_shutdown.xc | 2 +- legacy_tests/spi_master_checker.py | 2 +- .../src/spi_master_sync_benchmark.xc | 2 +- .../spi_master_sync_clock_port_sharing.xc | 2 +- .../src/spi_master_sync_multi_client.xc | 2 +- .../src/spi_master_sync_multi_device.xc | 2 +- .../src/spi_master_sync_rx_tx.xc | 2 +- .../src/spi_slave_benchmark.xc | 2 +- legacy_tests/spi_slave_checker.py | 2 +- .../spi_slave_rx_tx/src/spi_slave_rx_tx.xc | 2 +- .../test_master_async_multi_client.py | 2 +- .../test_master_async_multi_device.py | 2 +- legacy_tests/test_master_async_rx_tx.py | 2 +- legacy_tests/test_master_async_shutdown.py | 2 +- legacy_tests/test_master_sync_benchmark.py | 2 +- .../test_master_sync_clock_port_sharing.py | 2 +- legacy_tests/test_master_sync_multi_client.py | 2 +- legacy_tests/test_master_sync_multi_device.py | 2 +- legacy_tests/test_master_sync_rx_tx.py | 2 +- legacy_tests/test_slave_benchmark.py | 2 +- legacy_tests/test_slave_rx_tx.py | 2 +- lib_spi/api/spi.h | 120 ++- lib_spi/src/spi_async.xc | 2 +- lib_spi/src/spi_slave.xc | 2 +- lib_spi/src/spi_sync.xc | 2 +- python/setup.py | 2 +- settings.yml | 2 +- 63 files changed, 569 insertions(+), 2172 deletions(-) delete mode 100644 doc/images/spi_master_async_state.pdf create mode 100644 doc/images/spi_master_async_state.svg delete mode 100644 doc/images/spi_master_connect.pdf create mode 100644 doc/images/spi_master_connect.svg delete mode 100644 doc/images/spi_master_sync_state.pdf create mode 100644 doc/images/spi_master_sync_state.svg delete mode 100644 doc/images/spi_master_task_diag.pdf create mode 100644 doc/images/spi_master_task_diag.svg delete mode 100644 doc/images/spi_slave_connect.pdf create mode 100644 doc/images/spi_slave_connect.svg delete mode 100644 doc/images/spi_slave_task_diag.pdf create mode 100644 doc/images/spi_slave_task_diag.svg delete mode 100644 examples/AN00160_using_SPI_master/.cproject delete mode 100644 examples/AN00160_using_SPI_master/.project delete mode 100644 examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch create mode 100644 examples/AN00160_using_SPI_master/CMakeLists.txt delete mode 100644 examples/AN00160_using_SPI_master/Makefile delete mode 100644 examples/AN00161_using_SPI_slave/.cproject delete mode 100644 examples/AN00161_using_SPI_slave/.project delete mode 100644 examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch create mode 100644 examples/AN00161_using_SPI_slave/CMakeLists.txt delete mode 100644 examples/AN00161_using_SPI_slave/Makefile create mode 100644 examples/CMakeLists.txt diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 9ded6e3..bc86a06 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -6,6 +6,7 @@ lib_spi change log * CHANGED: Refresh to use latest doc builder and library format * ADDED: Support for XCommon CMake build system + * REMOVED: XCORE-200 targets in examples (now targets XK-EVK-XU316) 3.3.0 ----- diff --git a/Jenkinsfile b/Jenkinsfile index 3c7d392..6376d5b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -19,12 +19,12 @@ pipeline { ) string( name: 'TOOLS_VERSION', - defaultValue: '-j -b markp_xsim_expose_signals_from_usb_shim latest', + defaultValue: '15.3.1', description: 'The XTC tools version' ) string( name: 'XMOSDOC_VERSION', - defaultValue: 'v7.2.0', + defaultValue: 'v7.3.0', description: 'The xmosdoc version' ) string( diff --git a/doc/Doxyfile.inc b/doc/Doxyfile.inc index 0a55ac7..12418ea 100644 --- a/doc/Doxyfile.inc +++ b/doc/Doxyfile.inc @@ -1,7 +1,7 @@ # This file provides overrides to the Doxyfile configuration PROJECT_NAME = lib_spi -PROJECT_BRIEF = "SPI library" +PROJECT_BRIEF = "SPI Library" INPUT = ../lib_spi/api diff --git a/doc/images/spi_master_async_state.pdf b/doc/images/spi_master_async_state.pdf deleted file mode 100644 index 8fd6dfd9572853ab4cb7e0a49966cd82cfdd36e5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16039 zcmbum1ymi&7QczR1h)VO2(AZrcXxMpcMTBSU4n$*5ZocSySoH;cV|fMyYJoif3s$0 zt?5H|b^Xq++EulyPW58-M=CEYN(-c8fg`OuDSv`v0x$sV3@zcfxdHUjCbnkI<^bk* zNf8bJ0MLtCSUa0IzNgj(&L+YpMs~&~aJ;;5PR@=d1~zc+8Kdelb|2XgT94HB_j%MY zM0|7+(ILUEW9Rsh1?2PaxMU0pqo$Fsf8Fs|y1Jf>LY&ev9OI0Iehl~a&U>D0y(Y|5 z&33xxu-qTi+f9Axj(QvPv)_EUIv?}9B71bpW>sBl-ha62c2j>w{(>d{Jlg7cVifvX zmayM`$7vXw?vs3a7NdAfl)O<_8%y$|e_thC=Z?1ycW8htKhn<9rF7`B1K~7A(bB+} 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master clock speeds The asynchronous SPI master is limited only by the clock divider on the clock block. This means that for the 100MHz reference clock, -the asynchronous master can output a clock at up to 100MHz +the asynchronous master can output a clock at up to 100MHz, port timing and hardware permitting. .. list-table:: SPI master timings (asynchronous) :header-rows: 1 @@ -328,7 +328,7 @@ the slave select line. Operations such as ``spi.transfer8`` will block until the operation is completed on the bus. More information on interfaces and tasks can be be found in -the :ref:`XMOS Programming Guide`. By default the +the `XMOS Programming Guide `_. By default the SPI synchronous master mode component does not use any logical cores of its own. It is a *distributed* task which means it will perform its function on the logical core of the application task connected to @@ -475,7 +475,7 @@ SPI slave components are instantiated as parallel tasks that run in a ``par`` statement. The application can connect via an interface connection. -.. figure:: ../images/spi_slave_task_diag.pdf +.. figure:: ../images/spi_slave_task_diag.svg SPI slave task diagram @@ -542,9 +542,11 @@ subsequent transfers either provide or consume data:: } } -Note that the time taken to handle the callbacks will determine the -timing requirements of the SPI slave. See application note AN00161 for -more details on different ways of working with the SPI slave component. +.. note:: + + The time taken to handle the callbacks will determine the + timing requirements of the SPI slave. See application note AN00161 for + more details on different ways of working with the SPI slave component. |newpage| @@ -588,7 +590,7 @@ To configure the build, run the following from an XTC command prompt: .. code-block:: console cd examples - cd app_template + cd AN00160_using_SPI_master cmake -G "Unix Makefiles" -B build Any missing dependencies will be downloaded by the build system at this configure step. @@ -602,14 +604,19 @@ Finally, the application binaries can be built using ``xmake``: Running ======= -To run the application return to the ``/examples/app_template`` directory and run the following +To run the application return to the ``/examples/AN00160_using_SPI_master`` directory and run the following command: .. code-block:: console - xrun --xscope bin/app_template.xe + xrun --xscope bin/SYNC/app_spi_master_SYNC.xe + +As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: + + Sending SPI traffic + 2005400 + Done. -As application runs and prints "Hello world!" to the console. |newpage| @@ -618,38 +625,47 @@ As application runs and prints "Hello world!" to the console. Resource Usage ************** -TODO - Turn me into a table - - * - configuration: Master (synchronous, zero clock blocks) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D}; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (synchronous, one clock block) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb = XS1_CLKBLK_1; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (asynchronous) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb0 = XS1_CLKBLK_1; clock cb1 = XS1_CLKBLK_2; - - locals: interface spi_master_async_if i[1]; - - fn: spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (32 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (8 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); - - pins: 4 - - ports: 4 (1-bit) +Each of the SPI implementations use a number of `xcore` resources which include ports, clock-blocks and may include hardware threads. The table :numref:`res_use_table` + + +.. _res_use_table: + +.. list-table:: `xcore` resource usage for SPI + :widths: 20 30 5 10 5 + :header-rows: 1 + :stub-columns: 1 + + * - configuration + - api + - pins + - ports + - threads + * - Master (synchronous, zero clock blocks) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + - 4 + - 4 (1-bit) + - 0 + * - Master (synchronous, one clock block) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + - 4 + - 4 (1-bit) + - 0 + * - Master (asynchronous) + - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + - 4 + - 4 (1-bit) + - 1 + * - Slave (32 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); + - 4 + - 4 (1-bit) + - 1 + * - Slave (8 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); + - 4 + - 4 (1-bit) + - 1 + The number of pins is reduced if either of the data lines are not required. @@ -663,10 +679,12 @@ Master API All SPI master functions can be accessed via the ``spi.h`` header:: - #include + #include "spi.h" -You will also have to add ``lib_spi`` to the -``USED_MODULES`` field of your application Makefile. +You will also have to add ``lib_spi`` to the application's ``APP_DEPENDENT_MODULES`` list in +`CMakeLists.txt`, for example:: + + set(APP_DEPENDENT_MODULES "lib_spi") Supporting types ................ @@ -691,14 +709,14 @@ Creating an SPI master instance SPI master interface ..................... -.. doxygeninterface:: spi_master_if +.. doxygengroup:: spi_master_if |newpage| SPI master asynchronous interface ................................. -.. doxygeninterface:: spi_master_async_if +.. doxygengroup:: spi_master_async_if |newpage| @@ -726,7 +744,7 @@ Creating an SPI slave instance The SPI slave interface API ........................... -.. doxygeninterface:: spi_slave_callback_if +.. doxygengroup:: spi_slave_callback_if diff --git a/examples/AN00160_using_SPI_master/.cproject b/examples/AN00160_using_SPI_master/.cproject deleted file mode 100644 index 27de2ed..0000000 --- a/examples/AN00160_using_SPI_master/.cproject +++ /dev/null @@ -1,851 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00160_using_SPI_master/.project b/examples/AN00160_using_SPI_master/.project deleted file mode 100644 index b741264..0000000 --- a/examples/AN00160_using_SPI_master/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00160_using_SPI_master - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch b/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch deleted file mode 100644 index 3339834..0000000 --- a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch +++ /dev/null @@ -1,70 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00160_using_SPI_master/CMakeLists.txt b/examples/AN00160_using_SPI_master/CMakeLists.txt new file mode 100644 index 0000000..703ed39 --- /dev/null +++ b/examples/AN00160_using_SPI_master/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_master) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +list(APPEND APP_DEPENDENT_MODULES "lib_spi") + +# Flags +set(COMPILER_FLAGS_COMMON + -Os + -g + -report + -Wall + -Werror +) + +set(APP_COMPILER_FLAGS_SYNC + ${COMPILER_FLAGS_COMMON}) + +set(APP_COMPILER_FLAGS_ASYNC + ${COMPILER_FLAGS_COMMON} + -DSPI_USE_ASYNC=1) + + +XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master/Makefile b/examples/AN00160_using_SPI_master/Makefile deleted file mode 100644 index 3b788af..0000000 --- a/examples/AN00160_using_SPI_master/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -ADDITIONAL_FLAGS = -DXCORE_AI_EXPLORER=1 -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00160_using_SPI_master - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g $(ADDITIONAL_FLAGS) - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 1270725..3acd1b4 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -7,19 +7,12 @@ #include #include -/* These ports are used for the SPI master */ -#ifdef XCORE_AI_EXPLORER + out buffered port:32 p_sclk = WIFI_CLK; out port p_ss[1] = {WIFI_CS_N}; in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; -#else -out buffered port:32 p_sclk = on tile[0]: XS1_PORT_1I; -out port p_ss[1] = on tile[0]: {XS1_PORT_1J}; -in buffered port:32 p_miso = on tile[0]: XS1_PORT_1K; -out buffered port:32 p_mosi = on tile[0]: XS1_PORT_1L; -#endif clock clk0 = on tile[0]: XS1_CLKBLK_1; clock clk1 = on tile[0]: XS1_CLKBLK_2; @@ -33,7 +26,6 @@ void app(client spi_master_if spi) { uint8_t val; printstrln("Sending SPI traffic"); -#if XCORE_AI_EXPLORER p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); @@ -47,18 +39,6 @@ void app(client spi_master_if spi) reg = spi.transfer32(0x00); spi.end_transaction(0); printhexln(reg << 16 | reg >> 16); -#else - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0xab); - val = spi.transfer32(0xcc); - val = spi.transfer8(0xfe); - spi.end_transaction(100); - - delay_microseconds(40); - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0x22); - spi.end_transaction(100); -#endif printstrln("Done."); _exit(0); @@ -127,22 +107,9 @@ void async_app(client spi_master_async_if spi) spi.shutdown(); } -#if 1 -int main(void) { - interface spi_master_if i_spi[1]; - par { - on tile[0]: app(i_spi[0]); - on tile[0]: spi_master(i_spi, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - null); - } - return 0; -} -#endif -/* Uncomment the main below (and comment out the one above) to try the - async version. */ -#if 0 +#if SPI_USE_ASYNC + int main(void) { interface spi_master_async_if i_spi_async[1]; par { @@ -157,4 +124,18 @@ int main(void) { } return 0; } -#endif + +#else + +int main(void) { + interface spi_master_if i_spi[1]; + par { + on tile[0]: app(i_spi[0]); + on tile[0]: spi_master(i_spi, 1, + p_sclk, p_mosi, p_miso, p_ss, 1, + null); + } + return 0; +} + +#endif /*SPI_USE_ASYNC*/ diff --git a/examples/AN00161_using_SPI_slave/.cproject b/examples/AN00161_using_SPI_slave/.cproject deleted file mode 100644 index 6139ffa..0000000 --- a/examples/AN00161_using_SPI_slave/.cproject +++ /dev/null @@ -1,869 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00161_using_SPI_slave/.project b/examples/AN00161_using_SPI_slave/.project deleted file mode 100644 index 5c1ddbb..0000000 --- a/examples/AN00161_using_SPI_slave/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00161_using_SPI_slave - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch b/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch deleted file mode 100644 index 87a5113..0000000 --- a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00161_using_SPI_slave/CMakeLists.txt b/examples/AN00161_using_SPI_slave/CMakeLists.txt new file mode 100644 index 0000000..823970e --- /dev/null +++ b/examples/AN00161_using_SPI_slave/CMakeLists.txt @@ -0,0 +1,26 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_slave) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +list(APPEND APP_DEPENDENT_MODULES "lib_spi") + +# Flags +set( + APP_COMPILER_FLAGS + -Os + -g + -report + -Wall + -Werror +) + +XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00161_using_SPI_slave/Makefile b/examples/AN00161_using_SPI_slave/Makefile deleted file mode 100644 index 7b9a2f5..0000000 --- a/examples/AN00161_using_SPI_slave/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-L16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00161_using_SPI_slave - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g -report -DDEBUG_PRINT_ENABLE=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/AN00161_using_SPI_slave/src/main.xc index 6931682..659263c 100644 --- a/examples/AN00161_using_SPI_slave/src/main.xc +++ b/examples/AN00161_using_SPI_slave/src/main.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt new file mode 100644 index 0000000..2668e58 --- /dev/null +++ b/examples/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +project(lib_camera_examples) + +add_subdirectory(AN00160_using_SPI_master) +add_subdirectory(AN00161_using_SPI_slave) \ No newline at end of file diff --git a/legacy_tests/lib_spi_master_tester/src/common.h b/legacy_tests/lib_spi_master_tester/src/common.h index f002f32..753a74a 100644 --- a/legacy_tests/lib_spi_master_tester/src/common.h +++ b/legacy_tests/lib_spi_master_tester/src/common.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef COMMON_H_ #define COMMON_H_ diff --git a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h b/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h index 7bec60a..226fdad 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h +++ b/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ diff --git a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h b/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h index 0576379..43d0662 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h +++ b/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ diff --git a/legacy_tests/runtests.py b/legacy_tests/runtests.py index 270f4eb..2921a12 100755 --- a/legacy_tests/runtests.py +++ b/legacy_tests/runtests.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index d3c170e..9e5babd 100644 --- a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc b/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc index d5b5d14..82f5ed2 100644 --- a/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc +++ b/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index 64ba336..898a320 100644 --- a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc index e8233b4..38576f3 100644 --- a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc +++ b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc @@ -1,4 +1,4 @@ -// Copyright 2020-2021 XMOS LIMITED. +// Copyright 2020-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_checker.py b/legacy_tests/spi_master_checker.py index cb60ad8..bac4623 100644 --- a/legacy_tests/spi_master_checker.py +++ b/legacy_tests/spi_master_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2022 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest diff --git a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index cf79bfb..9364eb1 100644 --- a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc b/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc index 2e05a57..44c8521 100644 --- a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc +++ b/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc @@ -1,4 +1,4 @@ -// Copyright 2020-2021 XMOS LIMITED. +// Copyright 2020-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 04e71a1..688fdb8 100644 --- a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index f0e5459..b9bc669 100644 --- a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 4b02070..790ed37 100644 --- a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc b/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc index 6e212cd..6708438 100644 --- a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc +++ b/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/spi_slave_checker.py b/legacy_tests/spi_slave_checker.py index 43c82b6..de08d37 100644 --- a/legacy_tests/spi_slave_checker.py +++ b/legacy_tests/spi_slave_checker.py @@ -1,4 +1,4 @@ -# Copyright 2015-2022 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest diff --git a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc b/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc index 991d283..b10866b 100644 --- a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc +++ b/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/legacy_tests/test_master_async_multi_client.py b/legacy_tests/test_master_async_multi_client.py index 8714e2c..d38531c 100644 --- a/legacy_tests/test_master_async_multi_client.py +++ b/legacy_tests/test_master_async_multi_client.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_multi_device.py b/legacy_tests/test_master_async_multi_device.py index d817883..169017e 100644 --- a/legacy_tests/test_master_async_multi_device.py +++ b/legacy_tests/test_master_async_multi_device.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_rx_tx.py b/legacy_tests/test_master_async_rx_tx.py index f3b1099..019fe2b 100644 --- a/legacy_tests/test_master_async_rx_tx.py +++ b/legacy_tests/test_master_async_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_async_shutdown.py b/legacy_tests/test_master_async_shutdown.py index 090eaef..848176b 100644 --- a/legacy_tests/test_master_async_shutdown.py +++ b/legacy_tests/test_master_async_shutdown.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_benchmark.py b/legacy_tests/test_master_sync_benchmark.py index d64f928..f33e6cd 100644 --- a/legacy_tests/test_master_sync_benchmark.py +++ b/legacy_tests/test_master_sync_benchmark.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_clock_port_sharing.py b/legacy_tests/test_master_sync_clock_port_sharing.py index e14b0bb..6cdaeb6 100644 --- a/legacy_tests/test_master_sync_clock_port_sharing.py +++ b/legacy_tests/test_master_sync_clock_port_sharing.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_multi_client.py b/legacy_tests/test_master_sync_multi_client.py index 4d8b0ec..dafd2d8 100644 --- a/legacy_tests/test_master_sync_multi_client.py +++ b/legacy_tests/test_master_sync_multi_client.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_multi_device.py b/legacy_tests/test_master_sync_multi_device.py index 4f2ae50..556cb09 100644 --- a/legacy_tests/test_master_sync_multi_device.py +++ b/legacy_tests/test_master_sync_multi_device.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_master_sync_rx_tx.py b/legacy_tests/test_master_sync_rx_tx.py index 80b03e8..e5449cb 100644 --- a/legacy_tests/test_master_sync_rx_tx.py +++ b/legacy_tests/test_master_sync_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_master_checker import SPIMasterChecker diff --git a/legacy_tests/test_slave_benchmark.py b/legacy_tests/test_slave_benchmark.py index f8fb4bd..8c4ad28 100644 --- a/legacy_tests/test_slave_benchmark.py +++ b/legacy_tests/test_slave_benchmark.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_slave_checker import SPISlaveChecker diff --git a/legacy_tests/test_slave_rx_tx.py b/legacy_tests/test_slave_rx_tx.py index 04c0211..7d92f3f 100644 --- a/legacy_tests/test_slave_rx_tx.py +++ b/legacy_tests/test_slave_rx_tx.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import xmostest from spi_slave_checker import SPISlaveChecker diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index e3314f9..449105b 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -1,10 +1,29 @@ -// Copyright 2014-2021 XMOS LIMITED. +// Copyright 2014-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef _spi_h_ #define _spi_h_ #include #include #include +#include + +// These are needed for DOXYGEN to render properly +#ifndef __DOXYGEN__ +#define static_const_unsigned static const unsigned +#define static_const_size_t static const size_t +#define out_port out port +#define in_port in port +#define async_master_shutdown shutdown +#define async_master_send_stop_bit send_stop_bit +#define async_master_read read +#define async_master_write write +#define slave_void slave void +#define static_const_spi_mode_t static const spi_mode_t +#define static_const_spi_transfer_type_t static const spi_transfer_type_t +#define static_const_spi_transfer_type_t static const spi_transfer_type_t +#define uint32_t_movable_ptr_t uint32_t * movable +#define uint8_t_movable_ptr_t uint8_t * movable +#endif /** This type indicates what mode an SPI component should use */ typedef enum spi_mode_t { @@ -16,7 +35,14 @@ typedef enum spi_mode_t { /** This interface allows clients to interact with SPI master task. */ +#ifndef __DOXYGEN__ typedef interface spi_master_if { +#endif + + /** + * \addtogroup spi_master_if + * @{ + */ /** Begin a transaction. * @@ -67,7 +93,11 @@ typedef interface spi_master_if { * \returns the data read in from the MISO port. */ uint32_t transfer32(uint32_t data); +#ifndef __DOXYGEN__ } spi_master_if; +#endif + +/**@}*/ // END: addtogroup spi_master_if /** Task that implements the SPI proctocol in master mode that is connected to a multiple slaves on the bus. @@ -92,21 +122,29 @@ typedef interface spi_master_if { \param clk a clock for the component to use. */ [[distributable]] -void spi_master(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock ?clk); +void spi_master( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss[num_slaves], + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); + +/** + * \addtogroup spi_master_async_if + * @{ + */ /** Asynchronous interface to an SPI component. * * This interface allows programs to offload SPI bus transfers to another * task. An asynchronous notification occurs when the transfer is complete. */ +#ifndef __DOXYGEN__ typedef interface spi_master_async_if { +#endif /** Begin a transaction. * * This will start a transaction on the bus. During a transaction, no @@ -149,8 +187,8 @@ typedef interface spi_master_async_if { * transfer will consist of undefined values. * \param nbytes The number of bytes to transfer over the bus. */ - void init_transfer_array_8(uint8_t * movable inbuf, - uint8_t * movable outbuf, + void init_transfer_array_8(uint8_t_movable_ptr_t inbuf, + uint8_t_movable_ptr_t outbuf, size_t nbytes); /** Initialize Transfer an array of bytes over the spi bus. @@ -168,8 +206,8 @@ typedef interface spi_master_async_if { * transfer will consist of undefined values. * \param nwords The number of words to transfer over the bus. */ - void init_transfer_array_32(uint32_t * movable inbuf, - uint32_t * movable outbuf, + void init_transfer_array_32(uint32_t_movable_ptr_t inbuf, + uint32_t_movable_ptr_t outbuf, size_t nwords); @@ -192,8 +230,8 @@ typedef interface spi_master_async_if { * pointer that was transmitted during the transfer. */ [[clears_notification]] - void retrieve_transfer_buffers_8(uint8_t * movable &inbuf, - uint8_t * movable &outbuf); + void retrieve_transfer_buffers_8(REFERENCE_PARAM(uint8_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint8_t_movable_ptr_t, outbuf)); /** Retrieve transfer buffers. @@ -208,14 +246,18 @@ typedef interface spi_master_async_if { * pointer that was transmitted during the transfer. */ [[clears_notification]] - void retrieve_transfer_buffers_32(uint32_t * movable &inbuf, - uint32_t * movable &outbuf); + void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); /** Shut down the interface server. */ void shutdown(void); -} spi_master_async_if; + /**@}*/ // END: addtogroup spi_master_async_if + +#ifndef __DOXYGEN__ +} spi_master_async_if; +#endif /** SPI master component for asynchronous API. * @@ -235,22 +277,30 @@ typedef interface spi_master_async_if { * \param clk1 a clock for the component to use. */ [[combinable]] -void spi_master_async(server interface spi_master_async_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - out port p_ss[num_slaves], - static const size_t num_slaves, +void spi_master_async( + SERVER_INTERFACE(spi_master_async_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + in_buffered_port_32_t miso, + out_port p_ss[num_slaves], + static_const_size_t num_slaves, clock clk0, clock clk1); /**** SLAVE ****/ +/** + * \addtogroup spi_slave_callback_if + * @{ + */ + /** This interface allows clients to interact with SPI slave tasks by * completing callbacks that show how to handle data. */ +#ifndef __DOXYGEN__ typedef interface spi_slave_callback_if { +#endif /** This callback will get called when the master de-asserts on the slave * select line to end a transaction. @@ -280,8 +330,12 @@ typedef interface spi_slave_callback_if { * \param valid_bits the number of valid bits of data received from the master. */ void master_supplied_data(uint32_t datum, uint32_t valid_bits); - +#ifndef __DOXYGEN__ } spi_slave_callback_if; +#endif + + /**@}*/ // END: addtogroup spi_slave_callback_if + /** This type specifies the transfer size from the SPI slave component to the application */ @@ -307,13 +361,13 @@ typedef enum spi_transfer_type_t { * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. */ [[combinable]] - void spi_slave(client spi_slave_callback_if spi_i, - in port p_sclk, - in buffered port:32 p_mosi, - out buffered port:32 ?p_miso, - in port p_ss, + void spi_slave(CLIENT_INTERFACE(spi_slave_callback_if, spi_i), + in_port p_sclk, + in_buffered_port_32_t p_mosi, + NULLABLE_RESOURCE(out_buffered_port_32_t, p_miso), + in_port p_ss, clock clk, - static const spi_mode_t mode, - static const spi_transfer_type_t transfer_type); + static_const_spi_mode_t mode, + static_const_spi_transfer_type_t transfer_type); #endif // _spi_h_ diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc index 14abce2..aa38259 100644 --- a/lib_spi/src/spi_async.xc +++ b/lib_spi/src/spi_async.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 896f468..235453e 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc index e1c7577..e34a93a 100644 --- a/lib_spi/src/spi_sync.xc +++ b/lib_spi/src/spi_sync.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include diff --git a/python/setup.py b/python/setup.py index 766b8bb..8c6864f 100644 --- a/python/setup.py +++ b/python/setup.py @@ -1,4 +1,4 @@ -# Copyright 2020-2022 XMOS LIMITED. +# Copyright 2020-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import setuptools diff --git a/settings.yml b/settings.yml index 83f0a44..cdb68fc 100644 --- a/settings.yml +++ b/settings.yml @@ -11,7 +11,7 @@ documentation: linkcheck_ignore_regex: [''] latex_toc_depth: 3 latex_secnum_depth: 3 - cognidox_part_number: XM-006232-PC + cognidox_part_number: XM-015352-UG doxygen_projects: lib_spi: doxyfile_path: doc/Doxyfile.inc From 32c6632e55b169b41a7b2e85f97658dfa9221d1c Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 7 Jul 2025 12:12:59 +0100 Subject: [PATCH 18/57] Ensure all bits on a port are set high/low supporting wide ports for old spi API Compete spi_master_fwk wrapper with temp example --- CHANGELOG.rst | 2 +- Jenkinsfile | 4 +- .../AN00160_using_SPI_master/config.xscope | 2 +- examples/AN00160_using_SPI_master/src/main.xc | 30 +++++----- .../AN00160_using_SPI_master_fwk/src/main.xc | 24 ++++---- examples/CMakeLists.txt | 1 + lib_spi/api/spi.h | 29 +++++++--- lib_spi/api/spi_fwk.h | 3 - lib_spi/src/spi_async.xc | 6 +- lib_spi/src/spi_master.c | 1 - lib_spi/src/spi_master_fwk.xc | 58 ++++++++++--------- lib_spi/src/spi_sync.xc | 11 +++- 12 files changed, 95 insertions(+), 76 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 9a7f751..bc86a06 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -6,7 +6,7 @@ lib_spi change log * CHANGED: Refresh to use latest doc builder and library format * ADDED: Support for XCommon CMake build system - * REMOVED: XCORE-200 targets in examples (now targets xcore.ai explorer) + * REMOVED: XCORE-200 targets in examples (now targets XK-EVK-XU316) 3.3.0 ----- diff --git a/Jenkinsfile b/Jenkinsfile index 3c7d392..6376d5b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -19,12 +19,12 @@ pipeline { ) string( name: 'TOOLS_VERSION', - defaultValue: '-j -b markp_xsim_expose_signals_from_usb_shim latest', + defaultValue: '15.3.1', description: 'The XTC tools version' ) string( name: 'XMOSDOC_VERSION', - defaultValue: 'v7.2.0', + defaultValue: 'v7.3.0', description: 'The xmosdoc version' ) string( diff --git a/examples/AN00160_using_SPI_master/config.xscope b/examples/AN00160_using_SPI_master/config.xscope index bfdf1f8..1540288 100644 --- a/examples/AN00160_using_SPI_master/config.xscope +++ b/examples/AN00160_using_SPI_master/config.xscope @@ -14,7 +14,7 @@ - + diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 3acd1b4..8ea431f 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -8,20 +8,18 @@ #include -out buffered port:32 p_sclk = WIFI_CLK; -out port p_ss[1] = {WIFI_CS_N}; -in buffered port:32 p_miso = WIFI_MISO; -out buffered port:32 p_mosi = WIFI_MOSI; -out port p_rstn = WIFI_WUP_RST_N; +out buffered port:32 p_sclk = WIFI_CLK; +out port p_ss[1] = {WIFI_CS_N}; +in buffered port:32 p_miso = WIFI_MISO; +out buffered port:32 p_mosi = WIFI_MOSI; +out port p_rstn = WIFI_WUP_RST_N; clock clk0 = on tile[0]: XS1_CLKBLK_1; clock clk1 = on tile[0]: XS1_CLKBLK_2; /* This application function sends some traffic as SPI master using - * the synchronous interface. Since this is run in simulation - * there is no slave, so the incoming data (stored in the 'val' - * variable) will just be zero. - */ + * the synchronous interface. It reads the config register (address 0) + * of the WFM200S using a 16b command and prints the 32b read result */ void app(client spi_master_if spi) { uint8_t val; @@ -29,17 +27,19 @@ void app(client spi_master_if spi) p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); - spi.begin_transaction(0, 1000, SPI_MODE_1); + spi.begin_transaction(0, 1000, SPI_MODE_0); - uint32_t addr = 0; - uint32_t command = 0x8002 | (addr << 12); //Read command - val = spi.transfer8(command >> 8); + uint32_t reg_addr = 0; // Read reg 0 + uint32_t read_cmd = 0x8000; // Read + uint32_t num_16b_words = 2; // 32b + uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command + val = spi.transfer8(command >> 8);// MSB first val = spi.transfer8(command & 0xff); uint32_t reg; - reg = spi.transfer32(0x00); + reg = spi.transfer32(0x00); //Read result spi.end_transaction(0); - printhexln(reg << 16 | reg >> 16); + printhexln(reg >> 16); // Should be 0x5400 printstrln("Done."); _exit(0); } diff --git a/examples/AN00160_using_SPI_master_fwk/src/main.xc b/examples/AN00160_using_SPI_master_fwk/src/main.xc index fab2361..86b7386 100644 --- a/examples/AN00160_using_SPI_master_fwk/src/main.xc +++ b/examples/AN00160_using_SPI_master_fwk/src/main.xc @@ -9,7 +9,7 @@ out buffered port:32 p_sclk = WIFI_CLK; -out port p_ss[1] = {WIFI_CS_N}; +out port p_ss = WIFI_CS_N; in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; @@ -18,10 +18,8 @@ clock clk0 = on tile[0]: XS1_CLKBLK_1; clock clk1 = on tile[0]: XS1_CLKBLK_2; /* This application function sends some traffic as SPI master using - * the synchronous interface. Since this is run in simulation - * there is no slave, so the incoming data (stored in the 'val' - * variable) will just be zero. - */ + * the synchronous interface. It reads the config register (address 0) + * of the WFM200S using a 16b command and prints the 32b read result */ void app(client spi_master_if spi) { uint8_t val; @@ -29,18 +27,20 @@ void app(client spi_master_if spi) p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); - spi.begin_transaction(0, 1000, SPI_MODE_1); + spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N -for(int i=0;i<1000000;i++){ - uint32_t addr = 0; - uint32_t command = 0x8002 | (addr << 12); //Read command + spi.begin_transaction(0, 1000, SPI_MODE_0); + uint32_t reg_addr = 0; // Read reg 0 + uint32_t read_cmd = 0x8000; + uint32_t num_16b_words = 2; + uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command val = spi.transfer8(command >> 8); val = spi.transfer8(command & 0xff); - uint32_t reg; + uint32_t reg = 0; reg = spi.transfer32(0x00); spi.end_transaction(0); - printhexln(reg << 16 | reg >> 16); -} + printhexln(reg >> 16); // Should be 0x5400 + delay_microseconds(100000); printstrln("Done."); delay_microseconds(100000); diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index 2668e58..6f8e172 100644 --- a/examples/CMakeLists.txt +++ b/examples/CMakeLists.txt @@ -4,4 +4,5 @@ include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(lib_camera_examples) add_subdirectory(AN00160_using_SPI_master) +add_subdirectory(AN00160_using_SPI_master_fwk) add_subdirectory(AN00161_using_SPI_slave) \ No newline at end of file diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 6f7ed2f..efbcdaa 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -27,10 +27,10 @@ /** This type indicates what mode an SPI component should use */ typedef enum spi_mode_t { - SPI_MODE_0, /**< SPI Mode 0 - Polarity = 0, Clock Edge = 1 */ - SPI_MODE_1, /**< SPI Mode 1 - Polarity = 0, Clock Edge = 0 */ - SPI_MODE_2, /**< SPI Mode 2 - Polarity = 1, Clock Edge = 0 */ - SPI_MODE_3, /**< SPI Mode 3 - Polarity = 1, Clock Edge = 1 */ + SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Sampling clock Edge = 1 */ + SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Sampling clock Edge = 0 */ + SPI_MODE_2 = 2, /**< SPI Mode 2 - Polarity = 1, Sampling Clock Edge = 0 */ + SPI_MODE_3 = 3, /**< SPI Mode 3 - Polarity = 1, Sampling Clock Edge = 1 */ } spi_mode_t; @@ -93,6 +93,18 @@ typedef interface spi_master_if { * \returns the data read in from the MISO port. */ uint32_t transfer32(uint32_t data); + + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master_fwk. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is bit zero which is suitable + * for 1-bit ports or where bit 0 of a wider port is used. + * + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned ss_port_bit); + #ifndef __DOXYGEN__ } spi_master_if; #endif @@ -105,7 +117,7 @@ void spi_master_fwk( out_buffered_port_32_t sclk, NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), NULLABLE_RESOURCE(in_buffered_port_32_t, miso), - out_port p_ss[num_slaves], + out_port p_ss, static_const_size_t num_slaves, NULLABLE_RESOURCE(clock, clk)); @@ -128,8 +140,11 @@ void spi_master_fwk( \param sclk the SPI clock port. \param mosi the SPI MOSI (master out, slave in) port. \param miso the SPI MISO (master in, slave out) port. - \param p_ss an array of ports connected to the slave select signals - of the slave. + \param p_ss A port connected to the slave select signals + of the slave. Multiple slaves may be supported + by specifying, for example, a 4-bit port. + Please specify mapping of bits to slaves using + i.set_ss_port_bit() \param num_slaves The number of slave devices on the bus. \param clk a clock for the component to use. */ diff --git a/lib_spi/api/spi_fwk.h b/lib_spi/api/spi_fwk.h index 3a442fe..bc42744 100644 --- a/lib_spi/api/spi_fwk.h +++ b/lib_spi/api/spi_fwk.h @@ -244,9 +244,6 @@ inline void spi_master_delay_before_next_transfer( port_clear_trigger_time(spi->cs_port); /* Assert CS now */ - printstrln("here"); - printhexln(spi->cs_port); - printhexln(dev->cs_assert_val); port_out(spi->cs_port, dev->cs_assert_val); port_sync(spi->cs_port); diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc index aa38259..d95f977 100644 --- a/lib_spi/src/spi_async.xc +++ b/lib_spi/src/spi_async.xc @@ -173,7 +173,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], int currently_performing_a_transaction = 0; for(unsigned i=0;i 0xffff) delay_ticks(ss_deassert_time&0xffff0000); time += ss_deassert_time; - p_ss[active_device] @ time <: 1; + p_ss[active_device] @ time <: 0xffffffff; if(tr_fill > 0){ //begin a new transaction - the tail of the list is the next one to go diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c index 9a2f90a..7a9840c 100644 --- a/lib_spi/src/spi_master.c +++ b/lib_spi/src/spi_master.c @@ -213,7 +213,6 @@ void spi_master_end_transaction( port_sync(spi->cs_port); - printstrln("there"); port_out(spi->cs_port, cs_deassert_val); port_sync(spi->cs_port); diff --git a/lib_spi/src/spi_master_fwk.xc b/lib_spi/src/spi_master_fwk.xc index b4c2a6f..50939f2 100644 --- a/lib_spi/src/spi_master_fwk.xc +++ b/lib_spi/src/spi_master_fwk.xc @@ -17,63 +17,65 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], out buffered port:32 sclk, out buffered port:32 ?mosi, in buffered port:32 ?miso, - out port p_ss[num_slaves], + out port p_ss, // Note only one SS port supported - individual bits in port may be used however static const size_t num_slaves, clock ?cb){ - - // Declare the fwk_io_master - // MODE == 1 fixed for now - #define CPOL 0 - #define CPHA 1 - #define DIV 50 - if(isnull(cb)){ - printstrln("Must supply clockblock"); + printstrln("Must supply clockblock to this version of SPI"); + // We will hit an exception shortly after this if NULL } - + spi_master_t spi_ctx; spi_master_device_t spi_dev; unsafe{ - spi_master_device_init(&spi_dev, &spi_ctx, - 0, // cs pin in port - CPOL, CPHA, - spi_master_source_clock_xcore, - DIV, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); - spi_master_init(&spi_ctx, cb, (port)p_ss[0], (port)sclk, (port)mosi, (port)miso); + spi_master_init(&spi_ctx, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); } - int accepting_new_transactions = 1; + unsigned ss_port_bit[num_clients] = {0}; while(1){ select { case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode):{ accepting_new_transactions = 0; + + unsigned div = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz); + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + spi_master_device_init(&spi_dev, &spi_ctx, + ss_port_bit[x], + cpol, cpha, + spi_master_source_clock_ref, + div, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); spi_master_start_transaction(&spi_dev); break; } + case i[int x].end_transaction(unsigned ss_deassert_time):{ - //Unlock the transaction - accepting_new_transactions = 1; spi_master_end_transaction(&spi_dev); + // Unlock the transaction + accepting_new_transactions = 1; break; } + case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - printstrln("transfer8"); - printhexln((int)&data); - printhexln((int)&r); spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 1); - printstrln("transfer8"); break; } + case i[int x].transfer32(uint32_t data) -> uint32_t r:{ - printstrln("transfer32"); - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 4); - printstrln("transfer32"); + uint32_t read_val; + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); + r = byterev(read_val); + break; + } + + case i[int x].set_ss_port_bit(unsigned port_bit):{ + ss_port_bit[x] = port_bit; break; } } diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc index e34a93a..daf6df9 100644 --- a/lib_spi/src/spi_sync.xc +++ b/lib_spi/src/spi_sync.xc @@ -245,7 +245,7 @@ void spi_master(server interface spi_master_if i[num_clients], clock ?cb){ for(unsigned i=0;i 0xffff) @@ -321,7 +321,7 @@ void spi_master(server interface spi_master_if i[num_clients], time += ss_deassert_time; - p_ss[selected_device] @ time <: 1; + p_ss[selected_device] @ time <: 0xffffffff; break; } case i[int x].transfer8(uint8_t data)-> uint8_t r :{ @@ -340,6 +340,11 @@ void spi_master(server interface spi_master_if i[num_clients], } break; } + + case i[int x].set_ss_port_bit(unsigned port_bit):{ + // Do nothing this is invalid since this component sets all port bits high/low during select + break; + } } } From 3c4b0e5e8d799278ec31f01c3bf9eb68a9638cc2 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 7 Jul 2025 12:17:08 +0100 Subject: [PATCH 19/57] Fix merge --- examples/AN00160_using_SPI_master/src/main.xc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index bebdba7..bad72b8 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -7,20 +7,11 @@ #include #include - -<<<<<<< HEAD out buffered port:32 p_sclk = WIFI_CLK; out port p_ss[1] = {WIFI_CS_N}; in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; -======= -out buffered port:32 p_sclk = WIFI_CLK; -out port p_ss[1] = {WIFI_CS_N}; -in buffered port:32 p_miso = WIFI_MISO; -out buffered port:32 p_mosi = WIFI_MOSI; -out port p_rstn = WIFI_WUP_RST_N; ->>>>>>> origin/develop clock clk0 = on tile[0]: XS1_CLKBLK_1; clock clk1 = on tile[0]: XS1_CLKBLK_2; From e0a8ce4560fdcefa3aff8f5360c9e920459f6a66 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 7 Jul 2025 16:34:45 +0100 Subject: [PATCH 20/57] Move legacy sync and slave tests over to Pyxsim Correct repo name for archive asynch WIP working async multi client Add failing asycn multi device Split asynch rx_tx master into smaller tests for easier debug --- .gitignore | 3 +- Jenkinsfile | 66 +- .../AN00160_using_SPI_master/CMakeLists.txt | 2 +- .../AN00161_using_SPI_slave/CMakeLists.txt | 2 +- examples/deps.cmake | 3 + legacy_tests/.gitignore | 2 - legacy_tests/lib_spi_master_tester/.cproject | 817 - legacy_tests/lib_spi_master_tester/.makefile | 4 - legacy_tests/lib_spi_master_tester/.project | 47 - .../lib_spi_master_tester/module_build_info | 17 - .../lib_spi_master_tester/module_description | 1 - legacy_tests/master_benchmark.expect | 3 - legacy_tests/requirements.txt | 1 - legacy_tests/runtests.py | 48 - legacy_tests/slave.expect | 1 - legacy_tests/slave_benchmark.expect | 2 - .../spi_master_async_multi_client/.cproject | 3385 - .../spi_master_async_multi_client/.project | 47 - .../.settings/org.eclipse.cdt.core.prefs | 51 - .../spi_master_async_multi_client/Makefile | 42 - .../spi_master_async_multi_device/.cproject | 3384 - .../spi_master_async_multi_device/.project | 47 - .../spi_master_async_multi_device/Makefile | 41 - legacy_tests/spi_master_async_rx_tx/.cproject | 13441 ---- legacy_tests/spi_master_async_rx_tx/.project | 47 - .../.settings/org.eclipse.cdt.core.prefs | 181 - legacy_tests/spi_master_async_rx_tx/Makefile | 55 - .../spi_master_async_shutdown/Makefile | 40 - .../src/spi_master_async_shutdown.xc | 70 - legacy_tests/spi_master_checker.py | 160 - .../spi_master_sync_benchmark/.cproject | 10088 --- .../spi_master_sync_benchmark/.project | 47 - .../spi_master_sync_benchmark/Makefile | 49 - .../Makefile | 38 - .../spi_master_sync_multi_client/.cproject | 24363 ------- .../spi_master_sync_multi_client/.project | 47 - .../spi_master_sync_multi_client/Makefile | 50 - .../spi_master_sync_multi_device/.cproject | 25172 -------- .../spi_master_sync_multi_device/.project | 47 - .../spi_master_sync_multi_device/Makefile | 70 - legacy_tests/spi_master_sync_rx_tx/.cproject | 10089 --- legacy_tests/spi_master_sync_rx_tx/.project | 47 - .../.settings/org.eclipse.cdt.core.prefs | 151 - legacy_tests/spi_master_sync_rx_tx/Makefile | 49 - legacy_tests/spi_slave_benchmark/.cproject | 52897 ---------------- legacy_tests/spi_slave_benchmark/.project | 47 - .../.settings/org.eclipse.cdt.core.prefs | 321 - legacy_tests/spi_slave_benchmark/Makefile | 108 - .../spi_slave_benchmark/config.xscope | 3 - legacy_tests/spi_slave_checker.py | 105 - legacy_tests/spi_slave_rx_tx/.cproject | 52897 ---------------- legacy_tests/spi_slave_rx_tx/.project | 47 - .../.settings/org.eclipse.cdt.core.prefs | 321 - legacy_tests/spi_slave_rx_tx/Makefile | 109 - legacy_tests/spi_slave_rx_tx/config.xscope | 3 - .../test_master_async_multi_client.py | 38 - .../test_master_async_multi_device.py | 38 - legacy_tests/test_master_async_rx_tx.py | 42 - legacy_tests/test_master_async_shutdown.py | 40 - legacy_tests/test_master_sync_benchmark.py | 41 - .../test_master_sync_clock_port_sharing.py | 35 - legacy_tests/test_master_sync_multi_client.py | 42 - legacy_tests/test_master_sync_multi_device.py | 41 - legacy_tests/test_master_sync_rx_tx.py | 45 - legacy_tests/test_slave_benchmark.py | 42 - legacy_tests/test_slave_rx_tx.py | 49 - tests/CMakeLists.txt | 13 + tests/conftest.py | 27 + tests/expected/master_multi_device.expect | 5 + .../expected/master_sync.expect | 1 + tests/expected/slave.expect | 36 + tests/expected/slave_intertransaction.expect | 5 + tests/helpers.py | 115 + tests/requirements.txt | 37 + .../CMakeLists.txt | 64 + .../config.xscope | 0 .../src/spi_master_async_multi_client.xc | 8 +- .../test_params.json | 14 + .../CMakeLists.txt | 64 + .../config.xscope | 0 .../src/spi_master_async_multi_device.xc | 0 .../test_params.json | 14 + tests/spi_master_async_rx_tx/CMakeLists.txt | 91 + .../spi_master_async_rx_tx/config.xscope | 0 .../src/spi_master_async_rx_tx.xc | 49 +- tests/spi_master_async_rx_tx/test_params.json | 25 + tests/spi_master_checker.py | 172 + .../spi_master_sync_benchmark/CMakeLists.txt | 83 + .../spi_master_sync_benchmark}/config.xscope | 0 .../src/spi_master_sync_benchmark.xc | 1 + .../test_params.json | 6 + .../CMakeLists.txt | 26 + .../config.xscope | 0 .../spi_master_sync_clock_port_sharing.xc | 7 + .../CMakeLists.txt | 82 + .../config.xscope | 0 .../src/spi_master_sync_multi_client.xc | 1 + .../test_params.json | 6 + .../CMakeLists.txt | 82 + .../config.xscope | 0 .../src/spi_master_sync_multi_device.xc | 1 + .../test_params.json | 6 + tests/spi_master_sync_rx_tx/CMakeLists.txt | 82 + .../src/spi_master_sync_rx_tx.xc | 4 +- tests/spi_master_sync_rx_tx/test_params.json | 6 + .../spi_master_tester_common}/common.h | 2 + .../spi_async_tester.h | 0 .../spi_sync_tester.h | 2 +- tests/spi_slave_benchmark/CMakeLists.txt | 81 + .../spi_slave_benchmark}/config.xscope | 0 .../src/spi_slave_benchmark.xc | 12 +- tests/spi_slave_benchmark/test_params.json | 24 + tests/spi_slave_checker.py | 144 + tests/spi_slave_checker_intertransaction.py | 143 + tests/spi_slave_rx_tx/CMakeLists.txt | 81 + .../spi_slave_rx_tx}/config.xscope | 0 .../spi_slave_rx_tx/src/spi_slave_rx_tx.xc | 36 +- tests/spi_slave_rx_tx/test_params.json | 24 + tests/test_master_async_multi_client.py | 55 + tests/test_master_async_multi_device.py | 54 + tests/test_master_async_rx_tx.py | 56 + tests/test_master_sync_benchmark.py | 74 + tests/test_master_sync_clock_port_sharing.py | 51 + tests/test_master_sync_multi_client.py | 54 + tests/test_master_sync_multi_device.py | 53 + tests/test_master_sync_rx_tx.py | 51 + tests/test_slave_benchmark.py | 78 + tests/test_slave_rx_tx.py | 53 + 128 files changed, 2272 insertions(+), 199617 deletions(-) create mode 100644 examples/deps.cmake delete mode 100644 legacy_tests/.gitignore delete mode 100644 legacy_tests/lib_spi_master_tester/.cproject delete mode 100644 legacy_tests/lib_spi_master_tester/.makefile delete mode 100644 legacy_tests/lib_spi_master_tester/.project delete mode 100644 legacy_tests/lib_spi_master_tester/module_build_info delete mode 100644 legacy_tests/lib_spi_master_tester/module_description delete mode 100644 legacy_tests/master_benchmark.expect delete mode 100644 legacy_tests/requirements.txt delete mode 100755 legacy_tests/runtests.py delete mode 100644 legacy_tests/slave.expect delete mode 100644 legacy_tests/slave_benchmark.expect delete mode 100644 legacy_tests/spi_master_async_multi_client/.cproject delete mode 100644 legacy_tests/spi_master_async_multi_client/.project delete mode 100644 legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs delete mode 100644 legacy_tests/spi_master_async_multi_client/Makefile delete mode 100644 legacy_tests/spi_master_async_multi_device/.cproject delete mode 100644 legacy_tests/spi_master_async_multi_device/.project delete mode 100644 legacy_tests/spi_master_async_multi_device/Makefile delete mode 100644 legacy_tests/spi_master_async_rx_tx/.cproject delete mode 100644 legacy_tests/spi_master_async_rx_tx/.project delete mode 100644 legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs delete mode 100644 legacy_tests/spi_master_async_rx_tx/Makefile delete mode 100644 legacy_tests/spi_master_async_shutdown/Makefile delete mode 100644 legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc delete mode 100644 legacy_tests/spi_master_checker.py delete mode 100644 legacy_tests/spi_master_sync_benchmark/.cproject delete mode 100644 legacy_tests/spi_master_sync_benchmark/.project delete mode 100644 legacy_tests/spi_master_sync_benchmark/Makefile delete mode 100644 legacy_tests/spi_master_sync_clock_port_sharing/Makefile delete mode 100644 legacy_tests/spi_master_sync_multi_client/.cproject delete mode 100644 legacy_tests/spi_master_sync_multi_client/.project delete mode 100644 legacy_tests/spi_master_sync_multi_client/Makefile delete mode 100644 legacy_tests/spi_master_sync_multi_device/.cproject delete mode 100644 legacy_tests/spi_master_sync_multi_device/.project delete mode 100644 legacy_tests/spi_master_sync_multi_device/Makefile delete mode 100644 legacy_tests/spi_master_sync_rx_tx/.cproject delete mode 100644 legacy_tests/spi_master_sync_rx_tx/.project delete mode 100644 legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs delete mode 100644 legacy_tests/spi_master_sync_rx_tx/Makefile delete mode 100644 legacy_tests/spi_slave_benchmark/.cproject delete mode 100644 legacy_tests/spi_slave_benchmark/.project delete mode 100644 legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs delete mode 100644 legacy_tests/spi_slave_benchmark/Makefile delete mode 100644 legacy_tests/spi_slave_benchmark/config.xscope delete mode 100644 legacy_tests/spi_slave_checker.py delete mode 100644 legacy_tests/spi_slave_rx_tx/.cproject delete mode 100644 legacy_tests/spi_slave_rx_tx/.project delete mode 100644 legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs delete mode 100644 legacy_tests/spi_slave_rx_tx/Makefile delete mode 100644 legacy_tests/spi_slave_rx_tx/config.xscope delete mode 100644 legacy_tests/test_master_async_multi_client.py delete mode 100644 legacy_tests/test_master_async_multi_device.py delete mode 100644 legacy_tests/test_master_async_rx_tx.py delete mode 100644 legacy_tests/test_master_async_shutdown.py delete mode 100644 legacy_tests/test_master_sync_benchmark.py delete mode 100644 legacy_tests/test_master_sync_clock_port_sharing.py delete mode 100644 legacy_tests/test_master_sync_multi_client.py delete mode 100644 legacy_tests/test_master_sync_multi_device.py delete mode 100644 legacy_tests/test_master_sync_rx_tx.py delete mode 100644 legacy_tests/test_slave_benchmark.py delete mode 100644 legacy_tests/test_slave_rx_tx.py create mode 100644 tests/CMakeLists.txt create mode 100644 tests/conftest.py create mode 100644 tests/expected/master_multi_device.expect rename legacy_tests/master.expect => tests/expected/master_sync.expect (58%) create mode 100644 tests/expected/slave.expect create mode 100644 tests/expected/slave_intertransaction.expect create mode 100644 tests/helpers.py create mode 100644 tests/requirements.txt create mode 100644 tests/spi_master_async_multi_client/CMakeLists.txt rename {legacy_tests => tests}/spi_master_async_multi_client/config.xscope (100%) rename {legacy_tests => tests}/spi_master_async_multi_client/src/spi_master_async_multi_client.xc (94%) create mode 100644 tests/spi_master_async_multi_client/test_params.json create mode 100644 tests/spi_master_async_multi_device/CMakeLists.txt rename {legacy_tests => tests}/spi_master_async_multi_device/config.xscope (100%) rename {legacy_tests => tests}/spi_master_async_multi_device/src/spi_master_async_multi_device.xc (100%) create mode 100644 tests/spi_master_async_multi_device/test_params.json create mode 100644 tests/spi_master_async_rx_tx/CMakeLists.txt rename {legacy_tests => tests}/spi_master_async_rx_tx/config.xscope (100%) rename {legacy_tests => tests}/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc (81%) create mode 100644 tests/spi_master_async_rx_tx/test_params.json create mode 100644 tests/spi_master_checker.py create mode 100644 tests/spi_master_sync_benchmark/CMakeLists.txt rename {legacy_tests/spi_master_async_shutdown => tests/spi_master_sync_benchmark}/config.xscope (100%) rename {legacy_tests => tests}/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc (98%) create mode 100644 tests/spi_master_sync_benchmark/test_params.json create mode 100644 tests/spi_master_sync_clock_port_sharing/CMakeLists.txt rename {legacy_tests/spi_master_sync_benchmark => tests/spi_master_sync_clock_port_sharing}/config.xscope (100%) rename {legacy_tests/spi_master_sync_clock_port_sharing => tests/spi_master_sync_clock_port_sharing/src}/spi_master_sync_clock_port_sharing.xc (88%) create mode 100644 tests/spi_master_sync_multi_client/CMakeLists.txt rename {legacy_tests/spi_master_sync_clock_port_sharing => tests/spi_master_sync_multi_client}/config.xscope (100%) rename {legacy_tests => tests}/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc (97%) create mode 100644 tests/spi_master_sync_multi_client/test_params.json create mode 100644 tests/spi_master_sync_multi_device/CMakeLists.txt rename {legacy_tests/spi_master_sync_multi_client => tests/spi_master_sync_multi_device}/config.xscope (100%) rename {legacy_tests => tests}/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc (98%) create mode 100644 tests/spi_master_sync_multi_device/test_params.json create mode 100644 tests/spi_master_sync_rx_tx/CMakeLists.txt rename {legacy_tests => tests}/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc (97%) create mode 100644 tests/spi_master_sync_rx_tx/test_params.json rename {legacy_tests/lib_spi_master_tester/src => tests/spi_master_tester_common}/common.h (95%) rename {legacy_tests/lib_spi_master_tester/src => tests/spi_master_tester_common}/spi_async_tester.h (100%) rename {legacy_tests/lib_spi_master_tester/src => tests/spi_master_tester_common}/spi_sync_tester.h (99%) create mode 100644 tests/spi_slave_benchmark/CMakeLists.txt rename {legacy_tests/spi_master_sync_multi_device => tests/spi_slave_benchmark}/config.xscope (100%) rename {legacy_tests => tests}/spi_slave_benchmark/src/spi_slave_benchmark.xc (94%) create mode 100644 tests/spi_slave_benchmark/test_params.json create mode 100644 tests/spi_slave_checker.py create mode 100644 tests/spi_slave_checker_intertransaction.py create mode 100644 tests/spi_slave_rx_tx/CMakeLists.txt rename {legacy_tests/spi_master_sync_rx_tx => tests/spi_slave_rx_tx}/config.xscope (100%) rename {legacy_tests => tests}/spi_slave_rx_tx/src/spi_slave_rx_tx.xc (86%) create mode 100644 tests/spi_slave_rx_tx/test_params.json create mode 100644 tests/test_master_async_multi_client.py create mode 100644 tests/test_master_async_multi_device.py create mode 100644 tests/test_master_async_rx_tx.py create mode 100644 tests/test_master_sync_benchmark.py create mode 100644 tests/test_master_sync_clock_port_sharing.py create mode 100644 tests/test_master_sync_multi_client.py create mode 100644 tests/test_master_sync_multi_device.py create mode 100644 tests/test_master_sync_rx_tx.py create mode 100644 tests/test_slave_benchmark.py create mode 100644 tests/test_slave_rx_tx.py diff --git a/.gitignore b/.gitignore index 40b6123..cb0ca21 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,7 @@ build/ # satisfy parsing in XMOS source check based on regular expressions # (normal parsing is based on shell wildcards) -*/.venv* +*.venv* */build/* __gen +*tests/logs/* diff --git a/Jenkinsfile b/Jenkinsfile index 6376d5b..7bb8fd5 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -2,6 +2,13 @@ @Library('xmos_jenkins_shared_library@v0.39.0') _ +def clone_test_deps() { + dir("${WORKSPACE}") { + sh "git clone git@github.com:xmos/test_support" + sh "git -C test_support checkout v2.0.0" + } +} + getApproval() pipeline { @@ -57,12 +64,12 @@ pipeline { } stage('Library checks') { - steps { - warnError("Library checks failed") - { - runLibraryChecks("${WORKSPACE}/${REPO_NAME}", "${params.INFR_APPS_VERSION}") - } + steps { + warnError("Library checks failed") + { + runLibraryChecks("${WORKSPACE}/${REPO_NAME}", "${params.INFR_APPS_VERSION}") } + } } stage('Documentation') { @@ -74,33 +81,34 @@ pipeline { } - //stage('Tests') - //{ - // steps { - // withTools(params.TOOLS_VERSION) { - // dir("${REPO}/tests") { - // createVenv(reqFile: "requirements.txt") - // withVenv{ - // runPytest("--numprocesses=8 --testlevel=${params.TEST_LEVEL}) - // } - // } // dir - // } // withTools - // } // steps - // post - // { - // failure - // { - // //archiveArtifacts artifacts: "${REPO}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true - // } - // } - //} + stage('Tests') + { + steps { + withTools(params.TOOLS_VERSION) { + clone_test_deps() + dir("${REPO_NAME}/tests") { + createVenv(reqFile: "requirements.txt") + xcoreBuild() + withVenv{ + runPytest("--numprocesses=auto --testlevel=${params.TEST_LEVEL}") + } + } // dir + } // withTools + } // steps + post + { + always{ + archiveArtifacts artifacts: "${REPO_NAME}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true + } + } + } stage("Archive") { - steps - { - archiveSandbox(REPO_NAME) - } + steps + { + archiveSandbox(REPO_NAME) + } } } post { diff --git a/examples/AN00160_using_SPI_master/CMakeLists.txt b/examples/AN00160_using_SPI_master/CMakeLists.txt index 703ed39..32f1c3e 100644 --- a/examples/AN00160_using_SPI_master/CMakeLists.txt +++ b/examples/AN00160_using_SPI_master/CMakeLists.txt @@ -11,7 +11,7 @@ set(APP_XSCOPE_SRCS config.xscope) # Includes, Dependencies list(APPEND APP_INCLUDES src) -list(APPEND APP_DEPENDENT_MODULES "lib_spi") +include(${CMAKE_CURRENT_LIST_DIR}/../deps.cmake) # Flags set(COMPILER_FLAGS_COMMON diff --git a/examples/AN00161_using_SPI_slave/CMakeLists.txt b/examples/AN00161_using_SPI_slave/CMakeLists.txt index 823970e..42bc5a0 100644 --- a/examples/AN00161_using_SPI_slave/CMakeLists.txt +++ b/examples/AN00161_using_SPI_slave/CMakeLists.txt @@ -11,7 +11,7 @@ set(APP_XSCOPE_SRCS config.xscope) # Includes, Dependencies list(APPEND APP_INCLUDES src) -list(APPEND APP_DEPENDENT_MODULES "lib_spi") +include(${CMAKE_CURRENT_LIST_DIR}/../deps.cmake) # Flags set( diff --git a/examples/deps.cmake b/examples/deps.cmake new file mode 100644 index 0000000..38647e5 --- /dev/null +++ b/examples/deps.cmake @@ -0,0 +1,3 @@ +# Common dependencies for examples +set(APP_DEPENDENT_MODULES "lib_spi" +) \ No newline at end of file diff --git a/legacy_tests/.gitignore b/legacy_tests/.gitignore deleted file mode 100644 index 095cd5e..0000000 --- a/legacy_tests/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -.venv -Pipfile.lock diff --git a/legacy_tests/lib_spi_master_tester/.cproject b/legacy_tests/lib_spi_master_tester/.cproject deleted file mode 100644 index ed4c25c..0000000 --- a/legacy_tests/lib_spi_master_tester/.cproject +++ /dev/null @@ -1,817 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/legacy_tests/lib_spi_master_tester/.makefile b/legacy_tests/lib_spi_master_tester/.makefile deleted file mode 100644 index 3262365..0000000 --- a/legacy_tests/lib_spi_master_tester/.makefile +++ /dev/null @@ -1,4 +0,0 @@ -all: - @echo "** Module only - only builds as part of application **" -clean: - @echo "** Module only - only builds as part of application **" diff --git a/legacy_tests/lib_spi_master_tester/.project b/legacy_tests/lib_spi_master_tester/.project deleted file mode 100644 index ad9ecb2..0000000 --- a/legacy_tests/lib_spi_master_tester/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - lib_spi_master_tester - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/lib_spi_master_tester/module_build_info b/legacy_tests/lib_spi_master_tester/module_build_info deleted file mode 100644 index efa7315..0000000 --- a/legacy_tests/lib_spi_master_tester/module_build_info +++ /dev/null @@ -1,17 +0,0 @@ -# You can set flags specifically for your module by using the MODULE_XCC_FLAGS -# variable. So the following -# -# MODULE_XCC_FLAGS = $(XCC_FLAGS) -O3 -# -# specifies that everything in the modules should have the application -# build flags with -O3 appended (so the files will build at -# optimization level -O3). -# -# You can also set MODULE_XCC_C_FLAGS, MODULE_XCC_XC_FLAGS etc.. - -MODULE_XCC_XC_FLAGS = $(XCC_XC_FLAGS) - -# The following specifies the dependencies of the module. When an application -# includes a module it will also include all its dependencies. -# DEPENDENT_MODULES = - diff --git a/legacy_tests/lib_spi_master_tester/module_description b/legacy_tests/lib_spi_master_tester/module_description deleted file mode 100644 index 00a6de4..0000000 --- a/legacy_tests/lib_spi_master_tester/module_description +++ /dev/null @@ -1 +0,0 @@ -One line module description. diff --git a/legacy_tests/master_benchmark.expect b/legacy_tests/master_benchmark.expect deleted file mode 100644 index 79c832d..0000000 --- a/legacy_tests/master_benchmark.expect +++ /dev/null @@ -1,3 +0,0 @@ -SPI Master checker started -.* -.* diff --git a/legacy_tests/requirements.txt b/legacy_tests/requirements.txt deleted file mode 100644 index 4be5e8e..0000000 --- a/legacy_tests/requirements.txt +++ /dev/null @@ -1 +0,0 @@ -# python_version 2.7 diff --git a/legacy_tests/runtests.py b/legacy_tests/runtests.py deleted file mode 100755 index 2921a12..0000000 --- a/legacy_tests/runtests.py +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker - -if __name__ == "__main__": - xmostest.init() - - xmostest.register_group("lib_spi", - "spi_master_sim_tests", - "spi master simulator tests", - """ -Tests are performed by running the spi library connected to a -simulator model (written as a python plugin to xsim). The simulator -model checks that the signals comply to the spi specification and checks the -protocol speed of the transactions. Tests are run to test the following -features: - - * Transmission of packets - * Reception of packets - -The tests are run with transactions of varying number of bytes and with rx and -tx transactions interleaved. The tests are run at speeds of 10, 100 and 400 -Kbps. -""") - - xmostest.register_group("lib_spi", - "spi_slave_sim_tests", - "spi Slave simulator tests", - """ -Tests are performed by running the spi library connected to a -simulator model (written as a python plugin to xsim). The simulator -model checks that the signals comply to the spi specification and checks the -protocol speed of the transactions. Tests are run to test the following -features: - - * Transmission of packets - * Reception of packets - -The tests are run with transactions of varying number of bytes and with rx and -tx transactions interleaved. The tests are run at speeds of 10, 100 and 400 -Kbps. -""") - - xmostest.runtests() - - xmostest.finish() diff --git a/legacy_tests/slave.expect b/legacy_tests/slave.expect deleted file mode 100644 index 47ba373..0000000 --- a/legacy_tests/slave.expect +++ /dev/null @@ -1 +0,0 @@ -SPI Slave checker started diff --git a/legacy_tests/slave_benchmark.expect b/legacy_tests/slave_benchmark.expect deleted file mode 100644 index 4c3014e..0000000 --- a/legacy_tests/slave_benchmark.expect +++ /dev/null @@ -1,2 +0,0 @@ -SPI Slave checker started -.* diff --git a/legacy_tests/spi_master_async_multi_client/.cproject b/legacy_tests/spi_master_async_multi_client/.cproject deleted file mode 100644 index a52c77f..0000000 --- a/legacy_tests/spi_master_async_multi_client/.cproject +++ /dev/null @@ -1,3385 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_async_multi_client/.project b/legacy_tests/spi_master_async_multi_client/.project deleted file mode 100644 index eed8b6e..0000000 --- a/legacy_tests/spi_master_async_multi_client/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_multi_client - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index 350cef2..0000000 --- a/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,51 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1199496047/append=true -environment/project/com.xmos.cdt.toolchain.1199496047/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1212376291/append=true -environment/project/com.xmos.cdt.toolchain.1212376291/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1278560241/append=true -environment/project/com.xmos.cdt.toolchain.1278560241/appendContributed=true -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.171044913/append=true -environment/project/com.xmos.cdt.toolchain.171044913/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1840686372/append=true -environment/project/com.xmos.cdt.toolchain.1840686372/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1967321160/append=true -environment/project/com.xmos.cdt.toolchain.1967321160/appendContributed=true -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.2145625776/append=true -environment/project/com.xmos.cdt.toolchain.2145625776/appendContributed=true -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.414772137/append=true -environment/project/com.xmos.cdt.toolchain.414772137/appendContributed=true -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.523868563/append=true -environment/project/com.xmos.cdt.toolchain.523868563/appendContributed=true -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.829874614/append=true -environment/project/com.xmos.cdt.toolchain.829874614/appendContributed=true diff --git a/legacy_tests/spi_master_async_multi_client/Makefile b/legacy_tests/spi_master_async_multi_client/Makefile deleted file mode 100644 index dd408f7..0000000 --- a/legacy_tests/spi_master_async_multi_client/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_multi_client - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_401 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=0 -DCOMBINED=1 -XCC_FLAGS_411 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=1 -DCOMBINED=1 -XCC_FLAGS_401 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=0 -DCOMBINED=1 -XCC_FLAGS_411 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=1 -DCOMBINED=1 -XCC_FLAGS_300 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DCOMBINED=0 -XCC_FLAGS_310 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DCOMBINED=0 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_multi_device/.cproject b/legacy_tests/spi_master_async_multi_device/.cproject deleted file mode 100644 index 723082e..0000000 --- a/legacy_tests/spi_master_async_multi_device/.cproject +++ /dev/null @@ -1,3384 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_async_multi_device/.project b/legacy_tests/spi_master_async_multi_device/.project deleted file mode 100644 index 4deaf24..0000000 --- a/legacy_tests/spi_master_async_multi_device/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_multi_device - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_multi_device/Makefile b/legacy_tests/spi_master_async_multi_device/Makefile deleted file mode 100644 index ba36c44..0000000 --- a/legacy_tests/spi_master_async_multi_device/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_multi_device - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_20 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -XCC_FLAGS_21 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 - -XCC_FLAGS_60 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -XCC_FLAGS_61 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_rx_tx/.cproject b/legacy_tests/spi_master_async_rx_tx/.cproject deleted file mode 100644 index 3925f17..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.cproject +++ /dev/null @@ -1,13441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_async_rx_tx/.project b/legacy_tests/spi_master_async_rx_tx/.project deleted file mode 100644 index c1ce3b6..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_rx_tx - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8d20c6..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,181 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1010651779/append=true -environment/project/com.xmos.cdt.toolchain.1010651779/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1028334172/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1028334172/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.2028793850/append=true -environment/project/com.xmos.cdt.toolchain.2028793850/appendContributed=true -environment/project/com.xmos.cdt.toolchain.2044576147/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.2044576147/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.2044576147/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.2044576147/append=true -environment/project/com.xmos.cdt.toolchain.2044576147/appendContributed=true -environment/project/com.xmos.cdt.toolchain.2050679507/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.2050679507/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.270383583/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.270383583/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.270383583/append=true -environment/project/com.xmos.cdt.toolchain.270383583/appendContributed=true -environment/project/com.xmos.cdt.toolchain.33773005/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.33773005/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.33773005/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.33773005/append=true -environment/project/com.xmos.cdt.toolchain.33773005/appendContributed=true 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-environment/project/com.xmos.cdt.toolchain.727773042/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.727773042/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.727773042/append=true -environment/project/com.xmos.cdt.toolchain.727773042/appendContributed=true -environment/project/com.xmos.cdt.toolchain.76866540/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.76866540/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.76866540/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.76866540/append=true -environment/project/com.xmos.cdt.toolchain.76866540/appendContributed=true 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-environment/project/com.xmos.cdt.toolchain.818027705/append=true -environment/project/com.xmos.cdt.toolchain.818027705/appendContributed=true -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.860505498/append=true -environment/project/com.xmos.cdt.toolchain.860505498/appendContributed=true -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.92161155/append=true -environment/project/com.xmos.cdt.toolchain.92161155/appendContributed=true diff --git a/legacy_tests/spi_master_async_rx_tx/Makefile b/legacy_tests/spi_master_async_rx_tx/Makefile deleted file mode 100644 index fe3e714..0000000 --- a/legacy_tests/spi_master_async_rx_tx/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_2010 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_2110 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_6010 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_6110 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=0 - -XCC_FLAGS_2030 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_2130 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_6030 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_6130 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=0 - -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=1 - -XCC_FLAGS_3031 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_3131 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_7031 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_7131 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_shutdown/Makefile b/legacy_tests/spi_master_async_shutdown/Makefile deleted file mode 100644 index bf0be86..0000000 --- a/legacy_tests/spi_master_async_shutdown/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling - -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_shutdown - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_0 = $(COMMON_FLAGS) -DCOMBINED=0 -XCC_FLAGS_1 = $(COMMON_FLAGS) -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc deleted file mode 100644 index 38576f3..0000000 --- a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright 2020-2025 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include -#include -#include "spi.h" -#include "spi_async_tester.h" - -in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; -out buffered port:32 p_sclk = XS1_PORT_1C; -out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; - -out port setup_strobe_port = XS1_PORT_1E; -out port setup_data_port = XS1_PORT_16B; - -[[combinable]] -void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_enabled){ - unsigned inter_frame_gap = 1000; - unsigned device_id = 0; - spi_mode_t mode = SPI_MODE_0; - unsigned speed_in_kbps = 500; - unsigned count = 1; - - broadcast_settings(setup_strobe_port, setup_data_port, - mode, speed_in_kbps, mosi_enabled, miso_enabled, - device_id, inter_frame_gap, count); - - uint8_t tx[1] = {(tx_data, unsigned char[])[0]}; - uint8_t rx[1]; - uint8_t * movable tx_ptr = tx; - uint8_t * movable rx_ptr = rx; - - spi_i.begin_transaction(device_id, speed_in_kbps, mode); - spi_i.init_transfer_array_8(move(rx_ptr), move(tx_ptr), count); - - while(1){ - select { - case spi_i.transfer_complete():{ - spi_i.retrieve_transfer_buffers_8(rx_ptr, tx_ptr); - spi_i.end_transaction(inter_frame_gap); - spi_i.shutdown(); - return; - } - } - } -} - -int main(){ - interface spi_master_async_if i[1]; - for (int j = 0; j < 2; j++) { // go around a couple of times in order to exercise the shutdown - par { -#if COMBINED == 1 - [[combine]] - par { - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - app(i[0], 1, 1); - } -#else - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - app(i[0], 1, 1); -#endif - } - } - return 0; -} diff --git a/legacy_tests/spi_master_checker.py b/legacy_tests/spi_master_checker.py deleted file mode 100644 index bac4623..0000000 --- a/legacy_tests/spi_master_checker.py +++ /dev/null @@ -1,160 +0,0 @@ -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest - -class SPIMasterChecker(xmostest.SimThread): - """" - This simulator thread will act as SPI slave and check any transactions - caused by the master. - """ - def __init__(self, sck_port, mosi_port, miso_port, ss_ports, setup_strobe_port, setup_data_port): - self._miso_port = miso_port - self._mosi_port = mosi_port - self._sck_port = sck_port - self._ss_ports = ss_ports - self._setup_strobe_port = setup_strobe_port - self._setup_data_port = setup_data_port - - def get_setup_data(self, xsi, setup_strobe_port, setup_data_port): - self.wait_for_port_pins_change([setup_strobe_port]) - self.wait_for_port_pins_change([setup_strobe_port]) - return xsi.sample_port_pins(setup_data_port) - - def run(self): - xsi = self.xsi - - sck_value = xsi.sample_port_pins(self._sck_port) - ss_value = [] - - for i in range(len(self._ss_ports)): - ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) - - print("SPI Master checker started") - while True: - #first do the setup rx - strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) - - expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_frequency_in_khz = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_mosi_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - - clock_half_period = 1000000/(expected_frequency_in_khz*2) - - all_ss_deserted = True - for i in range(len(self._ss_ports)): - if (xsi.sample_port_pins(self._ss_ports[i]) == 0): - all_ss_deserted = False - break - - while not all_ss_deserted: - self.wait_for_port_pins_change(self._ss_ports) - all_ss_deserted = True - for i in range(len(self._ss_ports)): - all_ss_deserted = all_ss_deserted and (xsi.sample_port_pins(self._ss_ports[i]) == 1) - - error = False - - active_slave = -1 - - while(active_slave == -1): - self.wait_for_port_pins_change(self._ss_ports) - - for i in range(len(self._ss_ports)): - if xsi.sample_port_pins(self._ss_ports[i]) == 0: - active_slave = i - break - - - last_clock_event_time = xsi.get_time(); - - rx_bit_counter = 0 - tx_bit_counter = 0 - tx_data = [0xfe, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] - rx_data = [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] - rx_byte = 0 - tx_byte = tx_data[0] - # check the polarity - if xsi.sample_port_pins(self._sck_port) != expected_cpol: - print("ERROR: unexpected clock polarity at the slave select point") - error = True - clock_edge_number = 0 - - #probably not physically possible but good for testing - if expected_cpha == 0: - xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) - tx_bit_counter += 1 - tx_byte = tx_byte << 1 - - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) - sck_value = xsi.sample_port_pins(self._sck_port) - - while ss_value == 0: - self.wait_for_port_pins_change(self._ss_ports + [self._sck_port]) - - for i in range(len(self._ss_ports)): - if i != active_slave and xsi.sample_port_pins(self._ss_ports[i]) == 0: - error = True - print("Second slave selected during first transaction") - - if (ss_value == xsi.sample_port_pins(self._ss_ports[active_slave]) and (sck_value == xsi.sample_port_pins(self._sck_port))): - continue - - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) - sck_value = xsi.sample_port_pins(self._sck_port) - - if ss_value == 0: - clock_event_time = xsi.get_time(); - measured_time_elapsed = clock_event_time - last_clock_event_time - if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : - print("ERROR: Clock half period less than allowed for given SCLK frequency" ) - print("%d %d " % (measured_time_elapsed, clock_half_period)) - error = True - last_clock_event_time =clock_event_time - - #check that the clock edges never go faster than the expected clock rate - if ss_value == 0: - clock_edge_number += 1 - #print clock_edge_number - #the the clock must have transitioned - if sck_value == (expected_cpha ^ expected_cpol): - if expected_miso_enabled == 1: - #drive data out - xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) - tx_bit_counter += 1 - tx_byte = tx_byte << 1 - if (tx_bit_counter%8) == 0: - index = tx_bit_counter/8 - if index < 16: - tx_byte = tx_data[tx_bit_counter/8] - else: - tx_byte = 0; - - else: - #clock data in - if expected_mosi_enabled == 1: - rx_byte = rx_byte << 1 - rx_byte += xsi.sample_port_pins(self._mosi_port) - rx_bit_counter = rx_bit_counter + 1 - if((rx_bit_counter%8) == 0): - expected_rx_byte = rx_data[(rx_bit_counter/8) - 1] - #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) - if expected_rx_byte != rx_byte: - print("ERROR: slave recieved incorrect data Got:%02x Expected:%02x"%(rx_byte, expected_rx_byte)) - error = True - rx_byte = 0 - else: - if clock_edge_number != expected_num_bytes*2*8: - error = True - print("ERROR: incorrect number of clock edges at slave {seen}/{expect}".format(seen=clock_edge_number, expect=expected_num_bytes*2*8)) - if error: - print("Fail: CPOL:{cpol} CPHA:{cpha} KHz:{freq} MOSI Enabled:{mosi_enabled} MISO Enabled:{miso_enabled}".format( - cpol=expected_cpol, cpha=expected_cpha, - mosi_enabled = expected_mosi_enabled, miso_enabled = expected_miso_enabled, - freq=expected_frequency_in_khz)) diff --git a/legacy_tests/spi_master_sync_benchmark/.cproject b/legacy_tests/spi_master_sync_benchmark/.cproject deleted file mode 100644 index 0a15b19..0000000 --- a/legacy_tests/spi_master_sync_benchmark/.cproject +++ /dev/null @@ -1,10088 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_benchmark/.project b/legacy_tests/spi_master_sync_benchmark/.project deleted file mode 100644 index b9b73fc..0000000 --- a/legacy_tests/spi_master_sync_benchmark/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_benchmark - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_benchmark/Makefile b/legacy_tests/spi_master_sync_benchmark/Makefile deleted file mode 100644 index d84b971..0000000 --- a/legacy_tests/spi_master_sync_benchmark/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_benchmark - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/Makefile b/legacy_tests/spi_master_sync_clock_port_sharing/Makefile deleted file mode 100644 index d69943d..0000000 --- a/legacy_tests/spi_master_sync_clock_port_sharing/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_clock_port_sharing - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_0 = $(COMMON_FLAGS) -DCOMBINED=0 -XCC_FLAGS_1 = $(COMMON_FLAGS) -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_multi_client/.cproject b/legacy_tests/spi_master_sync_multi_client/.cproject deleted file mode 100644 index 32ef84f..0000000 --- a/legacy_tests/spi_master_sync_multi_client/.cproject +++ /dev/null @@ -1,24363 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_multi_client/.project b/legacy_tests/spi_master_sync_multi_client/.project deleted file mode 100644 index 4a0a4b4..0000000 --- a/legacy_tests/spi_master_sync_multi_client/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_multi_client - - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_multi_client/Makefile b/legacy_tests/spi_master_sync_multi_client/Makefile deleted file mode 100644 index 830c92e..0000000 --- a/legacy_tests/spi_master_sync_multi_client/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_multi_client - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_4010 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4110 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4001 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4101 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4011 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_4111 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_multi_device/.cproject b/legacy_tests/spi_master_sync_multi_device/.cproject deleted file mode 100644 index 6066327..0000000 --- a/legacy_tests/spi_master_sync_multi_device/.cproject +++ /dev/null @@ -1,25172 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_multi_device/.project b/legacy_tests/spi_master_sync_multi_device/.project deleted file mode 100644 index 4527cde..0000000 --- a/legacy_tests/spi_master_sync_multi_device/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_multi_device - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_multi_device/Makefile b/legacy_tests/spi_master_sync_multi_device/Makefile deleted file mode 100644 index c5e3933..0000000 --- a/legacy_tests/spi_master_sync_multi_device/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_multi_device - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_4010 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4110 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4001 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4101 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4011 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_4111 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_5010 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_5110 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_5001 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_5101 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_5011 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_5111 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_6010 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_6110 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_6001 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_6101 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_6011 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_6111 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_rx_tx/.cproject b/legacy_tests/spi_master_sync_rx_tx/.cproject deleted file mode 100644 index ee966f1..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.cproject +++ /dev/null @@ -1,10089 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_sync_rx_tx/.project b/legacy_tests/spi_master_sync_rx_tx/.project deleted file mode 100644 index f2f5e56..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_rx_tx - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index 5833210..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,151 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1231577380/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1231577380/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.195986837/append=true -environment/project/com.xmos.cdt.toolchain.195986837/appendContributed=true -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.200711552/append=true -environment/project/com.xmos.cdt.toolchain.200711552/appendContributed=true -environment/project/com.xmos.cdt.toolchain.276149167/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.276149167/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.989279270/append=true -environment/project/com.xmos.cdt.toolchain.989279270/appendContributed=true diff --git a/legacy_tests/spi_master_sync_rx_tx/Makefile b/legacy_tests/spi_master_sync_rx_tx/Makefile deleted file mode 100644 index ce87696..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_benchmark/.cproject b/legacy_tests/spi_slave_benchmark/.cproject deleted file mode 100644 index 2d4cbd1..0000000 --- a/legacy_tests/spi_slave_benchmark/.cproject +++ /dev/null @@ -1,52897 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_slave_benchmark/.project b/legacy_tests/spi_slave_benchmark/.project deleted file mode 100644 index 6818e6f..0000000 --- a/legacy_tests/spi_slave_benchmark/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_slave_benchmark - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index e9b0869..0000000 --- a/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,321 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1033470973/append=true -environment/project/com.xmos.cdt.toolchain.1033470973/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1049848630/append=true -environment/project/com.xmos.cdt.toolchain.1049848630/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1087889181/append=true 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-environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1119664378/append=true -environment/project/com.xmos.cdt.toolchain.1119664378/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester 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-environment/project/com.xmos.cdt.toolchain.756700961/append=true -environment/project/com.xmos.cdt.toolchain.756700961/appendContributed=true -environment/project/com.xmos.cdt.toolchain.768386498/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.768386498/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.768386498/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.768386498/append=true -environment/project/com.xmos.cdt.toolchain.768386498/appendContributed=true -environment/project/com.xmos.cdt.toolchain.784791863/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.784791863/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.818775535/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.818775535/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.818775535/append=true -environment/project/com.xmos.cdt.toolchain.818775535/appendContributed=true -environment/project/com.xmos.cdt.toolchain.846686479/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.846686479/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.846686479/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.846686479/append=true -environment/project/com.xmos.cdt.toolchain.846686479/appendContributed=true -environment/project/com.xmos.cdt.toolchain.891800503/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.891800503/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.891800503/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.891800503/append=true -environment/project/com.xmos.cdt.toolchain.891800503/appendContributed=true -environment/project/com.xmos.cdt.toolchain.990543979/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.990543979/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.990543979/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.990543979/append=true -environment/project/com.xmos.cdt.toolchain.990543979/appendContributed=true diff --git a/legacy_tests/spi_slave_benchmark/Makefile b/legacy_tests/spi_slave_benchmark/Makefile deleted file mode 100644 index 82c70b3..0000000 --- a/legacy_tests/spi_slave_benchmark/Makefile +++ /dev/null @@ -1,108 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_slave_benchmark - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_02108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_021032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_06108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_061032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_13108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_131032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_17108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_171032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_benchmark/config.xscope b/legacy_tests/spi_slave_benchmark/config.xscope deleted file mode 100644 index 1ba0f11..0000000 --- a/legacy_tests/spi_slave_benchmark/config.xscope +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/legacy_tests/spi_slave_checker.py b/legacy_tests/spi_slave_checker.py deleted file mode 100644 index de08d37..0000000 --- a/legacy_tests/spi_slave_checker.py +++ /dev/null @@ -1,105 +0,0 @@ -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest - -class SPISlaveChecker(xmostest.SimThread): - """" - This simulator thread will act as SPI slave and check any transactions - caused by the master. - """ - def __init__(self, sck_port, mosi_port, miso_port, ss_port, setup_strobe_port, setup_data_port, setup_resp_port): - self._miso_port = miso_port - self._mosi_port = mosi_port - self._sck_port = sck_port - self._ss_port = ss_port - self._setup_strobe_port = setup_strobe_port - self._setup_data_port = setup_data_port - self._setup_resp_port = setup_resp_port - - def get_setup_data(self, xsi, setup_strobe_port, setup_data_port): - self.wait_for_port_pins_change([setup_strobe_port]) - self.wait_for_port_pins_change([setup_strobe_port]) - return xsi.sample_port_pins(setup_data_port) - - def run(self): - xsi = self.xsi - - sck_value = xsi.sample_port_pins(self._sck_port) - ss_value = xsi.sample_port_pins(self._ss_port) - xsi.drive_port_pins(self._ss_port,1) - - print("SPI Slave checker started") - while True: - #first do the setup rx - strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) - - expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - xsi.drive_port_pins(self._sck_port, expected_cpol) - expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - initial_clock_delay = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - - self.wait_until(xsi.get_time() + 10000) - xsi.drive_port_pins(self._ss_port, 0) - self.wait_until(xsi.get_time() + initial_clock_delay) - tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] - rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] - rx_byte = 0 - tx_byte = tx_data[0] - - #set the first data on the mosi for the case where there is no clock edge - xsi.drive_port_pins(self._mosi_port, (tx_byte>>7)&1) - - ss_value = xsi.sample_port_pins(self._ss_port) - sck_value = xsi.sample_port_pins(self._sck_port) - - clock_val = (expected_cpol^expected_cpha)&1 - bit_count = 0 - total_bit_count = 0 - byte_count = 0 - - half_clock = 1000000/(2*kbps) - error = 0 - - while total_bit_count < expected_num_bits: - #clock edge and drive data out - xsi.drive_port_pins(self._sck_port, clock_val) - xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) - tx_byte = tx_byte<<1 - self.wait_until(xsi.get_time() + half_clock) - - #clockedge and read data in - xsi.drive_port_pins(self._sck_port, 1-clock_val) - val = xsi.sample_port_pins(self._miso_port) - self.wait_until(xsi.get_time() + half_clock) - rx_byte = (rx_byte<<1) + val - bit_count = bit_count + 1 - total_bit_count = total_bit_count + 1 - if bit_count == 8: - bit_count = 0 - if expected_miso_enabled: - if rx_byte != rx_data[byte_count]: - error = 1 - #print "rx got:%02x expected:%02x %d" % (rx_byte,rx_data[byte_count], byte_count) - rx_byte = 0 - byte_count = byte_count + 1 - if byte_count*8 < expected_num_bits: - tx_byte = tx_data[byte_count] - - #check the final few rx'd bits - if bit_count and expected_miso_enabled: - if rx_byte != rx_data[byte_count]>>(8-bit_count): - error = 1 - #print "sub bit rx got:%02x expected:%02x %d" % (rx_byte,rx_data[byte_count]>>(8-bit_count), byte_count) - self.wait_until(xsi.get_time() + half_clock) - - xsi.drive_port_pins(self._sck_port, expected_cpol) - xsi.drive_port_pins(self._ss_port, 1) - - self.wait_for_port_pins_change([self._setup_strobe_port]) - xsi.drive_port_pins(self._setup_resp_port, error) - self.wait_for_port_pins_change([self._setup_strobe_port]) diff --git a/legacy_tests/spi_slave_rx_tx/.cproject b/legacy_tests/spi_slave_rx_tx/.cproject deleted file mode 100644 index 1424324..0000000 --- a/legacy_tests/spi_slave_rx_tx/.cproject +++ /dev/null @@ -1,52897 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_slave_rx_tx/.project b/legacy_tests/spi_slave_rx_tx/.project deleted file mode 100644 index e9d7d69..0000000 --- a/legacy_tests/spi_slave_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_slave_rx_tx - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index d355de5..0000000 --- a/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,321 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1015056818/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1015056818/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.1130118063/append=true -environment/project/com.xmos.cdt.toolchain.1130118063/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1165201921/append=true -environment/project/com.xmos.cdt.toolchain.1165201921/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1165566074/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1165566074/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.617091556/append=true -environment/project/com.xmos.cdt.toolchain.617091556/appendContributed=true -environment/project/com.xmos.cdt.toolchain.655665246/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.655665246/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.655665246/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.655665246/append=true -environment/project/com.xmos.cdt.toolchain.655665246/appendContributed=true -environment/project/com.xmos.cdt.toolchain.665303255/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.665303255/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.665303255/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.665303255/append=true -environment/project/com.xmos.cdt.toolchain.665303255/appendContributed=true -environment/project/com.xmos.cdt.toolchain.670808726/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.670808726/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.670808726/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.670808726/append=true -environment/project/com.xmos.cdt.toolchain.670808726/appendContributed=true -environment/project/com.xmos.cdt.toolchain.676749111/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.676749111/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.676749111/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.676749111/append=true -environment/project/com.xmos.cdt.toolchain.676749111/appendContributed=true -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.676883664/append=true -environment/project/com.xmos.cdt.toolchain.676883664/appendContributed=true -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.678776223/append=true -environment/project/com.xmos.cdt.toolchain.678776223/appendContributed=true -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.680214508/append=true -environment/project/com.xmos.cdt.toolchain.680214508/appendContributed=true -environment/project/com.xmos.cdt.toolchain.747461949/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.747461949/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.747461949/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.747461949/append=true -environment/project/com.xmos.cdt.toolchain.747461949/appendContributed=true -environment/project/com.xmos.cdt.toolchain.750974751/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.750974751/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.750974751/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.750974751/append=true -environment/project/com.xmos.cdt.toolchain.750974751/appendContributed=true -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.77010454/append=true -environment/project/com.xmos.cdt.toolchain.77010454/appendContributed=true -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.779850310/append=true -environment/project/com.xmos.cdt.toolchain.779850310/appendContributed=true -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.798597172/append=true -environment/project/com.xmos.cdt.toolchain.798597172/appendContributed=true -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.863428765/append=true -environment/project/com.xmos.cdt.toolchain.863428765/appendContributed=true -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.912638989/append=true -environment/project/com.xmos.cdt.toolchain.912638989/appendContributed=true -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.932144966/append=true -environment/project/com.xmos.cdt.toolchain.932144966/appendContributed=true -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.969988333/append=true -environment/project/com.xmos.cdt.toolchain.969988333/appendContributed=true diff --git a/legacy_tests/spi_slave_rx_tx/Makefile b/legacy_tests/spi_slave_rx_tx/Makefile deleted file mode 100644 index 73ea857..0000000 --- a/legacy_tests/spi_slave_rx_tx/Makefile +++ /dev/null @@ -1,109 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling - -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_slave_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_02108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_021032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_06108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_061032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_13108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_131032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_17108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_171032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_rx_tx/config.xscope b/legacy_tests/spi_slave_rx_tx/config.xscope deleted file mode 100644 index 1ba0f11..0000000 --- a/legacy_tests/spi_slave_rx_tx/config.xscope +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/legacy_tests/test_master_async_multi_client.py b/legacy_tests/test_master_async_multi_client.py deleted file mode 100644 index d38531c..0000000 --- a/legacy_tests/test_master_async_multi_client.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_client_async(burnt_threads, mosi_enable, combine): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_multi_client/bin/{burnt}{mosi}{combined}/spi_master_async_multi_client_{burnt}{mosi}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'multi_client_async_{burnt}{mosi}{combined}'.format(burnt=burnt_threads, mosi=mosi_enable, combined=combine), - regexp=True) - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_async_multi_client/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - burnt_threads = 3 - for mosi_enabled in [0, 1]: - for combine in [0, 1]: - do_multi_client_async(burnt_threads+combine, mosi_enabled, combine) diff --git a/legacy_tests/test_master_async_multi_device.py b/legacy_tests/test_master_async_multi_device.py deleted file mode 100644 index 169017e..0000000 --- a/legacy_tests/test_master_async_multi_device.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_device_async(burnt_threads, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_multi_device/bin/{burnt}{mosi}/spi_master_async_multi_device_{burnt}{mosi}.xe".format(burnt=burnt_threads,mosi=mosi_enable) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_multi_device_{burnt}{mosi}'.format(burnt=burnt_threads, mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_async_multi_device/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [2, 6]: - for mosi_enabled in [0, 1]: - do_multi_device_async(burnt_threads, mosi_enabled) diff --git a/legacy_tests/test_master_async_rx_tx.py b/legacy_tests/test_master_async_rx_tx.py deleted file mode 100644 index 019fe2b..0000000 --- a/legacy_tests/test_master_async_rx_tx.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_rx_tx_async(burnt_threads, mosi_enable, speed_tests, combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_rx_tx/bin/{burnt}{mosi}{speed}{combined}/spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}'.format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - for mosi_enabled in [0, 1]: - do_rx_tx_async(6 + 1, mosi_enabled, 1, 1, "smoke") - - for burnt_threads in [2, 6]: - for combined in [0, 1]: - for mosi_enabled in [0, 1]: - do_rx_tx_async(burnt_threads + combined, mosi_enabled, 1, combined, "nightly") diff --git a/legacy_tests/test_master_async_shutdown.py b/legacy_tests/test_master_async_shutdown.py deleted file mode 100644 index 848176b..0000000 --- a/legacy_tests/test_master_async_shutdown.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_shutdown_async(combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_shutdown/bin/{combined}/spi_master_async_shutdown_{combined}.xe".format(combined=combine) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_shutdown_{combined}'.format(combined=combine), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - # do_shutdown_async(1, "smoke") - - # for combined in [0, 1]: - # do_shutdown_async(combined, "nightly") - pass \ No newline at end of file diff --git a/legacy_tests/test_master_sync_benchmark.py b/legacy_tests/test_master_sync_benchmark.py deleted file mode 100644 index f33e6cd..0000000 --- a/legacy_tests/test_master_sync_benchmark.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_benchmark_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_benchmark/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_benchmark_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master_benchmark.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_benchmark_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 7]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_benchmark_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_clock_port_sharing.py b/legacy_tests/test_master_sync_clock_port_sharing.py deleted file mode 100644 index 6cdaeb6..0000000 --- a/legacy_tests/test_master_sync_clock_port_sharing.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - -def do_clock_port_sharing(combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_clock_port_sharing/bin/{combined}/spi_master_sync_clock_port_sharing_{combined}.xe".format(combined=combine) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_clock_port_sharing_{combined}'.format(combined=combine), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - do_clock_port_sharing(1, "smoke") - do_clock_port_sharing(0, "nightly") diff --git a/legacy_tests/test_master_sync_multi_client.py b/legacy_tests/test_master_sync_multi_client.py deleted file mode 100644 index dafd2d8..0000000 --- a/legacy_tests/test_master_sync_multi_client.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_client_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_multi_client/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_multi_client_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_multi_client_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_client/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 4]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_multi_client_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_multi_device.py b/legacy_tests/test_master_sync_multi_device.py deleted file mode 100644 index 556cb09..0000000 --- a/legacy_tests/test_master_sync_multi_device.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_device_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_multi_device/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_multi_device_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_multi_device_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 7]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_multi_device_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_rx_tx.py b/legacy_tests/test_master_sync_rx_tx.py deleted file mode 100644 index e5449cb..0000000 --- a/legacy_tests/test_master_sync_rx_tx.py +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_rx_tx_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_rx_tx/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_rx_tx_sync(3, cb_enabled, miso_enabled, mosi_enabled, "smoke") - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_rx_tx_sync(7, cb_enabled, miso_enabled, mosi_enabled, "nightly") diff --git a/legacy_tests/test_slave_benchmark.py b/legacy_tests/test_slave_benchmark.py deleted file mode 100644 index 8c4ad28..0000000 --- a/legacy_tests/test_slave_benchmark.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_slave_checker import SPISlaveChecker -import os - - -def do_slave_benchmark(combined, burnt_threads, miso_enable, mode, transfer_size): - resources = xmostest.request_resource("xsim") - - binary = "spi_slave_benchmark/bin/{com}{burnt}{miso}{m}{t}/spi_slave_benchmark_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size) - - checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - "tile[0]:XS1_PORT_1B", - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") - - tester = xmostest.ComparisonTester(open('slave_benchmark.expect'), - 'lib_spi', - 'spi_slave_sim_tests', - 'spi_slave_benchmark_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_slave_benchmark/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for combined in [0,1]: - for mode in range(0, 4): - for burnt_threads in [2, 6]: - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_benchmark(combined, burnt_threads+combined, miso_enable, mode, transfer_size) diff --git a/legacy_tests/test_slave_rx_tx.py b/legacy_tests/test_slave_rx_tx.py deleted file mode 100644 index 7d92f3f..0000000 --- a/legacy_tests/test_slave_rx_tx.py +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_slave_checker import SPISlaveChecker -import os - - -def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size, testlevel): - - resources = xmostest.request_resource("xsim") - - binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size) - - checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - "tile[0]:XS1_PORT_1B", - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") - - tester = xmostest.ComparisonTester(open('slave.expect'), - 'lib_spi', - 'spi_slave_sim_tests', - 'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size), - {'combined': combined, 'burnt_threads': burnt_threads, 'miso_enable': miso_enable, 'mode': mode, 'transfer_size': transfer_size}, - regexp=True) - - tester.set_min_testlevel(testlevel) - - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_rx_tx(1, 2+1, miso_enable, 3, transfer_size, "smoke") - - for combined in [0,1]: - for mode in range(0, 4): - for burnt_threads in [2, 6]: - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_rx_tx(combined, burnt_threads+combined, miso_enable, mode, transfer_size, "nightly") diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt new file mode 100644 index 0000000..5d41217 --- /dev/null +++ b/tests/CMakeLists.txt @@ -0,0 +1,13 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(lib_spi_tests) + +add_subdirectory(spi_master_sync_benchmark) +add_subdirectory(spi_master_sync_rx_tx) +add_subdirectory(spi_master_sync_multi_device) +add_subdirectory(spi_master_sync_multi_client) +add_subdirectory(spi_master_sync_clock_port_sharing) +add_subdirectory(spi_slave_benchmark) +add_subdirectory(spi_slave_rx_tx) +add_subdirectory(spi_master_async_rx_tx) +add_subdirectory(spi_master_async_multi_client) diff --git a/tests/conftest.py b/tests/conftest.py new file mode 100644 index 0000000..142e77e --- /dev/null +++ b/tests/conftest.py @@ -0,0 +1,27 @@ +# Copyright 2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import pytest + +# from https://github.com/pytest-dev/pytest/issues/3730#issuecomment-567142496 +def pytest_configure(config): + config.addinivalue_line( + "markers", "uncollect_if(*, func): function to unselect tests from parametrization" + ) + +def pytest_collection_modifyitems(config, items): + removed = [] + kept = [] + for item in items: + m = item.get_closest_marker('uncollect_if') + if m: + func = m.kwargs['func'] + if func(**item.callspec.params): + removed.append(item) + continue + kept.append(item) + if removed: + config.hook.pytest_deselected(items=removed) + items[:] = kept + +def pytest_addoption(parser): + parser.addoption("--testlevel") diff --git a/tests/expected/master_multi_device.expect b/tests/expected/master_multi_device.expect new file mode 100644 index 0000000..b960bc0 --- /dev/null +++ b/tests/expected/master_multi_device.expect @@ -0,0 +1,5 @@ +SPI Master checker started +Transfers to device 0 complete +Transfers to device 1 complete +Transfers to device 0 complete +Transfers to device 1 complete diff --git a/legacy_tests/master.expect b/tests/expected/master_sync.expect similarity index 58% rename from legacy_tests/master.expect rename to tests/expected/master_sync.expect index 1bd90db..8903669 100644 --- a/legacy_tests/master.expect +++ b/tests/expected/master_sync.expect @@ -1 +1,2 @@ SPI Master checker started +Transfers complete diff --git a/tests/expected/slave.expect b/tests/expected/slave.expect new file mode 100644 index 0000000..0154375 --- /dev/null +++ b/tests/expected/slave.expect @@ -0,0 +1,36 @@ +SPI Slave checker started +Send initial settings +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 128 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 1 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 2 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 3 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 4 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 5 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 6 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 7 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 8 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 9 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 10 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 11 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 12 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 13 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 14 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 15 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 16 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 17 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 18 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 19 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 20 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 21 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 22 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 23 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 24 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 25 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 26 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 27 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 28 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 29 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 30 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 31 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 32 kbps \d+ init delay \d+ +Test completed diff --git a/tests/expected/slave_intertransaction.expect b/tests/expected/slave_intertransaction.expect new file mode 100644 index 0000000..c03ef1c --- /dev/null +++ b/tests/expected/slave_intertransaction.expect @@ -0,0 +1,5 @@ +SPI Slave checker started +Send initial settings +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 128 kbps \d+ init delay \d+ +Delay is \d+.\d+ ns +(Request exit on success|Request exit on error){1} diff --git a/tests/helpers.py b/tests/helpers.py new file mode 100644 index 0000000..43e3c3c --- /dev/null +++ b/tests/helpers.py @@ -0,0 +1,115 @@ +# Copyright 2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import os +import random +import sys +import Pyxsim as px +import pytest +import json +import csv +import threading +import itertools +from filelock import FileLock + +# Thread safe create a folder +def create_if_needed(folder): + lock_path = f"{folder}.lock" + # xdist can cause race conditions so use a lock + with FileLock(lock_path): + if not os.path.exists(folder): + os.makedirs(folder) + return folder + +# Read a JSON and get the test configs and IDs. Pass the JSON files +def generate_tests_from_json(test_params_json): + with open(test_params_json) as f: + params = json.load(f) + + # Prepare keys and values + keys = [] + values = [] + + for key, val_or_dict_list in params.items(): + if isinstance(val_or_dict_list[0], dict): + # Instead of keeping the key, we flatten the dicts inside the list + combined_keys = list(val_or_dict_list[0].keys()) # "COMBINED", "BURNT_THREADS" + # Save separate keys for later flattening + keys.extend(combined_keys) + # Convert list of dicts to list of tuples (flattened for combinations) + values.append([tuple(d[k] for k in combined_keys) for d in val_or_dict_list]) + else: + keys.append(key) + values.append(val_or_dict_list) + + # Generate combinations + combinations = itertools.product(*values) + + # Build final output + test_config_ids = [] + test_configs = [] + for combo in combinations: + test_config_id = {} + + key_idx = 0 + for val in combo: + if isinstance(val, tuple): # This only happens for THREAD_PROFILES + for subval in val: + key = keys[key_idx] + test_config_id[key] = subval + key_idx += 1 + else: + key = keys[key_idx] + test_config_id[key] = val + key_idx += 1 + + test_config = list(test_config_id.values()) + test_config_id = ", ".join(f"{k}={v}" for k, v in test_config_id.items()) + # print(test_config, test_config_id) + test_configs.append(test_config) + test_config_ids.append(test_config_id) + + return test_configs, test_config_ids + + +# Create a global lock +csv_write_lock = threading.Lock() +def write_csv_row(filepath, row): + """ + Thread-safe write to a CSV file. + + Args: + filepath (str): Path to the CSV file. + row (dict): A dictionary representing a single CSV row. + """ + with csv_write_lock: + file_exists = False + try: + with open(filepath, 'r', newline='') as f: + file_exists = True + except FileNotFoundError: + pass + + with open(filepath, 'a', newline='') as f: + writer = csv.DictWriter(f, fieldnames=row.keys()) + if not file_exists: + writer.writeheader() + writer.writerow(row) + +def sort_csv_table(file_path): + with csv_write_lock: + try: + with open(file_path, newline='') as f: + reader = csv.DictReader(f) + rows = list(reader) + fieldnames = reader.fieldnames + + # Sort rows by all columns lexicographically (as a tuple of values) + rows.sort(key=lambda row: tuple(row[col] for col in fieldnames)) + + with open(file_path, 'w', newline='') as f: + writer = csv.DictWriter(f, fieldnames=fieldnames) + writer.writeheader() + writer.writerows(rows) + + except FileNotFoundError: + assert 0, f"No CSV table {file_path} to sort" \ No newline at end of file diff --git a/tests/requirements.txt b/tests/requirements.txt new file mode 100644 index 0000000..d7a5e7a --- /dev/null +++ b/tests/requirements.txt @@ -0,0 +1,37 @@ +# python_version 3.12.1 +# pip_version 24.* +# +# The parse_version_from_requirements() function in the installPipfile.groovy +# file of the Jenkins Shared Library uses the python_version comment to set +# the version of python used. + +# Distributed (released) dependencies +# +# The python modules listed below specify a known working combination required +# by the python code in this repository. The procedure used to set up a +# suitable python environment for it installs the version of each module in +# the list. Using a specific version ensures a controlled infrastructure for +# development, testing and release of this repository. +# +# Another repository might depend on python code defined in this one. The +# procedure to set up a suitable python environment for that repository may +# pip-install this one as editable using this repository's setup.py file. The +# same modules should appear in the setup.py list as given below. + +pytest==8.3.3 +pytest-xdist==3.6.1 +filelock==3.18.0 + +# Development dependencies +# +# Each link listed below specifies the path to a setup.py file which are +# installed in editable mode with '-e $PATH' (without the quotes). +# +# If python code in this repository depends on python code under development +# in another repository, then an entry for that other respository should +# appear in this list instead of the released dependencies list. +# +# If this repository uses the setup functionality (e.g., script entry points) +# of its own setup.py file, then this list must include an entry for that +# setup.py file, e.g., '-e .' or '-e ./python' (without the quotes). +-e ./../../test_support diff --git a/tests/spi_master_async_multi_client/CMakeLists.txt b/tests/spi_master_async_multi_client/CMakeLists.txt new file mode 100644 index 0000000..c3b4500 --- /dev/null +++ b/tests/spi_master_async_multi_client/CMakeLists.txt @@ -0,0 +1,64 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mosi_enabled_list GET ${params_json} MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mosi_enabled_list_len LENGTH ${mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mosi_enabled_list_len "${mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(l RANGE 0 ${mosi_enabled_list_len}) + string(JSON mosi_enabled GET ${mosi_enabled_list} ${l}) + + set(config ${COMBINED}_${BURNT_THREADS}_${mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_async_multi_client) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${BURNT_THREADS} + -DCOMBINED=${COMBINED} + -DMOSI_ENABLED=${mosi_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_multi_client/config.xscope b/tests/spi_master_async_multi_client/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_multi_client/config.xscope rename to tests/spi_master_async_multi_client/config.xscope diff --git a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc similarity index 94% rename from legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc rename to tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index 9e5babd..358e7c7 100644 --- a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -19,6 +19,10 @@ clock cb1 = XS1_CLKBLK_2; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; +void flush_print(void){ + delay_microseconds(1000); +} + void app(client interface spi_master_async_if i, int mosi_enabled, int miso_enabled, chanend c, unsigned speed){ set_core_fast_mode_on(); @@ -56,7 +60,9 @@ void watcher(chanend c[CLIENTS]){ any_not_seen |= (seen[j] == 0); if(!any_not_seen){ - _Exit(0); + printf("Transfers complete\n"); + flush_print(); + _Exit(0); } break; } diff --git a/tests/spi_master_async_multi_client/test_params.json b/tests/spi_master_async_multi_client/test_params.json new file mode 100644 index 0000000..af35acc --- /dev/null +++ b/tests/spi_master_async_multi_client/test_params.json @@ -0,0 +1,14 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 4 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 3 + } + ], + "MOSI_ENABLED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_async_multi_device/CMakeLists.txt b/tests/spi_master_async_multi_device/CMakeLists.txt new file mode 100644 index 0000000..26dac43 --- /dev/null +++ b/tests/spi_master_async_multi_device/CMakeLists.txt @@ -0,0 +1,64 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mosi_enabled_list GET ${params_json} MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mosi_enabled_list_len LENGTH ${mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mosi_enabled_list_len "${mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(l RANGE 0 ${mosi_enabled_list_len}) + string(JSON mosi_enabled GET ${mosi_enabled_list} ${l}) + + set(config ${COMBINED}_${BURNT_THREADS}_${mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_async_multi_device) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${BURNT_THREADS} + -DCOMBINED=${COMBINED} + -DMOSI_ENABLED=${mosi_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_multi_device/config.xscope b/tests/spi_master_async_multi_device/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_multi_device/config.xscope rename to tests/spi_master_async_multi_device/config.xscope diff --git a/legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc b/tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc similarity index 100% rename from legacy_tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc rename to tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc diff --git a/tests/spi_master_async_multi_device/test_params.json b/tests/spi_master_async_multi_device/test_params.json new file mode 100644 index 0000000..af35acc --- /dev/null +++ b/tests/spi_master_async_multi_device/test_params.json @@ -0,0 +1,14 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 4 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 3 + } + ], + "MOSI_ENABLED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_async_rx_tx/CMakeLists.txt b/tests/spi_master_async_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..e4499dc --- /dev/null +++ b/tests/spi_master_async_rx_tx/CMakeLists.txt @@ -0,0 +1,91 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON speed_test_list GET ${params_json} SPEED_TESTS) +string(JSON transfer_width_list GET ${params_json} TRANSFER_WIDTH) +string(JSON spi_mode_list GET ${params_json} MODE) +string(JSON mosi_enabled_list GET ${params_json} MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON speed_test_list_len LENGTH ${speed_test_list}) +string(JSON transfer_width_list_len LENGTH ${transfer_width_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) +string(JSON mosi_enabled_list_len LENGTH ${mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR speed_test_list_len "${speed_test_list_len} - 1") +math(EXPR transfer_width_list_len "${transfer_width_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") +math(EXPR mosi_enabled_list_len "${mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(l RANGE 0 ${speed_test_list_len}) + string(JSON SPEED_TESTS GET ${speed_test_list} ${l}) + + foreach(m RANGE 0 ${mosi_enabled_list_len}) + string(JSON MOSI_ENABLED GET ${mosi_enabled_list} ${m}) + + foreach(n RANGE 0 ${transfer_width_list_len}) + string(JSON TRANSFER_WIDTH GET ${transfer_width_list} ${n}) + + foreach(o RANGE 0 ${spi_mode_list_len}) + string(JSON SPI_MODE GET ${spi_mode_list} ${o}) + + + set(config ${COMBINED}_${BURNT_THREADS}_${MOSI_ENABLED}_${SPEED_TESTS}_${TRANSFER_WIDTH}_${SPI_MODE}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_async_rx_tx) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${COMBINED} + -DBURNT_THREADS=${BURNT_THREADS} + -DMOSI_ENABLED=${MOSI_ENABLED} + -DSPEED_TESTS=${SPEED_TESTS} + -DTRANSFER_WIDTH=${TRANSFER_WIDTH} + -DSPI_MODE=${SPI_MODE} + -O2 + -g + -Wno-reinterpret-alignment) + + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_rx_tx/config.xscope b/tests/spi_master_async_rx_tx/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_rx_tx/config.xscope rename to tests/spi_master_async_rx_tx/config.xscope diff --git a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc similarity index 81% rename from legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc rename to tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index 898a320..a528279 100644 --- a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -22,39 +22,35 @@ typedef enum { SPI_TRANSFER_WIDTH_32 } t_transfer_width; +void flush_print(void){ + delay_microseconds(1000); +} + +/* This counts up to 16 bytes (steps of 4 if 32b) */ static void inc_state(unsigned &count, spi_mode_t &mode, unsigned &speed_index, t_transfer_width &transfer_width){ + // printf("count: %u, speed_idx: %u (%u), mode: %d width: %d\n", count, speed_index, SPEED_TESTS, mode, transfer_width * 24 + 8); if(count == 16){ - count=0; - if(mode == SPI_MODE_3){ - mode = SPI_MODE_0; - if(transfer_width == SPI_TRANSFER_WIDTH_32){ - transfer_width = SPI_TRANSFER_WIDTH_8; - if(speed_index == SPEED_TESTS){ - _Exit(0); - } else { - speed_index++; - } - } else { - transfer_width++; - } - } else { - mode++; + count = 0; + if(++speed_index == SPEED_TESTS){ + printf("Transfers complete\n"); + flush_print(); + _Exit(0); } } else { - if(transfer_width == SPI_TRANSFER_WIDTH_8) + if(transfer_width == SPI_TRANSFER_WIDTH_8){ count++; - else { + } else { count+=4; } } - - } + [[combinable]] void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_enabled){ - unsigned speed_lut[3] = {500, 200, 2000}; + // if testing just one speed, do fastest (idx 0) + unsigned speed_lut[3] = {2000, 200, 500}; uint8_t tx8[NUMBER_OF_TEST_BYTES]; uint8_t rx8[NUMBER_OF_TEST_BYTES]; @@ -76,9 +72,9 @@ void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_ unsigned speed_index = 0; unsigned device_id = 0; - spi_mode_t mode = SPI_MODE_0; + spi_mode_t mode = SPI_MODE; unsigned speed_in_kbps = speed_lut[speed_index]; - t_transfer_width transfer_width = SPI_TRANSFER_WIDTH_8; + t_transfer_width transfer_width = TRANSFER_WIDTH == 8 ? SPI_TRANSFER_WIDTH_8 : SPI_TRANSFER_WIDTH_32; unsigned count = 0; //bytes or words broadcast_settings(setup_strobe_port, setup_data_port, @@ -100,13 +96,16 @@ void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_ } spi_i.end_transaction(inter_frame_gap); + //verify the data if(transfer_width == SPI_TRANSFER_WIDTH_8){ if(miso_enabled){ for(unsigned j=0;j None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_ports = ss_ports + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self) -> None: + xsi: px.pyxsim.Xsi = self.xsi + + sck_value = xsi.sample_port_pins(self._sck_port) + ss_value = [] + + for i in range(len(self._ss_ports)): + ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) + + print("SPI Master checker started") + while True: + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_frequency_in_khz = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_mosi_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + + clock_half_period = 1000000000/(expected_frequency_in_khz*2) + + all_ss_deserted = True + for i in range(len(self._ss_ports)): + if (xsi.sample_port_pins(self._ss_ports[i]) == 0): + all_ss_deserted = False + break + + while not all_ss_deserted: + self.wait_for_port_pins_change(self._ss_ports) + all_ss_deserted = True + for i in range(len(self._ss_ports)): + all_ss_deserted = all_ss_deserted and (xsi.sample_port_pins(self._ss_ports[i]) == 1) + + error = False + + active_slave = -1 + + while(active_slave == -1): + self.wait_for_port_pins_change(self._ss_ports) + + for i in range(len(self._ss_ports)): + if xsi.sample_port_pins(self._ss_ports[i]) == 0: + active_slave = i + break + + last_clock_event_time = xsi.get_time() + + rx_bit_counter = 0 + tx_bit_counter = 0 + tx_data = [0xfe, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + # check the polarity + if xsi.sample_port_pins(self._sck_port) != expected_cpol: + print("ERROR: unexpected clock polarity at the slave select point") + error = True + clock_edge_number = 0 + + #probably not physically possible but good for testing + if expected_cpha == 0: + xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) + tx_bit_counter += 1 + tx_byte = tx_byte << 1 + + ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) + sck_value = xsi.sample_port_pins(self._sck_port) + + while ss_value == 0: + self.wait_for_port_pins_change(self._ss_ports + [self._sck_port]) + + for i in range(len(self._ss_ports)): + if i != active_slave and xsi.sample_port_pins(self._ss_ports[i]) == 0: + error = True + print("Second slave selected during first transaction") + + if (ss_value == xsi.sample_port_pins(self._ss_ports[active_slave]) and (sck_value == xsi.sample_port_pins(self._sck_port))): + continue + + ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) + sck_value = xsi.sample_port_pins(self._sck_port) + + if ss_value == 0: + clock_event_time = xsi.get_time() + measured_time_elapsed = clock_event_time - last_clock_event_time + if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : + print("ERROR: Clock half period less than allowed for given SCLK frequency" ) + print(f"{measured_time_elapsed} {clock_half_period}") + error = True + last_clock_event_time =clock_event_time + + #check that the clock edges never go faster than the expected clock rate + if ss_value == 0: + clock_edge_number += 1 + #print clock_edge_number + #the the clock must have transitioned + if sck_value == (expected_cpha ^ expected_cpol): + if expected_miso_enabled == 1: + #drive data out + xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) + tx_bit_counter += 1 + tx_byte = tx_byte << 1 + if (tx_bit_counter%8) == 0: + index = tx_bit_counter//8 + if index < 16: + tx_byte = tx_data[index] + else: + tx_byte = 0 + else: + #clock data in + if expected_mosi_enabled == 1: + rx_byte = rx_byte << 1 + rx_byte += xsi.sample_port_pins(self._mosi_port) + rx_bit_counter = rx_bit_counter + 1 + if((rx_bit_counter%8) == 0): + expected_rx_byte = rx_data[(rx_bit_counter//8) - 1] + #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) + if expected_rx_byte != rx_byte: + print(f"ERROR: slave recieved incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x}") + error = True + rx_byte = 0 + else: + if clock_edge_number != expected_num_bytes*2*8: + error = True + print(f"ERROR: incorrect number of clock edges at slave {clock_edge_number}/{expected_num_bytes*2*8}") + if error: + print(f"Fail: CPOL:{expected_cpol} CPHA:{expected_cpha} KHz:{expected_frequency_in_khz} MOSI Enabled:{expected_mosi_enabled} MISO Enabled:{expected_miso_enabled}") diff --git a/tests/spi_master_sync_benchmark/CMakeLists.txt b/tests/spi_master_sync_benchmark/CMakeLists.txt new file mode 100644 index 0000000..806db9d --- /dev/null +++ b/tests/spi_master_sync_benchmark/CMakeLists.txt @@ -0,0 +1,83 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_benchmark) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_shutdown/config.xscope b/tests/spi_master_sync_benchmark/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_shutdown/config.xscope rename to tests/spi_master_sync_benchmark/config.xscope diff --git a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc similarity index 98% rename from legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc rename to tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index 9364eb1..f5baf60 100644 --- a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -60,6 +60,7 @@ static unsigned get_max_word_speed(client interface spi_master_if i){ //unsigned test_speed = (min + max)/2; unsigned test_speed = min + (max-min)/32; t:> then; + // printf("testing: %u\n", test_speed); i.begin_transaction(0, test_speed, SPI_MODE_3); i.transfer32(0xff); i.transfer32(0xff); diff --git a/tests/spi_master_sync_benchmark/test_params.json b/tests/spi_master_sync_benchmark/test_params.json new file mode 100644 index 0000000..ea40c99 --- /dev/null +++ b/tests/spi_master_sync_benchmark/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 7], + "CB_ENABLED": [0, 1], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt b/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt new file mode 100644 index 0000000..898c8b7 --- /dev/null +++ b/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt @@ -0,0 +1,26 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + +project(spi_master_sync_clock_port_sharing) +set(target "XK-EVK-XU316") +set(APP_HW_TARGET ${target}) + +set(COMPILER_FLAGS_COMMON -O2 + -g + -Wno-reinterpret-alignment) + + +set(APP_COMPILER_FLAGS_COMBINED ${COMPILER_FLAGS_COMMON} + -DCOMBINED=1) + +set(APP_COMPILER_FLAGS_NOT_COMBINED ${COMPILER_FLAGS_COMMON} + -DCOMBINED=0) + + +set(APP_INCLUDES src ../spi_master_tester_common) + +XMOS_REGISTER_APP() diff --git a/legacy_tests/spi_master_sync_benchmark/config.xscope b/tests/spi_master_sync_clock_port_sharing/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_benchmark/config.xscope rename to tests/spi_master_sync_clock_port_sharing/config.xscope diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc similarity index 88% rename from legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc rename to tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc index 44c8521..7a395b8 100644 --- a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc +++ b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc @@ -23,6 +23,8 @@ void app(client interface spi_master_if spi_i, int mosi_enabled, int miso_enable timer always; int start; always :> start; + start += 1000; // wait 10us to start + while (1) { select { @@ -47,6 +49,9 @@ void app(client interface spi_master_if spi_i, int mosi_enabled, int miso_enable count++; if (count == 8) + printf("Transfers complete\n"); // This first one is missed. Can't work out why! + printf("Transfers complete\n"); + delay_microseconds(100); // Flush _Exit(0); break; @@ -60,6 +65,8 @@ void timebomb(){ tmr :> t; tmr when timerafter(t + 10000000) :> void; printf("Timeout!\n"); + delay_milliseconds(1); + printf("\n"); _Exit(1); } diff --git a/tests/spi_master_sync_multi_client/CMakeLists.txt b/tests/spi_master_sync_multi_client/CMakeLists.txt new file mode 100644 index 0000000..6a7e33f --- /dev/null +++ b/tests/spi_master_sync_multi_client/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_multi_client) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/config.xscope b/tests/spi_master_sync_multi_client/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_clock_port_sharing/config.xscope rename to tests/spi_master_sync_multi_client/config.xscope diff --git a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc similarity index 97% rename from legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc rename to tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 688fdb8..4dcedd1 100644 --- a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -40,6 +40,7 @@ void watcher(chanend c[CLIENTS]){ any_not_seen |= (seen[j] == 0); if(!any_not_seen){ + printf("Transfers complete\n"); _Exit(0); } break; diff --git a/tests/spi_master_sync_multi_client/test_params.json b/tests/spi_master_sync_multi_client/test_params.json new file mode 100644 index 0000000..317568c --- /dev/null +++ b/tests/spi_master_sync_multi_client/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 4], + "CB_ENABLED": [0, 1], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_multi_device/CMakeLists.txt b/tests/spi_master_sync_multi_device/CMakeLists.txt new file mode 100644 index 0000000..0b21045 --- /dev/null +++ b/tests/spi_master_sync_multi_device/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_multi_device) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_multi_client/config.xscope b/tests/spi_master_sync_multi_device/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_multi_client/config.xscope rename to tests/spi_master_sync_multi_device/config.xscope diff --git a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc similarity index 98% rename from legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc rename to tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index b9bc669..9b5d396 100644 --- a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -47,6 +47,7 @@ void app(client interface spi_master_if i, unsigned num_ss, test_transfer8 (i, setup_strobe_port, setup_data_port, 1, ifg, mode, KBPS, mosi_enabled, miso_enabled); + printf("Transfers complete\n"); _Exit(0); } diff --git a/tests/spi_master_sync_multi_device/test_params.json b/tests/spi_master_sync_multi_device/test_params.json new file mode 100644 index 0000000..ea40c99 --- /dev/null +++ b/tests/spi_master_sync_multi_device/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 7], + "CB_ENABLED": [0, 1], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_rx_tx/CMakeLists.txt b/tests/spi_master_sync_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..18bc1ac --- /dev/null +++ b/tests/spi_master_sync_rx_tx/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_rx_tx) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc similarity index 97% rename from legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc rename to tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 790ed37..b731760 100644 --- a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -17,7 +17,6 @@ out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ - #define SPEED_TESTS 1 unsigned speed_lut[SPEED_TESTS] = {1500}; @@ -33,7 +32,8 @@ void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } } - _Exit(1); + printf("Transfers complete\n"); + _Exit(0); } static void load(static const unsigned num_threads){ diff --git a/tests/spi_master_sync_rx_tx/test_params.json b/tests/spi_master_sync_rx_tx/test_params.json new file mode 100644 index 0000000..ea40c99 --- /dev/null +++ b/tests/spi_master_sync_rx_tx/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 7], + "CB_ENABLED": [0, 1], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/legacy_tests/lib_spi_master_tester/src/common.h b/tests/spi_master_tester_common/common.h similarity index 95% rename from legacy_tests/lib_spi_master_tester/src/common.h rename to tests/spi_master_tester_common/common.h index 753a74a..9ceb4b1 100644 --- a/legacy_tests/lib_spi_master_tester/src/common.h +++ b/tests/spi_master_tester_common/common.h @@ -18,8 +18,10 @@ static void send_data_to_tester( unsigned data){ setup_data_port <: data; sync(setup_data_port); + setup_strobe_port <: 1; // Twice to meet timing on harness setup_strobe_port <: 1; setup_strobe_port <: 0; + setup_strobe_port <: 0; } static void broadcast_settings( diff --git a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h b/tests/spi_master_tester_common/spi_async_tester.h similarity index 100% rename from legacy_tests/lib_spi_master_tester/src/spi_async_tester.h rename to tests/spi_master_tester_common/spi_async_tester.h diff --git a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h similarity index 99% rename from legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h rename to tests/spi_master_tester_common/spi_sync_tester.h index 43d0662..6c3a297 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -3,7 +3,7 @@ #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ -#define VERBOSE 0 +#define VERBOSE 1 #include "common.h" diff --git a/tests/spi_slave_benchmark/CMakeLists.txt b/tests/spi_slave_benchmark/CMakeLists.txt new file mode 100644 index 0000000..be00f67 --- /dev/null +++ b/tests/spi_slave_benchmark/CMakeLists.txt @@ -0,0 +1,81 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mode_list GET ${params_json} MODE) +string(JSON transfer_size_list GET ${params_json} TRANSFER_SIZE) +string(JSON miso_enabled_list GET ${params_json} MISO_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mode_list_len LENGTH ${mode_list}) +string(JSON transfer_size_list_len LENGTH ${transfer_size_list}) +string(JSON miso_enabled_list_len LENGTH ${miso_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mode_list_len "${mode_list_len} - 1") +math(EXPR transfer_size_list_len "${transfer_size_list_len} - 1") +math(EXPR miso_enabled_list_len "${miso_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(k RANGE 0 ${mode_list_len}) + string(JSON SPI_MODE GET ${mode_list} ${k}) + + foreach(l RANGE 0 ${transfer_size_list_len}) + string(JSON SPI_TRANSFER_SIZE GET ${transfer_size_list} ${l}) + + foreach(m RANGE 0 ${miso_enabled_list_len}) + string(JSON MISO_ENABLED GET ${miso_enabled_list} ${m}) + + set(config ${COMBINED}_${BURNT_THREADS}_${MISO_ENABLED}_${SPI_MODE}_${SPI_TRANSFER_SIZE}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_benchmark) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${COMBINED} + -DBURNT_THREADS=${BURNT_THREADS} + -DMISO_ENABLED=${MISO_ENABLED} + -DSPI_MODE=${SPI_MODE} + -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_${SPI_TRANSFER_SIZE} + -O2 + -g + -Wno-reinterpret-alignment) + + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_multi_device/config.xscope b/tests/spi_slave_benchmark/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_multi_device/config.xscope rename to tests/spi_slave_benchmark/config.xscope diff --git a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc similarity index 94% rename from legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc rename to tests/spi_slave_benchmark/src/spi_slave_benchmark.xc index 6708438..cafc687 100644 --- a/legacy_tests/spi_slave_benchmark/src/spi_slave_benchmark.xc +++ b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc @@ -41,8 +41,10 @@ static void send_data_to_tester( unsigned data){ setup_data_port <: data; sync(setup_data_port); + setup_strobe_port <: 1; // Dp each twice so checker doesn't miss at higher clock frequencies of xcore.ai setup_strobe_port <: 1; setup_strobe_port <: 0; + setup_strobe_port <: 0; } static void broadcast_settings( @@ -59,7 +61,7 @@ static void broadcast_settings( set_mode_bits(mode, cpol, cpha); - // printf("Testing: %d %d\n", kbps, initial_clock_delay); + // printf("Testing: %d %d\n", kbps, initial_clock_delay); setup_strobe_port <: 0; @@ -94,6 +96,7 @@ void app(server interface spi_slave_callback_if spi_i, case SPI_TRANSFER_SIZE_32:bpt = 32;break; } + // Clock delay after SS in nanoseconds unsigned cd_max = 40000; unsigned cd_min = 0; unsigned cd = (cd_max + cd_min)/2; @@ -124,12 +127,14 @@ void app(server interface spi_slave_callback_if spi_i, 0xfefdfbf7, 0xefdfbf7f }; int error = 0; + // printf("broadcast_settings\n"); broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); unsigned rx_count = 0; unsigned tx_count = 0; unsigned rep_count = 0; + while(1){ select { case spi_i.master_requires_data() -> uint32_t r:{ @@ -174,6 +179,7 @@ void app(server interface spi_slave_callback_if spi_i, } case spi_i.master_ends_transaction():{ + error |= request_response(setup_strobe_port, setup_resp_port); if(finding_speed){ @@ -208,7 +214,7 @@ void app(server interface spi_slave_callback_if spi_i, if(next_cd == cd){ rep_count++; if(rep_count == 8){ - printf("%d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps); + printf("RESULT: %d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps); _Exit(1); } @@ -224,6 +230,8 @@ void app(server interface spi_slave_callback_if spi_i, } } + + // printf("broadcast_NEW settings\n"); broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); error = 0; diff --git a/tests/spi_slave_benchmark/test_params.json b/tests/spi_slave_benchmark/test_params.json new file mode 100644 index 0000000..5efebf2 --- /dev/null +++ b/tests/spi_slave_benchmark/test_params.json @@ -0,0 +1,24 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 3 + }, + { + "COMBINED": 1, + "BURNT_THREADS": 7 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 2 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 6 + } + ], + "MISO_ENABLED": [0, 1], + "MODE": [0, 1, 2, 3], + "TRANSFER_SIZE": [8, 32], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py new file mode 100644 index 0000000..2f6c230 --- /dev/null +++ b/tests/spi_slave_checker.py @@ -0,0 +1,144 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import Pyxsim as px +from functools import partial + +# We need to disable output buffering for this test to work on MacOS; this has +# no effect on Linux systems. Let's redefine print once to avoid putting the +# same argument everywhere. +print = partial(print, flush=True) + + +class SPISlaveChecker(px.SimThread): + """" + This simulator thread will act as SPI slave and check any transactions + caused by the master. + """ + def __init__(self, + sck_port: str, + mosi_port: str, + miso_port: str, + ss_port: str, + setup_strobe_port: str, + setup_data_port: str, + setup_resp_port: str) -> None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_port = ss_port + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + self._setup_resp_port = setup_resp_port + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self): + xsi: px.pyxsim.Xsi = self.xsi + xsi.drive_port_pins(self._ss_port,1) + + print("SPI Slave checker started") + + # some timing constants + xsi_tick_freq_hz = float(1e15) # pending merge of https://github.com/xmos/test_support/blob/develop/lib/python/Pyxsim/pyxsim.py#L246-L265 + nanosecond_ticks = xsi_tick_freq_hz / 1e9 + microsecond_ticks = xsi_tick_freq_hz / 1e6 + millisecond_ticks = xsi_tick_freq_hz / 1e3 + + while True: + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + initial_clock_delay = int(self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) * nanosecond_ticks) + print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") + + # drive initial values while slave starts up for the first time + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + + time_trigger = xsi.get_time() + time_trigger += 10 * microsecond_ticks + self.wait_until(time_trigger) + + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 0) + + time_trigger += initial_clock_delay + self.wait_until(time_trigger) + + tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + + clock_val = (expected_cpol^expected_cpha)&1 + bit_count = 0 + total_bit_count = 0 + byte_count = 0 + + half_clock = millisecond_ticks/(2*kbps) + error = 0 + + while total_bit_count < expected_num_bits: + # print (f"Drive bit {total_bit_count} @ {xsi.get_time()}") + #clock edge and drive data out + xsi.drive_port_pins(self._sck_port, clock_val) + xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) + tx_byte = tx_byte<<1 + + time_trigger += half_clock + self.wait_until(time_trigger) + + #clockedge and read data in + xsi.drive_port_pins(self._sck_port, 1-clock_val) + val = xsi.sample_port_pins(self._miso_port) + + time_trigger += half_clock + self.wait_until(time_trigger) + + rx_byte = (rx_byte<<1) + val + bit_count = bit_count + 1 + total_bit_count = total_bit_count + 1 + if bit_count == 8: + bit_count = 0 + if expected_miso_enabled: + if rx_byte != rx_data[byte_count]: + error = 1 + print(f"frx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") + rx_byte = 0 + byte_count = byte_count + 1 + if byte_count*8 < expected_num_bits: + tx_byte = tx_data[byte_count] + + #check the final few rx'd bits + if bit_count and expected_miso_enabled: + if rx_byte != rx_data[byte_count]>>(8-bit_count): + error = 1 + print(f"sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count}") + + time_trigger += half_clock + self.wait_until(time_trigger) + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + + self.wait_for_port_pins_change([self._setup_strobe_port]) + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + xsi.drive_port_pins(self._setup_resp_port, error) + self.wait_for_port_pins_change([self._setup_strobe_port]) diff --git a/tests/spi_slave_checker_intertransaction.py b/tests/spi_slave_checker_intertransaction.py new file mode 100644 index 0000000..e4dd0a1 --- /dev/null +++ b/tests/spi_slave_checker_intertransaction.py @@ -0,0 +1,143 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. + +import Pyxsim as px +from functools import partial + +# We need to disable output buffering for this test to work on MacOS; this has +# no effect on Linux systems. Let's redefine print once to avoid putting the +# same argument everywhere. +print = partial(print, flush=True) + + +class SPISlaveIntertransactionChecker(px.SimThread): + """" + This simulator thread will act as SPI slave and check any transactions + caused by the master. + """ + def __init__(self, + sck_port: str, + mosi_port: str, + miso_port: str, + ss_port: str, + setup_strobe_port: str, + setup_data_port: str, + setup_resp_port: str, + master_req_exit_port: str, + starting_delay: int, + delay_step: int) -> None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_port = ss_port + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + self._setup_resp_port = setup_resp_port + self._master_req_exit_port = master_req_exit_port + self._intertransaction_delay = starting_delay + self._delay_step = delay_step + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self): + xsi: px.pyxsim.Xsi = self.xsi + xsi.drive_port_pins(self._ss_port,1) + + print("SPI Slave checker started") + + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + initial_clock_delay = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) * 1000 + print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") + + # drive initial values while slave starts up for the first time + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_until(xsi.get_time() + 10000000) + error = 0 + + while True: + self.wait_until(xsi.get_time() + self._intertransaction_delay) + + error_check = xsi.sample_port_pins(self._setup_strobe_port) + if error == 1 or error_check == 1: + print(f"Delay is {self._intertransaction_delay/1000} ns") + print("Request exit on error") + xsi.drive_port_pins(self._master_req_exit_port, 1) + + if self._intertransaction_delay > 0: + self._intertransaction_delay = self._intertransaction_delay - self._delay_step + if self._intertransaction_delay < 0: + self._intertransaction_delay = 0 + else: + print(f"Delay is {self._intertransaction_delay}") + print("Request exit on success") + xsi.drive_port_pins(self._master_req_exit_port, 1) + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 0) + self.wait_until(xsi.get_time() + initial_clock_delay) + + tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + + clock_val = (expected_cpol^expected_cpha)&1 + bit_count = 0 + total_bit_count = 0 + byte_count = 0 + + half_clock = 1000000000/(2*kbps) + + while total_bit_count < expected_num_bits: + # print "Drive bit %d" % total_bit_count + #clock edge and drive data out + xsi.drive_port_pins(self._sck_port, clock_val) + xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) + tx_byte = tx_byte<<1 + self.wait_until(xsi.get_time() + half_clock) + + #clockedge and read data in + xsi.drive_port_pins(self._sck_port, 1-clock_val) + val = xsi.sample_port_pins(self._miso_port) + self.wait_until(xsi.get_time() + half_clock) + rx_byte = (rx_byte<<1) + val + bit_count = bit_count + 1 + total_bit_count = total_bit_count + 1 + if bit_count == 8: + bit_count = 0 + if expected_miso_enabled: + if rx_byte != rx_data[byte_count]: + error = 1 + # print(f"frx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") + rx_byte = 0 + byte_count = byte_count + 1 + if byte_count*8 < expected_num_bits: + tx_byte = tx_data[byte_count] + + #check the final few rx'd bits + if bit_count and expected_miso_enabled: + if rx_byte != rx_data[byte_count]>>(8-bit_count): + error = 1 + # print(f"sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count}") + self.wait_until(xsi.get_time() + half_clock) + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) diff --git a/tests/spi_slave_rx_tx/CMakeLists.txt b/tests/spi_slave_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..41251b7 --- /dev/null +++ b/tests/spi_slave_rx_tx/CMakeLists.txt @@ -0,0 +1,81 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mode_list GET ${params_json} MODE) +string(JSON transfer_size_list GET ${params_json} TRANSFER_SIZE) +string(JSON miso_enabled_list GET ${params_json} MISO_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mode_list_len LENGTH ${mode_list}) +string(JSON transfer_size_list_len LENGTH ${transfer_size_list}) +string(JSON miso_enabled_list_len LENGTH ${miso_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mode_list_len "${mode_list_len} - 1") +math(EXPR transfer_size_list_len "${transfer_size_list_len} - 1") +math(EXPR miso_enabled_list_len "${miso_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(k RANGE 0 ${mode_list_len}) + string(JSON SPI_MODE GET ${mode_list} ${k}) + + foreach(l RANGE 0 ${transfer_size_list_len}) + string(JSON SPI_TRANSFER_SIZE GET ${transfer_size_list} ${l}) + + foreach(m RANGE 0 ${miso_enabled_list_len}) + string(JSON MISO_ENABLED GET ${miso_enabled_list} ${m}) + + set(config ${COMBINED}_${BURNT_THREADS}_${MISO_ENABLED}_${SPI_MODE}_${SPI_TRANSFER_SIZE}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_rx_tx) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${COMBINED} + -DBURNT_THREADS=${BURNT_THREADS} + -DMISO_ENABLED=${MISO_ENABLED} + -DSPI_MODE=${SPI_MODE} + -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_${SPI_TRANSFER_SIZE} + -O2 + -g + -Wno-reinterpret-alignment) + + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_rx_tx/config.xscope b/tests/spi_slave_rx_tx/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_rx_tx/config.xscope rename to tests/spi_slave_rx_tx/config.xscope diff --git a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc similarity index 86% rename from legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc rename to tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc index b10866b..99ae2b3 100644 --- a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc +++ b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc @@ -38,6 +38,9 @@ static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { #error Invalid transfer size given #endif +void flush_print(void){ + delay_microseconds(1000); +} static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ switch(mode){ @@ -55,6 +58,8 @@ static void send_data_to_tester( setup_data_port <: data; sync(setup_data_port); setup_strobe_port <: 1; + setup_strobe_port <: 1; + setup_strobe_port <: 0; setup_strobe_port <: 0; } @@ -87,12 +92,17 @@ static int request_response( in port setup_resp_port ){ int r; + setup_strobe_port <: 1; // Twice to make sure we are not too fast setup_strobe_port <: 1; setup_strobe_port <: 0; + setup_strobe_port <: 0; setup_resp_port :> r; return r; } + +// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits + [[combinable]] void app(server interface spi_slave_callback_if spi_i, int mosi_enabled, int miso_enabled){ @@ -108,6 +118,9 @@ void app(server interface spi_slave_callback_if spi_i, unsigned num_bits = NUMBER_OF_TEST_BYTES*8; //First check a multi byte transfer + printf("Send initial settings\n"); + // printf("%u\n", num_bits); + broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); @@ -116,6 +129,7 @@ void app(server interface spi_slave_callback_if spi_i, while(1){ select { case spi_i.master_requires_data() -> uint32_t r:{ + // printf("master_requires_data\n"); if(tx_byte_no < NUMBER_OF_TEST_BYTES){ switch(tt){ case SPI_TRANSFER_SIZE_8: @@ -133,16 +147,19 @@ void app(server interface spi_slave_callback_if spi_i, } if(!miso_enabled){ printf("Error: master cannot require data when miso is not enabled\n"); + flush_print(); _Exit(1); } break; } case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ + // printf("master_supplied_data\n"); for(unsigned i=0; i> (valid_bits - 8))&0xff; if(rx_data[rx_byte_no] != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", rx_data[rx_byte_no], d, num_bits); + flush_print(); _Exit(1); } rx_byte_no++; @@ -160,6 +177,7 @@ void app(server interface spi_slave_callback_if spi_i, if(datum != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", d, datum, num_bits); + flush_print(); _Exit(1); } } @@ -167,19 +185,31 @@ void app(server interface spi_slave_callback_if spi_i, } case spi_i.master_ends_transaction():{ + // printf("master_ends_transaction\n"); //Then check all sub word transfers - if(num_bits == NUMBER_OF_TEST_BYTES*8) + if(num_bits == NUMBER_OF_TEST_BYTES*8){ num_bits = 0; + } + if(num_bits == bpt){ + printf("Test completed\n"); + flush_print(); + _Exit(0); + } num_bits++; int r = request_response(setup_strobe_port, setup_resp_port); + if(r){ printf("Error: Master Rx error\n"); + flush_print(); _Exit(1); - } - if(num_bits > bpt) + if(num_bits > bpt){ + printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); + flush_print(); _Exit(1); + } + broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); diff --git a/tests/spi_slave_rx_tx/test_params.json b/tests/spi_slave_rx_tx/test_params.json new file mode 100644 index 0000000..5efebf2 --- /dev/null +++ b/tests/spi_slave_rx_tx/test_params.json @@ -0,0 +1,24 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 3 + }, + { + "COMBINED": 1, + "BURNT_THREADS": 7 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 2 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 6 + } + ], + "MISO_ENABLED": [0, 1], + "MODE": [0, 1, 2, 3], + "TRANSFER_SIZE": [8, 32], + "arch": ["xs2", "xs3"] +} diff --git a/tests/test_master_async_multi_client.py b/tests/test_master_async_multi_client.py new file mode 100644 index 0000000..9b3287f --- /dev/null +++ b/tests/test_master_async_multi_client.py @@ -0,0 +1,55 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +import os +from helpers import generate_tests_from_json, create_if_needed + + +appname = "spi_master_async_multi_client" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # tester = tester, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_multi_client(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) + diff --git a/tests/test_master_async_multi_device.py b/tests/test_master_async_multi_device.py new file mode 100644 index 0000000..c7906d8 --- /dev/null +++ b/tests/test_master_async_multi_device.py @@ -0,0 +1,54 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +import os +from helpers import generate_tests_from_json, create_if_needed + + +appname = "spi_master_async_multi_device" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # tester = tester, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_multi_device(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_async_rx_tx.py b/tests/test_master_async_rx_tx.py new file mode 100644 index 0000000..89f921c --- /dev/null +++ b/tests/test_master_async_rx_tx.py @@ -0,0 +1,56 @@ +# Copyright 2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed +from itertools import zip_longest + +appname = "spi_master_async_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, transfer_width, speed_tests, spi_mode, arch, id): + + id_string = f"{combined}_{burnt}_{mosi_enabled}_{speed_tests}_{transfer_width}_{spi_mode}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print() + print(f"{'Expected':<40}Actual") + for e, o in zip_longest(expected, output, fillvalue = ''): + print(f"{str(e):<40}{str(o)}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_rx_tx(capfd, params, request): + # print("***", params) + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_sync_benchmark.py b/tests/test_master_sync_benchmark.py new file mode 100644 index 0000000..7a482ee --- /dev/null +++ b/tests/test_master_sync_benchmark.py @@ -0,0 +1,74 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. + +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, write_csv_row, create_if_needed, sort_csv_table + +appname = "spi_master_sync_benchmark" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" +test_results_file = Path.cwd()/f"logs/{appname}.txt" + +# This logs to a csv file since we don't want to do checking - it's just benchmark results +class Resultlogger(Pyxsim.testers.ComparisonTester): + def __init__(self, id): + # Turn ID back into a dict + self.result = dict(item.split('=') for item in id.split(', ')) + + def run(self, output): + print(output) + ignore_list = ["SPI Master checker"] + result_8b = None + result_32b = None + for line in output: + if any(skip in line for skip in ignore_list): + continue + if result_8b is None: + result_8b = line + continue + if result_32b is None: + result_32b = line + self.result["result_8b"] = result_8b + self.result["result_32b"] = result_32b + assert result_8b and result_32b, "No timing results found" + + print(self.result) + write_csv_row(test_results_file, self.result) + +@pytest.fixture(scope="module", autouse=True) +def remove_test_results(): + create_if_needed(test_results_file.parent) + if test_results_file.exists(): + test_results_file.unlink() + yield + # Post test cleanup + sort_csv_table(test_results_file) + +def do_benchmark_sync(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists(), f"Binary file {binary} not present - please pre-build" + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + tester = Resultlogger(id) + + Pyxsim.run_on_simulator_( + binary, + tester = tester, + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_benchmark(capfd, params, request): + do_benchmark_sync(capfd, *params, request.node.callspec.id) \ No newline at end of file diff --git a/tests/test_master_sync_clock_port_sharing.py b/tests/test_master_sync_clock_port_sharing.py new file mode 100644 index 0000000..6f0f0eb --- /dev/null +++ b/tests/test_master_sync_clock_port_sharing.py @@ -0,0 +1,51 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker + + +appname = "spi_master_sync_clock_port_sharing" + +def do_test(capfd, combined, id): + id_string = f"{combined}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # tester = tester, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("combined", ["COMBINED", "NOT_COMBINED"], ids=["COMBINED=1", "COMBINED=0"]) +def test_master_sync_clock_port_sharing(capfd, combined, request): + do_test(capfd, combined, request.node.callspec.id) diff --git a/tests/test_master_sync_multi_client.py b/tests/test_master_sync_multi_client.py new file mode 100644 index 0000000..ae4e8c5 --- /dev/null +++ b/tests/test_master_sync_multi_client.py @@ -0,0 +1,54 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +import os +from helpers import generate_tests_from_json, create_if_needed + + +appname = "spi_master_sync_multi_client" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # tester = tester, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_rx_tx(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_sync_multi_device.py b/tests/test_master_sync_multi_device.py new file mode 100644 index 0000000..fb4e77f --- /dev/null +++ b/tests/test_master_sync_multi_device.py @@ -0,0 +1,53 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed + + +appname = "spi_master_sync_multi_device" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # tester = tester, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_rx_tx(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_sync_rx_tx.py b/tests/test_master_sync_rx_tx.py new file mode 100644 index 0000000..201223c --- /dev/null +++ b/tests/test_master_sync_rx_tx.py @@ -0,0 +1,51 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed + + +appname = "spi_master_sync_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + ["tile[0]:XS1_PORT_1B"], + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {output}") + + assert tester.run(output) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_rx_tx(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) \ No newline at end of file diff --git a/tests/test_slave_benchmark.py b/tests/test_slave_benchmark.py new file mode 100644 index 0000000..21203ea --- /dev/null +++ b/tests/test_slave_benchmark.py @@ -0,0 +1,78 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, write_csv_row, create_if_needed, sort_csv_table + +appname = "spi_slave_benchmark" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" +test_results_file = Path.cwd()/f"logs/{appname}.txt" + +# This logs to a csv file since we don't want to do checking - it's just benchmark results +class Resultlogger(Pyxsim.testers.ComparisonTester): + def __init__(self, id): + # Turn ID back into a dict + self.result = dict(item.split('=') for item in id.split(', ')) + + + def run(self, output): + # DUT outputs RESULT: SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps + + for line in output: + print(line) + ignore_list = ["SPI Slave checker", "Drive bit"] + result_clock_delay_ns = None + result_kbps = None + for line in output: + if any(skip in line for skip in ignore_list): + continue + if "RESULT:" in line: + result_clock_delay_ns = line.split(' ')[-1] + result_kbps = line.split(' ')[-2] + self.result["CLK_DLY_NS"] = result_clock_delay_ns + self.result["KBPS"] = result_kbps + + assert result_clock_delay_ns and result_kbps, "No timing results found" + + write_csv_row(test_results_file, self.result) + +@pytest.fixture(scope="module", autouse=True) +def remove_test_results(): + create_if_needed(test_results_file.parent) + if test_results_file.exists(): + test_results_file.unlink() + yield + # Post test cleanup + sort_csv_table(test_results_file) + +def do_benchmark_slave(capfd, combined, burnt, miso_enabled, spi_mode, transfer_size, arch, id): + id_string = f"{combined}_{burnt}_{miso_enabled}_{spi_mode}_{transfer_size}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + tester = Resultlogger(id) + + Pyxsim.run_on_simulator_( + binary, + tester = tester, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd + ) + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_benchmark(capfd, params, request): + do_benchmark_slave(capfd, *params, request.node.callspec.id) + diff --git a/tests/test_slave_rx_tx.py b/tests/test_slave_rx_tx.py new file mode 100644 index 0000000..4183e09 --- /dev/null +++ b/tests/test_slave_rx_tx.py @@ -0,0 +1,53 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, create_if_needed + +appname = "spi_slave_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_slave_rx_tx(capfd, combined, burnt, miso_enabled, spi_mode, transfer_size, arch, id): + id_string = f"{combined}_{burnt}_{miso_enabled}_{spi_mode}_{transfer_size}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + with open(filepath/f"expected/slave.expect") as exp: + expected = exp.read().splitlines() + expected = expected[:3 + transfer_size] + expected[-1:] + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = True, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd + ) + + out, err = capfd.readouterr() + output = out.split('\n')[:-1] + + with capfd.disabled(): + print(f"expected: {expected}") + print(f"Actual output: {out}") + + assert tester.run(output) + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_rx_tx(capfd, params, request): + do_slave_rx_tx(capfd, *params, request.node.callspec.id) From 08b8413f35c2a69433ffd525d2dae9f416ff0314 Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 15 Jul 2025 11:50:29 +0100 Subject: [PATCH 21/57] Fix incorrect clock polarity in SPI sync Fix spi async mode 0 Fix 32b async (modes 0 and 3 only) Remove modes 2,3 from async rx tx testing Remove extra simargs --- lib_spi/api/spi.h | 8 ++-- lib_spi/src/spi_async.xc | 37 ++++++++++++------- lib_spi/src/spi_sync.xc | 4 +- tests/CMakeLists.txt | 1 + .../src/spi_master_async_rx_tx.xc | 6 ++- tests/spi_master_async_rx_tx/test_params.json | 2 +- tests/spi_master_tester_common/common.h | 4 +- tests/test_master_async_multi_client.py | 1 - tests/test_master_async_multi_device.py | 3 +- tests/test_master_async_rx_tx.py | 2 +- tests/test_master_sync_clock_port_sharing.py | 1 - tests/test_master_sync_multi_client.py | 1 - tests/test_master_sync_multi_device.py | 1 - tests/test_master_sync_rx_tx.py | 1 + 14 files changed, 41 insertions(+), 31 deletions(-) diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 449105b..720c9c5 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -27,10 +27,10 @@ /** This type indicates what mode an SPI component should use */ typedef enum spi_mode_t { - SPI_MODE_0, /**< SPI Mode 0 - Polarity = 0, Clock Edge = 1 */ - SPI_MODE_1, /**< SPI Mode 1 - Polarity = 0, Clock Edge = 0 */ - SPI_MODE_2, /**< SPI Mode 2 - Polarity = 1, Clock Edge = 0 */ - SPI_MODE_3, /**< SPI Mode 3 - Polarity = 1, Clock Edge = 1 */ + SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Clock Edge = 0 */ + SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Clock Edge = 1 */ + SPI_MODE_2 = 2, /**< SPI Mode 2 - Polarity = 1, Clock Edge = 0 */ + SPI_MODE_3 = 3, /**< SPI Mode 3 - Polarity = 1, Clock Edge = 1 */ } spi_mode_t; diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc index aa38259..dfecf83 100644 --- a/lib_spi/src/spi_async.xc +++ b/lib_spi/src/spi_async.xc @@ -5,6 +5,7 @@ #include #include +#include #include "spi.h" typedef struct { @@ -25,10 +26,11 @@ static void transfer8_async( out buffered port:32 ?mosi, in buffered port:32 miso, uint8_t data){ + // printf("0x%x\n", data); if(!isnull(mosi)) { clearbuf(mosi); - mosi <: (bitrev(data)>>24); + mosi <: (bitrev(data)>>24); // This outputs LSb first so reverse. } clearbuf(miso); //TODO remove- if possible @@ -44,7 +46,7 @@ static void transfer32_async( if(!isnull(mosi)) { clearbuf(mosi); - mosi <: bitrev(data); + mosi <: bitrev(byterev(data)); } clearbuf(miso); //TODO remove - if possible @@ -99,7 +101,7 @@ static void setup_new_transaction( sync(p_ss[currently_selected_device]); } -static void init_init_transfer_array_8( +static void init_transfer_array_8( out buffered port:32 sclk, out buffered port:32 ?mosi, in buffered port:32 miso, @@ -111,14 +113,16 @@ static void init_init_transfer_array_8( asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - if((active_mode == SPI_MODE_1 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ + // In modes 0 and 2 we need to present the first data bit BEFORE we clock + if((active_mode == SPI_MODE_0 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ unsigned b = data>>7; asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); partout(mosi, 1, b); + sync(mosi); asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); data = data<<1; //This is shifted up as the MSB is already on this pin } - transfer8_async(sclk, mosi, miso, data); + transfer8_async(sclk, mosi, miso, data); } static void first_transfer_array_32( @@ -133,10 +137,12 @@ static void first_transfer_array_32( asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(32)); asm volatile ("settw res[%0], %1"::"r"(miso), "r"(32)); - if((active_mode == SPI_MODE_1 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ + // In modes 0 and 2 we need to present the first data bit BEFORE we clock + if((active_mode == SPI_MODE_0 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ unsigned b = bitrev(data); asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); partout(mosi, 1, b); + sync(mosi); asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); data = data<<1; //This is shifted up as the MSB is already on this pin } @@ -190,8 +196,9 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], start_clock(cb0); - if(!isnull(mosi)) - mosi <: 0xffffffff; + if(!isnull(mosi)){ + partout(mosi, 1, 0); + } clearbuf(miso); @@ -280,7 +287,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], buffer_rx = move(tr_buffer[index].buffer_rx); buffer_transfer_width = tr_buffer[index].buffer_transfer_width; if(buffer_transfer_width == 8){ - init_init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); + init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); } else { first_transfer_array_32(sclk, mosi, miso, active_mode, cb1, buffer_tx[0]); } @@ -314,7 +321,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], i[x].transfer_complete(); } else { buffer_transfer_width = 8; - init_init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); + init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); } } @@ -361,8 +368,10 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], if((current_index*sizeof(uint8_t)) == buffer_nbytes){ i[active_client].transfer_complete(); } else { - transfer8_async(sclk, mosi, miso, - ((uint8_t*movable)buffer_tx)[current_index]); + // We need to handle the mode 0 data before clock so now using this + init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[current_index]); + // transfer8_async(sclk, mosi, miso, + // ((uint8_t*movable)buffer_tx)[current_index]); } } else { data = bitrev(data); @@ -371,7 +380,9 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], if((current_index*sizeof(uint32_t)) == buffer_nbytes){ i[active_client].transfer_complete(); } else { - transfer32_async(sclk, mosi, miso, buffer_tx[current_index]); + // We need to handle the mode 0 data before clock so now using this + first_transfer_array_32(sclk, mosi, miso, active_mode, cb1, buffer_tx[current_index]); + // transfer32_async(sclk, mosi, miso, buffer_tx[current_index]); } } break; diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc index e34a93a..dd50c58 100644 --- a/lib_spi/src/spi_sync.xc +++ b/lib_spi/src/spi_sync.xc @@ -225,8 +225,8 @@ static uint32_t transfer32_sync_one_clkblk( static void get_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; + case SPI_MODE_0:cpol = 0; cpha= 0; break; + case SPI_MODE_1:cpol = 0; cpha= 1; break; case SPI_MODE_2:cpol = 1; cpha= 0; break; case SPI_MODE_3:cpol = 1; cpha= 1; break; } diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 5d41217..34cda08 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -11,3 +11,4 @@ add_subdirectory(spi_slave_benchmark) add_subdirectory(spi_slave_rx_tx) add_subdirectory(spi_master_async_rx_tx) add_subdirectory(spi_master_async_multi_client) +add_subdirectory(spi_master_async_multi_device) diff --git a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index a528279..eddbeb3 100644 --- a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -30,7 +30,6 @@ void flush_print(void){ static void inc_state(unsigned &count, spi_mode_t &mode, unsigned &speed_index, t_transfer_width &transfer_width){ - // printf("count: %u, speed_idx: %u (%u), mode: %d width: %d\n", count, speed_index, SPEED_TESTS, mode, transfer_width * 24 + 8); if(count == 16){ count = 0; if(++speed_index == SPEED_TESTS){ @@ -45,12 +44,13 @@ static void inc_state(unsigned &count, spi_mode_t &mode, count+=4; } } + // printf("count: %u, speed_idx: %u (%u), mode: %d width: %d\n", count, speed_index, SPEED_TESTS, mode, transfer_width * 24 + 8); } [[combinable]] void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_enabled){ // if testing just one speed, do fastest (idx 0) - unsigned speed_lut[3] = {2000, 200, 500}; + unsigned speed_lut[3] = {1000, 200, 500}; uint8_t tx8[NUMBER_OF_TEST_BYTES]; uint8_t rx8[NUMBER_OF_TEST_BYTES]; @@ -141,6 +141,8 @@ void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_ //setup the next spi_i.begin_transaction(device_id, speed_in_kbps, mode); if(transfer_width == SPI_TRANSFER_WIDTH_8){ + // for(int i = 0; i < count; i++) printf("tx 0x%x\n", tx_ptr8[i]); + spi_i.init_transfer_array_8(move(rx_ptr8), move(tx_ptr8), count); } else { spi_i.init_transfer_array_32(move(rx_ptr32), move(tx_ptr32), count/sizeof(uint32_t)); diff --git a/tests/spi_master_async_rx_tx/test_params.json b/tests/spi_master_async_rx_tx/test_params.json index fc409ee..e8ca317 100644 --- a/tests/spi_master_async_rx_tx/test_params.json +++ b/tests/spi_master_async_rx_tx/test_params.json @@ -20,6 +20,6 @@ "MOSI_ENABLED": [0, 1], "TRANSFER_WIDTH": [8, 32], "SPEED_TESTS": [1], - "MODE": [0, 1, 2, 3], + "MODE": [0, 3], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_tester_common/common.h b/tests/spi_master_tester_common/common.h index 9ceb4b1..608b9f1 100644 --- a/tests/spi_master_tester_common/common.h +++ b/tests/spi_master_tester_common/common.h @@ -5,8 +5,8 @@ static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; + case SPI_MODE_0:cpol = 0; cpha= 0; break; + case SPI_MODE_1:cpol = 0; cpha= 1; break; case SPI_MODE_2:cpol = 1; cpha= 0; break; case SPI_MODE_3:cpol = 1; cpha= 1; break; } diff --git a/tests/test_master_async_multi_client.py b/tests/test_master_async_multi_client.py index 9b3287f..b8f813d 100644 --- a/tests/test_master_async_multi_client.py +++ b/tests/test_master_async_multi_client.py @@ -33,7 +33,6 @@ def do_test(capfd, combined, burnt, mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # tester = tester, #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], diff --git a/tests/test_master_async_multi_device.py b/tests/test_master_async_multi_device.py index c7906d8..1682241 100644 --- a/tests/test_master_async_multi_device.py +++ b/tests/test_master_async_multi_device.py @@ -33,8 +33,7 @@ def do_test(capfd, combined, burnt, mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # tester = tester, - #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + # simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) diff --git a/tests/test_master_async_rx_tx.py b/tests/test_master_async_rx_tx.py index 89f921c..cf1eecb 100644 --- a/tests/test_master_async_rx_tx.py +++ b/tests/test_master_async_rx_tx.py @@ -33,7 +33,7 @@ def do_test(capfd, combined, burnt, mosi_enabled, transfer_width, speed_tests, s Pyxsim.run_on_simulator_( binary, - simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + #simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) diff --git a/tests/test_master_sync_clock_port_sharing.py b/tests/test_master_sync_clock_port_sharing.py index 6f0f0eb..4ad1d0a 100644 --- a/tests/test_master_sync_clock_port_sharing.py +++ b/tests/test_master_sync_clock_port_sharing.py @@ -30,7 +30,6 @@ def do_test(capfd, combined, id): Pyxsim.run_on_simulator_( binary, - # tester = tester, #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], diff --git a/tests/test_master_sync_multi_client.py b/tests/test_master_sync_multi_client.py index ae4e8c5..f8adf29 100644 --- a/tests/test_master_sync_multi_client.py +++ b/tests/test_master_sync_multi_client.py @@ -33,7 +33,6 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # tester = tester, #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], diff --git a/tests/test_master_sync_multi_device.py b/tests/test_master_sync_multi_device.py index fb4e77f..5070eed 100644 --- a/tests/test_master_sync_multi_device.py +++ b/tests/test_master_sync_multi_device.py @@ -32,7 +32,6 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # tester = tester, #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], diff --git a/tests/test_master_sync_rx_tx.py b/tests/test_master_sync_rx_tx.py index 201223c..516ec30 100644 --- a/tests/test_master_sync_rx_tx.py +++ b/tests/test_master_sync_rx_tx.py @@ -32,6 +32,7 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, + #simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) From 4b49b2440bf925dc0184132e25e72292987f75c5 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 16 Jul 2025 11:11:44 +0100 Subject: [PATCH 22/57] Disable master async tests for now --- tests/test_master_async_multi_client.py | 3 +++ tests/test_master_async_multi_device.py | 3 +++ tests/test_master_async_rx_tx.py | 3 +++ 3 files changed, 9 insertions(+) diff --git a/tests/test_master_async_multi_client.py b/tests/test_master_async_multi_client.py index b8f813d..e56a428 100644 --- a/tests/test_master_async_multi_client.py +++ b/tests/test_master_async_multi_client.py @@ -12,6 +12,9 @@ test_params_file = Path(__file__).parent / f"{appname}/test_params.json" def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + # Test disabled until we review SPI async + pytest.xfail() + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" diff --git a/tests/test_master_async_multi_device.py b/tests/test_master_async_multi_device.py index 1682241..51ca7b8 100644 --- a/tests/test_master_async_multi_device.py +++ b/tests/test_master_async_multi_device.py @@ -12,6 +12,9 @@ test_params_file = Path(__file__).parent / f"{appname}/test_params.json" def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + # Test disabled until we review SPI async + pytest.xfail() + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" diff --git a/tests/test_master_async_rx_tx.py b/tests/test_master_async_rx_tx.py index cf1eecb..dc28fa3 100644 --- a/tests/test_master_async_rx_tx.py +++ b/tests/test_master_async_rx_tx.py @@ -12,6 +12,9 @@ def do_test(capfd, combined, burnt, mosi_enabled, transfer_width, speed_tests, spi_mode, arch, id): + # Test disabled until we review SPI async + pytest.xfail() + id_string = f"{combined}_{burnt}_{mosi_enabled}_{speed_tests}_{transfer_width}_{spi_mode}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" From cdd885690881a164bf095edd50eaf7787a74248b Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 16 Jul 2025 15:00:10 +0100 Subject: [PATCH 23/57] Initial sync test pass rx/tx Fix SPI sync benchmark --- lib_spi/{api => src}/spi_fwk.h | 0 lib_spi/src/spi_master_fwk.xc | 85 ----------- lib_spi/src/spi_master_sync_fwk.xc | 137 ++++++++++++++++++ tests/spi_master_checker.py | 24 ++- .../spi_master_sync_benchmark/CMakeLists.txt | 16 +- .../src/spi_master_sync_benchmark.xc | 106 ++++++-------- .../test_params.json | 2 +- tests/spi_master_sync_rx_tx/CMakeLists.txt | 16 +- .../src/spi_master_sync_rx_tx.xc | 35 ++--- tests/spi_master_sync_rx_tx/test_params.json | 2 +- tests/test_master_sync_benchmark.py | 21 +-- tests/test_master_sync_rx_tx.py | 15 +- 12 files changed, 250 insertions(+), 209 deletions(-) rename lib_spi/{api => src}/spi_fwk.h (100%) delete mode 100644 lib_spi/src/spi_master_fwk.xc create mode 100644 lib_spi/src/spi_master_sync_fwk.xc diff --git a/lib_spi/api/spi_fwk.h b/lib_spi/src/spi_fwk.h similarity index 100% rename from lib_spi/api/spi_fwk.h rename to lib_spi/src/spi_fwk.h diff --git a/lib_spi/src/spi_master_fwk.xc b/lib_spi/src/spi_master_fwk.xc deleted file mode 100644 index 50939f2..0000000 --- a/lib_spi/src/spi_master_fwk.xc +++ /dev/null @@ -1,85 +0,0 @@ -// Copyright 2015-2025 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include - -#include "spi.h" -extern "C"{ - #include "spi_fwk.h" -} - -#pragma unsafe arrays -[[distributable]] -void spi_master_fwk(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss, // Note only one SS port supported - individual bits in port may be used however - static const size_t num_slaves, - clock ?cb){ - - if(isnull(cb)){ - printstrln("Must supply clockblock to this version of SPI"); - // We will hit an exception shortly after this if NULL - } - - spi_master_t spi_ctx; - spi_master_device_t spi_dev; - unsafe{ - spi_master_init(&spi_ctx, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); - } - - int accepting_new_transactions = 1; - unsigned ss_port_bit[num_clients] = {0}; - - while(1){ - select { - case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode):{ - accepting_new_transactions = 0; - - unsigned div = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz); - unsigned cpol = mode >> 1; - unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev, &spi_ctx, - ss_port_bit[x], - cpol, cpha, - spi_master_source_clock_ref, - div, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); - spi_master_start_transaction(&spi_dev); - break; - } - - case i[int x].end_transaction(unsigned ss_deassert_time):{ - spi_master_end_transaction(&spi_dev); - // Unlock the transaction - accepting_new_transactions = 1; - break; - } - - case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 1); - break; - } - - case i[int x].transfer32(uint32_t data) -> uint32_t r:{ - uint32_t read_val; - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); - r = byterev(read_val); - break; - } - - case i[int x].set_ss_port_bit(unsigned port_bit):{ - ss_port_bit[x] = port_bit; - break; - } - } - } - -} - diff --git a/lib_spi/src/spi_master_sync_fwk.xc b/lib_spi/src/spi_master_sync_fwk.xc new file mode 100644 index 0000000..d6961e8 --- /dev/null +++ b/lib_spi/src/spi_master_sync_fwk.xc @@ -0,0 +1,137 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include + +//TODO DEL these +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + +// Optional function to determine the actual set speed for particular clock settings. +unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ + unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 + / 2 + / (divider == 0 ? 1 : ((divider) * 2)); + + return actual_speed_khz; +} + + +// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate +// effectively using a ceil type function +void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz){ + // Clock blocks divide at / (2 * div) for div > 0 or / 1 where div == 0. Maximum clock block division is 255 * 2 = 510 + // Due to SPI needing to output each bit twice (to allow control over clock edges) the overal SPI clock rate is / 2 further + // to the divider. + // Steps get very granular as div -> 1 so use ref clock below 2MHz and core clock above 2MHz + // The minimum SPI clock speed is therefore 100e6 / (255 * 2 * 2) = 98kHz on the ref clock + // The minimum SPI clock speed at 800MHz core clock (typical highest) is 800e6 / (255 * 2 * 2) = 784kHz + if(speed_in_khz > 2000){ + *source_clock = spi_master_source_clock_xcore; + *divider = (PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } else { + *source_clock = spi_master_source_clock_ref; + *divider = (PLATFORM_REFERENCE_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } + + // Avoid overflow of the 8b divider reg. + if(*divider > 255){ + *divider = 255; + } +} + +#pragma unsafe arrays +[[distributable]] +void spi_master_fwk(server interface spi_master_if i[num_clients], + static const size_t num_clients, + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + out port p_ss, // Note only one SS port supported - individual bits in port may be used however + static const size_t num_slaves, + clock ?cb){ + + if(isnull(cb)){ + printstrln("Must supply clockblock to this version of SPI"); + // We will hit an exception shortly after this if NULL + } + + spi_master_t spi_ctx; + spi_master_device_t spi_dev; + unsafe{ + spi_master_init(&spi_ctx, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + } + + int accepting_new_transactions = 1; + unsigned ss_port_bit[num_clients] = {0}; + + while(1){ + select { + case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode):{ + // printf("begin_transaction: client %d\n", x); + accepting_new_transactions = 0; + + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + + // unsigned actual_speed_khz = spi_master_get_actual_clock_rate(source_clock, divider); + // printf("Actual speed_in_khz: %u div(%u) clock: %s (%u)MHz\n", + // actual_speed_khz, + // divider, + // ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), + // ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); + + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + spi_master_device_init(&spi_dev, &spi_ctx, + ss_port_bit[x], + cpol, cpha, + source_clock, + divider, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); + + spi_ctx.current_device = 0xffffffff;// This is needed to force mode and speed in spi_master_start_transaction() + // Otherwise fwk_spi sees the next transaction as the same settings as last + spi_master_start_transaction(&spi_dev); + break; + } + + case i[int x].end_transaction(unsigned ss_deassert_time):{ + spi_master_end_transaction(&spi_dev); + // Unlock the transaction + accepting_new_transactions = 1; + break; + } + + case i[int x].transfer8(uint8_t data)-> uint8_t r :{ + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 1); + break; + } + + case i[int x].transfer32(uint32_t data) -> uint32_t r:{ + uint32_t read_val; + data = byterev(data); + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); + r = byterev(read_val); + break; + } + + case i[int x].set_ss_port_bit(unsigned port_bit):{ + ss_port_bit[x] = port_bit; + break; + } + } + } + +} + diff --git a/tests/spi_master_checker.py b/tests/spi_master_checker.py index 1834f7e..b910368 100644 --- a/tests/spi_master_checker.py +++ b/tests/spi_master_checker.py @@ -40,6 +40,12 @@ def get_setup_data(self, def run(self) -> None: xsi: px.pyxsim.Xsi = self.xsi + # some timing constants + xsi_tick_freq_hz = float(1e15) # pending merge of https://github.com/xmos/test_support/blob/develop/lib/python/Pyxsim/pyxsim.py#L246-L265 + millisecond_ticks = xsi_tick_freq_hz / 1e3 + microsecond_ticks = xsi_tick_freq_hz / 1e6 + nanosecond_ticks = xsi_tick_freq_hz / 1e9 + sck_value = xsi.sample_port_pins(self._sck_port) ss_value = [] @@ -47,6 +53,7 @@ def run(self) -> None: ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) print("SPI Master checker started") + while True: #first do the setup rx strobe_val = xsi.sample_port_pins(self._setup_strobe_port) @@ -61,8 +68,9 @@ def run(self) -> None: expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + # print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} mosi {expected_miso_enabled} miso {expected_miso_enabled} expected_device_id {expected_device_id} expected_interframe_space {expected_interframe_space} expected_num_bytes {expected_num_bytes}") - clock_half_period = 1000000000/(expected_frequency_in_khz*2) + clock_half_period = millisecond_ticks / (expected_frequency_in_khz*2) all_ss_deserted = True for i in range(len(self._ss_ports)): @@ -97,8 +105,10 @@ def run(self) -> None: rx_byte = 0 tx_byte = tx_data[0] # check the polarity - if xsi.sample_port_pins(self._sck_port) != expected_cpol: - print("ERROR: unexpected clock polarity at the slave select point") + + sampled_cpol = xsi.sample_port_pins(self._sck_port) + if sampled_cpol != expected_cpol: + print(f"ERROR: unexpected clock polarity {sampled_cpol} (expected {expected_cpol}) at the slave select point, time: {xsi.get_time() / nanosecond_ticks}ns") error = True clock_edge_number = 0 @@ -129,10 +139,9 @@ def run(self) -> None: clock_event_time = xsi.get_time() measured_time_elapsed = clock_event_time - last_clock_event_time if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : - print("ERROR: Clock half period less than allowed for given SCLK frequency" ) - print(f"{measured_time_elapsed} {clock_half_period}") + print(f"ERROR: Clock half period less than allowed for given SCLK frequency, measured_time_elapsed: {measured_time_elapsed/nanosecond_ticks}ns clock_half_period:{clock_half_period/nanosecond_ticks}ns") error = True - last_clock_event_time =clock_event_time + last_clock_event_time = clock_event_time #check that the clock edges never go faster than the expected clock rate if ss_value == 0: @@ -161,8 +170,9 @@ def run(self) -> None: expected_rx_byte = rx_data[(rx_bit_counter//8) - 1] #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) if expected_rx_byte != rx_byte: - print(f"ERROR: slave recieved incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x}") + print(f"ERROR: slave recieved incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x} at time: {xsi.get_time() / nanosecond_ticks}ns") error = True + # print(f"Checker got byte: {rx_byte:02x} at time {xsi.get_time() / nanosecond_ticks}ns") rx_byte = 0 else: if clock_edge_number != expected_num_bytes*2*8: diff --git a/tests/spi_master_sync_benchmark/CMakeLists.txt b/tests/spi_master_sync_benchmark/CMakeLists.txt index 806db9d..1c9e5e0 100644 --- a/tests/spi_master_sync_benchmark/CMakeLists.txt +++ b/tests/spi_master_sync_benchmark/CMakeLists.txt @@ -7,19 +7,19 @@ file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) # Get individual fields from params_json string(JSON arch_list GET ${params_json} arch) string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) -string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON spi_mode_list GET ${params_json} SPI_MODE) string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) string(JSON arch_list_len LENGTH ${arch_list}) string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) -string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) # Subtract one off each of the lengths because RANGE includes last element math(EXPR arch_list_len "${arch_list_len} - 1") math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") -math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") @@ -38,13 +38,13 @@ foreach(i RANGE 0 ${arch_list_len}) foreach(j RANGE 0 ${burnt_threads_list_len}) string(JSON burnt_threads GET ${burnt_threads_list} ${j}) - foreach(k RANGE 0 ${cb_enabled_list_len}) - string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + foreach(k RANGE 0 ${spi_mode_list_len}) + string(JSON SPI_MODE GET ${spi_mode_list} ${k}) foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) - set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + set(config ${burnt_threads}_${SPI_MODE}_${miso_mosi_enabled}_${arch}) message(STATUS "building config ${config}") project(spi_master_sync_benchmark) @@ -64,9 +64,11 @@ foreach(i RANGE 0 ${arch_list_len}) list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") endif() + set(APP_INCLUDES src ../spi_master_tester_common) + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} -DBURNT_THREADS=${burnt_threads} - -DCB_ENABLED=${cb_enabled} + -DSPI_MODE=${SPI_MODE} -O2 -g -Wno-reinterpret-alignment) diff --git a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index f5baf60..d7497e7 100644 --- a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -5,9 +5,19 @@ #include #include #include "spi.h" +#include "spi_sync_tester.h" +extern "C"{ + #include "../src/spi_fwk.h" +} + +// access internal functions +extern void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz); +extern unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider); + + in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -15,72 +25,46 @@ clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; -static unsigned get_max_byte_speed(client interface spi_master_if i){ - unsigned now, then; - timer t; - t:> then; - i.begin_transaction(0, 100, SPI_MODE_3); - i.transfer8(0xff); - i.end_transaction(100); - t:> now; - unsigned best_time_so_far = now-then; - unsigned min = 0000, max = 6000; + +static unsigned get_max_speed(unsigned transfer_width, client interface spi_master_if i){ + unsigned min_test_speed = 1000, max_test_speed = 150000;//kbps + unsigned iteration = 0; + unsigned test_speed = min_test_speed; while(1){ - //unsigned test_speed = (min + max)/2; - unsigned test_speed = min + (max-min)/32; - t:> then; - i.begin_transaction(0, test_speed, SPI_MODE_3); - i.transfer8(test_speed); - i.end_transaction(100); - t:> now; - if(now-then < best_time_so_far){ - best_time_so_far = (now-then); - min = test_speed; + // Make sure we set the actual speed attainable + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, test_speed); + unsigned actual_test_speed = spi_master_get_actual_clock_rate(source_clock, divider); + + printf("testing:%u:%u:", transfer_width, actual_test_speed); + int error = 0; + if(transfer_width == 8){ + error = test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + SPI_MODE, actual_test_speed, MOSI_ENABLED, MISO_ENABLED); } else { - if(max == test_speed) - return test_speed; - max = test_speed; + error = test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + SPI_MODE, actual_test_speed, MOSI_ENABLED, MISO_ENABLED); } - } - return 1000; -} -static unsigned get_max_word_speed(client interface spi_master_if i){ - unsigned now, then; - timer t; - t:> then; - i.begin_transaction(0, 100, SPI_MODE_3); - i.transfer32(0xff); - i.transfer32(0xff); - i.end_transaction(100); - t:> now; - unsigned best_time_so_far = now-then; - unsigned min = 0000, max = 6000; - while(1){ - //unsigned test_speed = (min + max)/2; - unsigned test_speed = min + (max-min)/32; - t:> then; - // printf("testing: %u\n", test_speed); - i.begin_transaction(0, test_speed, SPI_MODE_3); - i.transfer32(0xff); - i.transfer32(0xff); - i.end_transaction(100); - t:> now; - if(now-then < best_time_so_far){ - best_time_so_far = (now-then); - min = test_speed; + + + if(error){ + printf("FAIL\n"); + test_speed = (test_speed + min_test_speed) / 2; + } else { - if(max == test_speed) - return test_speed; - max = test_speed; + printf("PASS\n"); + test_speed = (test_speed + max_test_speed) / 2; } + if(iteration++ == 7) return 0; // 7 always gets us there } - return 1000; + return 0; } void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ - printf("%d\n", get_max_byte_speed(i)); - printf("%d\n", get_max_word_speed(i)); + printf("%d\n", get_max_speed(8, i)); + printf("%d\n", get_max_speed(32, i)); _Exit(1); } @@ -105,16 +89,10 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif - int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); + spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_benchmark/test_params.json b/tests/spi_master_sync_benchmark/test_params.json index ea40c99..b57f2ab 100644 --- a/tests/spi_master_sync_benchmark/test_params.json +++ b/tests/spi_master_sync_benchmark/test_params.json @@ -1,6 +1,6 @@ { "BURNT_THREADS": [3, 7], - "CB_ENABLED": [0, 1], + "SPI_MODE": [0, 1, 2, 3], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_sync_rx_tx/CMakeLists.txt b/tests/spi_master_sync_rx_tx/CMakeLists.txt index 18bc1ac..c098237 100644 --- a/tests/spi_master_sync_rx_tx/CMakeLists.txt +++ b/tests/spi_master_sync_rx_tx/CMakeLists.txt @@ -7,19 +7,19 @@ file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) # Get individual fields from params_json string(JSON arch_list GET ${params_json} arch) string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) -string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON spi_mode_list GET ${params_json} SPI_MODE) string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) string(JSON arch_list_len LENGTH ${arch_list}) string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) -string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) # Subtract one off each of the lengths because RANGE includes last element math(EXPR arch_list_len "${arch_list_len} - 1") math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") -math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") @@ -38,13 +38,13 @@ foreach(i RANGE 0 ${arch_list_len}) foreach(j RANGE 0 ${burnt_threads_list_len}) string(JSON burnt_threads GET ${burnt_threads_list} ${j}) - foreach(k RANGE 0 ${cb_enabled_list_len}) - string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + foreach(k RANGE 0 ${spi_mode_list_len}) + string(JSON spi_mode GET ${spi_mode_list} ${k}) foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) - set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + set(config ${burnt_threads}_${miso_mosi_enabled}_${spi_mode}_${arch}) message(STATUS "building config ${config}") project(spi_master_sync_rx_tx) @@ -66,9 +66,9 @@ foreach(i RANGE 0 ${arch_list_len}) set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} -DBURNT_THREADS=${burnt_threads} - -DCB_ENABLED=${cb_enabled} + -DSPI_MODE=${spi_mode} -O2 - -g + -g -Wno-reinterpret-alignment) set(APP_INCLUDES src ../spi_master_tester_common) diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index b731760..8f21998 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -8,7 +8,7 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -16,21 +16,19 @@ clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; -void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ -#define SPEED_TESTS 1 - unsigned speed_lut[SPEED_TESTS] = {1500}; +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ +#define SPEED_TESTS 3 + unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 50000}; // Speed in kHz - for(spi_mode_t mode = SPI_MODE_0; mode <= SPI_MODE_3; mode ++){ - for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ - test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, - mode, speed_lut[speed_index], mosi_enabled, miso_enabled); - } + // printf("Device 8 SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } - for(spi_mode_t mode = SPI_MODE_0; mode <= SPI_MODE_3; mode ++){ - for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ - test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, - mode, speed_lut[speed_index], mosi_enabled, miso_enabled); - } + // printf("Device 32 SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } printf("Transfers complete\n"); _Exit(0); @@ -58,17 +56,12 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); - app(i[0], MOSI_ENABLED, MISO_ENABLED); + spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); + app(i[0], MOSI_ENABLED, MISO_ENABLED, SPI_MODE); load(BURNT_THREADS); } return 0; diff --git a/tests/spi_master_sync_rx_tx/test_params.json b/tests/spi_master_sync_rx_tx/test_params.json index ea40c99..3c82def 100644 --- a/tests/spi_master_sync_rx_tx/test_params.json +++ b/tests/spi_master_sync_rx_tx/test_params.json @@ -1,6 +1,6 @@ { "BURNT_THREADS": [3, 7], - "CB_ENABLED": [0, 1], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "SPI_MODE": [0, 1, 2, 3], "arch": ["xs2", "xs3"] } diff --git a/tests/test_master_sync_benchmark.py b/tests/test_master_sync_benchmark.py index 7a482ee..d36e26d 100644 --- a/tests/test_master_sync_benchmark.py +++ b/tests/test_master_sync_benchmark.py @@ -18,18 +18,20 @@ def __init__(self, id): self.result = dict(item.split('=') for item in id.split(', ')) def run(self, output): - print(output) ignore_list = ["SPI Master checker"] result_8b = None result_32b = None - for line in output: + for line in output: print(line) + for line in reversed(output): if any(skip in line for skip in ignore_list): continue - if result_8b is None: - result_8b = line - continue - if result_32b is None: - result_32b = line + if "PASS" in line: + width, speed = line.split(':')[1:3] + if int(width) == 8 and result_8b is None: + result_8b = speed + continue + if int(width) == 32 and result_32b is None: + result_32b = speed self.result["result_8b"] = result_8b self.result["result_32b"] = result_32b assert result_8b and result_32b, "No timing results found" @@ -46,8 +48,8 @@ def remove_test_results(): # Post test cleanup sort_csv_table(test_results_file) -def do_benchmark_sync(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): - id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" +def do_benchmark_sync(capfd, burnt, spi_mode, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists(), f"Binary file {binary} not present - please pre-build" @@ -66,6 +68,7 @@ def do_benchmark_sync(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): tester = tester, do_xe_prebuild = False, simthreads = [checker], + simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -clock-blocks -ports -ports-detailed -pads -functions'], capfd=capfd) diff --git a/tests/test_master_sync_rx_tx.py b/tests/test_master_sync_rx_tx.py index 516ec30..5b816ca 100644 --- a/tests/test_master_sync_rx_tx.py +++ b/tests/test_master_sync_rx_tx.py @@ -5,13 +5,13 @@ import pytest from spi_master_checker import SPIMasterChecker from helpers import generate_tests_from_json, create_if_needed - +from itertools import zip_longest appname = "spi_master_sync_rx_tx" test_params_file = Path(__file__).parent / f"{appname}/test_params.json" -def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): - id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" +def do_test(capfd, burnt, spi_mode, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists() @@ -32,7 +32,7 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - #simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) @@ -41,12 +41,15 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): output = out.split('\n')[:-1] with capfd.disabled(): - print(f"expected: {expected}") - print(f"Actual output: {output}") + print() + print(f"{'***EXPECTED***':<40}***ACTUAL***") + for e, o in zip_longest(expected, output, fillvalue = ''): + print(f"{str(e):<40}{str(o)}") assert tester.run(output) @pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) def test_master_sync_rx_tx(capfd, params, request): + # print("********", params) do_test(capfd, *params, request.node.callspec.id) \ No newline at end of file From ee8f0661001db7ae2af6fcfd9229d3d73c5d22ec Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 17 Jul 2025 13:58:17 +0100 Subject: [PATCH 24/57] Get asynch/sync master working with fwk_spi --- lib_spi/api/spi.h | 8 ++- lib_spi/src/spi_fwk.h | 24 ------- lib_spi/src/spi_master.c | 14 +--- lib_spi/src/spi_master_sync_fwk.xc | 31 ++++++--- lib_spi/src/spi_sync.xc | 6 +- tests/spi_master_checker.py | 65 +++++++++---------- .../src/spi_master_sync_clock_port_sharing.xc | 4 +- .../src/spi_master_sync_multi_client.xc | 11 ++-- .../test_params.json | 2 +- .../src/spi_master_sync_multi_device.xc | 10 +-- .../test_params.json | 2 +- .../src/spi_master_sync_rx_tx.xc | 2 +- .../spi_sync_tester.h | 3 +- tests/test_master_async_rx_tx.py | 4 +- tests/test_master_sync_benchmark.py | 2 +- tests/test_master_sync_clock_port_sharing.py | 2 +- tests/test_master_sync_multi_client.py | 7 +- tests/test_master_sync_multi_device.py | 14 ++-- tests/test_master_sync_rx_tx.py | 4 +- 19 files changed, 99 insertions(+), 116 deletions(-) diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 00a6699..d1cbec4 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -98,13 +98,17 @@ typedef interface spi_master_if { /** Sets the bit of port which is used for slave select (> 1b port type only) * and only for spi_master_fwk. spi_master sets all bits in each port high/low * - * The default value (if this is not called) is bit zero which is suitable - * for 1-bit ports or where bit 0 of a wider port is used. + * The default value (if this is not called) is the bit number is equal to + * the device_index (0->0, 1->1 etc.). * * \param ss_port_bit Which bit number in the port to use for slave select. */ void set_ss_port_bit(unsigned ss_port_bit); + /** Shut down the interface server. + */ + void shutdown(void); + #ifndef __DOXYGEN__ } spi_master_if; #endif diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index bc42744..031ca59 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -73,30 +73,6 @@ typedef enum { spi_master_source_clock_xcore /**< SCLK is derived from the core clock */ } spi_master_source_clock_t; -/** - * Convenience macro that may be used to specify SPI Mode 0 to - * spi_master_device_init() or spi_slave() in place of cpol and cpha. - */ -#define SPI_MODE_0 0,0 - -/** - * Convenience macro that may be used to specify SPI Mode 1 to - * spi_master_device_init() or spi_slave() in place of cpol and cpha. - */ -#define SPI_MODE_1 0,1 - -/** - * Convenience macro that may be used to specify SPI Mode 2 to - * spi_master_device_init() or spi_slave() in place of cpol and cpha. - */ -#define SPI_MODE_2 1,0 - -/** - * Convenience macro that may be used to specify SPI Mode 3 to - * spi_master_device_init() or spi_slave() in place of cpol and cpha. - */ -#define SPI_MODE_3 1,1 - /** * Struct to hold a SPI master context. * diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c index 7a9840c..dc38461 100644 --- a/lib_spi/src/spi_master.c +++ b/lib_spi/src/spi_master.c @@ -1,4 +1,4 @@ -// Copyright 2021-2022 XMOS LIMITED. +// Copyright 2021-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -9,12 +9,6 @@ void spi_master_start_transaction( { spi_master_t *spi = dev->spi_master_ctx; - /* Save thread bits on entry */ - dev->thread_mode = local_thread_mode_get_bits(); - - /* enable fast mode and high priority */ - local_thread_mode_set_bits(thread_mode_fast | thread_mode_high_priority); - if (dev->cs_assert_val != spi->current_device) { spi->current_device = dev->cs_assert_val; @@ -205,12 +199,6 @@ void spi_master_end_transaction( const uint32_t cs_deassert_val = 0xFFFFFFFF; spi_master_t *spi = dev->spi_master_ctx; - /* disable fast mode and high priority */ - local_thread_mode_clear_bits(thread_mode_fast | thread_mode_high_priority); - - /* Restore original thread bits on exit */ - local_thread_mode_set_bits(dev->thread_mode); - port_sync(spi->cs_port); port_out(spi->cs_port, cs_deassert_val); diff --git a/lib_spi/src/spi_master_sync_fwk.xc b/lib_spi/src/spi_master_sync_fwk.xc index d6961e8..9ccfb3d 100644 --- a/lib_spi/src/spi_master_sync_fwk.xc +++ b/lib_spi/src/spi_master_sync_fwk.xc @@ -14,6 +14,8 @@ extern "C"{ #include "spi_fwk.h" } +#define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device + // Optional function to determine the actual set speed for particular clock settings. unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 @@ -63,14 +65,19 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], // We will hit an exception shortly after this if NULL } - spi_master_t spi_ctx; + spi_master_t spi_master; spi_master_device_t spi_dev; unsafe{ - spi_master_init(&spi_ctx, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); } int accepting_new_transactions = 1; - unsigned ss_port_bit[num_clients] = {0}; + + // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) + uint8_t ss_port_bit[SPI_MAX_DEVICES]; + for(int i = 0; i < SPI_MAX_DEVICES; i++){ + ss_port_bit[i] = i; + } while(1){ select { @@ -92,16 +99,16 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], unsigned cpol = mode >> 1; unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev, &spi_ctx, - ss_port_bit[x], + spi_master_device_init(&spi_dev, &spi_master, + ss_port_bit[device_index], cpol, cpha, source_clock, divider, spi_master_sample_delay_0, 0, 0 ,0 ,0 ); - spi_ctx.current_device = 0xffffffff;// This is needed to force mode and speed in spi_master_start_transaction() - // Otherwise fwk_spi sees the next transaction as the same settings as last + spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() + // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client spi_master_start_transaction(&spi_dev); break; } @@ -114,7 +121,7 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], } case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&r, 1); + spi_master_transfer(&spi_dev, (uint8_t *)&data, &r, 1); break; } @@ -127,9 +134,17 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], } case i[int x].set_ss_port_bit(unsigned port_bit):{ + if(port_bit > SPI_MAX_DEVICES){ + printstrln("Invalid port bit - must be less than SPI_MAX_DEVICES"); + } ss_port_bit[x] = port_bit; break; } + + case i[int x].shutdown(void):{ + spi_master_deinit(&spi_master); + break; + } } } diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc index 48d8530..25a05c4 100644 --- a/lib_spi/src/spi_sync.xc +++ b/lib_spi/src/spi_sync.xc @@ -345,8 +345,12 @@ void spi_master(server interface spi_master_if i[num_clients], // Do nothing this is invalid since this component sets all port bits high/low during select break; } + + case i[int x].shutdown(void):{ + // Do nothing currently + break; + } } } - } diff --git a/tests/spi_master_checker.py b/tests/spi_master_checker.py index b910368..ccb0c4a 100644 --- a/tests/spi_master_checker.py +++ b/tests/spi_master_checker.py @@ -1,7 +1,6 @@ # Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import Pyxsim as px -from typing import Sequence from functools import partial # We need to disable output buffering for this test to work on MacOS; this has @@ -9,7 +8,6 @@ # same argument everywhere. print = partial(print, flush=True) - class SPIMasterChecker(px.SimThread): """" This simulator thread will act as SPI slave and check any transactions @@ -19,13 +17,14 @@ def __init__(self, sck_port: str, mosi_port: str, miso_port: str, - ss_ports: Sequence[str], + ss_port: str, setup_strobe_port: str, setup_data_port: str) -> None: self._miso_port = miso_port self._mosi_port = mosi_port self._sck_port = sck_port - self._ss_ports = ss_ports + self._ss_port = ss_port + self._ss_port_width = px.pyxsim.xsi_get_port_width(ss_port.split(':')[1] if ":" in ss_port else ss_port) # May need to trim on tile[x]: self._setup_strobe_port = setup_strobe_port self._setup_data_port = setup_data_port @@ -40,6 +39,8 @@ def get_setup_data(self, def run(self) -> None: xsi: px.pyxsim.Xsi = self.xsi + print("SPI Master checker started") + # some timing constants xsi_tick_freq_hz = float(1e15) # pending merge of https://github.com/xmos/test_support/blob/develop/lib/python/Pyxsim/pyxsim.py#L246-L265 millisecond_ticks = xsi_tick_freq_hz / 1e3 @@ -47,15 +48,11 @@ def run(self) -> None: nanosecond_ticks = xsi_tick_freq_hz / 1e9 sck_value = xsi.sample_port_pins(self._sck_port) - ss_value = [] - - for i in range(len(self._ss_ports)): - ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) - - print("SPI Master checker started") + ss_value = xsi.sample_port_pins(self._ss_port) + ss_deaserted_value = (0xffffffff >> (32 - self._ss_port_width)) while True: - #first do the setup rx + #first do the setup rx from DUT strobe_val = xsi.sample_port_pins(self._setup_strobe_port) if strobe_val == 1: self.wait_for_port_pins_change([self._setup_strobe_port]) @@ -73,29 +70,28 @@ def run(self) -> None: clock_half_period = millisecond_ticks / (expected_frequency_in_khz*2) all_ss_deserted = True - for i in range(len(self._ss_ports)): - if (xsi.sample_port_pins(self._ss_ports[i]) == 0): - all_ss_deserted = False - break + if (xsi.sample_port_pins(self._ss_port) != ss_deaserted_value): + all_ss_deserted = False + # Wait until all SS go high while not all_ss_deserted: - self.wait_for_port_pins_change(self._ss_ports) - all_ss_deserted = True - for i in range(len(self._ss_ports)): - all_ss_deserted = all_ss_deserted and (xsi.sample_port_pins(self._ss_ports[i]) == 1) + self.wait_for_port_pins_change([self._ss_port]) + all_ss_deserted = True if xsi.sample_port_pins(self._ss_port) == ss_deaserted_value else False error = False - active_slave = -1 + # Wait for any SS to assert + active_slave = -1 # no active slaves while(active_slave == -1): - self.wait_for_port_pins_change(self._ss_ports) - - for i in range(len(self._ss_ports)): - if xsi.sample_port_pins(self._ss_ports[i]) == 0: + self.wait_for_port_pins_change([self._ss_port]) + ss_port_val = xsi.sample_port_pins(self._ss_port) + for i in range(self._ss_port_width): + if ((ss_port_val >> i) & 1) == 0: + assert active_slave == -1, f"more than one SS asserted, SS port val: 0x{ss_port_val:x}" active_slave = i - break - + # print(f"active_slave: {active_slave}") + last_clock_event_time = xsi.get_time() rx_bit_counter = 0 @@ -118,21 +114,24 @@ def run(self) -> None: tx_bit_counter += 1 tx_byte = tx_byte << 1 - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) + ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) sck_value = xsi.sample_port_pins(self._sck_port) while ss_value == 0: - self.wait_for_port_pins_change(self._ss_ports + [self._sck_port]) + self.wait_for_port_pins_change([self._ss_port] + [self._sck_port]) - for i in range(len(self._ss_ports)): - if i != active_slave and xsi.sample_port_pins(self._ss_ports[i]) == 0: + # check no other SS asserted + ss_port_val = xsi.sample_port_pins(self._ss_port) & ss_deaserted_value + # print(f"{self._ss_port}, 0x{ss_port_val:x}, 0x{ss_deaserted_value:x}, {active_slave}, {(ss_deaserted_value & ~(1 << active_slave)):x}") + for i in range(self._ss_port_width): + if not ss_port_val & (1 << i) and i != active_slave: error = True - print("Second slave selected during first transaction") + print(f"Second slave selected during first transaction, SS port val: 0x{ss_port_val:x} at time: {xsi.get_time() / nanosecond_ticks}ns") - if (ss_value == xsi.sample_port_pins(self._ss_ports[active_slave]) and (sck_value == xsi.sample_port_pins(self._sck_port))): + if (ss_value == ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) and (sck_value == xsi.sample_port_pins(self._sck_port))): continue - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) + ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) sck_value = xsi.sample_port_pins(self._sck_port) if ss_value == 0: diff --git a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc index 7a395b8..c203221 100644 --- a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc +++ b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc @@ -9,7 +9,7 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -79,7 +79,7 @@ int main(){ #endif par { app(i[0], 1, 1); - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + spi_master_fwk(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); } } } diff --git a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 4dcedd1..3be02fd 100644 --- a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -9,11 +9,12 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; + out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -23,6 +24,7 @@ void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, c i.begin_transaction(0, 736, SPI_MODE_3); i.transfer8(0xff); i.end_transaction(100); + delay_microseconds(1); c <: 1; } } @@ -72,11 +74,6 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif /* * Tests: * - no client is ever starved @@ -86,7 +83,7 @@ int main(){ chan c[3]; interface spi_master_if i[3]; par { - spi_master(i, 3, p_sclk, MOSI, MISO, p_ss, 1, CB); + spi_master_fwk(i, 3, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED, c[0]); app(i[1], MOSI_ENABLED, MISO_ENABLED, c[1]); app(i[2], MOSI_ENABLED, MISO_ENABLED, c[2]); diff --git a/tests/spi_master_sync_multi_client/test_params.json b/tests/spi_master_sync_multi_client/test_params.json index 317568c..79f1f9b 100644 --- a/tests/spi_master_sync_multi_client/test_params.json +++ b/tests/spi_master_sync_multi_client/test_params.json @@ -1,6 +1,6 @@ { "BURNT_THREADS": [3, 4], - "CB_ENABLED": [0, 1], + "CB_ENABLED": [1], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index 9b5d396..3ed850e 100644 --- a/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -10,7 +10,7 @@ #define NUM_SS 2 in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[2] = {XS1_PORT_1B, XS1_PORT_1G}; +out port p_ss = XS1_PORT_4A; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -73,16 +73,10 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif - int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, CB); + spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, cb); app(i[0], NUM_SS, MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_multi_device/test_params.json b/tests/spi_master_sync_multi_device/test_params.json index ea40c99..20f1b4b 100644 --- a/tests/spi_master_sync_multi_device/test_params.json +++ b/tests/spi_master_sync_multi_device/test_params.json @@ -1,6 +1,6 @@ { "BURNT_THREADS": [3, 7], - "CB_ENABLED": [0, 1], + "CB_ENABLED": [1], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 8f21998..321cde5 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -18,7 +18,7 @@ out port setup_data_port = XS1_PORT_16B; void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ #define SPEED_TESTS 3 - unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 50000}; // Speed in kHz + unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 33000}; // Speed in kHz // printf("Device 8 SPI_MODE: %d\n", spi_mode); for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ diff --git a/tests/spi_master_tester_common/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h index 6c3a297..3004f54 100644 --- a/tests/spi_master_tester_common/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -25,10 +25,11 @@ int test_transfer8(client interface spi_master_if i, for(unsigned j=0;j Date: Mon, 21 Jul 2025 16:17:05 +0100 Subject: [PATCH 25/57] async multi-client pass --- .gitignore | 1 + doc/rst/lib_spi.rst | 4 +- lib_spi/api/spi.h | 24 ++ lib_spi/lib_build_info.cmake | 1 + lib_spi/module_build_info | 3 +- lib_spi/src/spi_async.xc | 5 + lib_spi/src/spi_master_async_fwk.xc | 347 ++++++++++++++++++ lib_spi/src/spi_master_shared_fwk.h | 23 ++ lib_spi/src/spi_master_shared_fwk.xc | 49 +++ lib_spi/src/spi_master_sync_fwk.xc | 54 +-- tests/CMakeLists.txt | 2 + tests/helpers.py | 18 +- .../src/spi_master_async_multi_client.xc | 56 ++- .../src/spi_master_async_multi_device.xc | 11 +- .../src/spi_master_async_rx_tx.xc | 46 ++- .../spi_master_async_shutdown/CMakeLists.txt | 21 ++ .../src/spi_master_async_shutdown.xc | 183 +++++++++ tests/spi_master_checker.py | 8 +- tests/spi_master_sync_shutdown/CMakeLists.txt | 21 ++ .../src/spi_master_sync_shutdown.xc | 51 +++ .../spi_async_tester.h | 2 +- .../spi_sync_tester.h | 5 +- tests/test_master_async_multi_client.py | 25 +- tests/test_master_async_multi_device.py | 17 +- tests/test_master_async_rx_tx.py | 21 +- tests/test_master_async_shutdown.py | 41 +++ tests/test_master_sync_clock_port_sharing.py | 11 +- tests/test_master_sync_multi_client.py | 15 +- tests/test_master_sync_multi_device.py | 20 +- tests/test_master_sync_rx_tx.py | 17 +- tests/test_master_sync_shutdown.py | 41 +++ tests/test_slave_rx_tx.py | 10 +- 32 files changed, 968 insertions(+), 185 deletions(-) create mode 100644 lib_spi/src/spi_master_async_fwk.xc create mode 100644 lib_spi/src/spi_master_shared_fwk.h create mode 100644 lib_spi/src/spi_master_shared_fwk.xc create mode 100644 tests/spi_master_async_shutdown/CMakeLists.txt create mode 100644 tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc create mode 100644 tests/spi_master_sync_shutdown/CMakeLists.txt create mode 100644 tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc create mode 100644 tests/test_master_async_shutdown.py create mode 100644 tests/test_master_sync_shutdown.py diff --git a/.gitignore b/.gitignore index cb0ca21..e0c142d 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,4 @@ build/ */build/* __gen *tests/logs/* +*.gtkw diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index db2ed6f..78fae76 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -433,10 +433,10 @@ Asynchronous master command buffering In order to provide asynchronous behaviour for multiple clients the asynchronous master will store up to one ``begin_transaction`` and one ``init_transfer_array_8`` or ``init_transfer_array_32`` from each client. This means that if the -master is busy doing a transfer for client *X*, then client *Y* will +master is busy doing a transfer for client *X*, then client *Y* will still be able to begin a transaction and send data fully asynchronously. Consequently, after client *Y* has issued -``init_transfer_array_8`` or ``init_transfer_array_32`` the it will be +``init_transfer_array_8`` or ``init_transfer_array_32`` it will be able to continue operation whilst waiting for the notification. Asynchronous master usage state machine diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index d1cbec4..defcaf3 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -280,6 +280,18 @@ typedef interface spi_master_async_if { void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master_fwk. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is the bit number is equal to + * the device_index (0->0, 1->1 etc.). + * + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned ss_port_bit); + + /** Shut down the interface server. */ void shutdown(void); @@ -319,6 +331,18 @@ void spi_master_async( clock clk0, clock clk1); +[[combinable]] +void spi_master_async_fwk( + SERVER_INTERFACE(spi_master_async_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + in_buffered_port_32_t miso, + out_port p_ss, + static_const_size_t num_slaves, + clock clk0, + clock clk1); + /**** SLAVE ****/ /** diff --git a/lib_spi/lib_build_info.cmake b/lib_spi/lib_build_info.cmake index 2074e40..11a0822 100644 --- a/lib_spi/lib_build_info.cmake +++ b/lib_spi/lib_build_info.cmake @@ -3,4 +3,5 @@ set(LIB_VERSION 3.4.0) set(LIB_INCLUDES api) set(LIB_DEPENDENT_MODULES "") set(LIB_COMPILER_FLAGS_spi_async.xc -Wno-reinterpret-alignment) +set(LIB_COMPILER_FLAGS_spi_master_async_fwk.xc -Wno-reinterpret-alignment) XMOS_REGISTER_MODULE() diff --git a/lib_spi/module_build_info b/lib_spi/module_build_info index a240d43..13ba169 100644 --- a/lib_spi/module_build_info +++ b/lib_spi/module_build_info @@ -1,3 +1,4 @@ VERSION = 3.4.0 -XCC_FLAGS_spi_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment +XCC_FLAGS_spi_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment +XCC_FLAGS_spi_master_async_fwk.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment \ No newline at end of file diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc index 49d1c4b..e83dad4 100644 --- a/lib_spi/src/spi_async.xc +++ b/lib_spi/src/spi_async.xc @@ -401,6 +401,11 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], break; } + case i[int x].set_ss_port_bit(unsigned port_bit):{ + // Do nothing this is invalid since this component sets all port bits high/low during select + break; + } + case i[int x].shutdown(void): move(buffer_rx); move(buffer_tx); diff --git a/lib_spi/src/spi_master_async_fwk.xc b/lib_spi/src/spi_master_async_fwk.xc new file mode 100644 index 0000000..23dc36f --- /dev/null +++ b/lib_spi/src/spi_master_async_fwk.xc @@ -0,0 +1,347 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include + +#include +#include "spi.h" +extern "C"{ +#include "spi_fwk.h" +} +#include "spi_master_shared_fwk.h" + +#define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device + +typedef struct { + unsigned client_id; + unsigned device_index; + unsigned speed_in_khz; + spi_mode_t mode; + size_t buffer_nbytes; + unsigned buffer_transfer_width; + uint32_t * movable buffer_tx; + uint32_t * movable buffer_rx; + +} transaction_request; +#define NBYTES_UNASSIGNED (-1) + + +[[combinable]] +void spi_master_async_fwk(server interface spi_master_async_if i[num_clients], + static const size_t num_clients, + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 miso, + out port p_ss, + static const size_t num_slaves, + clock cb0, + clock cb1){ + + //These buffer are for the transaction requests + transaction_request tr_buffer[num_clients]; ///FIXME num_clients + unsigned tr_tail = 0; + unsigned tr_fill = 0; + + //These buffers are for the active transaction + uint32_t * movable buffer_tx; + uint32_t * movable buffer_rx; + size_t buffer_nbytes; + unsigned buffer_current_index; + unsigned buffer_transfer_width; + + //These variables are for the active transaction state + unsigned active_device; + unsigned active_client; + unsigned active_mode; + int currently_performing_a_transaction = 0; + + //Setup fwk SPI master and device instance + spi_master_t spi_master; + spi_master_device_t spi_dev; + unsafe{ + spi_master_init(&spi_master, cb0, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + } + + // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) + uint8_t ss_port_bit[SPI_MAX_DEVICES]; + for(int i = 0; i < SPI_MAX_DEVICES; i++){ + ss_port_bit[i] = i; + } + + // Initial SS bit pattern - deselected + p_ss <: 0xffffffff; + + // TMP MISO vals + uint8_t r8; + uint32_t r32; + + // Use as way of implementing a default case. Setting the default_case_time to the current time makes an event happen immediately + // This is used for subsequent SPI transfers after the first during a transaction + timer tmr; + int default_case_time; + int default_case_enabled = 0; + + while(1){ + select { + case i[int x].begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode):{ + //if doing a transaction then buffer this one + if(currently_performing_a_transaction){ + //Note, the tr_fill should never exceed num_clients if the calling protocol is respected + unsigned index = (tr_tail + tr_fill)%num_clients; //FIXME div? + tr_buffer[index].device_index = device_index; + tr_buffer[index].speed_in_khz = speed_in_khz; + tr_buffer[index].mode = mode; + tr_buffer[index].client_id = x; + tr_buffer[index].buffer_nbytes = NBYTES_UNASSIGNED; + tr_fill++; + break; + } + + active_client = x; + active_device = device_index; + active_mode = mode; + + // Calculate clock divider and SPI mode vs CPOL/CPHA + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + + spi_master_device_init(&spi_dev, &spi_master, + ss_port_bit[device_index], + cpol, cpha, + source_clock, + divider, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); + + spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() + // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client + spi_master_start_transaction(&spi_dev); + + buffer_current_index = 0; + currently_performing_a_transaction = 1; + + break; + } + + case i[int x].init_transfer_array_8(uint8_t * movable inbuf, + uint8_t * movable outbuf, + size_t nbytes) :{ + // if(dbg) printstr("init_transfer_array_8 "); if(dbg) printintln(nbytes); + if(x != active_client){ + // Just buffer it + unsigned index; + for(unsigned j=0;j default_case_time; + default_case_enabled = 1; + } + } + break; + } + + case i[int x].init_transfer_array_32(uint32_t * movable inbuf, + uint32_t * movable outbuf, + size_t nwords):{ + if(x != active_client){ + // Just buffer it + unsigned index; + for(unsigned j=0;j default_case_time; + default_case_enabled = 1; + } + } + break; + } + + // This case handles the input from the last transfer + case default_case_enabled => tmr when timerafter(default_case_time) :> int _:{ + //put the data into the correct array and send the next data if need be + if(buffer_transfer_width == 8){ + uint32_t data = byterev((uint32_t)r8<<24); // TODO - this is just r8!??? + ((uint8_t*movable)buffer_rx)[buffer_current_index] = (uint8_t)data; + buffer_current_index++; + if((buffer_current_index*sizeof(uint8_t)) == buffer_nbytes){ + default_case_enabled = 0; + buffer_current_index = 0; + i[active_client].transfer_complete(); + } else { + spi_master_transfer(&spi_dev, &((uint8_t*movable)buffer_tx)[buffer_current_index], &r8, 1); + tmr :> default_case_time; + default_case_enabled = 1; + } + } else { + uint32_t data = byterev(r32); + buffer_rx[buffer_current_index] = data; + buffer_current_index++; + if((buffer_current_index*sizeof(uint32_t)) == buffer_nbytes){ + default_case_enabled = 0; + buffer_current_index = 0; + i[active_client].transfer_complete(); + } else { + uint32_t data = byterev(buffer_tx[buffer_current_index]); + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t*)&r32, 4); + tmr :> default_case_time; + default_case_enabled = 1; + } + } + break; + } + + //Note, end transaction can only be called from the active_client + case i[int x].end_transaction(unsigned ss_deassert_time):{ + //xassert(x == active_client); + + //An end_transaction can only be completed after all transfers + //have been completed + + spi_master_end_transaction(&spi_dev); + + if(tr_fill > 0){ + //begin a new transaction - the tail of the list is the next one to go + unsigned index = tr_tail%num_clients; + unsigned new_device_index = tr_buffer[index].device_index; + unsigned speed_in_khz = tr_buffer[index].speed_in_khz; + spi_mode_t mode = tr_buffer[index].mode; + + active_client = tr_buffer[index].client_id; + + tr_fill--; + tr_tail++; + + // Put in generic start transaction stuff (Functionise?) + // Calculate clock divider and SPI mode vs CPOL/CPHA + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + + spi_master_device_init(&spi_dev, &spi_master, + ss_port_bit[new_device_index], + cpol, cpha, + source_clock, + divider, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); + + spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() + // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client + spi_master_start_transaction(&spi_dev); + + active_device = new_device_index; + active_mode = mode; + + buffer_nbytes = tr_buffer[index].buffer_nbytes; + + if(buffer_nbytes != NBYTES_UNASSIGNED){ + buffer_tx = move(tr_buffer[index].buffer_tx); + buffer_rx = move(tr_buffer[index].buffer_rx); + buffer_transfer_width = tr_buffer[index].buffer_transfer_width; + if(buffer_transfer_width == 8){ + spi_master_transfer(&spi_dev, (uint8_t*movable)&buffer_tx[0], &r8, 1); + tmr :> default_case_time; + default_case_enabled = 1; + } else { + uint32_t data = byterev(buffer_tx[0]); + // uint32_t data = buffer_tx[0]; + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t*)&r32, 4); + tmr :> default_case_time; + default_case_enabled = 1; + } + buffer_current_index = 0; + } + } else { + currently_performing_a_transaction = 0; + } + break; + } + + case i[int x].retrieve_transfer_buffers_8(uint8_t * movable &inbuf, uint8_t * movable &outbuf):{ + inbuf = (uint8_t*movable)move(buffer_rx); + outbuf = (uint8_t*movable)move(buffer_tx); + break; + } + + case i[int x].retrieve_transfer_buffers_32(uint32_t * movable &inbuf, uint32_t * movable &outbuf):{ + inbuf = move(buffer_rx); + outbuf = move(buffer_tx); + break; + } + + case i[int x].set_ss_port_bit(unsigned port_bit):{ + if(port_bit > SPI_MAX_DEVICES){ + printstrln("Invalid port bit - must be less than SPI_MAX_DEVICES"); + } + ss_port_bit[x] = port_bit; + break; + } + + case i[int x].shutdown(void): + move(buffer_rx); + move(buffer_tx); + // When using XC, then we need to enable/init so ports are still on + p_ss <: 0xffffffff; + // These just reset the ports and clk + if (!isnull(mosi)) { + set_port_use_on(mosi); + } + set_port_use_on(miso); + set_port_use_on(sclk); + set_clock_on(cb0); + return; + } + } + +} diff --git a/lib_spi/src/spi_master_shared_fwk.h b/lib_spi/src/spi_master_shared_fwk.h new file mode 100644 index 0000000..478a548 --- /dev/null +++ b/lib_spi/src/spi_master_shared_fwk.h @@ -0,0 +1,23 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include + +//TODO DEL these +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + + +// Optional function to determine the actual set speed for particular clock settings. +unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider); + +// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate +// effectively using a ceil type function +void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz); \ No newline at end of file diff --git a/lib_spi/src/spi_master_shared_fwk.xc b/lib_spi/src/spi_master_shared_fwk.xc new file mode 100644 index 0000000..a509fdb --- /dev/null +++ b/lib_spi/src/spi_master_shared_fwk.xc @@ -0,0 +1,49 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include + +//TODO DEL these +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + + +// Optional function to determine the actual set speed for particular clock settings. +unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ + unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 + / 2 + / (divider == 0 ? 1 : ((divider) * 2)); + + return actual_speed_khz; +} + + +// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate +// effectively using a ceil type function +void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz){ + // Clock blocks divide at / (2 * div) for div > 0 or / 1 where div == 0. Maximum clock block division is 255 * 2 = 510 + // Due to SPI needing to output each bit twice (to allow control over clock edges) the overal SPI clock rate is / 2 further + // to the divider. + // Steps get very granular as div -> 1 so use ref clock below 2MHz and core clock above 2MHz + // The minimum SPI clock speed is therefore 100e6 / (255 * 2 * 2) = 98kHz on the ref clock + // The minimum SPI clock speed at 800MHz core clock (typical highest) is 800e6 / (255 * 2 * 2) = 784kHz + if(speed_in_khz > 2000){ + *source_clock = spi_master_source_clock_xcore; + *divider = (PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } else { + *source_clock = spi_master_source_clock_ref; + *divider = (PLATFORM_REFERENCE_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } + + // Avoid overflow of the 8b divider reg. + if(*divider > 255){ + *divider = 255; + } +} diff --git a/lib_spi/src/spi_master_sync_fwk.xc b/lib_spi/src/spi_master_sync_fwk.xc index 9ccfb3d..204dfaa 100644 --- a/lib_spi/src/spi_master_sync_fwk.xc +++ b/lib_spi/src/spi_master_sync_fwk.xc @@ -13,41 +13,10 @@ extern "C"{ #include "spi_fwk.h" } +#include "spi_master_shared_fwk.h" #define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device -// Optional function to determine the actual set speed for particular clock settings. -unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ - unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 - / 2 - / (divider == 0 ? 1 : ((divider) * 2)); - - return actual_speed_khz; -} - - -// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate -// effectively using a ceil type function -void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz){ - // Clock blocks divide at / (2 * div) for div > 0 or / 1 where div == 0. Maximum clock block division is 255 * 2 = 510 - // Due to SPI needing to output each bit twice (to allow control over clock edges) the overal SPI clock rate is / 2 further - // to the divider. - // Steps get very granular as div -> 1 so use ref clock below 2MHz and core clock above 2MHz - // The minimum SPI clock speed is therefore 100e6 / (255 * 2 * 2) = 98kHz on the ref clock - // The minimum SPI clock speed at 800MHz core clock (typical highest) is 800e6 / (255 * 2 * 2) = 784kHz - if(speed_in_khz > 2000){ - *source_clock = spi_master_source_clock_xcore; - *divider = (PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); - } else { - *source_clock = spi_master_source_clock_ref; - *divider = (PLATFORM_REFERENCE_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); - } - - // Avoid overflow of the 8b divider reg. - if(*divider > 255){ - *divider = 255; - } -} #pragma unsafe arrays [[distributable]] @@ -62,7 +31,7 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], if(isnull(cb)){ printstrln("Must supply clockblock to this version of SPI"); - // We will hit an exception shortly after this if NULL + // We will hit an exception shortly after this if cb is NULL } spi_master_t spi_master; @@ -83,7 +52,6 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], select { case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode):{ - // printf("begin_transaction: client %d\n", x); accepting_new_transactions = 0; spi_master_source_clock_t source_clock; @@ -91,7 +59,7 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); // unsigned actual_speed_khz = spi_master_get_actual_clock_rate(source_clock, divider); - // printf("Actual speed_in_khz: %u div(%u) clock: %s (%u)MHz\n", + // printf("Actual speed_in_khz: %u div(%u) clock: (%s) %uMHz\n", // actual_speed_khz, // divider, // ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), @@ -127,6 +95,8 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], case i[int x].transfer32(uint32_t data) -> uint32_t r:{ uint32_t read_val; + // For 32b words, we need to swap to big endian (standard for SPI) from little endian (XMOS) + // This means we transmit the MSByte first data = byterev(data); spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); r = byterev(read_val); @@ -142,8 +112,18 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], } case i[int x].shutdown(void):{ - spi_master_deinit(&spi_master); - break; + // We don't use spi_master_deinit(&spi_master); This completely turns off resources. + p_ss <: 0xffffffff; + + // If using XC, then we need to enable/init which is how XC does it + if (!isnull(mosi)) { + set_port_use_on(mosi); + } + set_port_use_on(miso); + set_port_use_on(sclk); + set_clock_on(cb); + + return; } } } diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 34cda08..ea8e29e 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -7,8 +7,10 @@ add_subdirectory(spi_master_sync_rx_tx) add_subdirectory(spi_master_sync_multi_device) add_subdirectory(spi_master_sync_multi_client) add_subdirectory(spi_master_sync_clock_port_sharing) +add_subdirectory(spi_master_sync_shutdown) add_subdirectory(spi_slave_benchmark) add_subdirectory(spi_slave_rx_tx) add_subdirectory(spi_master_async_rx_tx) add_subdirectory(spi_master_async_multi_client) add_subdirectory(spi_master_async_multi_device) +add_subdirectory(spi_master_async_shutdown) diff --git a/tests/helpers.py b/tests/helpers.py index 43e3c3c..aa8562d 100644 --- a/tests/helpers.py +++ b/tests/helpers.py @@ -10,6 +10,7 @@ import threading import itertools from filelock import FileLock +from itertools import zip_longest # Thread safe create a folder def create_if_needed(folder): @@ -112,4 +113,19 @@ def sort_csv_table(file_path): writer.writerows(rows) except FileNotFoundError: - assert 0, f"No CSV table {file_path} to sort" \ No newline at end of file + assert 0, f"No CSV table {file_path} to sort" + + +# Print the comparison in human friendly format +def print_expected_vs_output(expected, capfd): + out, err = capfd.readouterr() + output = out.split('\n')[:-1] # Need to trim last line + + with capfd.disabled(): + if err: + print(f"Exceptions encountered: {err}") # Show any exceptions + print(f"\n{'***EXPECTED***':<40}***ACTUAL***") + for e, o in zip_longest(expected, output, fillvalue = ''): + print(f"{str(e):<40}{str(o)}") + + return output \ No newline at end of file diff --git a/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index 358e7c7..1709512 100644 --- a/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -6,11 +6,10 @@ #include #include #include "spi.h" -#include "spi_async_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb0 = XS1_CLKBLK_1; @@ -24,37 +23,60 @@ void flush_print(void){ } void app(client interface spi_master_async_if i, int mosi_enabled, - int miso_enabled, chanend c, unsigned speed){ + int miso_enabled, streaming chanend c, unsigned speed){ set_core_fast_mode_on(); - uint32_t tx[1]; - uint32_t rx[1]; + uint32_t tx[8] = {0xed, 0xc0ffee, 0x0000000f, 0x000000f0, 0x00000f00, 0x0000f000, 0x000f0000, 0x00f00000}; + uint32_t rx[8] = {0x0}; uint32_t * movable tx_ptr = tx; uint32_t * movable rx_ptr = rx; while(1){ - i.begin_transaction(0, speed, SPI_MODE_3); - i.init_transfer_array_32(move(rx_ptr), move(tx_ptr), 1); + c <: 0; + i.begin_transaction(0, speed, SPI_MODE_0); + c <: 1; + i.init_transfer_array_32(move(rx_ptr), move(tx_ptr), sizeof(tx)/sizeof(tx[0])); + c <: 2; select { case i.transfer_complete():{ break; } } + c <: 3; i.retrieve_transfer_buffers_32(rx_ptr, tx_ptr); + + if(MOSI_ENABLED && (tx_ptr[0] != rx_ptr[0] || tx_ptr[1] != rx_ptr[1])){ + printf("Loopback didn't work!\n"); + printf("Tx: 0x%x 0x%x, Rx: 0x%x 0x%x\n", tx_ptr[0], tx_ptr[1], rx_ptr[0], rx_ptr[1]); + _Exit(1); + } else { + // printf("Loopback PASS\n"); + } + c <: 4; i.end_transaction(100); - c <: 1; + c <: 5; + + int holdoff_ticks = (10000 - speed) * 10; + delay_ticks(holdoff_ticks); //Ensure one client doesn't hog the test } } #define CLIENTS 3 [[combinable]] -void watcher(chanend c[CLIENTS]){ +void watcher(streaming chanend c[CLIENTS]){ int seen[CLIENTS] = {0}; set_core_fast_mode_on(); //TODO maybe put a timeout in here while(1){ select{ - case c[int i] :> int:{ - seen[i] = 1; + case c[int i] :> int token:{ + timer t; + int time; + t :> time; + // printf("Got %d from client: %d @ %d\n",token, i, time); + + if(token == 5){ + seen[i] = 1; + } int any_not_seen = 0; for(unsigned j=0;j +#include +#include +#include +#include "spi.h" +#include "spi_async_tester.h" + +in buffered port:32 p_miso = XS1_PORT_1A; +out port p_ss = XS1_PORT_1B; +out buffered port:32 p_sclk = XS1_PORT_1C; +out buffered port:32 p_mosi = XS1_PORT_1D; +clock cb0 = XS1_CLKBLK_1; +clock cb1 = XS1_CLKBLK_2; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; + +#define SPI_MODE SPI_MODE_0 +#define TRANSFER_WIDTH 8 +#define SPI_KBPS 10000 + +typedef enum { + SPI_TRANSFER_WIDTH_8, + SPI_TRANSFER_WIDTH_32 +} t_transfer_width; + +void flush_print(void){ + delay_microseconds(1000); +} + +/* This counts up to 16 bytes (steps of 4 if 32b) */ +static void inc_state(unsigned &count, spi_mode_t &mode, t_transfer_width &transfer_width){ + // printf("count: %u\n", count); + if(count == 16){ + printf("Transfers complete\n"); + flush_print(); + _Exit(0); + } else { + if(transfer_width == SPI_TRANSFER_WIDTH_8){ + count++; + } else { + count+=4; + } + } + // printf("count: %u, mode: %d width: %d\n", count, mode, transfer_width * 24 + 8); +} + +void app(client interface spi_master_async_if spi_i){ + uint8_t tx8[NUMBER_OF_TEST_BYTES]; + uint8_t rx8[NUMBER_OF_TEST_BYTES]; + + for(unsigned i=0;i None: expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - # print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} mosi {expected_miso_enabled} miso {expected_miso_enabled} expected_device_id {expected_device_id} expected_interframe_space {expected_interframe_space} expected_num_bytes {expected_num_bytes}") + # print(f"Got Settings cpol:{expected_cpol} cpha:{expected_cpha} mosi:{expected_miso_enabled} miso:{expected_miso_enabled} expected_frequency_in_khz:{expected_frequency_in_khz} expected_device_id:{expected_device_id} expected_interframe_space:{expected_interframe_space} expected_num_bytes:{expected_num_bytes}") clock_half_period = millisecond_ticks / (expected_frequency_in_khz*2) @@ -138,7 +138,7 @@ def run(self) -> None: clock_event_time = xsi.get_time() measured_time_elapsed = clock_event_time - last_clock_event_time if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : - print(f"ERROR: Clock half period less than allowed for given SCLK frequency, measured_time_elapsed: {measured_time_elapsed/nanosecond_ticks}ns clock_half_period:{clock_half_period/nanosecond_ticks}ns") + print(f"ERROR: Clock half period less than allowed for given SCLK frequency, measured_time_elapsed: {measured_time_elapsed/nanosecond_ticks:.2f}ns clock_half_period:{clock_half_period/nanosecond_ticks}ns, at time: {xsi.get_time() / nanosecond_ticks}ns") error = True last_clock_event_time = clock_event_time @@ -169,13 +169,13 @@ def run(self) -> None: expected_rx_byte = rx_data[(rx_bit_counter//8) - 1] #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) if expected_rx_byte != rx_byte: - print(f"ERROR: slave recieved incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x} at time: {xsi.get_time() / nanosecond_ticks}ns") + print(f"ERROR: slave received incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x} at time: {xsi.get_time() / nanosecond_ticks}ns") error = True # print(f"Checker got byte: {rx_byte:02x} at time {xsi.get_time() / nanosecond_ticks}ns") rx_byte = 0 else: if clock_edge_number != expected_num_bytes*2*8: error = True - print(f"ERROR: incorrect number of clock edges at slave {clock_edge_number}/{expected_num_bytes*2*8}") + print(f"ERROR: incorrect number of clock edges at slave {clock_edge_number}/{expected_num_bytes*2*8} at time: {xsi.get_time() / nanosecond_ticks}ns") if error: print(f"Fail: CPOL:{expected_cpol} CPHA:{expected_cpha} KHz:{expected_frequency_in_khz} MOSI Enabled:{expected_mosi_enabled} MISO Enabled:{expected_miso_enabled}") diff --git a/tests/spi_master_sync_shutdown/CMakeLists.txt b/tests/spi_master_sync_shutdown/CMakeLists.txt new file mode 100644 index 0000000..01665b5 --- /dev/null +++ b/tests/spi_master_sync_shutdown/CMakeLists.txt @@ -0,0 +1,21 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + +project(spi_master_sync_shutdown) +set(target "XK-EVK-XU316") +set(APP_HW_TARGET ${target}) + +set(COMPILER_FLAGS_COMMON -O2 + -g + -Wno-reinterpret-alignment) + + +set(APP_COMPILER_FLAGS ${COMPILER_FLAGS_COMMON}) + +set(APP_INCLUDES src ../spi_master_tester_common) + +XMOS_REGISTER_APP() diff --git a/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc new file mode 100644 index 0000000..3014919 --- /dev/null +++ b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc @@ -0,0 +1,51 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" +#include "spi_sync_tester.h" + +in buffered port:32 p_miso = XS1_PORT_1A; +out port p_ss = XS1_PORT_1B; +out buffered port:32 p_sclk = XS1_PORT_1C; +out buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; + +#define SPI_MODE SPI_MODE_0 +#define SPI_KBPS 10000 + +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ + for(int loop = 0; loop < 10; loop++){ + test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); + + i.shutdown(); + + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); + + i.shutdown(); + } + + printf("Transfers complete\n"); + _Exit(0); +} + + +int main(){ + interface spi_master_if i[1]; + par { + { + while(1){ + spi_master_fwk(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + } + } + app(i[0], 1, 1, SPI_MODE); + } + return 0; +} diff --git a/tests/spi_master_tester_common/spi_async_tester.h b/tests/spi_master_tester_common/spi_async_tester.h index 226fdad..a2dcbb9 100644 --- a/tests/spi_master_tester_common/spi_async_tester.h +++ b/tests/spi_master_tester_common/spi_async_tester.h @@ -3,7 +3,7 @@ #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ -#define VERBOSE 0 +#define VERBOSE 1 #include "common.h" diff --git a/tests/spi_master_tester_common/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h index 3004f54..8770877 100644 --- a/tests/spi_master_tester_common/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -56,7 +56,10 @@ int test_transfer32(client interface spi_master_if i, mode, speed_in_kbps, mosi_enabled, miso_enabled, device_id, inter_frame_gap, NUMBER_OF_TEST_BYTES); i.begin_transaction(device_id, speed_in_kbps, mode); for(unsigned j=0;j Date: Fri, 25 Jul 2025 10:55:48 +0100 Subject: [PATCH 26/57] Bump to 4.0.0, remove second clockblock from async and consolidate SPI master changes --- CHANGELOG.rst | 8 + README.rst | 2 +- examples/AN00160_using_SPI_master/src/main.xc | 6 +- lib_spi/api/spi.h | 21 +- lib_spi/lib_build_info.cmake | 5 +- lib_spi/module_build_info | 5 +- lib_spi/src/spi_async.xc | 419 ------------------ ...aster_async_fwk.xc => spi_master_async.xc} | 11 +- ...aster_shared_fwk.h => spi_master_shared.h} | 15 + ...ter_shared_fwk.xc => spi_master_shared.xc} | 76 ++++ ..._master_sync_fwk.xc => spi_master_sync.xc} | 3 +- lib_spi/src/spi_sync.xc | 356 --------------- .../src/spi_master_async_multi_client.xc | 7 +- .../src/spi_master_async_multi_device.xc | 5 +- .../src/spi_master_async_rx_tx.xc | 7 +- .../src/spi_master_async_shutdown.xc | 5 +- 16 files changed, 125 insertions(+), 826 deletions(-) delete mode 100644 lib_spi/src/spi_async.xc rename lib_spi/src/{spi_master_async_fwk.xc => spi_master_async.xc} (98%) rename lib_spi/src/{spi_master_shared_fwk.h => spi_master_shared.h} (56%) rename lib_spi/src/{spi_master_shared_fwk.xc => spi_master_shared.xc} (51%) rename lib_spi/src/{spi_master_sync_fwk.xc => spi_master_sync.xc} (99%) delete mode 100644 lib_spi/src/spi_sync.xc diff --git a/CHANGELOG.rst b/CHANGELOG.rst index bc86a06..4550173 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,6 +1,14 @@ lib_spi change log ================== +4.0.0 +----- + + * CHANGED: SPI master async reduced clock blocks from two to one + * CHANGED: SPI master sync increased max speed to 25+ Mbps + * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 + * RESOLVED: Non-funcional tests + 3.4.0 ----- diff --git a/README.rst b/README.rst index 0d86554..8c35180 100644 --- a/README.rst +++ b/README.rst @@ -5,7 +5,7 @@ lib_spi: SPI library #################### :vendor: XMOS -:version: 3.4.0 +:version: 4.0.0 :scope: General Use :description: SPI Master and Slave components :category: General Purpose diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index bad72b8..516df3f 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -13,8 +13,7 @@ in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; -clock clk0 = on tile[0]: XS1_CLKBLK_1; -clock clk1 = on tile[0]: XS1_CLKBLK_2; +clock clk = on tile[0]: XS1_CLKBLK_1; /* This application function sends some traffic as SPI master using * the synchronous interface. It reads the config register (address 0) @@ -116,8 +115,7 @@ int main(void) { par { async_app(i_spi_async[0]); spi_master_async(i_spi_async, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - clk0, clk1); + p_sclk, p_mosi, p_miso, p_ss, 1, clk); } } } diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index defcaf3..14e2b4d 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -313,26 +313,12 @@ typedef interface spi_master_async_if { * \param sclk the SPI clock port. * \param mosi the SPI MOSI (master out, slave in) port. * \param miso the SPI MISO (master in, slave out) port. - * \param p_ss an array of ports connected to the slave select signals - * of the slave. + * \param p_ss a port of any width which outputs the slave select signals * \param num_slaves The number of slave devices on the bus. - * \param clk0 a clock for the component to use. - * \param clk1 a clock for the component to use. + * \param clk a clock block for the component to use. */ [[combinable]] void spi_master_async( - SERVER_INTERFACE(spi_master_async_if, i[num_clients]), - static_const_size_t num_clients, - out_buffered_port_32_t sclk, - NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), - in_buffered_port_32_t miso, - out_port p_ss[num_slaves], - static_const_size_t num_slaves, - clock clk0, - clock clk1); - -[[combinable]] -void spi_master_async_fwk( SERVER_INTERFACE(spi_master_async_if, i[num_clients]), static_const_size_t num_clients, out_buffered_port_32_t sclk, @@ -340,8 +326,7 @@ void spi_master_async_fwk( in_buffered_port_32_t miso, out_port p_ss, static_const_size_t num_slaves, - clock clk0, - clock clk1); + clock clk); /**** SLAVE ****/ diff --git a/lib_spi/lib_build_info.cmake b/lib_spi/lib_build_info.cmake index 11a0822..6649354 100644 --- a/lib_spi/lib_build_info.cmake +++ b/lib_spi/lib_build_info.cmake @@ -1,7 +1,6 @@ set(LIB_NAME lib_spi) -set(LIB_VERSION 3.4.0) +set(LIB_VERSION 4.0.0) set(LIB_INCLUDES api) set(LIB_DEPENDENT_MODULES "") -set(LIB_COMPILER_FLAGS_spi_async.xc -Wno-reinterpret-alignment) -set(LIB_COMPILER_FLAGS_spi_master_async_fwk.xc -Wno-reinterpret-alignment) +set(LIB_COMPILER_FLAGS_spi_master_async.xc -Wno-reinterpret-alignment) XMOS_REGISTER_MODULE() diff --git a/lib_spi/module_build_info b/lib_spi/module_build_info index 13ba169..933bf31 100644 --- a/lib_spi/module_build_info +++ b/lib_spi/module_build_info @@ -1,4 +1,3 @@ -VERSION = 3.4.0 +VERSION = 4.0.0 -XCC_FLAGS_spi_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment -XCC_FLAGS_spi_master_async_fwk.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment \ No newline at end of file +XCC_FLAGS_spi_master_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment \ No newline at end of file diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc deleted file mode 100644 index e83dad4..0000000 --- a/lib_spi/src/spi_async.xc +++ /dev/null @@ -1,419 +0,0 @@ -// Copyright 2015-2025 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include - -#include -#include "spi.h" - -typedef struct { - unsigned client_id; - unsigned device_index; - unsigned speed_in_khz; - spi_mode_t mode; - size_t buffer_nbytes; - unsigned buffer_transfer_width; - uint32_t * movable buffer_tx; - uint32_t * movable buffer_rx; - -} transaction_request; -#define NBYTES_UNASSIGNED (-1) - -static void transfer8_async( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - uint8_t data){ - // printf("0x%x\n", data); - - if(!isnull(mosi)) { - clearbuf(mosi); - mosi <: (bitrev(data)>>24); // This outputs LSb first so reverse. - } - - clearbuf(miso); //TODO remove- if possible - - partout(sclk, 16, 0xaaaa); -} - -static void transfer32_async( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - uint32_t data){ - - if(!isnull(mosi)) { - clearbuf(mosi); - mosi <: bitrev(byterev(data)); - } - - clearbuf(miso); //TODO remove - if possible - - //output 64 bits of clock - sclk <: 0xaaaaaaaa; - sclk <: 0xaaaaaaaa; -} - -static void setup_new_transaction( - out buffered port:32 sclk, - out port p_ss[], - clock cb0, - spi_mode_t mode, - unsigned new_device_index, - unsigned speed_in_khz, - unsigned ¤tly_selected_device){ - //xassert(device_index < num_slaves); - switch(mode){ - case SPI_MODE_0: - set_port_inv(sclk); - partout(sclk,1,1); - break; - case SPI_MODE_1: - set_port_no_inv(sclk); - partout(sclk,1,0); - break; - case SPI_MODE_2: - set_port_inv(sclk); - partout(sclk,1,0); - break; - case SPI_MODE_3: - set_port_no_inv(sclk); - partout(sclk,1,1); - break; - } - sync(sclk); - - //Wait for the chip deassert time if need be - if(new_device_index == currently_selected_device) - sync(p_ss[currently_selected_device]); - - //Set the clock divider - stop_clock(cb0); - unsigned d = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz); - configure_clock_ref(cb0, d); - start_clock(cb0); - - //Do a slave select - currently_selected_device = new_device_index; - p_ss[currently_selected_device] <: 0; - sync(p_ss[currently_selected_device]); -} - -static void init_transfer_array_8( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - spi_mode_t active_mode, - clock cb1, - uint8_t data - ){ - if(!isnull(mosi)) - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - - // In modes 0 and 2 we need to present the first data bit BEFORE we clock - if((active_mode == SPI_MODE_0 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ - unsigned b = data>>7; - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); - partout(mosi, 1, b); - sync(mosi); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); - data = data<<1; //This is shifted up as the MSB is already on this pin - } - transfer8_async(sclk, mosi, miso, data); -} - -static void first_transfer_array_32( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - spi_mode_t active_mode, - clock cb1, - uint32_t data){ - - if(!isnull(mosi)) - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(32)); - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(32)); - - // In modes 0 and 2 we need to present the first data bit BEFORE we clock - if((active_mode == SPI_MODE_0 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ - unsigned b = bitrev(data); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); - partout(mosi, 1, b); - sync(mosi); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); - data = data<<1; //This is shifted up as the MSB is already on this pin - } - transfer32_async(sclk, mosi, miso, data); -} - -[[combinable]] -void spi_master_async(server interface spi_master_async_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock cb0, - clock cb1){ - - //These buffer are for the transaction requests - transaction_request tr_buffer[8]; ///FIXME num_clients - unsigned tr_tail = 0; - unsigned tr_fill = 0; - - //These buffers are for the active transaction - uint32_t * movable buffer_tx; - uint32_t * movable buffer_rx; - size_t buffer_nbytes; - unsigned current_index; - unsigned buffer_transfer_width; - - //These variables are for the active transaction state - unsigned active_device; - unsigned active_client; - unsigned active_mode; - int currently_performing_a_transaction = 0; - - for(unsigned i=0;i 0xffff) - delay_ticks(ss_deassert_time&0xffff0000); - time += ss_deassert_time; - p_ss[active_device] @ time <: 0xffffffff; - - if(tr_fill > 0){ - //begin a new transaction - the tail of the list is the next one to go - unsigned index = tr_tail%num_clients; - unsigned new_device_index = tr_buffer[index].device_index; - unsigned speed_in_khz = tr_buffer[index].speed_in_khz; - spi_mode_t mode = tr_buffer[index].mode; - - active_client = tr_buffer[index].client_id; - - tr_fill--; - tr_tail++; - - setup_new_transaction(sclk, p_ss, cb0, mode, new_device_index, - speed_in_khz, active_device); - active_device = new_device_index; - active_mode = mode; - - buffer_nbytes = tr_buffer[index].buffer_nbytes; - - if(buffer_nbytes != NBYTES_UNASSIGNED){ - buffer_tx = move(tr_buffer[index].buffer_tx); - buffer_rx = move(tr_buffer[index].buffer_rx); - buffer_transfer_width = tr_buffer[index].buffer_transfer_width; - if(buffer_transfer_width == 8){ - init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); - } else { - first_transfer_array_32(sclk, mosi, miso, active_mode, cb1, buffer_tx[0]); - } - current_index = 0; - } - } else { - currently_performing_a_transaction = 0; - } - break; - } - case i[int x].init_transfer_array_8(uint8_t * movable inbuf, - uint8_t * movable outbuf, size_t nbytes) :{ - - if(x != active_client){ - unsigned index; - for(unsigned j=0;j uint32_t data :{ - //put the data into the correct array and send the next data if need be - if(buffer_transfer_width == 8){ - data = bitrev(data<<24); - ((uint8_t*movable)buffer_rx)[current_index] = (uint8_t)data; - current_index++; - if((current_index*sizeof(uint8_t)) == buffer_nbytes){ - i[active_client].transfer_complete(); - } else { - // We need to handle the mode 0 data before clock so now using this - init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[current_index]); - // transfer8_async(sclk, mosi, miso, - // ((uint8_t*movable)buffer_tx)[current_index]); - } - } else { - data = bitrev(data); - buffer_rx[current_index] = data; - current_index++; - if((current_index*sizeof(uint32_t)) == buffer_nbytes){ - i[active_client].transfer_complete(); - } else { - // We need to handle the mode 0 data before clock so now using this - first_transfer_array_32(sclk, mosi, miso, active_mode, cb1, buffer_tx[current_index]); - // transfer32_async(sclk, mosi, miso, buffer_tx[current_index]); - } - } - break; - } - case i[int x].retrieve_transfer_buffers_8(uint8_t * movable &inbuf, - uint8_t * movable &outbuf):{ - inbuf = (uint8_t*movable)move(buffer_rx); - outbuf = (uint8_t*movable)move(buffer_tx); - break; - } - - case i[int x].retrieve_transfer_buffers_32(uint32_t * movable &inbuf, - uint32_t * movable &outbuf):{ - inbuf = move(buffer_rx); - outbuf = move(buffer_tx); - break; - } - - case i[int x].set_ss_port_bit(unsigned port_bit):{ - // Do nothing this is invalid since this component sets all port bits high/low during select - break; - } - - case i[int x].shutdown(void): - move(buffer_rx); - move(buffer_tx); - set_port_use_on(sclk); - if(!isnull(mosi)) set_port_use_on(mosi); - if(!isnull(miso)) set_port_use_on(miso); - return; - } - } - -} diff --git a/lib_spi/src/spi_master_async_fwk.xc b/lib_spi/src/spi_master_async.xc similarity index 98% rename from lib_spi/src/spi_master_async_fwk.xc rename to lib_spi/src/spi_master_async.xc index 23dc36f..83016c7 100644 --- a/lib_spi/src/spi_master_async_fwk.xc +++ b/lib_spi/src/spi_master_async.xc @@ -10,7 +10,7 @@ extern "C"{ #include "spi_fwk.h" } -#include "spi_master_shared_fwk.h" +#include "spi_master_shared.h" #define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device @@ -29,15 +29,14 @@ typedef struct { [[combinable]] -void spi_master_async_fwk(server interface spi_master_async_if i[num_clients], +void spi_master_async(server interface spi_master_async_if i[num_clients], static const size_t num_clients, out buffered port:32 sclk, out buffered port:32 ?mosi, in buffered port:32 miso, out port p_ss, static const size_t num_slaves, - clock cb0, - clock cb1){ + clock cb){ //These buffer are for the transaction requests transaction_request tr_buffer[num_clients]; ///FIXME num_clients @@ -61,7 +60,7 @@ void spi_master_async_fwk(server interface spi_master_async_if i[num_clients], spi_master_t spi_master; spi_master_device_t spi_dev; unsafe{ - spi_master_init(&spi_master, cb0, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); } // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) @@ -339,7 +338,7 @@ void spi_master_async_fwk(server interface spi_master_async_if i[num_clients], } set_port_use_on(miso); set_port_use_on(sclk); - set_clock_on(cb0); + set_clock_on(cb); return; } } diff --git a/lib_spi/src/spi_master_shared_fwk.h b/lib_spi/src/spi_master_shared.h similarity index 56% rename from lib_spi/src/spi_master_shared_fwk.h rename to lib_spi/src/spi_master_shared.h index 478a548..c4a105e 100644 --- a/lib_spi/src/spi_master_shared_fwk.h +++ b/lib_spi/src/spi_master_shared.h @@ -14,6 +14,21 @@ extern "C"{ #include "spi_fwk.h" } +// Clockblock-less SPI transfer functions. These are slow (max around 1 Mbps) but are suitable for control transfer +// When clockblock resources are scarce +int8_t transfer8_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint8_t data, const unsigned period, + unsigned cpol, unsigned cpha); + +uint32_t transfer32_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint32_t data, const unsigned period, + const unsigned cpol, const unsigned cpha); // Optional function to determine the actual set speed for particular clock settings. unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider); diff --git a/lib_spi/src/spi_master_shared_fwk.xc b/lib_spi/src/spi_master_shared.xc similarity index 51% rename from lib_spi/src/spi_master_shared_fwk.xc rename to lib_spi/src/spi_master_shared.xc index a509fdb..1a8e8b7 100644 --- a/lib_spi/src/spi_master_shared_fwk.xc +++ b/lib_spi/src/spi_master_shared.xc @@ -15,6 +15,82 @@ extern "C"{ } +#pragma unsafe arrays +uint8_t transfer8_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint8_t data, const unsigned period, + unsigned cpol, unsigned cpha){ + unsigned time, d, c = 0xaaaa>>(cpol ^ cpha); + time = partout_timestamped(sclk, 1, cpol); + time += 40; + + for(unsigned i=0;i<8;i++){ + partout_timed(sclk, 1, c, time); + c>>=1; + //sclk @ time <:>> c; + + if(!isnull(mosi)){ + partout_timed(mosi, 1, data>>7, time); + data<<=1; + } + time += period / 2; + + partout_timed(sclk, 1, c, time); + c>>=1; + if(!isnull(miso)){ + unsigned t; + miso @ time - 1 :> t; + d = (d<<1) + (t&1); + } + time += (period + 1)/2; + } + partout_timed(sclk, 1, cpol, time); + sync(sclk); + return d; +} + +#pragma unsafe arrays +uint32_t transfer32_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint32_t data, const unsigned period, + const unsigned cpol, const unsigned cpha){ + unsigned time; + uint32_t d; + time = partout_timestamped(sclk, 1, cpol); + time += 100; + + //bitrev the data + for(unsigned j=0;j<2;j++){ + unsigned c = 0xaaaaaaaa>>(cpol ^ cpha); + for(unsigned i=0;i<16;i++){ + partout_timed(sclk, 1, c, time); + if(!isnull(mosi)){ + partout_timed(mosi, 1, data>>31, time); + data<<=1; + } + c>>=1; + time += period / 2; + partout_timed(sclk, 1, c, time); + c>>=1; + if(!isnull(miso)){ + unsigned t; + miso @ time - 1 :> t; + d = (d<<1) + (t&1); + } + time += (period + 1)/2; + } + time += 80; + } + partout_timed(sclk, 1, cpol, time); + sync(sclk); + return d; +} + + // Optional function to determine the actual set speed for particular clock settings. unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 diff --git a/lib_spi/src/spi_master_sync_fwk.xc b/lib_spi/src/spi_master_sync.xc similarity index 99% rename from lib_spi/src/spi_master_sync_fwk.xc rename to lib_spi/src/spi_master_sync.xc index 204dfaa..73fee38 100644 --- a/lib_spi/src/spi_master_sync_fwk.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -13,7 +13,7 @@ extern "C"{ #include "spi_fwk.h" } -#include "spi_master_shared_fwk.h" +#include "spi_master_shared.h" #define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device @@ -129,4 +129,3 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], } } - diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc deleted file mode 100644 index 25a05c4..0000000 --- a/lib_spi/src/spi_sync.xc +++ /dev/null @@ -1,356 +0,0 @@ -// Copyright 2015-2025 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include - -#include "spi.h" - -static const uint16_t ziptable[256] = { 0x0000, 0xc000, 0x3000, 0xf000, 0x0c00, - 0xcc00, 0x3c00, 0xfc00, 0x0300, 0xc300, 0x3300, 0xf300, 0x0f00, 0xcf00, - 0x3f00, 0xff00, 0x00c0, 0xc0c0, 0x30c0, 0xf0c0, 0x0cc0, 0xccc0, 0x3cc0, - 0xfcc0, 0x03c0, 0xc3c0, 0x33c0, 0xf3c0, 0x0fc0, 0xcfc0, 0x3fc0, 0xffc0, - 0x0030, 0xc030, 0x3030, 0xf030, 0x0c30, 0xcc30, 0x3c30, 0xfc30, 0x0330, - 0xc330, 0x3330, 0xf330, 0x0f30, 0xcf30, 0x3f30, 0xff30, 0x00f0, 0xc0f0, - 0x30f0, 0xf0f0, 0x0cf0, 0xccf0, 0x3cf0, 0xfcf0, 0x03f0, 0xc3f0, 0x33f0, - 0xf3f0, 0x0ff0, 0xcff0, 0x3ff0, 0xfff0, 0x000c, 0xc00c, 0x300c, 0xf00c, - 0x0c0c, 0xcc0c, 0x3c0c, 0xfc0c, 0x030c, 0xc30c, 0x330c, 0xf30c, 0x0f0c, - 0xcf0c, 0x3f0c, 0xff0c, 0x00cc, 0xc0cc, 0x30cc, 0xf0cc, 0x0ccc, 0xcccc, - 0x3ccc, 0xfccc, 0x03cc, 0xc3cc, 0x33cc, 0xf3cc, 0x0fcc, 0xcfcc, 0x3fcc, - 0xffcc, 0x003c, 0xc03c, 0x303c, 0xf03c, 0x0c3c, 0xcc3c, 0x3c3c, 0xfc3c, - 0x033c, 0xc33c, 0x333c, 0xf33c, 0x0f3c, 0xcf3c, 0x3f3c, 0xff3c, 0x00fc, - 0xc0fc, 0x30fc, 0xf0fc, 0x0cfc, 0xccfc, 0x3cfc, 0xfcfc, 0x03fc, 0xc3fc, - 0x33fc, 0xf3fc, 0x0ffc, 0xcffc, 0x3ffc, 0xfffc, 0x0003, 0xc003, 0x3003, - 0xf003, 0x0c03, 0xcc03, 0x3c03, 0xfc03, 0x0303, 0xc303, 0x3303, 0xf303, - 0x0f03, 0xcf03, 0x3f03, 0xff03, 0x00c3, 0xc0c3, 0x30c3, 0xf0c3, 0x0cc3, - 0xccc3, 0x3cc3, 0xfcc3, 0x03c3, 0xc3c3, 0x33c3, 0xf3c3, 0x0fc3, 0xcfc3, - 0x3fc3, 0xffc3, 0x0033, 0xc033, 0x3033, 0xf033, 0x0c33, 0xcc33, 0x3c33, - 0xfc33, 0x0333, 0xc333, 0x3333, 0xf333, 0x0f33, 0xcf33, 0x3f33, 0xff33, - 0x00f3, 0xc0f3, 0x30f3, 0xf0f3, 0x0cf3, 0xccf3, 0x3cf3, 0xfcf3, 0x03f3, - 0xc3f3, 0x33f3, 0xf3f3, 0x0ff3, 0xcff3, 0x3ff3, 0xfff3, 0x000f, 0xc00f, - 0x300f, 0xf00f, 0x0c0f, 0xcc0f, 0x3c0f, 0xfc0f, 0x030f, 0xc30f, 0x330f, - 0xf30f, 0x0f0f, 0xcf0f, 0x3f0f, 0xff0f, 0x00cf, 0xc0cf, 0x30cf, 0xf0cf, - 0x0ccf, 0xcccf, 0x3ccf, 0xfccf, 0x03cf, 0xc3cf, 0x33cf, 0xf3cf, 0x0fcf, - 0xcfcf, 0x3fcf, 0xffcf, 0x003f, 0xc03f, 0x303f, 0xf03f, 0x0c3f, 0xcc3f, - 0x3c3f, 0xfc3f, 0x033f, 0xc33f, 0x333f, 0xf33f, 0x0f3f, 0xcf3f, 0x3f3f, - 0xff3f, 0x00ff, 0xc0ff, 0x30ff, 0xf0ff, 0x0cff, 0xccff, 0x3cff, 0xfcff, - 0x03ff, 0xc3ff, 0x33ff, 0xf3ff, 0x0fff, 0xcfff, 0x3fff, 0xffff -}; - -static const uint8_t unshuffle[256] = { - 0x00, 0x10, 0x01, 0x11, 0x20, 0x30, 0x21, 0x31, - 0x02, 0x12, 0x03, 0x13, 0x22, 0x32, 0x23, 0x33, - 0x40, 0x50, 0x41, 0x51, 0x60, 0x70, 0x61, 0x71, - 0x42, 0x52, 0x43, 0x53, 0x62, 0x72, 0x63, 0x73, - 0x04, 0x14, 0x05, 0x15, 0x24, 0x34, 0x25, 0x35, - 0x06, 0x16, 0x07, 0x17, 0x26, 0x36, 0x27, 0x37, - 0x44, 0x54, 0x45, 0x55, 0x64, 0x74, 0x65, 0x75, - 0x46, 0x56, 0x47, 0x57, 0x66, 0x76, 0x67, 0x77, - 0x80, 0x90, 0x81, 0x91, 0xa0, 0xb0, 0xa1, 0xb1, - 0x82, 0x92, 0x83, 0x93, 0xa2, 0xb2, 0xa3, 0xb3, - 0xc0, 0xd0, 0xc1, 0xd1, 0xe0, 0xf0, 0xe1, 0xf1, - 0xc2, 0xd2, 0xc3, 0xd3, 0xe2, 0xf2, 0xe3, 0xf3, - 0x84, 0x94, 0x85, 0x95, 0xa4, 0xb4, 0xa5, 0xb5, - 0x86, 0x96, 0x87, 0x97, 0xa6, 0xb6, 0xa7, 0xb7, - 0xc4, 0xd4, 0xc5, 0xd5, 0xe4, 0xf4, 0xe5, 0xf5, - 0xc6, 0xd6, 0xc7, 0xd7, 0xe6, 0xf6, 0xe7, 0xf7, - 0x08, 0x18, 0x09, 0x19, 0x28, 0x38, 0x29, 0x39, - 0x0a, 0x1a, 0x0b, 0x1b, 0x2a, 0x3a, 0x2b, 0x3b, - 0x48, 0x58, 0x49, 0x59, 0x68, 0x78, 0x69, 0x79, - 0x4a, 0x5a, 0x4b, 0x5b, 0x6a, 0x7a, 0x6b, 0x7b, - 0x0c, 0x1c, 0x0d, 0x1d, 0x2c, 0x3c, 0x2d, 0x3d, - 0x0e, 0x1e, 0x0f, 0x1f, 0x2e, 0x3e, 0x2f, 0x3f, - 0x4c, 0x5c, 0x4d, 0x5d, 0x6c, 0x7c, 0x6d, 0x7d, - 0x4e, 0x5e, 0x4f, 0x5f, 0x6e, 0x7e, 0x6f, 0x7f, - 0x88, 0x98, 0x89, 0x99, 0xa8, 0xb8, 0xa9, 0xb9, - 0x8a, 0x9a, 0x8b, 0x9b, 0xaa, 0xba, 0xab, 0xbb, - 0xc8, 0xd8, 0xc9, 0xd9, 0xe8, 0xf8, 0xe9, 0xf9, - 0xca, 0xda, 0xcb, 0xdb, 0xea, 0xfa, 0xeb, 0xfb, - 0x8c, 0x9c, 0x8d, 0x9d, 0xac, 0xbc, 0xad, 0xbd, - 0x8e, 0x9e, 0x8f, 0x9f, 0xae, 0xbe, 0xaf, 0xbf, - 0xcc, 0xdc, 0xcd, 0xdd, 0xec, 0xfc, 0xed, 0xfd, - 0xce, 0xde, 0xcf, 0xdf, 0xee, 0xfe, 0xef, 0xff -}; - - - -#pragma unsafe arrays -static uint8_t transfer8_sync_zero_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint8_t data, const unsigned period, - unsigned cpol, unsigned cpha){ - unsigned time, d, c = 0xaaaa>>(cpol ^ cpha); - time = partout_timestamped(sclk, 1, cpol); - time += 40; - - for(unsigned i=0;i<8;i++){ - partout_timed(sclk, 1, c, time); - c>>=1; - //sclk @ time <:>> c; - - if(!isnull(mosi)){ - partout_timed(mosi, 1, data>>7, time); - data<<=1; - } - time += period / 2; - - partout_timed(sclk, 1, c, time); - c>>=1; - if(!isnull(miso)){ - unsigned t; - miso @ time - 1 :> t; - d = (d<<1) + (t&1); - } - time += (period + 1)/2; - } - partout_timed(sclk, 1, cpol, time); - sync(sclk); - return d; -} - -#pragma unsafe arrays -static uint32_t transfer32_sync_zero_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint32_t data, const unsigned period, - const unsigned cpol, const unsigned cpha){ - unsigned time; - uint32_t d; - time = partout_timestamped(sclk, 1, cpol); - time += 100; - - //bitrev the data - for(unsigned j=0;j<2;j++){ - unsigned c = 0xaaaaaaaa>>(cpol ^ cpha); - for(unsigned i=0;i<16;i++){ - partout_timed(sclk, 1, c, time); - if(!isnull(mosi)){ - partout_timed(mosi, 1, data>>31, time); - data<<=1; - } - c>>=1; - time += period / 2; - partout_timed(sclk, 1, c, time); - c>>=1; - if(!isnull(miso)){ - unsigned t; - miso @ time - 1 :> t; - d = (d<<1) + (t&1); - } - time += (period + 1)/2; - } - time += 80; - } - partout_timed(sclk, 1, cpol, time); - sync(sclk); - return d; -} - -#pragma unsafe arrays -static unsigned zip8(uint8_t a){ - return ziptable[a]; -} - -#pragma unsafe arrays -static void zip32(uint32_t a, uint32_t &x, uint32_t &y){ - //This can be improved - y = zip8(a&0xff); - a=a>>8; - y = (y << 16)| (zip8(a&0xff)); - a=a>>8; - x = zip8(a&0xff); - a=a>>8; - x = (x << 16)| (zip8(a&0xff)); -} - -#pragma unsafe arrays -static uint8_t unzip_16(unsigned d){ - d = d & 0x55aa; - d = d | (d>>8); - return bitrev(unshuffle[d&0xff])>>24; -} - -#pragma unsafe arrays -static uint16_t unzip_32(unsigned d){ - return unzip_16(d&0xffff) |(unzip_16(d>>16)<<8); -} - -static unsigned make_8bit_clock(unsigned cpol, unsigned cpha){ - return (0xaaaa >> (cpha)) ^ - cpol; -} -static uint8_t transfer8_sync_one_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint8_t data, - unsigned cpol, unsigned cpha){ - unsigned double_clock = make_8bit_clock(cpol, cpha); - uint16_t double_data = zip8(data); - unsigned t = partout_timestamped(sclk, 1, cpol); - t+=80; - partout_timed(sclk, 17, double_clock, t); - if(!isnull(mosi))partout_timed(mosi, 16, double_data, t); - if(!isnull(miso)) miso @ t + 31 :> double_data; - return unzip_16(double_data); -} - -static uint32_t transfer32_sync_one_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint32_t data, - unsigned cpol, unsigned cpha){ - - unsigned t; - unsigned double_clock = 0xaaaaaaaa>>(cpol ^ cpha); - - uint32_t double_data_0; - uint32_t double_data_1; - zip32(data, double_data_0, double_data_1); - t = partout_timestamped(sclk, 1, cpol); - t+=80; - sclk @ t <: double_clock; - if(!isnull(mosi))mosi @ t<: double_data_0; - sclk <: double_clock; - if(!isnull(mosi))mosi <: double_data_1; - if(!isnull(miso))miso @ t + 31:> double_data_0; - if(!isnull(miso))miso :> double_data_1; - - return byterev(unzip_32(double_data_0) | (unzip_32(double_data_1)<<16)); -} - -static void get_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 0; break; - case SPI_MODE_1:cpol = 0; cpha= 1; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -///////////////////////////////////////////////////////////////////////////////////////////////////// -#pragma unsafe arrays -[[distributable]] -void spi_master(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock ?cb){ - - for(unsigned i=0;i i[int x].begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode):{ - //Get the mode bits from the spi_mode - get_mode_bits(mode, cpol, cpha); - - //xassert(device_index < num_slaves); - if (!isnull(cb)){ - set_port_use_on(sclk); - configure_out_port(sclk, cb, 0); - } - - sync(sclk); - //Wait for the chip deassert time if need be - if(device_index == selected_device) - sync(p_ss[selected_device]); - - //Set the expected clock idle state on the clock port - partout(sclk, 1, cpol); - sync(sclk); - - if(isnull(cb)){ - //Calculate the clock period from the speed_in_khz - period = (XS1_TIMER_KHZ + speed_in_khz - 1)/speed_in_khz;//round up - } else { - //Set the clock divider - stop_clock(cb); - unsigned d = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz);//FIXME this has to round up too - configure_clock_ref(cb, d); - start_clock(cb); - } - - //Lock the begin transaction - accepting_new_transactions = 0; - - //Do a slave select - selected_device = device_index; - p_ss[selected_device] <: 0; - break; - } - case i[int x].end_transaction(unsigned ss_deassert_time):{ - //Unlock the transaction - accepting_new_transactions = 1; - - unsigned time; - partout(sclk, 1, cpol); - sync(sclk); - p_ss[selected_device] <: 0xffffffff @ time; - - //TODO should this be allowed? (0.6ms max without it) - if(ss_deassert_time > 0xffff) - delay_ticks(ss_deassert_time&0xffff0000); - - time += ss_deassert_time; - - p_ss[selected_device] @ time <: 0xffffffff; - break; - } - case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - if(isnull(cb)) { - r = transfer8_sync_zero_clkblk(sclk, mosi, miso, data, period, cpol, cpha); - } else { - r = transfer8_sync_one_clkblk(sclk, mosi, miso, data, cpol, cpha); - } - break; - } - case i[int x].transfer32(uint32_t data) -> uint32_t r:{ - if(isnull(cb)) { - r = transfer32_sync_zero_clkblk(sclk, mosi, miso, data, period, cpol, cpha); - } else { - r = transfer32_sync_one_clkblk(sclk, mosi, miso, data, cpol, cpha); - } - break; - } - - case i[int x].set_ss_port_bit(unsigned port_bit):{ - // Do nothing this is invalid since this component sets all port bits high/low during select - break; - } - - case i[int x].shutdown(void):{ - // Do nothing currently - break; - } - } - } -} - diff --git a/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index 1709512..d36a5a2 100644 --- a/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -12,8 +12,7 @@ in buffered port:32 p_miso = XS1_PORT_1A; out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -118,11 +117,11 @@ int main(){ #if COMBINED == 1 [[combine]] par { - spi_master_async_fwk(i, 3, p_sclk, MOSI, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i, 3, p_sclk, MOSI, p_miso, p_ss, 1, cb); watcher(c); } #else - spi_master_async_fwk(i, 3, p_sclk, MOSI, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i, 3, p_sclk, MOSI, p_miso, p_ss, 1, cb); watcher(c); #endif app(i[0], MOSI_ENABLED, 1, c[0], 5000); diff --git a/tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc b/tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc index 4a02a38..98b07ba 100644 --- a/tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc +++ b/tests/spi_master_async_multi_device/src/spi_master_async_multi_device.xc @@ -13,8 +13,7 @@ in buffered port:32 p_miso = XS1_PORT_1A; out port p_ss = XS1_PORT_4A; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -189,7 +188,7 @@ static void load(static const unsigned num_threads){ int main(){ interface spi_master_async_if i[1]; par { - spi_master_async_fwk(i, 1, p_sclk, MOSI, p_miso, p_ss, 2, cb0, cb1); + spi_master_async(i, 1, p_sclk, MOSI, p_miso, p_ss, 2, cb); app(i[0], NUM_SS, MOSI_ENABLED, 1); load(BURNT_THREADS); } diff --git a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index 8b9fd32..a790b15 100644 --- a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -11,8 +11,7 @@ in buffered port:32 p_miso = XS1_PORT_1A; out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -186,12 +185,12 @@ int main(){ #if COMBINED == 1 [[combine]] par { - spi_master_async_fwk(i, 1, p_sclk, MOSI, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i, 1, p_sclk, MOSI, p_miso, p_ss, 1, cb); app(i[0], MOSI_ENABLED, 1); } load(BURNT_THREADS); #else - spi_master_async_fwk(i, 1, p_sclk, MOSI, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i, 1, p_sclk, MOSI, p_miso, p_ss, 1, cb); app(i[0], MOSI_ENABLED, 1); load(BURNT_THREADS); #endif diff --git a/tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc b/tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc index d66b2d8..d575bad 100644 --- a/tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc +++ b/tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc @@ -11,8 +11,7 @@ in buffered port:32 p_miso = XS1_PORT_1A; out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -174,7 +173,7 @@ int main(){ interface spi_master_async_if i[1]; par { while(1){ - spi_master_async_fwk(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); // printf("restarting spi\n"); } app(i[0]); From 9afe1995aed375b54abc559b2d3a58af22ceae09 Mon Sep 17 00:00:00 2001 From: Ed Date: Fri, 25 Jul 2025 11:31:59 +0100 Subject: [PATCH 27/57] Missing renames and version WIP sync shutdown Remove print Expand shutdown test Remove old test app Shutdown sync/ distributed known bug --- .../AN00160_using_SPI_master/CMakeLists.txt | 5 + examples/AN00160_using_SPI_master/src/main.xc | 138 +++++---- .../CMakeLists.txt | 26 -- .../AN00160_using_SPI_master_fwk/LICENSE.rst | 84 ------ .../AN00160_using_SPI_master_fwk/README.rst | 46 --- .../config.xscope | 23 -- .../doc/rst/AN00160.rst | 266 ------------------ .../doc/rst/images/Makefile | 19 -- .../doc/rst/images/block_diagram.odg | Bin 18906 -> 0 bytes .../doc/rst/images/block_diagram.pdf | Bin 26106 -> 0 bytes .../doc/rst/images/run_config_sim.png | Bin 121580 -> 0 bytes .../doc/rst/images/run_config_trace.png | Bin 113567 -> 0 bytes .../doc/rst/images/task_diag.odg | Bin 12566 -> 0 bytes .../doc/rst/images/task_diag.pdf | Bin 19961 -> 0 bytes .../doc/rst/images/vcd1.png | Bin 213200 -> 0 bytes .../doc/rst/images/vcd2.png | Bin 229593 -> 0 bytes .../doc/rst/xdoc.conf | 2 - .../AN00160_using_SPI_master_fwk/src/main.xc | 61 ---- examples/AN00161_using_SPI_slave/src/main.xc | 5 +- examples/CMakeLists.txt | 1 - lib_spi/api/spi.h | 16 +- lib_spi/src/spi_fwk.h | 2 +- lib_spi/src/spi_master_shared.h | 7 +- lib_spi/src/spi_master_sync.xc | 144 ++++++---- settings.yml | 2 +- tests/spi_master_checker.py | 8 +- .../src/spi_master_sync_benchmark.xc | 2 +- .../src/spi_master_sync_clock_port_sharing.xc | 2 +- .../src/spi_master_sync_multi_client.xc | 2 +- .../src/spi_master_sync_multi_device.xc | 2 +- .../src/spi_master_sync_rx_tx.xc | 2 +- tests/spi_master_sync_shutdown/CMakeLists.txt | 57 +++- .../src/spi_master_sync_shutdown.xc | 59 ++-- .../spi_master_sync_shutdown/test_params.json | 5 + .../spi_sync_tester.h | 4 +- tests/test_master_sync_shutdown.py | 18 +- 36 files changed, 306 insertions(+), 702 deletions(-) delete mode 100644 examples/AN00160_using_SPI_master_fwk/CMakeLists.txt delete mode 100644 examples/AN00160_using_SPI_master_fwk/LICENSE.rst delete mode 100644 examples/AN00160_using_SPI_master_fwk/README.rst delete mode 100644 examples/AN00160_using_SPI_master_fwk/config.xscope delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.odg delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/block_diagram.pdf delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/run_config_sim.png delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/run_config_trace.png delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/task_diag.odg delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/task_diag.pdf delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/vcd1.png delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/images/vcd2.png delete mode 100644 examples/AN00160_using_SPI_master_fwk/doc/rst/xdoc.conf delete mode 100644 examples/AN00160_using_SPI_master_fwk/src/main.xc create mode 100644 tests/spi_master_sync_shutdown/test_params.json diff --git a/examples/AN00160_using_SPI_master/CMakeLists.txt b/examples/AN00160_using_SPI_master/CMakeLists.txt index 32f1c3e..8f75c78 100644 --- a/examples/AN00160_using_SPI_master/CMakeLists.txt +++ b/examples/AN00160_using_SPI_master/CMakeLists.txt @@ -25,6 +25,11 @@ set(COMPILER_FLAGS_COMMON set(APP_COMPILER_FLAGS_SYNC ${COMPILER_FLAGS_COMMON}) +set(APP_COMPILER_FLAGS_SYNC_NO_CLKBLK + -DCLKBLK=null + ${COMPILER_FLAGS_COMMON}) + + set(APP_COMPILER_FLAGS_ASYNC ${COMPILER_FLAGS_COMMON} -DSPI_USE_ASYNC=1) diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 516df3f..30b9b69 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -8,7 +8,7 @@ #include out buffered port:32 p_sclk = WIFI_CLK; -out port p_ss[1] = {WIFI_CS_N}; +out port p_ss = WIFI_CS_N; in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; @@ -25,6 +25,9 @@ void app(client spi_master_if spi) p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); + spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N + + spi.begin_transaction(0, 1000, SPI_MODE_0); uint32_t reg_addr = 0; // Read reg 0 @@ -39,70 +42,83 @@ void app(client spi_master_if spi) printhexln(reg >> 16); // Should be 0x5400 printstrln("Done."); - _exit(0); + spi.shutdown(); } /* This application function sends some traffic as SPI master using - * the asynchronous interface. Since this is run in simulation - * there is no slave, so the incoming data (stored in the 'val' - * variable) will just be zero. - */ + * the synchronous interface. It reads the config register (address 0) + * of the WFM200S using a 16b command and prints the 32b read result */ void async_app(client spi_master_async_if spi) { - uint8_t indata[10]; - uint8_t outdata[10]; - uint8_t * movable inbuf = indata; - uint8_t * movable outbuf = outdata; - - printstrln("Sending SPI traffic (async)"); - delay_microseconds(30); - - // Fill the out buffer with data - outbuf[0] = 0xab; - outbuf[1] = 0xcc; - outbuf[2] = 0; outbuf[3] = 0; outbuf[4] = 0; - outbuf[5] = 0xfe; - spi.begin_transaction(0, 100, SPI_MODE_0); - - // This call passes the buffers over to the SPI task, after - // this the application cannot access the buffers until - // the retrieve_transfer_buffers_8 function is called. - spi.init_transfer_array_8(move(inbuf), - move(outbuf), - 6); - - // Your application can do calculation here whilst the spi task - // transfers the buffer. - - // A select will wait for an event. In this case the event we are waiting - // for is the transfer_complete() notification event from the SPI task. - select { - case spi.transfer_complete(): - // Once the transfer is complete, we can retrieve the - // buffers back into the inbuf and outbuf pointer variables - spi.retrieve_transfer_buffers_8(inbuf, outbuf); - break; - } - spi.end_transaction(100); + spi.set_ss_port_bit(1); + printstrln("Sending aynch SPI traffic"); + + p_rstn <: 0x2; //Take out of reset and wait + delay_microseconds(1000); + spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N - delay_microseconds(40); - spi.begin_transaction(0, 100, SPI_MODE_0); - outbuf[0] = 0x22; - spi.init_transfer_array_8(move(inbuf), - move(outbuf), - 1); - select { - case spi.transfer_complete(): - spi.retrieve_transfer_buffers_8(inbuf, outbuf); - break; - } - spi.end_transaction(100); + spi.begin_transaction(0, 1000, SPI_MODE_0); - printstrln("Done."); + // Build command + uint32_t reg_addr = 0; // Read reg 0 + uint32_t read_cmd = 0x8000; + uint32_t num_16b_words = 2; + uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command - spi.shutdown(); + uint8_t inbuffer[2]; // Dummy for write command + uint8_t outbuffer[2]; + + // memcpy(outbuffer, &command, sizeof(command)); + outbuffer[0] = (command >> 8) & 0xff; // MSB first + outbuffer[1] = command & 0xff; + + uint8_t * movable inbuf = inbuffer; + uint8_t * movable outbuf = outbuffer; + + + // This call passes the buffers over to the SPI task, after + // this the application cannot access the buffers until + // the retrieve_transfer_buffers_8 function is called. + + spi.init_transfer_array_8(move(inbuf), + move(outbuf), + 2); + + // A select will wait for an event. In this case the event we are waiting + // for is the transfer_complete() notification event from the SPI task. + select { + case spi.transfer_complete(): + // Once the transfer is complete, we can retrieve the + // buffers back into the inbuf and outbuf pointer variables + spi.retrieve_transfer_buffers_8(inbuf, outbuf); + break; + } + + spi.begin_transaction(0, 1000, SPI_MODE_0); + + uint32_t inbuffer32[1] = {0}; + uint32_t outbuffer32[1] = {0}; // Dummy for read reg + uint32_t * movable inbuf32 = inbuffer32; + uint32_t * movable outbuf32 = outbuffer32; + + spi.init_transfer_array_32(move(inbuf32), + move(outbuf32), + 1); + + select { + case spi.transfer_complete(): + // Once the transfer is complete, we can retrieve the + // buffers back into the inbuf and outbuf pointer variables + spi.retrieve_transfer_buffers_32(inbuf32, outbuf32); + break; + } + + printhexln(*inbuf32 >> 16); // Should be 0x5400 + printstrln("Done."); + + spi.shutdown(); } @@ -114,23 +130,23 @@ int main(void) { on tile[0]: { par { async_app(i_spi_async[0]); - spi_master_async(i_spi_async, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, clk); + spi_master_async(i_spi_async, 1, p_sclk, p_mosi, p_miso, p_ss, 1, clk); } } } return 0; } -#else +#else // SYNC +#ifndef CLKBLK +#define CLKBLK clk +#endif int main(void) { interface spi_master_if i_spi[1]; par { on tile[0]: app(i_spi[0]); - on tile[0]: spi_master(i_spi, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - null); + on tile[0]: spi_master(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, CLKBLK); } return 0; } diff --git a/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt b/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt deleted file mode 100644 index 6a397c5..0000000 --- a/examples/AN00160_using_SPI_master_fwk/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -cmake_minimum_required(VERSION 3.21) -include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) -project(app_spi_master) - -# Sandbox configuration -set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) - -# Target, xscope -set(APP_HW_TARGET XCORE-AI-EXPLORER) -set(APP_XSCOPE_SRCS config.xscope) - -# Includes, Dependencies -list(APPEND APP_INCLUDES src) -list(APPEND APP_DEPENDENT_MODULES "lib_spi") - -# Flags -set(APP_COMPILER_FLAGS - -Os - -g - -report - -Wall - -Werror -) - - -XMOS_REGISTER_APP() \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master_fwk/LICENSE.rst b/examples/AN00160_using_SPI_master_fwk/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/examples/AN00160_using_SPI_master_fwk/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. 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The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/examples/AN00160_using_SPI_master_fwk/README.rst b/examples/AN00160_using_SPI_master_fwk/README.rst deleted file mode 100644 index 39f206a..0000000 --- a/examples/AN00160_using_SPI_master_fwk/README.rst +++ /dev/null @@ -1,46 +0,0 @@ -How to use the SPI library as SPI master -======================================== - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE drive an SPI bus as SPI master. The application is the simplest -example of setting up the library and performing a couple of -transactions. The code can then be run in simulation to see the -outputted waveforms. - -The note covers both the synchronous and asynchronous use of the SPI -master components provided from the library. - -Required tools and libraries -............................ - -* xTIMEcomposer Tools - Version 14.0 -* XMOS SPI library - Version 3.0.0 - -Required hardware -................. - -This application note is designed to run in simulation so requires no -XMOS hardware. - -Prerequisites -............. - - - This document assumes familiarity with the XMOS xCORE - architecture, the SPI bus protocol, the XMOS tool chain and the xC - language. Documentation related to these aspects which are not - specific to this application note are linked to in the references appendix. - - - For descriptions of XMOS related terms found in this document - please see the XMOS Glossary [#]_. - - - For the full API listing of the XMOS SPI Device Library please see - the library user guide [#]_. - - .. [#] http://www.xmos.com/published/glossary - - .. [#] http://www.xmos.com/support/libraries/lib_spi - - diff --git a/examples/AN00160_using_SPI_master_fwk/config.xscope b/examples/AN00160_using_SPI_master_fwk/config.xscope deleted file mode 100644 index 1540288..0000000 --- a/examples/AN00160_using_SPI_master_fwk/config.xscope +++ /dev/null @@ -1,23 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst b/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst deleted file mode 100644 index 6708d25..0000000 --- a/examples/AN00160_using_SPI_master_fwk/doc/rst/AN00160.rst +++ /dev/null @@ -1,266 +0,0 @@ -.. include:: ../../README.rst - -|newpage| - -Overview --------- - -Introduction -............ - -The XMOS SPI library is a library that provides -software defined, industry-standard, SPI (serial peripheral interface) -components that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. - -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. - -The library includes features such as SPI master and SPI slave modes, -supported speeds of up to 100 Mbit, multiple slave device support and -support for all configurations of clock polarity and phase. - -Block diagram -............. - -.. figure:: images/block_diagram.* - :scale: 100% - :align: center - - Block diagram of SPI master application example - -SPI master example ------------------- - -The example in this application note uses the XMOS SPI library to -perform some bus transactions as SPI master. The binary is then run in -simulation so the user can see the waveform output in the VCD tracing -perspective in the xTIMEcomposer. - -The application consists of two tasks: - - - A task that drives the SPI bus - - - An application task that connects to the SPI task - -These tasks communicate via the use of xC interfaces. - -The following diagram shows the task and communication structure of -the application. - -.. figure:: images/task_diag.* - - Task diagram of SPI master example - -Makefile additions for this example -................................... - -To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: - - USED_MODULES = ... lib_spi - -You can then access the SPI functions in your source code via the -spi.h header file:: - - #include - -Declaring ports -............... - -The SPI library connects to external pins via xCORE ports. In -``main.xc`` these are declared as variables of type ``port`` at the -start of the file: - -.. literalinclude:: main.xc - :start-on: p_sclk - :end-on: p_mosi - -Note that the slave select declaration (``p_ss``) is an array of -ports. This is what the SPI library expects since there may be many -slave select lines for multiple devices. - -How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will -depend on the exact device being used. See the device datasheet for details. - -|newpage| - -The application main() function -............................... - -Below is the source code for the main function of this application, -which is taken from the source file ``main.xc`` - -.. literalinclude:: main.xc - :start-on: int main - :end-before: Uncomment - -Looking at this in more detail you can see the following: - - - The par functionality describes running two separate tasks in parallel - - - The ``spi_master`` task drives the SPI bus and takes the ports it - will use as arguments. - - - The ``app`` task communicates to the ``spi_master`` task via the - shared interface argument ``i_spi``. This is an array since the - SPI master task could connect to many other tasks in parallel. - -The app() function -.................. - -The ``app`` function uses its interface connection to the SPI master -task to perform SPI transactions. It performs two transactions (each -transaction will assert the slave select line, transfer some data and then -de-assert the slave select line). The functions in the SPI master -interface can be found in the SPI library user guide. - -.. literalinclude:: main.xc - :start-on: void app - :end-before: This application function - -Note that when ``begin_transaction`` is called the device is selected -by the first argument. In this case it is ``0``, so the zero-th -element of the ``p_ss`` array will be used for the slave select -line. This is the method that is used to communiate with multiple SPI -slave devices. The speed and mode of the SPI protocol is also set at -in the ``begin_transaction`` call. - -|newpage| - -Setting up the run configuration for the application -.................................................... - -To run the application binary in the simulator, first the application -must be built by pressing the :menuitem:`Build` button in the -xTIMEcomposer. This will create the ``AN00160_using_SPI_master.xe`` -binary in the ``bin`` folder of the project. The xTIMEcomposer may -have to import the SPI library if you do not already have it in your -workspace; this will occur automatically on build. - -Then a *Run Configuration* needs to be set up. This can be done by -selecting the :menuitem:`Run,Run Configurations..` menu. You can -create a new run configuration by right clicking on the -:menuitem:`xCORE application` group in the left hand pane and -:menuitem:`new`. However, in this example a run configuration has -already been created for you. - -Looking at this run configuration, you can see the simulator has been -selected under :menuitem:`Device Options:`: - -.. image:: images/run_config_sim.png - :width: 70% - :align: center - -|newpage| - -In the :menuitem:`Simulator` tab of the run configuration. The -:menuitem:`Enable signal tracing` check box has been enabled and a -:menuitem:`Tile Trace Option` has been added to trace the ports on -tile[0]: - -.. image:: images/run_config_trace.png - :width: 70% - :align: center - -|newpage| - -Running the application -....................... - -By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit -Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` -button in the run configuration dialog, the program -will run. In the console window you will get this output:: - - Sending SPI traffic - Done. - -After this it will immediately swith the the VCD tracing perspective -(since signal tracing was enabled in the run configuration). In this -perspective you can drag ports from within the tree in the -:menuitem:`Signals` pane on the left hand side to the -:menuitem:`Waves` pane on the right: - -.. image:: images/vcd1.png - :width: 70% - :align: center - -By dragging in the four ports used by the application (1I, 1J, 1K and -1L) you can see that the application has driven the correct SPI -signal. Note that you need to expand each port and drag in just the -port value, the other traces (such as ``tile[0]_XS1_PORT_1J_inuse``) -just show the internal port state and are not so interesting here. - -.. image:: images/vcd2.png - :width: 70% - :align: center - -|newpage| - -Using the asynchronous interface -................................ - -There is an alternative ``main()`` function in the program to try: - -.. literalinclude:: main.xc - :start-on: Uncomment - -By uncommenting this main (and commenting out the original main) the -application will use the ``spi_master_async`` task instead of the -synchronous ``spi_master`` task. This task still drives the SPI bus -but runs on a separate logical core and will drive the bus in parallel -to your application. This way your application can overlap processing -with communication. - -The ``async_app()`` function performs the same function as the -``app()`` function using the asynchronous interface. The big -difference is that pointers have to be passed to the SPI task that -point to the buffers to send from/receive into. These need to be -*movable* pointers (see the xC programing guide for more information) -that can be passed to another task: - -.. literalinclude:: main.xc - :start-on: async_app - :end-on: outbuf - -|newpage| - -Once the pointers have been initialized they can be passed and later -retrieved from the SPI master task: - -.. literalinclude:: main.xc - :start-on: traffic (async) - :end-on: end_transaction - -|appendix| -|newpage| - -References ----------- - -.. nopoints:: - - * XMOS Tools User Guide - - http://www.xmos.com/published/xtimecomposer-user-guide - - * XMOS xCORE Programming Guide - - http://www.xmos.com/published/xmos-programming-guide - - * XMOS SPI Library - - http://www.xmos.com/support/libraries/lib_spi - -|newpage| - -Full source code listing ------------------------- - -.. literalinclude:: main.xc - :largelisting: - -|newpage| - diff --git a/examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile b/examples/AN00160_using_SPI_master_fwk/doc/rst/images/Makefile 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It reads the config register (address 0) - * of the WFM200S using a 16b command and prints the 32b read result */ -void app(client spi_master_if spi) -{ - uint8_t val; - printstrln("Sending SPI traffic"); - - p_rstn <: 0x2; //Take out of reset and wait - delay_microseconds(1000); - spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N - - spi.begin_transaction(0, 1000, SPI_MODE_0); - uint32_t reg_addr = 0; // Read reg 0 - uint32_t read_cmd = 0x8000; - uint32_t num_16b_words = 2; - uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command - val = spi.transfer8(command >> 8); - val = spi.transfer8(command & 0xff); - uint32_t reg = 0; - reg = spi.transfer32(0x00); - spi.end_transaction(0); - printhexln(reg >> 16); // Should be 0x5400 - delay_microseconds(100000); - - printstrln("Done."); - delay_microseconds(100000); - _exit(0); -} - - -int main(void) { - interface spi_master_if i_spi[1]; - par { - on tile[0]: app(i_spi[0]); - on tile[0]: spi_master_fwk(i_spi, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - clk0); - } - return 0; -} - diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/AN00161_using_SPI_slave/src/main.xc index 659263c..9799e3f 100644 --- a/examples/AN00161_using_SPI_slave/src/main.xc +++ b/examples/AN00161_using_SPI_slave/src/main.xc @@ -1,12 +1,13 @@ // Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include -#include #include #include #include #include +#include "spi.h" + /* These ports are used for the SPI slave task */ in port p_sclk = on tile[0]: XS1_PORT_1E; in port p_ss = on tile[0]: XS1_PORT_1F; @@ -17,7 +18,7 @@ clock cb = on tile[0]: XS1_CLKBLK_1; /* These ports are used for the SPI master task which is used to test the SPI slave (via simulator loopback). */ out buffered port:32 p_test_sclk = on tile[0]: XS1_PORT_1I; -out port p_test_ss[1] = on tile[0]: {XS1_PORT_1J}; +out port p_test_ss = on tile[0]: XS1_PORT_1J; in buffered port:32 p_test_miso = on tile[0]: XS1_PORT_1K; out buffered port:32 p_test_mosi = on tile[0]: XS1_PORT_1L; diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index 6f8e172..2668e58 100644 --- a/examples/CMakeLists.txt +++ b/examples/CMakeLists.txt @@ -4,5 +4,4 @@ include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) project(lib_camera_examples) add_subdirectory(AN00160_using_SPI_master) -add_subdirectory(AN00160_using_SPI_master_fwk) add_subdirectory(AN00161_using_SPI_slave) \ No newline at end of file diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 14e2b4d..6988704 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -96,7 +96,7 @@ typedef interface spi_master_if { /** Sets the bit of port which is used for slave select (> 1b port type only) - * and only for spi_master_fwk. spi_master sets all bits in each port high/low + * and only for spi_master. spi_master sets all bits in each port high/low * * The default value (if this is not called) is the bit number is equal to * the device_index (0->0, 1->1 etc.). @@ -117,7 +117,7 @@ typedef interface spi_master_if { [[distributable]] -void spi_master_fwk( +void spi_master( SERVER_INTERFACE(spi_master_if, i[num_clients]), static_const_size_t num_clients, out_buffered_port_32_t sclk, @@ -152,16 +152,6 @@ void spi_master_fwk( \param num_slaves The number of slave devices on the bus. \param clk a clock for the component to use. */ -[[distributable]] -void spi_master( - SERVER_INTERFACE(spi_master_if, i[num_clients]), - static_const_size_t num_clients, - out_buffered_port_32_t sclk, - NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), - NULLABLE_RESOURCE(in_buffered_port_32_t, miso), - out_port p_ss[num_slaves], - static_const_size_t num_slaves, - NULLABLE_RESOURCE(clock, clk)); /** * \addtogroup spi_master_async_if @@ -282,7 +272,7 @@ typedef interface spi_master_async_if { /** Sets the bit of port which is used for slave select (> 1b port type only) - * and only for spi_master_fwk. spi_master sets all bits in each port high/low + * and only for spi_master. spi_master sets all bits in each port high/low * * The default value (if this is not called) is the bit number is equal to * the device_index (0->0, 1->1 etc.). diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 031ca59..681772d 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -209,7 +209,7 @@ void spi_master_transfer( * \param dev The active SPI device. * \param delay_ticks The number of reference clock ticks to delay. */ -inline void spi_master_delay_before_next_transfer( +static inline void spi_master_delay_before_next_transfer( spi_master_device_t *dev, uint32_t delay_ticks) { diff --git a/lib_spi/src/spi_master_shared.h b/lib_spi/src/spi_master_shared.h index c4a105e..98aec9d 100644 --- a/lib_spi/src/spi_master_shared.h +++ b/lib_spi/src/spi_master_shared.h @@ -4,11 +4,6 @@ #include #include -//TODO DEL these -#include -#include -#include - #include "spi.h" extern "C"{ #include "spi_fwk.h" @@ -16,7 +11,7 @@ extern "C"{ // Clockblock-less SPI transfer functions. These are slow (max around 1 Mbps) but are suitable for control transfer // When clockblock resources are scarce -int8_t transfer8_sync_zero_clkblk( +uint8_t transfer8_sync_zero_clkblk( out buffered port:32 sclk, out buffered port:32 ?mosi, in buffered port:32 ?miso, diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 73fee38..7bfd939 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -15,36 +15,44 @@ extern "C"{ } #include "spi_master_shared.h" -#define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device - #pragma unsafe arrays [[distributable]] -void spi_master_fwk(server interface spi_master_if i[num_clients], +void spi_master(server interface spi_master_if i[num_clients], static const size_t num_clients, out buffered port:32 sclk, out buffered port:32 ?mosi, in buffered port:32 ?miso, - out port p_ss, // Note only one SS port supported - individual bits in port may be used however + out port p_ss, // Note only one SS port supported - individual bits in port may be used for different devices however static const size_t num_slaves, clock ?cb){ - if(isnull(cb)){ - printstrln("Must supply clockblock to this version of SPI"); - // We will hit an exception shortly after this if cb is NULL - } - + // For clock-block based fast SPI spi_master_t spi_master; spi_master_device_t spi_dev; - unsafe{ - spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + + // For clock-blockless slow SPI + unsigned clkblkless_period_ticks; + + // For all SPI types + unsigned cpol = 0; + unsigned cpha = 0; + + if(!isnull(cb)){ + unsafe{ + spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + } + } else { + // Initial SS bit pattern - deselected + p_ss <: 0xffffffff; + sync(p_ss); } int accepting_new_transactions = 1; // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) - uint8_t ss_port_bit[SPI_MAX_DEVICES]; - for(int i = 0; i < SPI_MAX_DEVICES; i++){ + uint8_t ss_port_bit[num_slaves]; + for(int i = 0; i < num_slaves; i++){ ss_port_bit[i] = i; } @@ -54,75 +62,111 @@ void spi_master_fwk(server interface spi_master_if i[num_clients], unsigned speed_in_khz, spi_mode_t mode):{ accepting_new_transactions = 0; + // Grab mode bits + cpol = mode >> 1; + cpha = mode & 0x1; + + // Fast SPI state spi_master_source_clock_t source_clock; unsigned divider; - spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); - - // unsigned actual_speed_khz = spi_master_get_actual_clock_rate(source_clock, divider); - // printf("Actual speed_in_khz: %u div(%u) clock: (%s) %uMHz\n", - // actual_speed_khz, - // divider, - // ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), - // ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); - - unsigned cpol = mode >> 1; - unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev, &spi_master, - ss_port_bit[device_index], - cpol, cpha, - source_clock, - divider, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); - - spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() - // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client - spi_master_start_transaction(&spi_dev); + + if(isnull(cb)){ + // Set the expected clock idle state on the clock port + partout(sclk, 1, cpol); + sync(sclk); + + unsigned ss_port_val = ~(1 << ss_port_bit[device_index]); + p_ss <: ss_port_val; + clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1)/speed_in_khz;// round up + } else { + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + + // unsigned actual_speed_khz = spi_master_get_actual_clock_rate(source_clock, divider); + // printf("Actual speed_in_khz: %u div(%u) clock: (%s) %uMHz\n", + // actual_speed_khz, + // divider, + // ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), + // ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); + + spi_master_device_init(&spi_dev, &spi_master, + ss_port_bit[device_index], + cpol, cpha, + source_clock, + divider, + spi_master_sample_delay_0, + 0, 0 ,0 ,0 ); + + spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() + // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client + spi_master_start_transaction(&spi_dev); + } + break; } case i[int x].end_transaction(unsigned ss_deassert_time):{ - spi_master_end_transaction(&spi_dev); + + // NEED TO WAIT -> Deassert time + if(isnull(cb)){ + p_ss <: 0xffffffff; + } else { + spi_master_end_transaction(&spi_dev); + } + // Unlock the transaction accepting_new_transactions = 1; + break; } case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - spi_master_transfer(&spi_dev, (uint8_t *)&data, &r, 1); + if(isnull(cb)){ + r = transfer8_sync_zero_clkblk(sclk, mosi, miso, data, clkblkless_period_ticks, cpol, cpha); + } else { + spi_master_transfer(&spi_dev, (uint8_t *)&data, &r, 1); + } + break; } case i[int x].transfer32(uint32_t data) -> uint32_t r:{ - uint32_t read_val; - // For 32b words, we need to swap to big endian (standard for SPI) from little endian (XMOS) - // This means we transmit the MSByte first - data = byterev(data); - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); - r = byterev(read_val); + if(isnull(cb)){ + r = transfer32_sync_zero_clkblk(sclk, mosi, miso, data, clkblkless_period_ticks, cpol, cpha); + } else { + // For 32b words, we need to swap to big endian (standard for SPI) from little endian (XMOS) + // This means we transmit the MSByte first + data = byterev(data); + uint32_t read_val; + spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); + r = byterev(read_val); + } + break; } case i[int x].set_ss_port_bit(unsigned port_bit):{ - if(port_bit > SPI_MAX_DEVICES){ - printstrln("Invalid port bit - must be less than SPI_MAX_DEVICES"); + if(port_bit > num_slaves){ + printstrln("Invalid port bit - must be less than num_slaves"); } ss_port_bit[x] = port_bit; + break; } case i[int x].shutdown(void):{ - // We don't use spi_master_deinit(&spi_master); This completely turns off resources. p_ss <: 0xffffffff; - // If using XC, then we need to enable/init which is how XC does it if (!isnull(mosi)) { set_port_use_on(mosi); } - set_port_use_on(miso); + if (!isnull(miso)) { + set_port_use_on(miso); + } set_port_use_on(sclk); - set_clock_on(cb); - + if(!isnull(cb)){ + set_clock_on(cb); + } + return; } } diff --git a/settings.yml b/settings.yml index cdb68fc..110d6f4 100644 --- a/settings.yml +++ b/settings.yml @@ -3,7 +3,7 @@ lib_name: lib_spi project: '{{lib_name}}' title: '{{lib_name}}: SPI Library' -version: 3.4.0 +version: 4.0.0 documentation: exclude_patterns_path: doc/exclude_patterns.inc diff --git a/tests/spi_master_checker.py b/tests/spi_master_checker.py index eafdcce..f8d3d35 100644 --- a/tests/spi_master_checker.py +++ b/tests/spi_master_checker.py @@ -77,10 +77,10 @@ def run(self) -> None: while not all_ss_deserted: self.wait_for_port_pins_change([self._ss_port]) all_ss_deserted = True if xsi.sample_port_pins(self._ss_port) == ss_deaserted_value else False + # print("ALL HIGH", ss_deaserted_value) error = False - # Wait for any SS to assert active_slave = -1 # no active slaves while(active_slave == -1): @@ -126,7 +126,7 @@ def run(self) -> None: for i in range(self._ss_port_width): if not ss_port_val & (1 << i) and i != active_slave: error = True - print(f"Second slave selected during first transaction, SS port val: 0x{ss_port_val:x} at time: {xsi.get_time() / nanosecond_ticks}ns") + print(f"Error: Second slave selected during first transaction, SS port val: 0x{ss_port_val:x} at time: {xsi.get_time() / nanosecond_ticks}ns") if (ss_value == ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) and (sck_value == xsi.sample_port_pins(self._sck_port))): continue @@ -145,7 +145,7 @@ def run(self) -> None: #check that the clock edges never go faster than the expected clock rate if ss_value == 0: clock_edge_number += 1 - #print clock_edge_number + # print(f"MISO clock_edge_number: {clock_edge_number}") #the the clock must have transitioned if sck_value == (expected_cpha ^ expected_cpol): if expected_miso_enabled == 1: @@ -171,7 +171,7 @@ def run(self) -> None: if expected_rx_byte != rx_byte: print(f"ERROR: slave received incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x} at time: {xsi.get_time() / nanosecond_ticks}ns") error = True - # print(f"Checker got byte: {rx_byte:02x} at time {xsi.get_time() / nanosecond_ticks}ns") + # print(f"Checker correctly got byte: {rx_byte:02x} at time {xsi.get_time() / nanosecond_ticks}ns") rx_byte = 0 else: if clock_edge_number != expected_num_bytes*2*8: diff --git a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index d7497e7..1c7707d 100644 --- a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -92,7 +92,7 @@ static void load(static const unsigned num_threads){ int main(){ interface spi_master_if i[1]; par { - spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc index c203221..5dee37a 100644 --- a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc +++ b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc @@ -79,7 +79,7 @@ int main(){ #endif par { app(i[0], 1, 1); - spi_master_fwk(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); } } } diff --git a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 3be02fd..62827f5 100644 --- a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -83,7 +83,7 @@ int main(){ chan c[3]; interface spi_master_if i[3]; par { - spi_master_fwk(i, 3, p_sclk, MOSI, MISO, p_ss, 1, cb); + spi_master(i, 3, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED, c[0]); app(i[1], MOSI_ENABLED, MISO_ENABLED, c[1]); app(i[2], MOSI_ENABLED, MISO_ENABLED, c[2]); diff --git a/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index 3ed850e..c8fcdf9 100644 --- a/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -76,7 +76,7 @@ static void load(static const unsigned num_threads){ int main(){ interface spi_master_if i[1]; par { - spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, cb); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, cb); app(i[0], NUM_SS, MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 321cde5..e991624 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -60,7 +60,7 @@ static void load(static const unsigned num_threads){ int main(){ interface spi_master_if i[1]; par { - spi_master_fwk(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED, SPI_MODE); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_shutdown/CMakeLists.txt b/tests/spi_master_sync_shutdown/CMakeLists.txt index 01665b5..7100164 100644 --- a/tests/spi_master_sync_shutdown/CMakeLists.txt +++ b/tests/spi_master_sync_shutdown/CMakeLists.txt @@ -1,21 +1,60 @@ cmake_minimum_required(VERSION 3.21) include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON distributed_list GET ${params_json} DISTRIBUTED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON distributed_list_len LENGTH ${distributed_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR distributed_list_len "${distributed_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") + + set(APP_PCA_ENABLE ON) set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) -project(spi_master_sync_shutdown) -set(target "XK-EVK-XU316") -set(APP_HW_TARGET ${target}) -set(COMPILER_FLAGS_COMMON -O2 - -g - -Wno-reinterpret-alignment) +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${distributed_list_len}) + string(JSON distributed GET ${distributed_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + set(config ${distributed}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") + project(spi_master_sync_shutdown) + set(APP_HW_TARGET ${target}) -set(APP_COMPILER_FLAGS ${COMPILER_FLAGS_COMMON}) + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DDISTRIBUTED=${distributed} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) -set(APP_INCLUDES src ../spi_master_tester_common) + XMOS_REGISTER_APP() -XMOS_REGISTER_APP() + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc index 3014919..038f3ac 100644 --- a/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc +++ b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc @@ -7,25 +7,33 @@ #include "spi.h" #include "spi_sync_tester.h" -in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss = XS1_PORT_1B; -out buffered port:32 p_sclk = XS1_PORT_1C; -out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb = XS1_CLKBLK_1; -out port setup_strobe_port = XS1_PORT_1E; -out port setup_data_port = XS1_PORT_16B; +in buffered port:32 p_miso = on tile[0]: XS1_PORT_1A; +out port p_ss = on tile[0]: XS1_PORT_1B; +out buffered port:32 p_sclk = on tile[0]: XS1_PORT_1C; +out buffered port:32 p_mosi = on tile[0]: XS1_PORT_1D; +clock cb = on tile[0]: XS1_CLKBLK_1; + +out port setup_strobe_port = on tile[0]: XS1_PORT_1E; +out port setup_data_port = on tile[0]: XS1_PORT_16B; #define SPI_MODE SPI_MODE_0 -#define SPI_KBPS 10000 +#define SPI_KBPS 1000 + + +// We can only distribute if the main par is a flat list of tasks, not a loop +// However a clean exit should result in no exception +#if DISTRIBUTED +#define LOOPS 1 +#else +#define LOOPS 5 +#endif void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ - for(int loop = 0; loop < 10; loop++){ + for(int loop = 0; loop < LOOPS; loop++){ test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); - i.shutdown(); - test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); @@ -33,19 +41,38 @@ void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, i } printf("Transfers complete\n"); - _Exit(0); -} + // Should exit normally, no need for forced exit +} int main(){ interface spi_master_if i[1]; par { +#if DISTRIBUTED + par + { + #if CB_ENABLED + [[distribute]] + spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + #else + [[distribute]] + spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + #endif + app(i[0], 1, 1, SPI_MODE); + } +#else // NOT distributed - uses own thread + par { - while(1){ - spi_master_fwk(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + on tile[0]: { + #if CB_ENABLED + for(int loop = 0; loop < LOOPS; loop++){spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb);} + #else + for(int loop = 0; loop < LOOPS; loop++){spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null);} + #endif } + on tile[0]: app(i[0], 1, 1, SPI_MODE); } - app(i[0], 1, 1, SPI_MODE); +#endif // NOT distributed } return 0; } diff --git a/tests/spi_master_sync_shutdown/test_params.json b/tests/spi_master_sync_shutdown/test_params.json new file mode 100644 index 0000000..32b490a --- /dev/null +++ b/tests/spi_master_sync_shutdown/test_params.json @@ -0,0 +1,5 @@ +{ + "DISTRIBUTED": [0, 1], + "CB_ENABLED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_tester_common/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h index 8770877..c172633 100644 --- a/tests/spi_master_tester_common/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -29,14 +29,14 @@ int test_transfer8(client interface spi_master_if i, if(miso_enabled){ if(rx != rx_data[j]) error = 1; if(VERBOSE && (rx != rx_data[j])) - printf("Got: %02x Expected: %02x\n", rx, rx_data[j]); + printf("Device Got: %02x Expected: %02x from MISO\n", rx, rx_data[j]); } } i.end_transaction(inter_frame_gap); if(error) - printf("ERROR: master got the wrong data\n"); + printf("ERROR: master got the wrong data from device over MISO\n"); return error; } diff --git a/tests/test_master_sync_shutdown.py b/tests/test_master_sync_shutdown.py index 596dbeb..9c26f42 100644 --- a/tests/test_master_sync_shutdown.py +++ b/tests/test_master_sync_shutdown.py @@ -7,12 +7,20 @@ from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output appname = "spi_master_sync_shutdown" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" -def do_test(capfd): +def do_test(distributed, cb_enabled, arch, capfd): filepath = Path(__file__).resolve().parent - binary = filepath/f"{appname}/bin/{appname}.xe" + id_string = f"{distributed}_{cb_enabled}_{arch}" + app_build = "distributed" if distributed else "own_thread" + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists() + # Known issue when clock block is NULL and SPI master sync is distributed - compiler bug on task cleanup + # http://bugzilla.xmos.local/show_bug.cgi?id=19049 + if distributed == 1 and cb_enabled == 0: + pytest.xfail() + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1A", @@ -37,5 +45,7 @@ def do_test(capfd): output = print_expected_vs_output(expected, capfd) assert tester.run(output), output -def test_master_sync_rx_tx(capfd, request): - do_test(capfd) \ No newline at end of file + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_shutdown(capfd, params, request): + do_test(*params, capfd) \ No newline at end of file From 288633a7165820af2b19663f129cd5ee945caed2 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 28 Jul 2025 08:28:22 +0100 Subject: [PATCH 28/57] Avoid client hogging in multi-client sync Remove SPI slave fwk API Use spi_device contextand provide device arg for set_ss_port_bit Missing file from last commit --- examples/AN00160_using_SPI_master/src/main.xc | 6 +- lib_spi/api/spi.h | 6 +- lib_spi/src/spi_fwk.h | 77 ------------------- lib_spi/src/spi_master_async.xc | 37 ++++----- lib_spi/src/spi_master_sync.xc | 23 +++--- .../src/spi_master_sync_multi_client.xc | 5 +- .../test_params.json | 2 +- tests/test_master_async_shutdown.py | 4 +- tests/test_master_sync_multi_client.py | 4 +- 9 files changed, 43 insertions(+), 121 deletions(-) diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 30b9b69..ea222b3 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -25,7 +25,7 @@ void app(client spi_master_if spi) p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); - spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N + spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 spi.begin_transaction(0, 1000, SPI_MODE_0); @@ -51,13 +51,11 @@ void app(client spi_master_if spi) void async_app(client spi_master_async_if spi) { - spi.set_ss_port_bit(1); - printstrln("Sending aynch SPI traffic"); p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); - spi.set_ss_port_bit(1); // We are using bit 1 in WIFI_CS_N + spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 spi.begin_transaction(0, 1000, SPI_MODE_0); diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 6988704..07b6431 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -101,9 +101,10 @@ typedef interface spi_master_if { * The default value (if this is not called) is the bit number is equal to * the device_index (0->0, 1->1 etc.). * + * \param device_index The index of the device for which the port bit is to be set. * \param ss_port_bit Which bit number in the port to use for slave select. */ - void set_ss_port_bit(unsigned ss_port_bit); + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); /** Shut down the interface server. */ @@ -277,9 +278,10 @@ typedef interface spi_master_async_if { * The default value (if this is not called) is the bit number is equal to * the device_index (0->0, 1->1 etc.). * + * \param device_index The index of the device for which the port bit is to be set. * \param ss_port_bit Which bit number in the port to use for slave select. */ - void set_ss_port_bit(unsigned ss_port_bit); + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); /** Shut down the interface server. diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 681772d..3d03cc0 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -296,82 +296,5 @@ typedef void (*slave_transaction_ended_t)(void *app_data, uint8_t **out_buf, siz /**@}*/ // END: addtogroup hil_spi_master -/** - * \addtogroup hil_spi_slave hil_spi_slave - * - * The public API for using the HIL SPI slave. - * @{ - */ - -/** - * Callback group representing callback events that can occur during the - * operation of the SPI slave task. Must be initialized by the application - * prior to passing it to one of the SPI slaves. - */ -typedef struct { - /** Pointer to the application's slave_transaction_started_t function to be called by the SPI device */ - SPI_CALLBACK_ATTR slave_transaction_started_t slave_transaction_started; - - /** Pointer to the application's slave_transaction_ended_t function to be called by the SPI device - * Note: The time spent in this callback must be less than the minimum CS deassertion to reassertion - * time. If this is violated the first word of the proceeding transaction will be lost. - */ - SPI_CALLBACK_ATTR slave_transaction_ended_t slave_transaction_ended; - - /** Pointer to application specific data which is passed to each callback. */ - void *app_data; -} spi_slave_callback_group_t; -#endif - -#if 0 -/** - * Initializes a SPI slave. - * - * \note Verified at 25000 kbps, with a 2000ns CS assertion to first clock - * in all modes. - * - * The CS to first clock minimum delay, sometimes referred to - * as setup time, will vary based on the duration of the - * slave_transaction_started callback. This parameter will be application - * specific. To determine the typical value, time the duration of the - * slave_transaction_started callback, and add 2000ns as a safety factor. - * If slave_transaction_started has a non-deterministic runtime, perhaps - * due to waiting on an XCORE resource, then the application developer must - * decide an appropriate CS to first SCLK specification. - * - * The minimum delay between consecutive transactions varies based - * on SPI mode, and if MISO is used. - * MISO | CPOL | CPHA | Min Delay (ns) - * --------------------------------------- - * enabled | 0 | 0 | 2270 - * enabled | 0 | 1 | 2240 - * enabled | 1 | 0 | 2240 - * enabled | 1 | 1 | 2270 - * disabled | 0 | 0 | 440 - * disabled | 0 | 1 | 420 - * disabled | 1 | 0 | 430 - * disabled | 1 | 1 | 430 - * - * \param spi_cbg The spi_slave_callback_group_t context to use. - * \param p_sclk The SPI slave's SCLK port. Must be a 1-bit port. - * \param p_mosi The SPI slave's MOSI port. Must be a 1-bit port. - * \param p_miso The SPI slave's MISO port. Must be a 1-bit port. - * \param p_cs The SPI slave's CS port. Must be a 1-bit port. - * \param clock_block The clock block to use for the SPI slave. - * \param cpol The clock polarity to use. - * \param cpha The clock phase to use. - */ -void spi_slave( - const spi_slave_callback_group_t *spi_cbg, - port_t p_sclk, - port_t p_mosi, - port_t p_miso, - port_t p_cs, - xclock_t clk, - int cpol, - int cpha, - uint32_t thread_mode); - -/**@}*/ // END: addtogroup hil_spi_slave #endif \ No newline at end of file diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 83016c7..218d323 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -58,7 +58,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], //Setup fwk SPI master and device instance spi_master_t spi_master; - spi_master_device_t spi_dev; + spi_master_device_t spi_dev[num_slaves]; unsafe{ spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); } @@ -110,7 +110,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], unsigned cpol = mode >> 1; unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev, &spi_master, + spi_master_device_init(&spi_dev[device_index], &spi_master, ss_port_bit[device_index], cpol, cpha, source_clock, @@ -118,9 +118,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], spi_master_sample_delay_0, 0, 0 ,0 ,0 ); - spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() - // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client - spi_master_start_transaction(&spi_dev); + spi_master_start_transaction(&spi_dev[device_index]); buffer_current_index = 0; currently_performing_a_transaction = 1; @@ -158,7 +156,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], i[x].transfer_complete(); } else { buffer_transfer_width = 8; - spi_master_transfer(&spi_dev, (uint8_t*movable)&buffer_tx[0], &r8, 1); + spi_master_transfer(&spi_dev[active_device], (uint8_t*movable)&buffer_tx[0], &r8, 1); tmr :> default_case_time; default_case_enabled = 1; } @@ -196,7 +194,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], buffer_transfer_width = 32; uint32_t data = byterev(buffer_tx[0]); // uint32_t data = buffer_tx[0]; - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t*)&r32, 4); + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); tmr :> default_case_time; default_case_enabled = 1; } @@ -216,7 +214,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], buffer_current_index = 0; i[active_client].transfer_complete(); } else { - spi_master_transfer(&spi_dev, &((uint8_t*movable)buffer_tx)[buffer_current_index], &r8, 1); + spi_master_transfer(&spi_dev[active_device], &((uint8_t*movable)buffer_tx)[buffer_current_index], &r8, 1); tmr :> default_case_time; default_case_enabled = 1; } @@ -230,7 +228,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], i[active_client].transfer_complete(); } else { uint32_t data = byterev(buffer_tx[buffer_current_index]); - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t*)&r32, 4); + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); tmr :> default_case_time; default_case_enabled = 1; } @@ -245,7 +243,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], //An end_transaction can only be completed after all transfers //have been completed - spi_master_end_transaction(&spi_dev); + spi_master_end_transaction(&spi_dev[active_device]); if(tr_fill > 0){ //begin a new transaction - the tail of the list is the next one to go @@ -267,7 +265,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], unsigned cpol = mode >> 1; unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev, &spi_master, + spi_master_device_init(&spi_dev[new_device_index], &spi_master, ss_port_bit[new_device_index], cpol, cpha, source_clock, @@ -275,9 +273,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], spi_master_sample_delay_0, 0, 0 ,0 ,0 ); - spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() - // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client - spi_master_start_transaction(&spi_dev); + spi_master_start_transaction(&spi_dev[new_device_index]); active_device = new_device_index; active_mode = mode; @@ -289,13 +285,13 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], buffer_rx = move(tr_buffer[index].buffer_rx); buffer_transfer_width = tr_buffer[index].buffer_transfer_width; if(buffer_transfer_width == 8){ - spi_master_transfer(&spi_dev, (uint8_t*movable)&buffer_tx[0], &r8, 1); + spi_master_transfer(&spi_dev[active_device], (uint8_t*movable)&buffer_tx[0], &r8, 1); tmr :> default_case_time; default_case_enabled = 1; } else { uint32_t data = byterev(buffer_tx[0]); // uint32_t data = buffer_tx[0]; - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t*)&r32, 4); + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); tmr :> default_case_time; default_case_enabled = 1; } @@ -319,11 +315,12 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], break; } - case i[int x].set_ss_port_bit(unsigned port_bit):{ - if(port_bit > SPI_MAX_DEVICES){ - printstrln("Invalid port bit - must be less than SPI_MAX_DEVICES"); + case i[int x].set_ss_port_bit(unsigned device_index, unsigned port_bit):{ + if(device_index > num_slaves){ + printstrln("Invalid port bit - must be less than num_slaves"); } - ss_port_bit[x] = port_bit; + ss_port_bit[device_index] = port_bit; + break; } diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 7bfd939..67b60c3 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -29,7 +29,8 @@ void spi_master(server interface spi_master_if i[num_clients], // For clock-block based fast SPI spi_master_t spi_master; - spi_master_device_t spi_dev; + spi_master_device_t spi_dev[num_slaves]; + unsigned current_device; // For clock-blockless slow SPI unsigned clkblkless_period_ticks; @@ -56,11 +57,13 @@ void spi_master(server interface spi_master_if i[num_clients], ss_port_bit[i] = i; } + while(1){ select { case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode):{ accepting_new_transactions = 0; + current_device = device_index; // Grab mode bits cpol = mode >> 1; @@ -88,7 +91,7 @@ void spi_master(server interface spi_master_if i[num_clients], // ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), // ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); - spi_master_device_init(&spi_dev, &spi_master, + spi_master_device_init(&spi_dev[current_device], &spi_master, ss_port_bit[device_index], cpol, cpha, source_clock, @@ -96,9 +99,7 @@ void spi_master(server interface spi_master_if i[num_clients], spi_master_sample_delay_0, 0, 0 ,0 ,0 ); - spi_master.current_device = 0xffffffff; // This is needed to force mode and speed in spi_master_start_transaction() - // Otherwise fwk_spi sees the next transaction on the existing device as the same settings as last on the same client - spi_master_start_transaction(&spi_dev); + spi_master_start_transaction(&spi_dev[current_device]); } break; @@ -110,7 +111,7 @@ void spi_master(server interface spi_master_if i[num_clients], if(isnull(cb)){ p_ss <: 0xffffffff; } else { - spi_master_end_transaction(&spi_dev); + spi_master_end_transaction(&spi_dev[current_device]); } // Unlock the transaction @@ -123,7 +124,7 @@ void spi_master(server interface spi_master_if i[num_clients], if(isnull(cb)){ r = transfer8_sync_zero_clkblk(sclk, mosi, miso, data, clkblkless_period_ticks, cpol, cpha); } else { - spi_master_transfer(&spi_dev, (uint8_t *)&data, &r, 1); + spi_master_transfer(&spi_dev[current_device], (uint8_t *)&data, &r, 1); } break; @@ -137,18 +138,18 @@ void spi_master(server interface spi_master_if i[num_clients], // This means we transmit the MSByte first data = byterev(data); uint32_t read_val; - spi_master_transfer(&spi_dev, (uint8_t *)&data, (uint8_t *)&read_val, 4); + spi_master_transfer(&spi_dev[current_device], (uint8_t *)&data, (uint8_t *)&read_val, 4); r = byterev(read_val); } break; } - case i[int x].set_ss_port_bit(unsigned port_bit):{ - if(port_bit > num_slaves){ + case i[int x].set_ss_port_bit(unsigned device_index, unsigned port_bit):{ + if(device_index > num_slaves){ printstrln("Invalid port bit - must be less than num_slaves"); } - ss_port_bit[x] = port_bit; + ss_port_bit[device_index] = port_bit; break; } diff --git a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 62827f5..7416584 100644 --- a/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -14,6 +14,7 @@ out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; +#define SPEED_KBPS 10000 out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -21,10 +22,10 @@ out port setup_data_port = XS1_PORT_16B; void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, chanend c){ set_core_fast_mode_on(); while(1){ - i.begin_transaction(0, 736, SPI_MODE_3); + i.begin_transaction(0, SPEED_KBPS, SPI_MODE_3); i.transfer8(0xff); i.end_transaction(100); - delay_microseconds(1); + delay_microseconds(10); // Allow other clients to access SPI and avoid hogging by one c <: 1; } } diff --git a/tests/spi_master_sync_multi_device/test_params.json b/tests/spi_master_sync_multi_device/test_params.json index 20f1b4b..3f57237 100644 --- a/tests/spi_master_sync_multi_device/test_params.json +++ b/tests/spi_master_sync_multi_device/test_params.json @@ -1,6 +1,6 @@ { "BURNT_THREADS": [3, 7], - "CB_ENABLED": [1], + "CB_ENABLED": [1, 0], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], "arch": ["xs2", "xs3"] } diff --git a/tests/test_master_async_shutdown.py b/tests/test_master_async_shutdown.py index cc1a5d0..bc39771 100644 --- a/tests/test_master_async_shutdown.py +++ b/tests/test_master_async_shutdown.py @@ -29,7 +29,7 @@ def do_test(capfd): Pyxsim.run_on_simulator_( binary, - # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) @@ -37,5 +37,5 @@ def do_test(capfd): output = print_expected_vs_output(expected, capfd) assert tester.run(output), output -def test_master_sync_rx_tx(capfd, request): +def test_master_async_shutdown(capfd, request): do_test(capfd) \ No newline at end of file diff --git a/tests/test_master_sync_multi_client.py b/tests/test_master_sync_multi_client.py index 9094beb..a3dcaf5 100644 --- a/tests/test_master_sync_multi_client.py +++ b/tests/test_master_sync_multi_client.py @@ -32,7 +32,7 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd, @@ -43,5 +43,5 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): @pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) -def test_master_sync_rx_tx(capfd, params, request): +def test_master_sync_multi_client(capfd, params, request): do_test(capfd, *params, request.node.callspec.id) From 14cef5bacb305bd0f65955269937a8af5d352b88 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 28 Jul 2025 12:12:37 +0100 Subject: [PATCH 29/57] Ensure minimum SS deassert SMall fix --- lib_spi/src/spi_master_async.xc | 1 + lib_spi/src/spi_master_sync.xc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 218d323..2a4234a 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -243,6 +243,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], //An end_transaction can only be completed after all transfers //have been completed + spi_dev[active_device].cs_to_cs_delay_ticks = ss_deassert_time; spi_master_end_transaction(&spi_dev[active_device]); if(tr_fill > 0){ diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 67b60c3..6796128 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -110,7 +110,9 @@ void spi_master(server interface spi_master_if i[num_clients], // NEED TO WAIT -> Deassert time if(isnull(cb)){ p_ss <: 0xffffffff; + delay_ticks(ss_deassert_time); } else { + spi_dev[current_device].cs_to_cs_delay_ticks = ss_deassert_time; spi_master_end_transaction(&spi_dev[current_device]); } From f25e313578ede0b9a911baa6778a16ef6044278d Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 28 Jul 2025 14:29:03 +0100 Subject: [PATCH 30/57] Add in support for SS and MISO sample delays --- CHANGELOG.rst | 1 + README.rst | 3 ++- lib_spi/api/spi.h | 31 +++++++++++++++++++++++++-- lib_spi/src/spi_fwk.h | 15 ++++++------- lib_spi/src/spi_master_async.xc | 37 +++++++++++++++++++++------------ lib_spi/src/spi_master_sync.xc | 22 ++++++++++++++------ 6 files changed, 80 insertions(+), 29 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 4550173..dc79e94 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -6,6 +6,7 @@ lib_spi change log * CHANGED: SPI master async reduced clock blocks from two to one * CHANGED: SPI master sync increased max speed to 25+ Mbps + * ADDED: Shutdown method for SPI sync * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/README.rst b/README.rst index 8c35180..13d9adb 100644 --- a/README.rst +++ b/README.rst @@ -33,7 +33,8 @@ Features Known issues ************ -* None +* SPI sync (clockblock-less version only) exit task causes exception on exit when distributed. + This is caused by a know XC compiler bug. Please providea clock block if the shutdown method is used. **************** Development repo diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 07b6431..cb2a841 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -6,7 +6,9 @@ #include #include #include - +extern "C" { +#include "../src/spi_fwk.h" +} // These are needed for DOXYGEN to render properly #ifndef __DOXYGEN__ #define static_const_unsigned static const unsigned @@ -25,7 +27,7 @@ #define uint8_t_movable_ptr_t uint8_t * movable #endif -/** This type indicates what mode an SPI component should use */ +/** This type indicates what clocking mode a SPI component should use */ typedef enum spi_mode_t { SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Sampling clock Edge = 1 */ SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Sampling clock Edge = 0 */ @@ -34,6 +36,31 @@ typedef enum spi_mode_t { } spi_mode_t; +/** This type contains timing settings for SS assert to clock delay and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65534 which equates to 655 us + * over which the setting will overflow back to zero */ +typedef struct spi_master_ss_clock_timing_t { + uint32_t cs_to_clk_delay_ticks; + uint32_t clk_to_cs_delay_ticks; +} spi_master_ss_clock_timing_t; + + +/** This type contains timing settings for capturing the MISO pin. + * When the SPI clock is above 20MHz it is usually necessary to delay the + * sampling of the MISO pin. These settings can be coarse grained using + * miso_sample_delay setting which increments in SPI half clocks or + * fine grained in units of core clock (eg. 600MHz) using the + * miso_pad_delay setting. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html */ +typedef struct spi_master_miso_capture_timing_t { + spi_master_sample_delay_t miso_sample_delay; + uint32_t miso_pad_delay; +} spi_master_miso_capture_timing_t; + + /** This interface allows clients to interact with SPI master task. */ #ifndef __DOXYGEN__ typedef interface spi_master_if { diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 3d03cc0..3f8d3cb 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -12,6 +12,9 @@ */ #define SPI_MASTER_MINIMUM_DELAY 10 +/* Default delay from clock to SS, SS de-assert to SS assert and SS to clock */ +#define SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS 15 // 150 nanoseconds + #include /* for size_t */ #include #include /* for byterev() */ @@ -24,7 +27,6 @@ #else #define xclock_t clock #define port_t port -#define thread_mode_t int #endif /* The SETC constant for pad delay is missing from xs2a_user.h */ @@ -58,11 +60,11 @@ inline void spi_io_port_outpw( * for the SPI master sample delay. */ typedef enum { - spi_master_sample_delay_0 = 0, /**< Samples 1/2 clock cycle after output from device */ - spi_master_sample_delay_1 = 1, /**< Samples 3/4 clock cycle after output from device */ - spi_master_sample_delay_2 = 2, /**< Samples 1 clock cycle after output from device */ - spi_master_sample_delay_3 = 3, /**< Samples 1 and 1/4 clock cycle after output from device */ - spi_master_sample_delay_4 = 4, /**< Samples 1 and 1/2 clock cycle after output from device */ + spi_master_sample_delay_1_2 = 0, /**< Samples 1/2 clock cycle after output from device */ + spi_master_sample_delay_3_4 = 1, /**< Samples 3/4 clock cycle after output from device */ + spi_master_sample_delay_1_0 = 2, /**< Samples 1 clock cycle after output from device */ + spi_master_sample_delay_5_4 = 3, /**< Samples 1 and 1/4 clock cycle after output from device */ + spi_master_sample_delay_3_2 = 4, /**< Samples 1 and 1/2 clock cycle after output from device */ } spi_master_sample_delay_t; /** @@ -107,7 +109,6 @@ typedef struct { uint32_t cs_to_clk_delay_ticks; uint32_t clk_to_cs_delay_ticks; uint32_t cs_to_cs_delay_ticks; - thread_mode_t thread_mode; } spi_master_device_t; /** diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 2a4234a..52c5b6e 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -7,9 +7,6 @@ #include #include "spi.h" -extern "C"{ -#include "spi_fwk.h" -} #include "spi_master_shared.h" #define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device @@ -59,8 +56,16 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], //Setup fwk SPI master and device instance spi_master_t spi_master; spi_master_device_t spi_dev[num_slaves]; + spi_master_ss_clock_timing_t device_ss_clock_timing[num_slaves]; // Initialised below + spi_master_miso_capture_timing_t device_miso_capture_timing[num_slaves] = {{0}};// Default no delay + unsafe{ spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + for(int i = 0; i < num_slaves; i++){ + device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + } } // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) @@ -110,15 +115,18 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], unsigned cpol = mode >> 1; unsigned cpha = mode & 0x1; - spi_master_device_init(&spi_dev[device_index], &spi_master, - ss_port_bit[device_index], - cpol, cpha, - source_clock, - divider, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); + spi_master_device_init(&spi_dev[active_device], &spi_master, + ss_port_bit[active_device], + cpol, cpha, + source_clock, + divider, + device_miso_capture_timing[active_device].miso_sample_delay, + device_miso_capture_timing[active_device].miso_pad_delay, + device_ss_clock_timing[active_device].clk_to_cs_delay_ticks, + device_ss_clock_timing[active_device].cs_to_clk_delay_ticks, + spi_dev[active_device].cs_to_cs_delay_ticks); // Write same value back - spi_master_start_transaction(&spi_dev[device_index]); + spi_master_start_transaction(&spi_dev[active_device]); buffer_current_index = 0; currently_performing_a_transaction = 1; @@ -271,8 +279,11 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], cpol, cpha, source_clock, divider, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); + device_miso_capture_timing[new_device_index].miso_sample_delay, + device_miso_capture_timing[new_device_index].miso_pad_delay, + device_ss_clock_timing[new_device_index].clk_to_cs_delay_ticks, + device_ss_clock_timing[new_device_index].cs_to_clk_delay_ticks, + spi_dev[new_device_index].cs_to_cs_delay_ticks); // Write same value back spi_master_start_transaction(&spi_dev[new_device_index]); diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 6796128..a593502 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -10,9 +10,6 @@ #include #include "spi.h" -extern "C"{ - #include "spi_fwk.h" -} #include "spi_master_shared.h" @@ -30,6 +27,8 @@ void spi_master(server interface spi_master_if i[num_clients], // For clock-block based fast SPI spi_master_t spi_master; spi_master_device_t spi_dev[num_slaves]; + spi_master_ss_clock_timing_t device_ss_clock_timing[num_slaves]; // Initialised below + spi_master_miso_capture_timing_t device_miso_capture_timing[num_slaves] = {{0}}; unsigned current_device; // For clock-blockless slow SPI @@ -42,6 +41,14 @@ void spi_master(server interface spi_master_if i[num_clients], if(!isnull(cb)){ unsafe{ spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + // Set default timings + for(int i = 0; i < num_slaves; i++){ + device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_miso_capture_timing[i].miso_pad_delay = spi_master_sample_delay_1_2; // Half a SPI clock + device_miso_capture_timing[i].miso_sample_delay = 0; // Default no delay + spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + } } } else { // Initial SS bit pattern - deselected @@ -92,12 +99,15 @@ void spi_master(server interface spi_master_if i[num_clients], // ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); spi_master_device_init(&spi_dev[current_device], &spi_master, - ss_port_bit[device_index], + ss_port_bit[current_device], cpol, cpha, source_clock, divider, - spi_master_sample_delay_0, - 0, 0 ,0 ,0 ); + device_miso_capture_timing[current_device].miso_sample_delay, + device_miso_capture_timing[current_device].miso_pad_delay, + device_ss_clock_timing[current_device].clk_to_cs_delay_ticks, + device_ss_clock_timing[current_device].cs_to_clk_delay_ticks, + spi_dev[current_device].cs_to_cs_delay_ticks); // Write same value back spi_master_start_transaction(&spi_dev[current_device]); } From 1d2caf6478baaaff16a5c9a73e8b8a5413a7a229 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 30 Jul 2025 12:25:34 +0100 Subject: [PATCH 31/57] Fix SS port glitch issue Sort out includes C vs XC Remove debug from spi master checker --- lib_spi/src/spi_fwk.h | 42 ++++++++++++++++++++++--- lib_spi/src/spi_master.c | 7 +++++ lib_spi/src/spi_master_async.xc | 2 +- lib_spi/src/spi_master_sync.xc | 8 ++--- tests/spi_master_checker.py | 8 ++--- tests/test_master_async_multi_device.py | 2 +- tests/test_master_sync_multi_device.py | 2 +- 7 files changed, 54 insertions(+), 17 deletions(-) diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 3f8d3cb..7035b57 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -7,23 +7,41 @@ */ /** - * The minimum number of clock ticks that should - * be specified for any SPI master delay value. - */ -#define SPI_MASTER_MINIMUM_DELAY 10 + * The minimum number of reference clock ticks that should + * be specified for any SPI master delay value. This value + * is carefully tuned so that the SETPT can be followed by + * the OUT in time so that we avoid this from the XS3 architecture manual: + * + * For a transfer initiated by a SETPT instruction, the direction will be input + * unless an output is executed before the time specified by the SETPT instruction. + * This means the SS port may go high impedance briefly which is undesirable. */ +#define SPI_MASTER_MINIMUM_DELAY (PLATFORM_REFERENCE_MHZ * 80 / PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) /* Default delay from clock to SS, SS de-assert to SS assert and SS to clock */ -#define SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS 15 // 150 nanoseconds +#define SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS 20 // 200 nanoseconds + #include /* for size_t */ #include #include /* for byterev() */ #include +#include #ifndef __XC__ #include #include #include #include +#include +// Copy from xs1.h because this doesn't get included for non __XC__ files +/** + * Tests whether a time input from a timer is considered to come after + * another time input from a timer. The comparison is the same as that + * performed by the function timerafter(). + * \param A The first time to compare. + * \param B The second time to compare. + * \return Whether the first time is after the second. + */ +#define timeafter(A, B) ((int)((B) - (A)) < 0) #else #define xclock_t clock #define port_t port @@ -202,6 +220,18 @@ void spi_master_transfer( size_t len); #ifndef __XC__ + +/** + * Implements a blocking (busy wait) delay for a number of ref ticks + * + * \param delay_ticks The number of reference clock ticks to delay. + */ +static inline void blocking_wait_ticks(uint32_t delay_ticks){ + uint32_t wait_time = get_reference_time(); + wait_time += delay_ticks; + while(!timeafter(get_reference_time(), wait_time)); +} + /** * Enforces a minimum delay between the time this is called and * the next transfer. It must be called during a transaction. @@ -230,6 +260,8 @@ static inline void spi_master_delay_before_next_transfer( */ if (delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + delay_ticks, dev->cs_assert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); } } #endif diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c index dc38461..f4c67e2 100644 --- a/lib_spi/src/spi_master.c +++ b/lib_spi/src/spi_master.c @@ -3,6 +3,8 @@ #include #include #include "spi_fwk.h" +#include + void spi_master_start_transaction( spi_master_device_t *dev) @@ -189,7 +191,10 @@ void spi_master_transfer( * is allowed to deassert. */ if (dev->clk_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + // Use port time port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->clk_to_cs_delay_ticks, dev->cs_assert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); } } @@ -212,6 +217,8 @@ void spi_master_end_transaction( */ if (dev->cs_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->cs_to_cs_delay_ticks, cs_deassert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); } } diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 52c5b6e..8756245 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -68,7 +68,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], } } - // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) + // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) uint8_t ss_port_bit[SPI_MAX_DEVICES]; for(int i = 0; i < SPI_MAX_DEVICES; i++){ ss_port_bit[i] = i; diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index a593502..6baa7a8 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -58,7 +58,7 @@ void spi_master(server interface spi_master_if i[num_clients], int accepting_new_transactions = 1; - // By default use the port bit which is the number of the client (client 0 uses port bit 0 etc.) + // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) uint8_t ss_port_bit[num_slaves]; for(int i = 0; i < num_slaves; i++){ ss_port_bit[i] = i; @@ -85,9 +85,9 @@ void spi_master(server interface spi_master_if i[num_clients], partout(sclk, 1, cpol); sync(sclk); - unsigned ss_port_val = ~(1 << ss_port_bit[device_index]); + unsigned ss_port_val = ~(1 << ss_port_bit[current_device]); p_ss <: ss_port_val; - clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1)/speed_in_khz;// round up + clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1) / speed_in_khz;// round up (rounds speed down) } else { spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); @@ -116,8 +116,6 @@ void spi_master(server interface spi_master_if i[num_clients], } case i[int x].end_transaction(unsigned ss_deassert_time):{ - - // NEED TO WAIT -> Deassert time if(isnull(cb)){ p_ss <: 0xffffffff; delay_ticks(ss_deassert_time); diff --git a/tests/spi_master_checker.py b/tests/spi_master_checker.py index f8d3d35..96c2648 100644 --- a/tests/spi_master_checker.py +++ b/tests/spi_master_checker.py @@ -114,19 +114,19 @@ def run(self) -> None: tx_bit_counter += 1 tx_byte = tx_byte << 1 - ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) + ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) # Select of interest sck_value = xsi.sample_port_pins(self._sck_port) while ss_value == 0: self.wait_for_port_pins_change([self._ss_port] + [self._sck_port]) - + # check no other SS asserted ss_port_val = xsi.sample_port_pins(self._ss_port) & ss_deaserted_value # print(f"{self._ss_port}, 0x{ss_port_val:x}, 0x{ss_deaserted_value:x}, {active_slave}, {(ss_deaserted_value & ~(1 << active_slave)):x}") for i in range(self._ss_port_width): - if not ss_port_val & (1 << i) and i != active_slave: + if (ss_port_val & (1 << i) == 0) and (i != active_slave): error = True - print(f"Error: Second slave selected during first transaction, SS port val: 0x{ss_port_val:x} at time: {xsi.get_time() / nanosecond_ticks}ns") + print(f"Error: Additional slave selected during first transaction, SS port val:0x{ss_port_val:x} (active slave:{active_slave} mask 0x{ss_deaserted_value:x}) at time: {xsi.get_time() / nanosecond_ticks}ns") if (ss_value == ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) and (sck_value == xsi.sample_port_pins(self._sck_port))): continue diff --git a/tests/test_master_async_multi_device.py b/tests/test_master_async_multi_device.py index 0434fd8..b92e80b 100644 --- a/tests/test_master_async_multi_device.py +++ b/tests/test_master_async_multi_device.py @@ -33,7 +33,7 @@ def do_test(capfd, combined, burnt, mosi_enabled, arch, id): Pyxsim.run_on_simulator_( binary, - # simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -pads -functions'], do_xe_prebuild = False, simthreads = [checker], capfd=capfd) diff --git a/tests/test_master_sync_multi_device.py b/tests/test_master_sync_multi_device.py index 12af438..5d222f6 100644 --- a/tests/test_master_sync_multi_device.py +++ b/tests/test_master_sync_multi_device.py @@ -31,7 +31,7 @@ def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): regexp = False, ordered = True) - simargs = ['--vcd-tracing', '-o trace.vcd -tile tile[0] -pads -ports -functions'] + simargs = ['--vcd-tracing', '-o trace.vcd -tile tile[0] -pads -ports -ports-detailed -functions -instructions -cycles -cores'] simargs = [] # Disable VCD tracing Pyxsim.run_on_simulator_( From c3fb839d6fd27ce24a6313295effcef2d96c7798 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 30 Jul 2025 14:52:54 +0100 Subject: [PATCH 32/57] Add SPI timing methods to masters --- lib_spi/api/spi.h | 58 +++++++++++++++++++++++++++++---- lib_spi/src/spi_master_async.xc | 12 +++++++ lib_spi/src/spi_master_sync.xc | 12 ++++++- 3 files changed, 75 insertions(+), 7 deletions(-) diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index cb2a841..10d8c78 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -38,7 +38,7 @@ typedef enum spi_mode_t { /** This type contains timing settings for SS assert to clock delay and last * clock to SS de-assert delay. The unit is reference timer ticks which is - * nominally 10 ns. The maximum setting is 65534 which equates to 655 us + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us * over which the setting will overflow back to zero */ typedef struct spi_master_ss_clock_timing_t { uint32_t cs_to_clk_delay_ticks; @@ -121,19 +121,44 @@ typedef interface spi_master_if { */ uint32_t transfer32(uint32_t data); - /** Sets the bit of port which is used for slave select (> 1b port type only) * and only for spi_master. spi_master sets all bits in each port high/low * * The default value (if this is not called) is the bit number is equal to - * the device_index (0->0, 1->1 etc.). + * the device_index (device 0-> bit 0, device 1-> bit 1 etc.). * * \param device_index The index of the device for which the port bit is to be set. * \param ss_port_bit Which bit number in the port to use for slave select. */ void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); - /** Shut down the interface server. + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * These settings only affect the fast SPI master which uses a clock block. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * These settings only affect the fast SPI master which uses a clock block. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); + + /** Shut down the interface server. See known issues in README.rst. */ void shutdown(void); @@ -259,7 +284,6 @@ typedef interface spi_master_async_if { uint32_t_movable_ptr_t outbuf, size_t nwords); - /** Transfer completed notification. * * This notification occurs when a transfer is completed. @@ -298,7 +322,6 @@ typedef interface spi_master_async_if { void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); - /** Sets the bit of port which is used for slave select (> 1b port type only) * and only for spi_master. spi_master sets all bits in each port high/low * @@ -310,6 +333,29 @@ typedef interface spi_master_async_if { */ void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); /** Shut down the interface server. */ diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 8756245..6d7a890 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -65,6 +65,8 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_miso_capture_timing[i].miso_pad_delay = spi_master_sample_delay_1_2; // Half a SPI clock + device_miso_capture_timing[i].miso_sample_delay = 0; // Default no delay } } @@ -336,6 +338,16 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], break; } + case i[int x].set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing):{ + device_miso_capture_timing[x] = miso_capture_timing; + break; + } + + case i[int x].set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing):{ + device_ss_clock_timing[x] = ss_clock_timing; + break; + } + case i[int x].shutdown(void): move(buffer_rx); move(buffer_tx); diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 6baa7a8..75a43ff 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -45,9 +45,9 @@ void spi_master(server interface spi_master_if i[num_clients], for(int i = 0; i < num_slaves; i++){ device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; device_miso_capture_timing[i].miso_pad_delay = spi_master_sample_delay_1_2; // Half a SPI clock device_miso_capture_timing[i].miso_sample_delay = 0; // Default no delay - spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; } } } else { @@ -164,6 +164,16 @@ void spi_master(server interface spi_master_if i[num_clients], break; } + case i[int x].set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing):{ + device_miso_capture_timing[x] = miso_capture_timing; + break; + } + + case i[int x].set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing):{ + device_ss_clock_timing[x] = ss_clock_timing; + break; + } + case i[int x].shutdown(void):{ p_ss <: 0xffffffff; // If using XC, then we need to enable/init which is how XC does it From 5cd67c4eb336f47ef96be4f9b6c988ba76a08f71 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 31 Jul 2025 13:58:24 +0100 Subject: [PATCH 33/57] Initial docs update --- CHANGELOG.rst | 1 + doc/images/spi_master_connect.odg | Bin 12758 -> 14167 bytes doc/images/spi_master_connect.svg | 976 ++++++++++++++++++++++++++++-- doc/images/spi_slave_connect.svg | 851 ++++++++++++++++++++++++-- doc/images/wavedrom_mode0.js | 13 +- doc/images/wavedrom_mode0.png | Bin 19051 -> 19070 bytes doc/images/wavedrom_mode1.js | 13 +- doc/images/wavedrom_mode1.png | Bin 19070 -> 19051 bytes doc/rst/lib_spi.rst | 71 ++- lib_spi/api/spi.h | 8 +- lib_spi/src/spi_master_sync.xc | 2 +- 11 files changed, 1792 insertions(+), 143 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index dc79e94..ff7d0c9 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -7,6 +7,7 @@ lib_spi change log * CHANGED: SPI master async reduced clock blocks from two to one * CHANGED: SPI master sync increased max speed to 25+ Mbps * ADDED: Shutdown method for SPI sync + * ADDED: SPI master optional MISO and SS timing adjustments * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/doc/images/spi_master_connect.odg b/doc/images/spi_master_connect.odg index 245e2f5f9ee17924268376c32114b0e20e2a9016..f77d0eeb477ef3b3569e7ca002449fcbd07cd73c 100644 GIT binary patch literal 14167 zcmd73V}K^fwk}-gvTb(Rwr$(C?dr18&?tJ zGBehbD4r zp}v#3tqrY)Scf{J`)|s`&cW8y!PxOn zcLxp*{#%Rq$oy|1{Yd?_0`(0IjjfD7>eJSN*3j9(;a5{|v$g^Tkdp-a)q((k{zv^^ zRr`0akRLf5o!qUA9e-)AX{|Y|G@*3-R5YurZOL#>5s_oS4YL^VsZ-31~C3O4i_5mx#Mw9Kk??AUZyAv zdn3R+&@h3f^6CBMsf_jL-Ql%})s06Kp)JzBPNzG;gME#J?q_wkxetUwUCVKmxJMX& z^wkJ*xt@=Bo@9Er5?nKtIiPWbc6hy!VTVB2$*1)BhzknC+EGL^nRtX0MgjWv6Q_N2 z$4at^kekxZe5Tf$*D({v28>Monu|`KJNGQnE#O<`TmN2r1yLMWP(k0VfiFNmal6N4 zJ$iq{Ra%ICnmL+9YfokBryQB}n;_$IoA@*cMfKUA;W)A|n*}7xaJyVe#xmMCRa?U- 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + xCORE device + + + + + + + + + + + + SCLK + + + + + + + + 1 bitport + + + + + + + + + + + + MOSI + + + + + + + + 1 bitport + + + + + + + + + + + + MISO + + + + + + + + 1 bitport + + + + + + + + + + + + SS0 + + + + + + + + + + + + SSn + + + + + + + + Anyport + + + + + + ... + + + + + + + diff --git a/doc/images/spi_slave_connect.svg b/doc/images/spi_slave_connect.svg index 364f764..42ac8cd 100644 --- a/doc/images/spi_slave_connect.svg +++ b/doc/images/spi_slave_connect.svg @@ -1,46 +1,807 @@ - - - - - - - - - - - - - - - - -xCORE device - -SCLK - - -1 bit -port - -MOSI - - -1 bit -port - -MISO - - -1 bit -port - -SS - - -1 bit -port - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + xCORE device + + + + + + + + + + + + SCLK + + + + + + + + 1 bitport + + + + + + + + + + + + MOSI + + + + + + + + 1 bitport + + + + + + + + + + + + MISO + + + + + + + + 1 bitport + + + + + + + + + + + + SS + + + + + + + + 1 bitport + + + + + + + diff --git a/doc/images/wavedrom_mode0.js b/doc/images/wavedrom_mode0.js index 3cee681..4ffa214 100644 --- a/doc/images/wavedrom_mode0.js +++ b/doc/images/wavedrom_mode0.js @@ -1,8 +1,9 @@ {signal: [ -{name: 'CLK', wave: '0..101010|10....', node: '...B'}, -{name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, -{name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, -{name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, -{ node: '.a.b........c..d'} ], -edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] + {name: 'CLK', wave: '0...10101|010...', node: '...B'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', 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zQ)#iF!KWW;vzBaL<0hy7RjXK`e?M^K%+>#4H=os~{(cR#ea_H5)mAqifzI#Q!?B%j z8-oZha1FnpDzvhPo;d_Ms|da_P!+nN+5xgI@EwbXL$D99DFNk!9l{G;oXC6ep`s>s zTW38w9|0Uf_ diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 78fae76..147af4c 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -68,7 +68,7 @@ relative to the clock. The timings are given by: The setup and hold timings are inherited from the underlying xCORE device. For details on these timing please refer to the device datasheet. -Mode 0 - CPOL: 0 CPHA 1 +Mode 0 - CPOL: 0 CPHA 0 ======================= .. figure:: ../images/wavedrom_mode0.png @@ -76,9 +76,9 @@ Mode 0 - CPOL: 0 CPHA 1 Mode 0 -The master and slave will drive out their first data bit on the first rising edge of the clock and sample on the subsequent falling edge. +The master and slave will drive out their first data bit before the first rising edge of the clock then drive on subsequent falling edges. They will sample on rising edges. -Mode 1 - CPOL: 0 CPHA 0 +Mode 1 - CPOL: 0 CPHA 1 ======================= .. figure:: ../images/wavedrom_mode1.png @@ -86,8 +86,7 @@ Mode 1 - CPOL: 0 CPHA 0 Mode 1 -The master and slave will drive out their first data bit before the first rising edge of the clock then drive on subsequent falling edges. They will sample on rising edges. - +The master and slave will drive out their first data bit on the first rising edge of the clock and sample on the subsequent falling edge. Mode 2 - CPOL: 1 CPHA 0 ======================= @@ -168,12 +167,28 @@ the asynchronous master can output a clock at up to 100MHz, port timing and hard - MOSI enabled - Max kbps (62.5 MHz core) - Max kbps (125 MHz core) - * - 2 + * - 1 - x - x - 100000 - 100000 +MISO port timing +================ + +Port timing is affected by chip pad and PCB delays. For clock, slave-select and MOSI all of the delays will be broadly matched. +This means port timing adjustment is normally not required even up to the fastest support SPI clock rates. + +For MISO, there will be a 'round trip delay' starting with the clock edge and finishing at the xCORE's input port. +Since this delay will mean the xCORE will be sampling early, it may be necessary to delay the sampling of the MISO +pin to capture within the required window, particularly if the SPI clock is above 20 MHz. + +Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the +API section which exposes the controls available for optimising setup and hold capture. + +For details on how to calculate and adjust round-trip port timing, please consult the `IO timings for xcore.ai `_ document. + + |newpage| @@ -183,8 +198,8 @@ Connecting to the xCORE SPI master The SPI wires need to be connected to the xCORE device as shown in :numref:`spi_master_xcore_connect`. The signals can be connected to any -one bit ports on the device provide they do not overlap any other used -ports and are all on the same tile. +one bit ports, with the exception of slave select which may be any width +port. All ports must be on the same tile. .. _spi_master_xcore_connect: @@ -198,8 +213,8 @@ need not be connected. However, **asynchronous mode is only supported if the MISO line is connected**. The master component of this library supports multiple slaves on unique -slave select wires. This means that a single slave select assertion -cannot be used to communicate with multiple slaves at the same time. +slave select wires. The bit of the port used for each device is configurable +and so multiple slaves may share the same select bit if needed. SPI slave timings ================= @@ -283,7 +298,7 @@ For example, the following code instantiates an SPI master component and connect to it:: out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss[1] = {XS1_PORT_1B}; + out port p_ss = XS1_PORT_1B; out buffered port:22 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock clk_spi = XS1_CLKBLK_1; @@ -305,7 +320,7 @@ devices via different slave lines. The final parameter of the ``spi_master`` task is an optional clock block. If the clock block is supplied then the maximum transfer rate of the SPI bus is increased (see :numref:`spi_master_sync_timings`). If -``null`` is supplied instead then the performance is less but no clock +``null`` is supplied instead then the performance is lower but no clock block is used. The application can use the client end of the interface connection to @@ -339,7 +354,7 @@ Synchronous master usage state machine The function calls made on the SPI master interface must follow the sequence shown by the state machine in :numref:`spi_master_usage_state_machine`. -If this sequence is not followed then the behavior is undefined. +If this sequence is not followed then the behaviour is undefined. .. _spi_master_usage_state_machine: @@ -359,7 +374,7 @@ operation is complete. In cases where the application cannot afford to wait for this long the asynchronous API can be used. The asynchronous API offloads operations to another task. Calls are -provide to initiate reads and writes and notifications are provided +provided to initiate reads and writes and notifications are provided when the operation completes. This API requires more management in the application but can provide much more efficient operation. It is particularly suitable for applications where the SPI bus is @@ -369,17 +384,16 @@ Setting up an asynchronous SPI master component is done in the same manner as the synchronous component:: out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss[1] = {XS1_PORT_1B}; + out port p_ss = XS1_PORT_1B; out buffered port:22 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; - clock cb0 = XS1_CLKBLK_1; - clock cb1 = XS1_CLKBLK_2; + clock cb = XS1_CLKBLK_1; int main(void) { spi_master_async_if i_spi[1]; par { - spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); my_application(i_spi[0]); } return 0; @@ -402,7 +416,7 @@ bytes coming back from the slave:: // create and send initial data fill_buffer_with_data(outdata); - spi.begin_transaction(0, 100, SPI_MODE_0); + spi.begin_transaction(0, 1000, SPI_MODE_0); spi.init_transfer_array_8(move(buf_in), move(buf_out), 100); while (1) { select { @@ -445,7 +459,7 @@ Asynchronous master usage state machine The function calls made on the SPI master asynchronous interface must follow the sequence shown by the state machine in :numref:`spi_master_usage_state_machine_async`. -If this sequence is not followed then the behavior is undefined. +If this sequence is not followed then the behaviour is undefined. .. _spi_master_usage_state_machine_async: @@ -483,10 +497,10 @@ For example, the following code instantiates an SPI slave component and connect to it:: out buffered port:32 p_miso = XS1_PORT_1E; - in port p_ss = XS1_PORT_1F; + in port p_ss = XS1_PORT_1F; in port p_sclk = XS1_PORT_1G; in buffered port:32 p_mosi = XS1_PORT_1H; - clock cb = XS1_CLKBLK_1; + clock cb = XS1_CLKBLK_1; int main(void) { interface spi_slave_callback_if i_spi; @@ -643,17 +657,17 @@ Each of the SPI implementations use a number of `xcore` resources which include * - Master (synchronous, zero clock blocks) - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); - 4 - - 4 (1-bit) + - 3 * 1-bit, 1 * any-bit - 0 * - Master (synchronous, one clock block) - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - 4 - - 4 (1-bit) + - 3 * 1-bit, 1 * any-bit - 0 * - Master (asynchronous) - - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); + - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - 4 - - 4 (1-bit) + - 3 * 1-bit, 1 * any-bit - 1 * - Slave (32 bit transfer mode) - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); @@ -693,6 +707,10 @@ The following type is used to configure the SPI components. .. doxygenenum:: spi_mode_t +.. doxygenstruct:: spi_master_ss_clock_timing_t + +.. doxygenstruct:: spi_master_miso_capture_timing_t + |newpage| Creating an SPI master instance @@ -700,7 +718,6 @@ Creating an SPI master instance .. doxygenfunction:: spi_master -|newpage| .. doxygenfunction:: spi_master_async diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 10d8c78..dceb3b1 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -29,10 +29,10 @@ extern "C" { /** This type indicates what clocking mode a SPI component should use */ typedef enum spi_mode_t { - SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Sampling clock Edge = 1 */ - SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Sampling clock Edge = 0 */ - SPI_MODE_2 = 2, /**< SPI Mode 2 - Polarity = 1, Sampling Clock Edge = 0 */ - SPI_MODE_3 = 3, /**< SPI Mode 3 - Polarity = 1, Sampling Clock Edge = 1 */ + SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Phase = 0 */ + SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Phase = 1 */ + SPI_MODE_2 = 2, /**< SPI Mode 2 - Polarity = 1, Phase = 0 */ + SPI_MODE_3 = 3, /**< SPI Mode 3 - Polarity = 1, Phase = 1 */ } spi_mode_t; diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 75a43ff..72dd806 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -87,7 +87,7 @@ void spi_master(server interface spi_master_if i[num_clients], unsigned ss_port_val = ~(1 << ss_port_bit[current_device]); p_ss <: ss_port_val; - clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1) / speed_in_khz;// round up (rounds speed down) + clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1) / speed_in_khz; // round up (rounds speed down) } else { spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); From d366add80cb6330f21ebd2971485245adbfe0699 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 31 Jul 2025 14:26:32 +0100 Subject: [PATCH 34/57] Adding CBless sync master tests (broken currently) Fix sync rx tx tweak ranges in benchmark test remove unneeded tracing Bring upper bound of speed down in CBless Limit max speed so test is happy --- .../spi_master_sync_benchmark/CMakeLists.txt | 62 +++++++++------- .../src/spi_master_sync_benchmark.xc | 41 ++++++++++- .../test_params.json | 1 + tests/spi_master_sync_rx_tx/CMakeLists.txt | 72 ++++++++++--------- .../src/spi_master_sync_rx_tx.xc | 15 +++- tests/spi_master_sync_rx_tx/test_params.json | 1 + .../spi_sync_tester.h | 2 +- tests/test_master_sync_benchmark.py | 8 +-- tests/test_master_sync_rx_tx.py | 4 +- 9 files changed, 135 insertions(+), 71 deletions(-) diff --git a/tests/spi_master_sync_benchmark/CMakeLists.txt b/tests/spi_master_sync_benchmark/CMakeLists.txt index 1c9e5e0..bb400a0 100644 --- a/tests/spi_master_sync_benchmark/CMakeLists.txt +++ b/tests/spi_master_sync_benchmark/CMakeLists.txt @@ -9,11 +9,13 @@ string(JSON arch_list GET ${params_json} arch) string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) string(JSON spi_mode_list GET ${params_json} SPI_MODE) string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) string(JSON arch_list_len LENGTH ${arch_list}) string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) # Subtract one off each of the lengths because RANGE includes last element @@ -21,6 +23,7 @@ math(EXPR arch_list_len "${arch_list_len} - 1") math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") set(APP_PCA_ENABLE ON) @@ -44,41 +47,46 @@ foreach(i RANGE 0 ${arch_list_len}) foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) - set(config ${burnt_threads}_${SPI_MODE}_${miso_mosi_enabled}_${arch}) - message(STATUS "building config ${config}") + foreach(m RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${m}) - project(spi_master_sync_benchmark) - set(APP_HW_TARGET ${target}) + set(config ${burnt_threads}_${SPI_MODE}_${miso_mosi_enabled}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") - string(FIND "${config}" "mosi" pos) - if(NOT pos EQUAL -1) - list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") - else() - list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") - endif() + project(spi_master_sync_benchmark) + set(APP_HW_TARGET ${target}) - string(FIND "${config}" "miso" pos) - if(NOT pos EQUAL -1) - list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") - else() - list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") - endif() + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() - set(APP_INCLUDES src ../spi_master_tester_common) + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() - set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} - -DBURNT_THREADS=${burnt_threads} - -DSPI_MODE=${SPI_MODE} - -O2 - -g - -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DSPI_MODE=${SPI_MODE} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) - XMOS_REGISTER_APP() - message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") - unset(APP_COMPILER_FLAGS_${config}) - unset(CONFIG_COMPILER_FLAGS) + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() endforeach() endforeach() endforeach() diff --git a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc index 1c7707d..560472b 100644 --- a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -25,18 +25,47 @@ clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; +#if CB_ENABLED + #define MAX_TEST_SPEED 150000 + #define MIN_TEST_SPEED 10000 +#else + #if BURNT_THREADS > 3 + #define MAX_TEST_SPEED 3000 + #else + #define MAX_TEST_SPEED 4000 // Above this speed SPI synch tends to fail badly so limit upper + #endif + #define MIN_TEST_SPEED 1000 +#endif static unsigned get_max_speed(unsigned transfer_width, client interface spi_master_if i){ - unsigned min_test_speed = 1000, max_test_speed = 150000;//kbps + unsigned min_test_speed = MIN_TEST_SPEED, max_test_speed = MAX_TEST_SPEED;//kbps unsigned iteration = 0; unsigned test_speed = min_test_speed; while(1){ // Make sure we set the actual speed attainable +#if CB_ENABLED spi_master_source_clock_t source_clock; unsigned divider; spi_master_determine_clock_settings(&source_clock, ÷r, test_speed); unsigned actual_test_speed = spi_master_get_actual_clock_rate(source_clock, divider); + // Improve MISO timing + if(MISO_ENABLED){ + spi_master_miso_capture_timing_t miso_capture_timing = {0}; + if(actual_test_speed > 50000){ + miso_capture_timing.miso_sample_delay = (actual_test_speed - 50000) / 18000; + printf("MISO delay setting: %d\n", miso_capture_timing.miso_sample_delay); + } else { + miso_capture_timing.miso_sample_delay = spi_master_sample_delay_1_2; + } + miso_capture_timing.miso_pad_delay = 0; + i.set_miso_capture_timing(0, miso_capture_timing); + } +#else + unsigned clkblkless_period_ticks = (XS1_TIMER_KHZ + test_speed - 1) / test_speed; + unsigned actual_test_speed = XS1_TIMER_KHZ / clkblkless_period_ticks; +#endif + printf("testing:%u:%u:", transfer_width, actual_test_speed); int error = 0; if(transfer_width == 8){ @@ -57,7 +86,7 @@ static unsigned get_max_speed(unsigned transfer_width, client interface spi_mast printf("PASS\n"); test_speed = (test_speed + max_test_speed) / 2; } - if(iteration++ == 7) return 0; // 7 always gets us there + if(iteration++ == 5) return 0; // This always gets us there } return 0; } @@ -89,10 +118,16 @@ static void load(static const unsigned num_threads){ #define MISO null #endif +#if CB_ENABLED +#define CB cb +#else +#define CB null +#endif + int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); app(i[0], MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_benchmark/test_params.json b/tests/spi_master_sync_benchmark/test_params.json index b57f2ab..5e8cb1e 100644 --- a/tests/spi_master_sync_benchmark/test_params.json +++ b/tests/spi_master_sync_benchmark/test_params.json @@ -2,5 +2,6 @@ "BURNT_THREADS": [3, 7], "SPI_MODE": [0, 1, 2, 3], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "CB_ENABLED": [1, 0], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_sync_rx_tx/CMakeLists.txt b/tests/spi_master_sync_rx_tx/CMakeLists.txt index c098237..a71c61f 100644 --- a/tests/spi_master_sync_rx_tx/CMakeLists.txt +++ b/tests/spi_master_sync_rx_tx/CMakeLists.txt @@ -9,11 +9,13 @@ string(JSON arch_list GET ${params_json} arch) string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) string(JSON spi_mode_list GET ${params_json} SPI_MODE) string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) string(JSON arch_list_len LENGTH ${arch_list}) string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) # Subtract one off each of the lengths because RANGE includes last element @@ -21,6 +23,7 @@ math(EXPR arch_list_len "${arch_list_len} - 1") math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") set(APP_PCA_ENABLE ON) @@ -44,38 +47,43 @@ foreach(i RANGE 0 ${arch_list_len}) foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) - set(config ${burnt_threads}_${miso_mosi_enabled}_${spi_mode}_${arch}) - message(STATUS "building config ${config}") - - project(spi_master_sync_rx_tx) - set(APP_HW_TARGET ${target}) - - string(FIND "${config}" "mosi" pos) - if(NOT pos EQUAL -1) - list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") - else() - list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") - endif() - - string(FIND "${config}" "miso" pos) - if(NOT pos EQUAL -1) - list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") - else() - list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") - endif() - - set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} - -DBURNT_THREADS=${burnt_threads} - -DSPI_MODE=${spi_mode} - -O2 - -g - -Wno-reinterpret-alignment) - set(APP_INCLUDES src ../spi_master_tester_common) - - XMOS_REGISTER_APP() - - unset(APP_COMPILER_FLAGS_${config}) - unset(CONFIG_COMPILER_FLAGS) + foreach(m RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${m}) + + set(config ${burnt_threads}_${miso_mosi_enabled}_${spi_mode}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_rx_tx) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DSPI_MODE=${spi_mode} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() endforeach() endforeach() endforeach() diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index e991624..7cc80b2 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -16,8 +16,14 @@ clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; -void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ +#if CB_ENABLED #define SPEED_TESTS 3 +#else +#define SPEED_TESTS 1 +#endif + + +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 33000}; // Speed in kHz // printf("Device 8 SPI_MODE: %d\n", spi_mode); @@ -56,11 +62,16 @@ static void load(static const unsigned num_threads){ #define MISO null #endif +#if CB_ENABLED +#define CB cb +#else +#define CB null +#endif int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, cb); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); app(i[0], MOSI_ENABLED, MISO_ENABLED, SPI_MODE); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_rx_tx/test_params.json b/tests/spi_master_sync_rx_tx/test_params.json index 3c82def..0087ae2 100644 --- a/tests/spi_master_sync_rx_tx/test_params.json +++ b/tests/spi_master_sync_rx_tx/test_params.json @@ -2,5 +2,6 @@ "BURNT_THREADS": [3, 7], "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], "SPI_MODE": [0, 1, 2, 3], + "CB_ENABLED": [1, 0], "arch": ["xs2", "xs3"] } diff --git a/tests/spi_master_tester_common/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h index c172633..efbca24 100644 --- a/tests/spi_master_tester_common/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -64,7 +64,7 @@ int test_transfer32(client interface spi_master_if i, if(miso_enabled){ if(rx != (rx_data, unsigned[])[j]) error = 1; if(VERBOSE && (rx != (rx_data, unsigned[])[j])) - printf("%08x %08x\n", rx ,(rx_data, unsigned[])[j]); + printf("Device Got: %08x Expected: %08x from MISO\n", rx ,(rx_data, unsigned[])[j]); } } i.end_transaction(inter_frame_gap); diff --git a/tests/test_master_sync_benchmark.py b/tests/test_master_sync_benchmark.py index 1a316af..5231cc8 100644 --- a/tests/test_master_sync_benchmark.py +++ b/tests/test_master_sync_benchmark.py @@ -18,7 +18,7 @@ def __init__(self, id): self.result = dict(item.split('=') for item in id.split(', ')) def run(self, output): - ignore_list = ["SPI Master checker"] + ignore_list = ["SPI Master checker", "MISO delay setting"] result_8b = None result_32b = None for line in output: print(line) @@ -48,8 +48,8 @@ def remove_test_results(): # Post test cleanup sort_csv_table(test_results_file) -def do_benchmark_sync(capfd, burnt, spi_mode, miso_mosi_enabled, arch, id): - id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{arch}" +def do_benchmark_sync(capfd, burnt, spi_mode, miso_mosi_enabled, cb_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{cb_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists(), f"Binary file {binary} not present - please pre-build" @@ -68,7 +68,7 @@ def do_benchmark_sync(capfd, burnt, spi_mode, miso_mosi_enabled, arch, id): tester = tester, do_xe_prebuild = False, simthreads = [checker], - simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -clock-blocks -ports -ports-detailed -pads -functions'], + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -clock-blocks -ports -ports-detailed -pads -functions'], capfd=capfd) diff --git a/tests/test_master_sync_rx_tx.py b/tests/test_master_sync_rx_tx.py index faf2194..a65902d 100644 --- a/tests/test_master_sync_rx_tx.py +++ b/tests/test_master_sync_rx_tx.py @@ -10,8 +10,8 @@ appname = "spi_master_sync_rx_tx" test_params_file = Path(__file__).parent / f"{appname}/test_params.json" -def do_test(capfd, burnt, spi_mode, miso_mosi_enabled, arch, id): - id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{arch}" +def do_test(capfd, burnt, spi_mode, miso_mosi_enabled, cb_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{cb_enabled}_{arch}" filepath = Path(__file__).resolve().parent binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists() From b20fd9dea11996ae8bbfb54655bdef4a933af615 Mon Sep 17 00:00:00 2001 From: Ed Date: Sun, 3 Aug 2025 16:16:30 +0100 Subject: [PATCH 35/57] Update max speeds in docs Fix issue with sync no-CB shutdown --- CHANGELOG.rst | 1 + README.rst | 3 +-- doc/rst/lib_spi.rst | 22 +++++++++---------- examples/AN00160_using_SPI_master/src/main.xc | 2 +- lib_spi/src/spi_fwk.h | 10 ++++----- lib_spi/src/spi_master_async.xc | 2 +- lib_spi/src/spi_master_sync.xc | 2 +- tests/test_master_sync_shutdown.py | 5 ----- 8 files changed, 21 insertions(+), 26 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index ff7d0c9..3883d3d 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -10,6 +10,7 @@ lib_spi change log * ADDED: SPI master optional MISO and SS timing adjustments * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests + * REMOVED: Support for XS1 devices 3.4.0 ----- diff --git a/README.rst b/README.rst index 13d9adb..8c35180 100644 --- a/README.rst +++ b/README.rst @@ -33,8 +33,7 @@ Features Known issues ************ -* SPI sync (clockblock-less version only) exit task causes exception on exit when distributed. - This is caused by a know XC compiler bug. Please providea clock block if the shutdown method is used. +* None **************** Development repo diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 147af4c..6f9f3bc 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -126,30 +126,30 @@ timings can be seen in :numref:`spi_master_sync_timings`. :header-rows: 1 * - Clock blocks - - MISO enabled - MOSI enabled + - MISO enabled - Max kbps (62.5 MHz core) - Max kbps (125 MHz core) * - 0 - 1 - 0 - - 2497 - - 3366 + - 2500 + - 3500 * - 0 - 1 - 1 - - 1765 - - 3366 + - 1200 + - 1300 * - 1 - 1 - 0 - - 2149 - - 2149 + - 62500 + - 75000 * - 1 - 1 - 1 - - 2149 - - 2149 + - 62500 + - 75000 Asynchronous SPI master clock speeds @@ -170,8 +170,8 @@ the asynchronous master can output a clock at up to 100MHz, port timing and hard * - 1 - x - x - - 100000 - - 100000 + - 62500 + - 75000 MISO port timing ================ diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index ea222b3..f872897 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -25,8 +25,8 @@ void app(client spi_master_if spi) p_rstn <: 0x2; //Take out of reset and wait delay_microseconds(1000); - spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 + spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 spi.begin_transaction(0, 1000, SPI_MODE_0); diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 7035b57..4c74339 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -33,8 +33,7 @@ #include #include // Copy from xs1.h because this doesn't get included for non __XC__ files -/** - * Tests whether a time input from a timer is considered to come after +/**Tests whether a time input from a timer is considered to come after * another time input from a timer. The comparison is the same as that * performed by the function timerafter(). * \param A The first time to compare. @@ -42,9 +41,10 @@ * \return Whether the first time is after the second. */ #define timeafter(A, B) ((int)((B) - (A)) < 0) -#else -#define xclock_t clock -#define port_t port +#else /* __XC__ defined */ +/* When using XC, ensure we don't define as resource types to avoid issues with automatics */ +#define xclock_t unsigned +#define port_t unsigned #endif /* The SETC constant for pad delay is missing from xs2a_user.h */ diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 6d7a890..e785b6f 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -60,7 +60,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], spi_master_miso_capture_timing_t device_miso_capture_timing[num_slaves] = {{0}};// Default no delay unsafe{ - spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)sclk, (port_t)mosi, (port_t)miso); for(int i = 0; i < num_slaves; i++){ device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index 72dd806..ce841a4 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -40,7 +40,7 @@ void spi_master(server interface spi_master_if i[num_clients], if(!isnull(cb)){ unsafe{ - spi_master_init(&spi_master, cb, (port)p_ss, (port)sclk, (port)mosi, (port)miso); + spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)sclk, (port_t)mosi, (port_t)miso); // Set default timings for(int i = 0; i < num_slaves; i++){ device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; diff --git a/tests/test_master_sync_shutdown.py b/tests/test_master_sync_shutdown.py index 9c26f42..35cd7e7 100644 --- a/tests/test_master_sync_shutdown.py +++ b/tests/test_master_sync_shutdown.py @@ -16,11 +16,6 @@ def do_test(distributed, cb_enabled, arch, capfd): binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists() - # Known issue when clock block is NULL and SPI master sync is distributed - compiler bug on task cleanup - # http://bugzilla.xmos.local/show_bug.cgi?id=19049 - if distributed == 1 and cb_enabled == 0: - pytest.xfail() - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1A", From 4e88557dddfb630ea69acf2710d421f4c1272ad2 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 4 Aug 2025 12:24:09 +0100 Subject: [PATCH 36/57] Shutdown for slave with test --- CHANGELOG.rst | 3 +- lib_spi/api/spi.h | 16 +- lib_spi/src/spi_fwk.h | 49 ---- lib_spi/src/spi_slave.xc | 251 ++++++++-------- tests/CMakeLists.txt | 1 + tests/spi_slave_checker.py | 1 + tests/spi_slave_shutdown/CMakeLists.txt | 52 ++++ tests/spi_slave_shutdown/config.xscope | 3 + .../src/spi_slave_shutdown.xc | 273 ++++++++++++++++++ tests/spi_slave_shutdown/test_params.json | 4 + tests/test_slave_shutdown.py | 51 ++++ 11 files changed, 532 insertions(+), 172 deletions(-) create mode 100644 tests/spi_slave_shutdown/CMakeLists.txt create mode 100644 tests/spi_slave_shutdown/config.xscope create mode 100644 tests/spi_slave_shutdown/src/spi_slave_shutdown.xc create mode 100644 tests/spi_slave_shutdown/test_params.json create mode 100644 tests/test_slave_shutdown.py diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 3883d3d..4b4e1f7 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -5,8 +5,9 @@ lib_spi change log ----- * CHANGED: SPI master async reduced clock blocks from two to one - * CHANGED: SPI master sync increased max speed to 25+ Mbps + * CHANGED: SPI master sync increased max speed to 50+ Mbps * ADDED: Shutdown method for SPI sync + * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index dceb3b1..122f76d 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -158,7 +158,7 @@ typedef interface spi_master_if { */ void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); - /** Shut down the interface server. See known issues in README.rst. + /** Shut down the SPI master interface server. */ void shutdown(void); @@ -357,7 +357,7 @@ typedef interface spi_master_async_if { */ void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); - /** Shut down the interface server. + /** Shut down the SPI master interface server. */ void shutdown(void); @@ -435,6 +435,18 @@ typedef interface spi_slave_callback_if { * \param valid_bits the number of valid bits of data received from the master. */ void master_supplied_data(uint32_t datum, uint32_t valid_bits); + + /** Request shut down the SPI slave interface client. + */ + [[notification]] + slave void request_shutdown(void); + + /** Acknowledgment that the SPI slave task has been shutdown. + */ + [[clears_notification]] + [[guarded]] + void shutdown_complete(void); + #ifndef __DOXYGEN__ } spi_slave_callback_if; #endif diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 4c74339..03d6865 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -282,52 +282,3 @@ void spi_master_end_transaction( void spi_master_deinit( spi_master_t *spi); -#ifndef __XC__ -/** - * Master has started a transaction - * - * This callback function will be called when the SPI master has asserted - * this slave's chip select. - * - * The input and output buffer may be the same; however, partial byte/incomplete - * reads will result in out_buf bits being masked off due to a partial bit output. - * - * \param app_data A pointer to application specific data provided - * by the application. Used to share data between - * \param out_buf The buffer to send to the master - * \param outbuf_len The length in bytes of out_buf - * \param in_buf The buffer to receive into from the master - * \param inbuf_len The length in bytes of in_buf - */ -typedef void (*slave_transaction_started_t)(void *app_data, uint8_t **out_buf, size_t *outbuf_len, uint8_t **in_buf, size_t *inbuf_len); - -/** - * Master has ended a transaction - * - * This callback function will be called when the SPI master has de-asserted - * this slave's chip select. - * - * The value of bytes_read contains the number of full bytes that are in - * in_buf. When read_bits is greater than 0, the byte after the last full byte - * contains the partial bits read. - * - * \param app_data A pointer to application specific data provided - * by the application. Used to share data between - * \param out_buf The buffer that had been provided to be sent to the master - * \param bytes_written The length in bytes of out_buf that had been written - * \param in_buf The buffer that had been provided to be received into from the master - * \param bytes_read The length in bytes of in_buf that has been read in to - * \param read_bits The length in bits of in_buf - */ -typedef void (*slave_transaction_ended_t)(void *app_data, uint8_t **out_buf, size_t bytes_written, uint8_t **in_buf, size_t bytes_read, size_t read_bits); - -/** - * This attribute must be specified on all SPI callback functions - * provided by the application. - */ -#define SPI_CALLBACK_ATTR __attribute__((fptrgroup("spi_callback"))) - -/**@}*/ // END: addtogroup hil_spi_master - - -#endif \ No newline at end of file diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 235453e..30e0cea 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -19,124 +19,135 @@ void spi_slave(client spi_slave_callback_if spi_i, static const spi_mode_t mode, static const spi_transfer_type_t transfer_type){ - //first setup the ports - - set_port_inv(ss); - - stop_clock(clk); - set_clock_src(clk, sclk); - - if(!isnull(miso)) - configure_out_port_strobed_slave(miso, ss, clk, 0); - configure_in_port_strobed_slave(mosi, ss, clk); - - start_clock(clk); - - switch(mode){ - case SPI_MODE_0: - case SPI_MODE_2: - set_port_inv(sclk); - break; - case SPI_MODE_1: - case SPI_MODE_3: - set_port_no_inv(sclk); - break; - } - sync(sclk); - - int ss_val; - - //set the transfer width - if(transfer_type == SPI_TRANSFER_SIZE_8){ - if(!isnull(miso)) - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - } - - uint32_t buffer; - - ss when pinseq(!ASSERTED) :> ss_val; - while(1){ - select { - case ss when pinsneq(ss_val) :> ss_val:{ - - if(!isnull(miso)) - clearbuf(miso); - - if(ss_val != ASSERTED){ - unsigned remaining_bits = endin(mosi); - uint32_t data; - mosi :> data; - if(remaining_bits){ //FIXME can this be more then tw? - data = bitrev(data); - if(transfer_type == SPI_TRANSFER_SIZE_8) - data >>= (32-8); - spi_i.master_supplied_data(data, remaining_bits); - } - clearbuf(mosi); - spi_i.master_ends_transaction(); - break; - } - if(!isnull(miso)){ - uint32_t data = spi_i.master_requires_data(); - - if(transfer_type == SPI_TRANSFER_SIZE_8){ - data = (bitrev(data)>>24); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); - partout(miso, 1, data); - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); - data = data>>1; - partout(miso, 7, data); - } else { - partout(miso, 8, data); - } + //first setup the ports + + set_port_inv(ss); + + stop_clock(clk); + set_clock_src(clk, sclk); + + if(!isnull(miso)) + configure_out_port_strobed_slave(miso, ss, clk, 0); + configure_in_port_strobed_slave(mosi, ss, clk); + + start_clock(clk); + + switch(mode){ + case SPI_MODE_0: + case SPI_MODE_2: + set_port_inv(sclk); + break; + case SPI_MODE_1: + case SPI_MODE_3: + set_port_no_inv(sclk); + break; + } + sync(sclk); + + int ss_val; + + //set the transfer width + if(transfer_type == SPI_TRANSFER_SIZE_8){ + if(!isnull(miso)) + asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); + asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); + } + + uint32_t buffer; + + ss when pinseq(!ASSERTED) :> ss_val; + while(1){ + select { + case ss when pinsneq(ss_val) :> ss_val:{ + if(!isnull(miso)) + clearbuf(miso); + + if(ss_val != ASSERTED){ + unsigned remaining_bits = endin(mosi); + uint32_t data; + mosi :> data; + if(remaining_bits){ //FIXME can this be more then tw? + data = bitrev(data); + if(transfer_type == SPI_TRANSFER_SIZE_8) + data >>= (32-8); + spi_i.master_supplied_data(data, remaining_bits); + } + clearbuf(mosi); + spi_i.master_ends_transaction(); + break; + } + + if(!isnull(miso)){ + uint32_t data = spi_i.master_requires_data(); + + if(transfer_type == SPI_TRANSFER_SIZE_8){ + data = (bitrev(data)>>24); + if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); + partout(miso, 1, data); + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); + data = data>>1; + partout(miso, 7, data); + } else { + partout(miso, 8, data); + } } else { - data = bitrev(data); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); - partout(miso, 1, data); - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); - data = data>>1; - partout(miso, 31, data); - } else { - miso <: data; - } - } - buffer = spi_i.master_requires_data(); - - if(transfer_type == SPI_TRANSFER_SIZE_8){ - buffer = (bitrev(buffer)>>24); - } else { - buffer = bitrev(buffer); - } - } - clearbuf(mosi); - break; - } - - case mosi :> int i:{ - if(transfer_type == SPI_TRANSFER_SIZE_8){ - if(!isnull(miso)){ - //clearbuf(miso);//FIXME this is not correct - do something better - partout(miso, 8, buffer); - buffer = spi_i.master_requires_data(); - buffer = (bitrev(buffer)>>24); - } - spi_i.master_supplied_data(bitrev(i)>>24, 8); - - } else { - if(!isnull(miso)){ - //clearbuf(miso);//FIXME this is not correct - do something better - miso <: buffer; - buffer = spi_i.master_requires_data(); - buffer = bitrev(buffer); - } - spi_i.master_supplied_data(bitrev(i), 32); - } - break; - } - - } - } - } + data = bitrev(data); + if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); + partout(miso, 1, data); + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); + data = data>>1; + partout(miso, 31, data); + } else { + miso <: data; + } + } + buffer = spi_i.master_requires_data(); + + if(transfer_type == SPI_TRANSFER_SIZE_8){ + buffer = (bitrev(buffer)>>24); + } else { + buffer = bitrev(buffer); + } + } + clearbuf(mosi); + break; + } // case ss + + case mosi :> int i:{ + if(transfer_type == SPI_TRANSFER_SIZE_8){ + if(!isnull(miso)){ + //clearbuf(miso);//FIXME this is not correct - do something better + partout(miso, 8, buffer); + buffer = spi_i.master_requires_data(); + buffer = (bitrev(buffer)>>24); + } + spi_i.master_supplied_data(bitrev(i)>>24, 8); + } else { + if(!isnull(miso)){ + //clearbuf(miso);//FIXME this is not correct - do something better + miso <: buffer; + buffer = spi_i.master_requires_data(); + buffer = bitrev(buffer); + } + spi_i.master_supplied_data(bitrev(i), 32); + } + break; + } // case mosi + + case spi_i.request_shutdown():{ + set_port_use_on(mosi); + if (!isnull(miso)) { + set_port_use_on(miso); + } + set_port_use_on(sclk); + set_port_use_on(ss); + set_clock_on(clk); + spi_i.shutdown_complete(); + return; + break; + } + } // select + } // while(1) +} diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index ea8e29e..b663fe6 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -10,6 +10,7 @@ add_subdirectory(spi_master_sync_clock_port_sharing) add_subdirectory(spi_master_sync_shutdown) add_subdirectory(spi_slave_benchmark) add_subdirectory(spi_slave_rx_tx) +add_subdirectory(spi_slave_shutdown) add_subdirectory(spi_master_async_rx_tx) add_subdirectory(spi_master_async_multi_client) add_subdirectory(spi_master_async_multi_device) diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py index 2f6c230..49ac04d 100644 --- a/tests/spi_slave_checker.py +++ b/tests/spi_slave_checker.py @@ -141,4 +141,5 @@ def run(self): xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 1) xsi.drive_port_pins(self._setup_resp_port, error) + self.wait_for_port_pins_change([self._setup_strobe_port]) diff --git a/tests/spi_slave_shutdown/CMakeLists.txt b/tests/spi_slave_shutdown/CMakeLists.txt new file mode 100644 index 0000000..4a850d0 --- /dev/null +++ b/tests/spi_slave_shutdown/CMakeLists.txt @@ -0,0 +1,52 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON combined_list GET ${params_json} COMBINED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON combined_list_len LENGTH ${combined_list}) + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR combined_list_len "${combined_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${combined_list_len}) + string(JSON combined GET ${combined_list} ${j}) + + set(config ${combined}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_shutdown) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${combined} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() +endforeach() diff --git a/tests/spi_slave_shutdown/config.xscope b/tests/spi_slave_shutdown/config.xscope new file mode 100644 index 0000000..1ba0f11 --- /dev/null +++ b/tests/spi_slave_shutdown/config.xscope @@ -0,0 +1,3 @@ + + + diff --git a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc new file mode 100644 index 0000000..c3adaca --- /dev/null +++ b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc @@ -0,0 +1,273 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" + +out buffered port:32 p_miso = XS1_PORT_1A; +in port p_ss = XS1_PORT_1B; +in port p_sclk = XS1_PORT_1C; +in buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; +in port setup_resp_port = XS1_PORT_1F; + +#define NUMBER_OF_TEST_BYTES 16 +#define KBPS 1000 +#define SPI_MODE SPI_MODE_0 +#define BURNT_THREADS 0 +#define TRANSFER_SIZE SPI_TRANSFER_SIZE_8 + +static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, + 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f +}; + +static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, + 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, +}; + + +#if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) +#define BITS_PER_TRANSFER 8 +#elif (TRANSFER_SIZE == SPI_TRANSFER_SIZE_32) +#define BITS_PER_TRANSFER 32 +#else +#error Invalid transfer size given +#endif + +void flush_print(void){ + delay_microseconds(10); +} + +static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ + switch(mode){ + case SPI_MODE_0:cpol = 0; cpha= 1; break; + case SPI_MODE_1:cpol = 0; cpha= 0; break; + case SPI_MODE_2:cpol = 1; cpha= 0; break; + case SPI_MODE_3:cpol = 1; cpha= 1; break; + } +} + +static void send_data_to_tester( + out port setup_strobe_port, + out port setup_data_port, + unsigned data){ + setup_data_port <: data; + sync(setup_data_port); + setup_strobe_port <: 1; + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; +} + +static void broadcast_settings( + out port setup_strobe_port, + out port setup_data_port, + spi_mode_t mode, + int mosi_enabled, + int miso_enabled, + unsigned num_bits, + unsigned kbps, + unsigned initial_clock_delay // in ns +){ + unsigned cpha, cpol; + + set_mode_bits(mode, cpol, cpha); + + setup_strobe_port <: 0; + + send_data_to_tester(setup_strobe_port, setup_data_port, cpol); + send_data_to_tester(setup_strobe_port, setup_data_port, cpha); + send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); + send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); + send_data_to_tester(setup_strobe_port, setup_data_port, kbps); + send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); +} + +static int request_response( + out port setup_strobe_port, + in port setup_resp_port +){ + int r; + setup_strobe_port <: 1; // Twice to make sure we are not too fast + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; + setup_resp_port :> r; + return r; + +} + +// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits + +[[combinable]] +void app(server interface spi_slave_callback_if spi_i, + int mosi_enabled, int miso_enabled){ + + unsigned bpt = 0; + spi_transfer_type_t tt = TRANSFER_SIZE; + switch(tt){ + case SPI_TRANSFER_SIZE_8:bpt = 8;break; + case SPI_TRANSFER_SIZE_32:bpt = 32;break; + } + + + unsigned num_bits = NUMBER_OF_TEST_BYTES*8; + + //First check a multi byte transfer + printf("Send initial settings\n"); + // printf("%u\n", num_bits); + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + + unsigned rx_byte_no = 0; + unsigned tx_byte_no = 0; + while(1){ + select { + case spi_i.master_requires_data() -> uint32_t r:{ + // printf("master_requires_data\n"); + if(tx_byte_no < NUMBER_OF_TEST_BYTES){ + switch(tt){ + case SPI_TRANSFER_SIZE_8: + r = tx_data[tx_byte_no]; + tx_byte_no++; + break; + case SPI_TRANSFER_SIZE_32: + r = (tx_data[tx_byte_no+3]<<0) + | (tx_data[tx_byte_no+2]<<8) + | (tx_data[tx_byte_no+1]<<16) + | (tx_data[tx_byte_no+0]<<24); + tx_byte_no+=4; + break; + } + } + if(!miso_enabled){ + printf("Error: master cannot require data when miso is not enabled\n"); + flush_print(); + _Exit(1); + } + break; + } + case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ + // printf("master_supplied_data\n"); + for(unsigned i=0; i> (valid_bits - 8))&0xff; + if(rx_data[rx_byte_no] != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + rx_data[rx_byte_no], d, num_bits); + flush_print(); + _Exit(1); + } + rx_byte_no++; + datum <<= 8; + } + + if(valid_bits < 8){ + datum <<= (8-valid_bits); + } else + datum >>= (valid_bits-8); + datum &= 0xff; + + if(valid_bits&0x7){ + uint32_t d =(rx_data[rx_byte_no]>>(8-(valid_bits&0x7)))<<(8-(valid_bits&0x7)); + if(datum != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + d, datum, num_bits); + flush_print(); + _Exit(1); + } + } + break; + } + + case spi_i.master_ends_transaction():{ + // printf("master_ends_transaction\n"); + //Then check all sub word transfers + if(num_bits == NUMBER_OF_TEST_BYTES*8){ + num_bits = 0; + } + if(num_bits == bpt){ + int r = request_response(setup_strobe_port, setup_resp_port); + if(r){ + printf("Error: Master Rx error\n"); + flush_print(); + _Exit(1); + } + spi_i.request_shutdown(); + break; + } + num_bits++; + + int r = request_response(setup_strobe_port, setup_resp_port); + + if(r){ + printf("Error: Master Rx error\n"); + flush_print(); + _Exit(1); + } + if(num_bits > bpt){ + printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); + flush_print(); + _Exit(1); + } + + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + rx_byte_no = 0; + tx_byte_no = 0; + break; + } + + case spi_i.shutdown_complete(): + printf("Test completed\n"); + flush_print(); + return; + break; + } + } +} + +static void load(static const unsigned num_threads){ + switch(num_threads){ + case 0: return; + case 3: par {par(int i=0;i<3;i++) while(1);}break; + case 6: par {par(int i=0;i<6;i++) while(1);}break; + case 7: par {par(int i=0;i<7;i++) while(1);}break; + } +} + +#define MISO p_miso +#define MOSI_ENABLED 1 +#define MISO_ENABLED 1 +#define NUM_LOOPS 3 + +int main(){ + interface spi_slave_callback_if i; + par { +#if COMBINED == 1 + for(int n = 0; n < NUM_LOOPS; n++){ + [[combine]] + par { + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + app(i, MOSI_ENABLED, MISO_ENABLED); + } + } +#else + // This will NOT combine + for(int n = 0; n < NUM_LOOPS; n++) + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + for(int n = 0; n < NUM_LOOPS; n++) + app(i, MOSI_ENABLED, MISO_ENABLED); +#endif + load(BURNT_THREADS); + } + return 0; +} diff --git a/tests/spi_slave_shutdown/test_params.json b/tests/spi_slave_shutdown/test_params.json new file mode 100644 index 0000000..909d30f --- /dev/null +++ b/tests/spi_slave_shutdown/test_params.json @@ -0,0 +1,4 @@ +{ + "COMBINED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/test_slave_shutdown.py b/tests/test_slave_shutdown.py new file mode 100644 index 0000000..1eecb44 --- /dev/null +++ b/tests/test_slave_shutdown.py @@ -0,0 +1,51 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_slave_shutdown" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(combined, arch, capfd): + filepath = Path(__file__).resolve().parent + id_string = f"{combined}_{arch}" + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + with open(filepath/f"expected/slave.expect") as exp: + expected = exp.read().splitlines() + transfer_size = 8 + NUM_LOOPS = 3 # See spi_slave_shutdown.xc for equivalent define. Must match + expected = expected[:3 + transfer_size] + expected[-1:] + expected = expected + expected[1:] * (NUM_LOOPS - 1) # We don't want SPI Slave checker started after the first time + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = True, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd, + timeout=60) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_shutdown(capfd, params, request): + do_test(*params, capfd) \ No newline at end of file From b816669097294ace3f11238c6f2d4dd439da3c80 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 4 Aug 2025 14:26:06 +0100 Subject: [PATCH 37/57] Add array transfer method for spi SYNC --- lib_spi/api/spi.h | 22 ++++++++++-- lib_spi/src/spi_master_sync.xc | 35 ++++++++++++++++-- .../src/spi_master_sync_rx_tx.xc | 6 ++++ .../spi_sync_tester.h | 36 +++++++++++++++++++ 4 files changed, 93 insertions(+), 6 deletions(-) diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 122f76d..732cb2e 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -80,7 +80,8 @@ typedef interface spi_master_if { * * \param device_index the index of the slave device to interact with. * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ). + * the transaction (in kHZ). When using the version + * with clockblock, the minimum speed is 100 kHz. * \param mode The mode of spi transfers during this transaction. */ [[guarded]] @@ -113,7 +114,8 @@ typedef interface spi_master_if { /** Transfer a 32-bit word over the spi bus. * * This function will transmit and receive 32 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first. + * bus. The data will be transmitted least-significant bit first and + * most significant byte first (big endian) * * \param data the data to transmit the MOSI port. * @@ -121,6 +123,20 @@ typedef interface spi_master_if { */ uint32_t transfer32(uint32_t data); + /** Transfer an array of byes over the spi bus. + * + * This function will transmit and receive 32 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first in byte + * order in memory. Note that XMOS uses little endian and so 32b data etc. + * may need byteswap() first. + * + * \param data_out Reference to data to transmit the MOSI port. + * \param data_in Reference to data to receive from the MISO port. + * \param num_bytes Constant value to size the array to be transferred. + * + */ + void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static const size_t num_bytes); + /** Sets the bit of port which is used for slave select (> 1b port type only) * and only for spi_master. spi_master sets all bits in each port high/low * @@ -228,7 +244,7 @@ typedef interface spi_master_async_if { * * \param device_index the index of the slave device to interact with. * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ) + * the transaction (in kHZ). The minimum speed is 100 kHz. * \param mode The mode of spi transfers during this transaction */ void begin_transaction(unsigned device_index, diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index ce841a4..c70b92a 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -3,11 +3,9 @@ #include #include #include - -//TODO DEL these -#include #include #include +#include #include "spi.h" #include "spi_master_shared.h" @@ -155,6 +153,37 @@ void spi_master(server interface spi_master_if i[num_clients], break; } + case i[int x].transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static const size_t num_bytes):{ + if(isnull(cb)){ + for(int n = 0; n < num_bytes; n++){ + uint8_t send; + if(!isnull(mosi)){ + send = data_out[n]; + } + uint8_t recv = transfer8_sync_zero_clkblk(sclk, mosi, miso, send, clkblkless_period_ticks, cpol, cpha); + if(!isnull(miso)){ + data_in[n] = recv; + } + } + } else { + // Remote references not allowed in XC so need to memcpy + uint8_t data[num_bytes]; + if(!isnull(data_out)){ + memcpy(data, data_out, num_bytes); + } + unsafe{ + // Do in-place transfer + uint8_t * unsafe data_alias = data; + spi_master_transfer(&spi_dev[current_device], data, data_alias, num_bytes); + } + if(!isnull(data_in)){ + memcpy(data_in, data, num_bytes); + } + } + + break; + } + case i[int x].set_ss_port_bit(unsigned device_index, unsigned port_bit):{ if(device_index > num_slaves){ printstrln("Invalid port bit - must be less than num_slaves"); diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 7cc80b2..b7d98e0 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -36,6 +36,12 @@ void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, i test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } + // printf("Device array SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); + } + printf("Transfers complete\n"); _Exit(0); } diff --git a/tests/spi_master_tester_common/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h index efbca24..d35b50c 100644 --- a/tests/spi_master_tester_common/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -74,6 +74,42 @@ int test_transfer32(client interface spi_master_if i, return error; } +int test_transfer_array(client interface spi_master_if i, + out port setup_strobe_port, + out port setup_data_port, + unsigned device_id, + unsigned inter_frame_gap, + spi_mode_t mode, + unsigned speed_in_kbps, + int mosi_enabled, + int miso_enabled){ + + int error = 0; + broadcast_settings(setup_strobe_port, setup_data_port, mode, speed_in_kbps, + mosi_enabled, miso_enabled, device_id, inter_frame_gap, NUMBER_OF_TEST_BYTES); + + i.begin_transaction(device_id, speed_in_kbps, mode); + + uint8_t rx_array[NUMBER_OF_TEST_BYTES]; + i.transfer_array(tx_data, rx_array, NUMBER_OF_TEST_BYTES); + + // Now check + for(unsigned j=0;j Date: Mon, 4 Aug 2025 17:31:00 +0100 Subject: [PATCH 38/57] Review feedback Remove old requirements and python folder Readme updated to 75 MHz speed --- CHANGELOG.rst | 1 + Jenkinsfile | 4 +-- README.rst | 2 +- doc/rst/lib_spi.rst | 4 ++- examples/deps.cmake | 3 +- lib_spi/api/spi.h | 15 ++++---- lib_spi/src/spi_master_sync.xc | 1 + python/setup.py | 20 ----------- requirements.txt | 34 ------------------- .../src/spi_master_async_rx_tx.xc | 2 +- .../src/spi_master_sync_clock_port_sharing.xc | 6 ++-- .../src/spi_master_sync_rx_tx.xc | 3 +- tests/test_master_sync_clock_port_sharing.py | 2 ++ 13 files changed, 26 insertions(+), 71 deletions(-) delete mode 100644 python/setup.py delete mode 100644 requirements.txt diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 4b4e1f7..2f20a61 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -9,6 +9,7 @@ lib_spi change log * ADDED: Shutdown method for SPI sync * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments + * ADDED: Array transfer method for SPI sync * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests * REMOVED: Support for XS1 devices diff --git a/Jenkinsfile b/Jenkinsfile index 7bb8fd5..d73361b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,6 +1,6 @@ // This file relates to internal XMOS infrastructure and should be ignored by external users -@Library('xmos_jenkins_shared_library@v0.39.0') _ +@Library('xmos_jenkins_shared_library@v0.42.0') _ def clone_test_deps() { dir("${WORKSPACE}") { @@ -36,7 +36,7 @@ pipeline { ) string( name: 'INFR_APPS_VERSION', - defaultValue: 'v2.1.0', + defaultValue: 'v3.1.1', description: 'The infr_apps version' ) } diff --git a/README.rst b/README.rst index 8c35180..393b24a 100644 --- a/README.rst +++ b/README.rst @@ -25,7 +25,7 @@ Features ******** * SPI master and SPI slave modes. -* Supports speed of up to 100 Mbit. +* Supports speed of up to 75 Mbit. * Multiple slave device support * All clock polarity and phase configurations supported. diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 6f9f3bc..55e8665 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -68,6 +68,8 @@ relative to the clock. The timings are given by: The setup and hold timings are inherited from the underlying xCORE device. For details on these timing please refer to the device datasheet. +When operating above 20 Mbps please also see :ref:`MISO port timing` + Mode 0 - CPOL: 0 CPHA 0 ======================= @@ -186,7 +188,7 @@ pin to capture within the required window, particularly if the SPI clock is abov Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the API section which exposes the controls available for optimising setup and hold capture. -For details on how to calculate and adjust round-trip port timing, please consult the `IO timings for xcore.ai `_ document. +For details on how to calculate and adjust round-trip port timing, please consult the `IO timings for xcore.ai `_ or `IO timings for xCORE200 `_ document. |newpage| diff --git a/examples/deps.cmake b/examples/deps.cmake index 38647e5..e0f172e 100644 --- a/examples/deps.cmake +++ b/examples/deps.cmake @@ -1,3 +1,2 @@ # Common dependencies for examples -set(APP_DEPENDENT_MODULES "lib_spi" -) \ No newline at end of file +set(APP_DEPENDENT_MODULES "lib_spi") diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index 732cb2e..bee624e 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -20,6 +20,7 @@ extern "C" { #define async_master_read read #define async_master_write write #define slave_void slave void +#define static_const_size_t static const size_t #define static_const_spi_mode_t static const spi_mode_t #define static_const_spi_transfer_type_t static const spi_transfer_type_t #define static_const_spi_transfer_type_t static const spi_transfer_type_t @@ -105,7 +106,7 @@ typedef interface spi_master_if { * This function will transmit and receive 8 bits of data over the SPI * bus. The data will be transmitted least-significant bit first. * - * \param data the data to transmit the MOSI port. + * \param data the data to transmit the MOSI port. * * \returns the data read in from the MISO port. */ @@ -123,19 +124,21 @@ typedef interface spi_master_if { */ uint32_t transfer32(uint32_t data); - /** Transfer an array of byes over the spi bus. + /** Transfer an array of bytes over the SPI interface. * * This function will transmit and receive 32 bits of data over the SPI * bus. The data will be transmitted least-significant bit first in byte * order in memory. Note that XMOS uses little endian and so 32b data etc. * may need byteswap() first. * - * \param data_out Reference to data to transmit the MOSI port. - * \param data_in Reference to data to receive from the MISO port. - * \param num_bytes Constant value to size the array to be transferred. + * \param data_out Reference to data to transmit the MOSI port. May be null + * if only a read is needed. + * \param data_in Reference to data to receive from the MISO port. May be + * null if only a write is needed. + * \param num_bytes Constant value of the size of the array to be transferred. * */ - void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static const size_t num_bytes); + void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static_const_size_t num_bytes); /** Sets the bit of port which is used for slave select (> 1b port type only) * and only for spi_master. spi_master sets all bits in each port high/low diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index c70b92a..076afa6 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include diff --git a/python/setup.py b/python/setup.py deleted file mode 100644 index 8c6864f..0000000 --- a/python/setup.py +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright 2020-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import setuptools - -# Another repository might depend on python code defined in this one. The -# procedure to set up a suitable python environment for that repository may -# pip-install this one as editable using this setup.py file. To minimise the -# chance of version conflicts while ensuring a minimal degree of conformity, -# the 3rd-party modules listed here require the same major version and at -# least the same minor version as specified in the requirements.txt file. -# The same modules should appear in the requirements.txt file as given below. -setuptools.setup( - name='lib_spi', - packages=setuptools.find_packages(), - install_requires=[ - 'flake8~=5.0', - ], - dependency_links=[ - ], -) diff --git a/requirements.txt b/requirements.txt deleted file mode 100644 index 5b960fd..0000000 --- a/requirements.txt +++ /dev/null @@ -1,34 +0,0 @@ -# python_version 3.10.5 -# -# The parse_version_from_requirements() function in the installPipfile.groovy -# file of the Jenkins Shared Library uses the python_version comment to set -# the version of python used. - -# Distributed (released) dependencies -# -# The python modules listed below specify a known working combination required -# by the python code in this repository. The procedure used to set up a -# suitable python environment for it installs the version of each module in -# the list. Using a specific version ensures a controlled infrastructure for -# development, testing and release of this repository. -# -# Another repository might depend on python code defined in this one. The -# procedure to set up a suitable python environment for that repository may -# pip-install this one as editable using this repository's setup.py file. The -# same modules should appear in the setup.py list as given below. - -flake8==5.0.4 - -# Development dependencies -# -# Each link listed below specifies the path to a setup.py file which are -# installed in editable mode with '-e $PATH' (without the quotes). -# -# If python code in this repository depends on python code under development -# in another repository, then an entry for that other respository should -# appear in this list instead of the released dependencies list. -# -# If this repository uses the setup functionality (e.g., script entry points) -# of its own setup.py file, then this list must include an entry for that -# setup.py file, e.g., '-e .' or '-e ./python' (without the quotes). --e ./python diff --git a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index a790b15..c245d8b 100644 --- a/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -115,7 +115,7 @@ void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_ uint8_t rx = rx_ptr8[j]; if(rx != rx_data[j]) { printf("Error, incorrect 8b data at idx %u received: 0x%x expecting(0x%x)\n", j, rx, rx_data[j]); - printf("Speed: %, mode: %u, count: %u\n", speed_in_kbps, mode, count); + printf("Speed: %u, mode: %u, count: %u\n", speed_in_kbps, mode, count); flush_print(); _Exit(1); } diff --git a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc index 5dee37a..e541e52 100644 --- a/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc +++ b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc @@ -48,11 +48,11 @@ void app(client interface spi_master_if spi_i, int mosi_enabled, int miso_enable } count++; - if (count == 8) - printf("Transfers complete\n"); // This first one is missed. Can't work out why! - printf("Transfers complete\n"); + if (count == 8){ + printf("Transfers complete\n"); delay_microseconds(100); // Flush _Exit(0); + } break; } diff --git a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index b7d98e0..710df2a 100644 --- a/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -18,13 +18,14 @@ out port setup_data_port = XS1_PORT_16B; #if CB_ENABLED #define SPEED_TESTS 3 +unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 33000}; // Speed in kHz #else #define SPEED_TESTS 1 +unsigned speed_lut[SPEED_TESTS] = {1000}; // Speed in kHz #endif void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ - unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 33000}; // Speed in kHz // printf("Device 8 SPI_MODE: %d\n", spi_mode); for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ diff --git a/tests/test_master_sync_clock_port_sharing.py b/tests/test_master_sync_clock_port_sharing.py index b508c51..c965c85 100644 --- a/tests/test_master_sync_clock_port_sharing.py +++ b/tests/test_master_sync_clock_port_sharing.py @@ -15,6 +15,8 @@ def do_test(capfd, combined, id): binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" assert binary.exists() + pytest.xfail("Changing clock port clockblock is expected to affect the next transfer") + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1A", From 55ed18d672372718c03995cbea9a50f18e2b0c9c Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 5 Aug 2025 10:04:48 +0100 Subject: [PATCH 39/57] WIP slave test common + ss deassert JSL @ 0.41 --- Jenkinsfile | 2 +- doc/exclude_patterns.inc | 3 +- doc/rst/lib_spi.rst | 10 +- tests/CMakeLists.txt | 1 + tests/spi_master_sync_shutdown/CMakeLists.txt | 1 + tests/spi_slave_checker.py | 2 +- tests/spi_slave_rx_tx/CMakeLists.txt | 1 + tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc | 74 +------- tests/spi_slave_shutdown/CMakeLists.txt | 2 +- .../src/spi_slave_shutdown.xc | 81 +------- tests/spi_slave_ss_deassert/CMakeLists.txt | 61 ++++++ tests/spi_slave_ss_deassert/config.xscope | 3 + .../src/spi_slave_ss_deassert.xc | 173 ++++++++++++++++++ tests/spi_slave_ss_deassert/test_params.json | 5 + tests/spi_slave_tester_common/common.h | 86 +++++++++ tests/test_master_async_rx_tx.py | 2 +- tests/test_slave_ss_deassert.py | 49 +++++ 17 files changed, 397 insertions(+), 159 deletions(-) create mode 100644 tests/spi_slave_ss_deassert/CMakeLists.txt create mode 100644 tests/spi_slave_ss_deassert/config.xscope create mode 100644 tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc create mode 100644 tests/spi_slave_ss_deassert/test_params.json create mode 100644 tests/spi_slave_tester_common/common.h create mode 100644 tests/test_slave_ss_deassert.py diff --git a/Jenkinsfile b/Jenkinsfile index d73361b..11dbdb2 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,6 +1,6 @@ // This file relates to internal XMOS infrastructure and should be ignored by external users -@Library('xmos_jenkins_shared_library@v0.42.0') _ +@Library('xmos_jenkins_shared_library@v0.41.0') _ def clone_test_deps() { dir("${WORKSPACE}") { diff --git a/doc/exclude_patterns.inc b/doc/exclude_patterns.inc index 0636e6c..d4616be 100644 --- a/doc/exclude_patterns.inc +++ b/doc/exclude_patterns.inc @@ -2,8 +2,9 @@ **CHANGELOG* **LICENSE* +**.pytest_cache/* #TODO remove these **index* **resource_usage_summary* **AN00160* -**AN00161* \ No newline at end of file +**AN00161* diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 55e8665..97f70c7 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -26,8 +26,11 @@ and either one or two data wires. .. _spi_wire_table: .. list-table:: SPI data wires + :header-rows: 1 :class: vertical-borders horizontal-borders + * - Signal + - Description * - *SCLK* - Clock line, driven by the master * - *MOSI* @@ -56,8 +59,11 @@ is used to shift the sampling phase. The following for sections illustrate the M relative to the clock. The timings are given by: .. list-table:: SPI timings + :header-rows: 1 :class: vertical-borders horizontal-borders + * - Parameter + - Description * - *t1* - The minimum time from the start of the transaction to data being valid on the data pins. * - *t2* @@ -68,7 +74,7 @@ relative to the clock. The timings are given by: The setup and hold timings are inherited from the underlying xCORE device. For details on these timing please refer to the device datasheet. -When operating above 20 Mbps please also see :ref:`MISO port timing` +When operating above 20 Mbps please also see the :ref:`MISO port timing` section. Mode 0 - CPOL: 0 CPHA 0 ======================= @@ -175,6 +181,8 @@ the asynchronous master can output a clock at up to 100MHz, port timing and hard - 62500 - 75000 +.. _miso_port_timing: + MISO port timing ================ diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index b663fe6..59314ac 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -11,6 +11,7 @@ add_subdirectory(spi_master_sync_shutdown) add_subdirectory(spi_slave_benchmark) add_subdirectory(spi_slave_rx_tx) add_subdirectory(spi_slave_shutdown) +add_subdirectory(spi_slave_ss_deassert) add_subdirectory(spi_master_async_rx_tx) add_subdirectory(spi_master_async_multi_client) add_subdirectory(spi_master_async_multi_device) diff --git a/tests/spi_master_sync_shutdown/CMakeLists.txt b/tests/spi_master_sync_shutdown/CMakeLists.txt index 7100164..b467726 100644 --- a/tests/spi_master_sync_shutdown/CMakeLists.txt +++ b/tests/spi_master_sync_shutdown/CMakeLists.txt @@ -49,6 +49,7 @@ foreach(i RANGE 0 ${arch_list_len}) -O2 -g -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) XMOS_REGISTER_APP() diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py index 49ac04d..c67156e 100644 --- a/tests/spi_slave_checker.py +++ b/tests/spi_slave_checker.py @@ -119,7 +119,7 @@ def run(self): if expected_miso_enabled: if rx_byte != rx_data[byte_count]: error = 1 - print(f"frx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") + print(f"tester rx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") rx_byte = 0 byte_count = byte_count + 1 if byte_count*8 < expected_num_bits: diff --git a/tests/spi_slave_rx_tx/CMakeLists.txt b/tests/spi_slave_rx_tx/CMakeLists.txt index 41251b7..b719463 100644 --- a/tests/spi_slave_rx_tx/CMakeLists.txt +++ b/tests/spi_slave_rx_tx/CMakeLists.txt @@ -68,6 +68,7 @@ foreach(i RANGE 0 ${arch_list_len}) -g -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_slave_tester_common) XMOS_REGISTER_APP() message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") diff --git a/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc index 99ae2b3..c8dbe8c 100644 --- a/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc +++ b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc @@ -5,6 +5,7 @@ #include #include #include "spi.h" +#include "common.h" out buffered port:32 p_miso = XS1_PORT_1A; in port p_ss = XS1_PORT_1B; @@ -16,19 +17,8 @@ out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; in port setup_resp_port = XS1_PORT_1F; -#define NUMBER_OF_TEST_BYTES 16 #define KBPS 1000 -static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, - 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f -}; - -static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, - 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, -}; - #if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) #define BITS_PER_TRANSFER 8 @@ -38,68 +28,6 @@ static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { #error Invalid transfer size given #endif -void flush_print(void){ - delay_microseconds(1000); -} - -static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -static void send_data_to_tester( - out port setup_strobe_port, - out port setup_data_port, - unsigned data){ - setup_data_port <: data; - sync(setup_data_port); - setup_strobe_port <: 1; - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_strobe_port <: 0; -} - -static void broadcast_settings( - out port setup_strobe_port, - out port setup_data_port, - spi_mode_t mode, - int mosi_enabled, - int miso_enabled, - unsigned num_bits, - unsigned kbps, - unsigned initial_clock_delay // in ns -){ - unsigned cpha, cpol; - - set_mode_bits(mode, cpol, cpha); - - setup_strobe_port <: 0; - - send_data_to_tester(setup_strobe_port, setup_data_port, cpol); - send_data_to_tester(setup_strobe_port, setup_data_port, cpha); - send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); - send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); - send_data_to_tester(setup_strobe_port, setup_data_port, kbps); - send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); -} - -static int request_response( - out port setup_strobe_port, - in port setup_resp_port -){ - int r; - setup_strobe_port <: 1; // Twice to make sure we are not too fast - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_strobe_port <: 0; - setup_resp_port :> r; - return r; - -} // This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits diff --git a/tests/spi_slave_shutdown/CMakeLists.txt b/tests/spi_slave_shutdown/CMakeLists.txt index 4a850d0..1eb36ad 100644 --- a/tests/spi_slave_shutdown/CMakeLists.txt +++ b/tests/spi_slave_shutdown/CMakeLists.txt @@ -42,7 +42,7 @@ foreach(i RANGE 0 ${arch_list_len}) -O2 -g -Wno-reinterpret-alignment) - set(APP_INCLUDES src ../spi_master_tester_common) + set(APP_INCLUDES src ../spi_slave_tester_common) XMOS_REGISTER_APP() diff --git a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc index c3adaca..b4cba01 100644 --- a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc +++ b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc @@ -5,6 +5,7 @@ #include #include #include "spi.h" +#include "common.h" out buffered port:32 p_miso = XS1_PORT_1A; in port p_ss = XS1_PORT_1B; @@ -22,87 +23,7 @@ in port setup_resp_port = XS1_PORT_1F; #define BURNT_THREADS 0 #define TRANSFER_SIZE SPI_TRANSFER_SIZE_8 -static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, - 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f -}; -static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, - 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, -}; - - -#if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) -#define BITS_PER_TRANSFER 8 -#elif (TRANSFER_SIZE == SPI_TRANSFER_SIZE_32) -#define BITS_PER_TRANSFER 32 -#else -#error Invalid transfer size given -#endif - -void flush_print(void){ - delay_microseconds(10); -} - -static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -static void send_data_to_tester( - out port setup_strobe_port, - out port setup_data_port, - unsigned data){ - setup_data_port <: data; - sync(setup_data_port); - setup_strobe_port <: 1; - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_strobe_port <: 0; -} - -static void broadcast_settings( - out port setup_strobe_port, - out port setup_data_port, - spi_mode_t mode, - int mosi_enabled, - int miso_enabled, - unsigned num_bits, - unsigned kbps, - unsigned initial_clock_delay // in ns -){ - unsigned cpha, cpol; - - set_mode_bits(mode, cpol, cpha); - - setup_strobe_port <: 0; - - send_data_to_tester(setup_strobe_port, setup_data_port, cpol); - send_data_to_tester(setup_strobe_port, setup_data_port, cpha); - send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); - send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); - send_data_to_tester(setup_strobe_port, setup_data_port, kbps); - send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); -} - -static int request_response( - out port setup_strobe_port, - in port setup_resp_port -){ - int r; - setup_strobe_port <: 1; // Twice to make sure we are not too fast - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_strobe_port <: 0; - setup_resp_port :> r; - return r; - -} // This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits diff --git a/tests/spi_slave_ss_deassert/CMakeLists.txt b/tests/spi_slave_ss_deassert/CMakeLists.txt new file mode 100644 index 0000000..be78943 --- /dev/null +++ b/tests/spi_slave_ss_deassert/CMakeLists.txt @@ -0,0 +1,61 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON spi_mode_list GET ${params_json} SPI_MODE) +string(JSON transfer_size_list GET ${params_json} TRANSFER_SIZE) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) +string(JSON transfer_size_list_len LENGTH ${transfer_size_list}) + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") +math(EXPR transfer_size_list_len "${transfer_size_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${spi_mode_list_len}) + string(JSON spi_mode GET ${spi_mode_list} ${j}) + + foreach(j RANGE 0 ${transfer_size_list_len}) + string(JSON transfer_size GET ${transfer_size_list} ${j}) + + + set(config ${spi_mode}_${transfer_size}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_ss_deassert) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DSPI_MODE=${spi_mode} + -DTRANSFER_SIZE=${transfer_size} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_slave_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/tests/spi_slave_ss_deassert/config.xscope b/tests/spi_slave_ss_deassert/config.xscope new file mode 100644 index 0000000..1ba0f11 --- /dev/null +++ b/tests/spi_slave_ss_deassert/config.xscope @@ -0,0 +1,3 @@ + + + diff --git a/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc b/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc new file mode 100644 index 0000000..3718571 --- /dev/null +++ b/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc @@ -0,0 +1,173 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" +#include "common.h" + +out buffered port:32 p_miso = XS1_PORT_1A; +in port p_ss = XS1_PORT_1B; +in port p_sclk = XS1_PORT_1C; +in buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; +in port setup_resp_port = XS1_PORT_1F; + +#define KBPS 1000 +#define BURNT_THREADS 6 +#define MOSI_ENABLED 1 +#define MISO_ENABLED 1 + + +#if (TRANSFER_SIZE == 8) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_8 +#elif (TRANSFER_SIZE == 32) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_32 +#else +#error Invalid transfer size given +#endif + + +// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits + +[[combinable]] +void app(server interface spi_slave_callback_if spi_i, + int mosi_enabled, int miso_enabled){ + + unsigned bpt = 0; + spi_transfer_type_t tt = SPI_TRANSFER_SIZE; + switch(tt){ + case SPI_TRANSFER_SIZE_8:bpt = 8;break; + case SPI_TRANSFER_SIZE_32:bpt = 32;break; + } + + + unsigned num_bits = NUMBER_OF_TEST_BYTES*8; + + //First check a multi byte transfer + printf("Send initial settings\n"); + // printf("%u\n", num_bits); + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + + unsigned rx_byte_no = 0; + unsigned tx_byte_no = 0; + while(1){ + select { + case spi_i.master_requires_data() -> uint32_t r:{ + // printf("master_requires_data\n"); + if(tx_byte_no < NUMBER_OF_TEST_BYTES){ + switch(tt){ + case SPI_TRANSFER_SIZE_8: + r = tx_data[tx_byte_no]; + tx_byte_no++; + break; + case SPI_TRANSFER_SIZE_32: + r = (tx_data[tx_byte_no+3]<<0) + | (tx_data[tx_byte_no+2]<<8) + | (tx_data[tx_byte_no+1]<<16) + | (tx_data[tx_byte_no+0]<<24); + tx_byte_no+=4; + break; + } + } + if(!miso_enabled){ + printf("Error: master cannot require data when miso is not enabled\n"); + _Exit(1); + } + break; + } + case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ + // printf("master_supplied_data\n"); + for(unsigned i=0; i> (valid_bits - 8))&0xff; + if(rx_data[rx_byte_no] != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + rx_data[rx_byte_no], d, num_bits); + _Exit(1); + } + rx_byte_no++; + datum <<= 8; + } + + if(valid_bits < 8){ + datum <<= (8-valid_bits); + } else + datum >>= (valid_bits-8); + datum &= 0xff; + + if(valid_bits&0x7){ + uint32_t d =(rx_data[rx_byte_no]>>(8-(valid_bits&0x7)))<<(8-(valid_bits&0x7)); + if(datum != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + d, datum, num_bits); + _Exit(1); + } + } + break; + } + + case spi_i.master_ends_transaction():{ + // printf("master_ends_transaction\n"); + //Then check all sub word transfers + if(num_bits == NUMBER_OF_TEST_BYTES*8){ + num_bits = 0; + } + if(num_bits == bpt){ + printf("Test completed\n"); + _Exit(0); + } + num_bits++; + + int r = request_response(setup_strobe_port, setup_resp_port); + + if(r){ + printf("Error: Master Rx error\n"); + _Exit(1); + } + if(num_bits > bpt){ + printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); + _Exit(1); + } + + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + rx_byte_no = 0; + tx_byte_no = 0; + break; + } + } + } +} + +static void load(static const unsigned num_threads){ + switch(num_threads){ + case 3: par {par(int i=0;i<3;i++) while(1);}break; + case 6: par {par(int i=0;i<6;i++) while(1);}break; + case 7: par {par(int i=0;i<7;i++) while(1);}break; + } +} +#define MOSI_ENABLED 1 + +#if MISO_ENABLED +#define MISO p_miso +#else +#define MISO null +#endif + +int main(){ + interface spi_slave_callback_if i; + par { + + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + app(i, MOSI_ENABLED, MISO_ENABLED); + load(BURNT_THREADS); + } + return 0; +} diff --git a/tests/spi_slave_ss_deassert/test_params.json b/tests/spi_slave_ss_deassert/test_params.json new file mode 100644 index 0000000..842de12 --- /dev/null +++ b/tests/spi_slave_ss_deassert/test_params.json @@ -0,0 +1,5 @@ +{ + "SPI_MODE": [0, 1, 2, 3], + "TRANSFER_SIZE": [8, 32], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_slave_tester_common/common.h b/tests/spi_slave_tester_common/common.h new file mode 100644 index 0000000..06d8232 --- /dev/null +++ b/tests/spi_slave_tester_common/common.h @@ -0,0 +1,86 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#ifndef COMMON_SLAVE_H_ +#define COMMON_SLAVE_H_ + +static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ + switch(mode){ + case SPI_MODE_0:cpol = 0; cpha= 0; break; + case SPI_MODE_1:cpol = 0; cpha= 1; break; + case SPI_MODE_2:cpol = 1; cpha= 0; break; + case SPI_MODE_3:cpol = 1; cpha= 1; break; + } +} + +static void send_data_to_tester( + out port setup_strobe_port, + out port setup_data_port, + unsigned data){ + setup_data_port <: data; + sync(setup_data_port); + setup_strobe_port <: 1; // Twice to meet timing on harness + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; +} + +static void broadcast_settings( + out port setup_strobe_port, + out port setup_data_port, + spi_mode_t mode, + int mosi_enabled, + int miso_enabled, + unsigned num_bits, + unsigned kbps, + unsigned initial_clock_delay // in ns + +){ + unsigned cpha, cpol; + + set_mode_bits(mode, cpol, cpha); + + setup_strobe_port <: 0; + setup_strobe_port <: 0; + + send_data_to_tester(setup_strobe_port, setup_data_port, cpol); + send_data_to_tester(setup_strobe_port, setup_data_port, cpha); + send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); + send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); + send_data_to_tester(setup_strobe_port, setup_data_port, kbps); + send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); +} + +static int request_response( + out port setup_strobe_port, + in port setup_resp_port +){ + int r; + setup_strobe_port <: 1; // Twice to make sure we are not too fast + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; + setup_resp_port :> r; + return r; + +} + +void flush_print(void){ + delay_microseconds(10); +} + +#define NUMBER_OF_TEST_BYTES 16 +#define NUMBER_OF_TEST_WORDS (NUMBER_OF_TEST_BYTES/sizeof(uint32_t)) + +static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, + 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f +}; + +static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, + 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, +}; + + + +#endif /* COMMON_SLAVE_H_ */ diff --git a/tests/test_master_async_rx_tx.py b/tests/test_master_async_rx_tx.py index 432ca2e..b7f5fb8 100644 --- a/tests/test_master_async_rx_tx.py +++ b/tests/test_master_async_rx_tx.py @@ -1,4 +1,4 @@ -# Copyright 2025 XMOS LIMITED. +# Copyright 2015-2025 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. from pathlib import Path import Pyxsim diff --git a/tests/test_slave_ss_deassert.py b/tests/test_slave_ss_deassert.py new file mode 100644 index 0000000..90a81a8 --- /dev/null +++ b/tests/test_slave_ss_deassert.py @@ -0,0 +1,49 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_slave_ss_deassert" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, spi_mode, transfer_size, arch, id): + id_string = f"{spi_mode}_{transfer_size}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + pytest.xfail("This test is work in progress") + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + with open(filepath/f"expected/slave.expect") as exp: + expected = exp.read().splitlines() + expected = expected[:3 + transfer_size] + expected[-1:] + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = True, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd + ) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output) + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_ss_deassert(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) From 5e3e86dbdd02451142cd62cd23aef30dd997e2ed Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 5 Aug 2025 11:32:49 +0100 Subject: [PATCH 40/57] Fix spi slave incorrect modes --- CHANGELOG.rst | 1 + Jenkinsfile | 2 +- lib_spi/src/spi_slave.xc | 10 ++++++---- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 2f20a61..ac08298 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -11,6 +11,7 @@ lib_spi change log * ADDED: SPI master optional MISO and SS timing adjustments * ADDED: Array transfer method for SPI sync * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 + * RESOLVED: SPI slave swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests * REMOVED: Support for XS1 devices diff --git a/Jenkinsfile b/Jenkinsfile index 11dbdb2..9287804 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -36,7 +36,7 @@ pipeline { ) string( name: 'INFR_APPS_VERSION', - defaultValue: 'v3.1.1', + defaultValue: 'v2.1.0', description: 'The infr_apps version' ) } diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 30e0cea..1a8f1bc 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -33,11 +33,11 @@ void spi_slave(client spi_slave_callback_if spi_i, start_clock(clk); switch(mode){ - case SPI_MODE_0: + case SPI_MODE_1: case SPI_MODE_2: set_port_inv(sclk); break; - case SPI_MODE_1: + case SPI_MODE_0: case SPI_MODE_3: set_port_no_inv(sclk); break; @@ -82,7 +82,8 @@ void spi_slave(client spi_slave_callback_if spi_i, if(transfer_type == SPI_TRANSFER_SIZE_8){ data = (bitrev(data)>>24); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ + // Send data before clock + if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); @@ -93,7 +94,8 @@ void spi_slave(client spi_slave_callback_if spi_i, } } else { data = bitrev(data); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ + // Send data before clock + if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); From b14f25dd4691cb4648d6e1aa330295f58c877bd8 Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 5 Aug 2025 13:48:57 +0100 Subject: [PATCH 41/57] Fix benchmark slave Fix slave bench & repo checks --- CHANGELOG.rst | 2 +- Jenkinsfile | 4 +- lib_spi/src/spi_slave.xc | 38 ++++++++---- tests/spi_slave_benchmark/CMakeLists.txt | 1 + .../src/spi_slave_benchmark.xc | 62 ++----------------- 5 files changed, 34 insertions(+), 73 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index ac08298..12ea099 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -9,7 +9,7 @@ lib_spi change log * ADDED: Shutdown method for SPI sync * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments - * ADDED: Array transfer method for SPI sync + * ADDED: Array transfer method for SPI master sync * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: SPI slave swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/Jenkinsfile b/Jenkinsfile index 9287804..2ce8cc8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -36,7 +36,7 @@ pipeline { ) string( name: 'INFR_APPS_VERSION', - defaultValue: 'v2.1.0', + defaultValue: 'v3.1.1', description: 'The infr_apps version' ) } @@ -67,7 +67,7 @@ pipeline { steps { warnError("Library checks failed") { - runLibraryChecks("${WORKSPACE}/${REPO_NAME}", "${params.INFR_APPS_VERSION}") + runRepoChecks("${WORKSPACE}/${REPO_NAME}") } } } diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 1a8f1bc..9d498a0 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -26,9 +26,19 @@ void spi_slave(client spi_slave_callback_if spi_i, stop_clock(clk); set_clock_src(clk, sclk); - if(!isnull(miso)) - configure_out_port_strobed_slave(miso, ss, clk, 0); configure_in_port_strobed_slave(mosi, ss, clk); + if(!isnull(miso)){ + configure_out_port_strobed_slave(miso, ss, clk, 0); + } + + // note do NOT configure MISO yet. We will leave this as an input so Hi-Z + // TODO + if(transfer_type == SPI_TRANSFER_SIZE_8){ + asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); + if(!isnull(miso)){ + asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); // Transfer width + } + } start_clock(clk); @@ -46,12 +56,6 @@ void spi_slave(client spi_slave_callback_if spi_i, int ss_val; - //set the transfer width - if(transfer_type == SPI_TRANSFER_SIZE_8){ - if(!isnull(miso)) - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - } uint32_t buffer; @@ -59,12 +63,18 @@ void spi_slave(client spi_slave_callback_if spi_i, while(1){ select { case ss when pinsneq(ss_val) :> ss_val:{ - if(!isnull(miso)) + if(!isnull(miso)){ clearbuf(miso); + } if(ss_val != ASSERTED){ unsigned remaining_bits = endin(mosi); uint32_t data; + // Make MISO go Hi-Z if SS not asserted. It will switch + // to output again on the next out or partout + if(!isnull(miso)){ + // TODO + } mosi :> data; if(remaining_bits){ //FIXME can this be more then tw? data = bitrev(data); @@ -76,13 +86,17 @@ void spi_slave(client spi_slave_callback_if spi_i, spi_i.master_ends_transaction(); break; } - + + // ss_val == ASSERTED if(!isnull(miso)){ uint32_t data = spi_i.master_requires_data(); + // Enable MISO and set transfer width if SPI_TRANSFER_SIZE_8 + // TODO + if(transfer_type == SPI_TRANSFER_SIZE_8){ data = (bitrev(data)>>24); - // Send data before clock + // Send data before clock. Use ref clock to allow port to output in absence of SPI clock if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); @@ -94,7 +108,7 @@ void spi_slave(client spi_slave_callback_if spi_i, } } else { data = bitrev(data); - // Send data before clock + // Send data before clock. Use ref clock to allow port to output in absence of SPI clock if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); diff --git a/tests/spi_slave_benchmark/CMakeLists.txt b/tests/spi_slave_benchmark/CMakeLists.txt index be00f67..22c6706 100644 --- a/tests/spi_slave_benchmark/CMakeLists.txt +++ b/tests/spi_slave_benchmark/CMakeLists.txt @@ -68,6 +68,7 @@ foreach(i RANGE 0 ${arch_list_len}) -g -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_slave_tester_common) XMOS_REGISTER_APP() message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") diff --git a/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc index cafc687..95d67da 100644 --- a/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc +++ b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc @@ -5,6 +5,7 @@ #include #include #include "spi.h" +#include "common.h" out buffered port:32 p_miso = XS1_PORT_1A; in port p_ss = XS1_PORT_1B; @@ -26,69 +27,14 @@ in port setup_resp_port = XS1_PORT_1F; #endif -static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -static void send_data_to_tester( - out port setup_strobe_port, - out port setup_data_port, - unsigned data){ - setup_data_port <: data; - sync(setup_data_port); - setup_strobe_port <: 1; // Dp each twice so checker doesn't miss at higher clock frequencies of xcore.ai - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_strobe_port <: 0; -} - -static void broadcast_settings( - out port setup_strobe_port, - out port setup_data_port, - spi_mode_t mode, - int mosi_enabled, - int miso_enabled, - unsigned num_bits, - unsigned kbps, - unsigned initial_clock_delay // in ns -){ - unsigned cpha, cpol; - - set_mode_bits(mode, cpol, cpha); - - // printf("Testing: %d %d\n", kbps, initial_clock_delay); - - setup_strobe_port <: 0; - - send_data_to_tester(setup_strobe_port, setup_data_port, cpol); - send_data_to_tester(setup_strobe_port, setup_data_port, cpha); - send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); - send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); - send_data_to_tester(setup_strobe_port, setup_data_port, kbps); - send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); -} - -static int request_response( - out port setup_strobe_port, - in port setup_resp_port -){ - int r; - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_resp_port :> r; - return r; - -} [[combinable]] void app(server interface spi_slave_callback_if spi_i, int mosi_enabled, int miso_enabled){ + (const void*)tx_data; // Remove warning of unused var + (const void*)rx_data; // Remove warning of unused var + unsigned bpt = 0; spi_transfer_type_t tt = TRANSFER_SIZE; switch(tt){ From 048db4748fc5cd29227d6c143031f308adde0096 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 6 Aug 2025 11:30:54 +0100 Subject: [PATCH 42/57] Docs update, remove slave SS deassert as already covered and MISO HI-z feature for slave --- CHANGELOG.rst | 2 + doc/images/wavedrom_mode0.js | 2 +- doc/images/wavedrom_mode1.js | 2 +- doc/images/wavedrom_mode2.js | 2 +- doc/images/wavedrom_mode3.js | 2 +- doc/rst/lib_spi.rst | 6 +- lib_spi/api/spi.h | 47 +++-- lib_spi/src/spi_slave.xc | 26 +-- tests/CMakeLists.txt | 1 - tests/spi_slave_checker.py | 35 +++- tests/spi_slave_ss_deassert/CMakeLists.txt | 61 ------ tests/spi_slave_ss_deassert/config.xscope | 3 - .../src/spi_slave_ss_deassert.xc | 173 ------------------ tests/spi_slave_ss_deassert/test_params.json | 5 - tests/spi_slave_tester_common/common.h | 2 + tests/test_slave_ss_deassert.py | 49 ----- 16 files changed, 78 insertions(+), 340 deletions(-) delete mode 100644 tests/spi_slave_ss_deassert/CMakeLists.txt delete mode 100644 tests/spi_slave_ss_deassert/config.xscope delete mode 100644 tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc delete mode 100644 tests/spi_slave_ss_deassert/test_params.json delete mode 100644 tests/test_slave_ss_deassert.py diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 12ea099..e22128a 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -10,6 +10,8 @@ lib_spi change log * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments * ADDED: Array transfer method for SPI master sync + * ADDED: SPI slave MISO goes Hi-Z when SS is deasserted supporting + multiple slaves on a single external master * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: SPI slave swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/doc/images/wavedrom_mode0.js b/doc/images/wavedrom_mode0.js index 4ffa214..3459572 100644 --- a/doc/images/wavedrom_mode0.js +++ b/doc/images/wavedrom_mode0.js @@ -2,7 +2,7 @@ {name: 'CLK', wave: '0...10101|010...', node: '...B'}, {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, + {name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, { node: '.a.b........c..d'} ], edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] diff --git a/doc/images/wavedrom_mode1.js b/doc/images/wavedrom_mode1.js index 3cee681..8318057 100644 --- a/doc/images/wavedrom_mode1.js +++ b/doc/images/wavedrom_mode1.js @@ -2,7 +2,7 @@ {name: 'CLK', wave: '0..101010|10....', node: '...B'}, {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, -{name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, +{name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, { node: '.a.b........c..d'} ], edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] } \ No newline at end of file diff --git a/doc/images/wavedrom_mode2.js b/doc/images/wavedrom_mode2.js index 3c8d21f..47cc95f 100644 --- a/doc/images/wavedrom_mode2.js +++ b/doc/images/wavedrom_mode2.js @@ -2,7 +2,7 @@ {name: 'CLK', wave: '1...01010|101...', node: '...B'}, {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, + {name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, { node: '.a.b........c..d'} ], edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] diff --git a/doc/images/wavedrom_mode3.js b/doc/images/wavedrom_mode3.js index 59ff12b..9e11736 100644 --- a/doc/images/wavedrom_mode3.js +++ b/doc/images/wavedrom_mode3.js @@ -2,7 +2,7 @@ {name: 'CLK', wave: '1..010101|01..', node: '...B'}, {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, + {name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, { node: '.a.b........c..d'} ], edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 97f70c7..231874b 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -55,7 +55,7 @@ SPI Modes The data sample points for SPI are defined by the clock polarity (CPOL) and clock phase (CPHA) parameters. SPI clock polarity may be inverted or non-inverted by the CPOL and the CPHA parameter -is used to shift the sampling phase. The following for sections illustrate the MISO and MOSI data lines +is used to shift the sampling phase. The following four sections illustrate the MISO and MOSI data lines relative to the clock. The timings are given by: .. list-table:: SPI timings @@ -137,7 +137,7 @@ timings can be seen in :numref:`spi_master_sync_timings`. - MOSI enabled - MISO enabled - Max kbps (62.5 MHz core) - - Max kbps (125 MHz core) + - Max kbps (100 MHz core) * - 0 - 1 - 0 @@ -755,7 +755,7 @@ All SPI slave functions can be accessed via the ``spi.h`` header:: #include You will also have to add ``lib_spi`` to the -``USED_MODULES`` field of your application Makefile. +``LIB_DEPENDENT_MODULES`` field of your application CMakefile. Creating an SPI slave instance .............................. diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index bee624e..e3f5154 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -7,7 +7,7 @@ #include #include extern "C" { -#include "../src/spi_fwk.h" + #include "../src/spi_fwk.h" } // These are needed for DOXYGEN to render properly #ifndef __DOXYGEN__ @@ -187,18 +187,6 @@ typedef interface spi_master_if { /**@}*/ // END: addtogroup spi_master_if - -[[distributable]] -void spi_master( - SERVER_INTERFACE(spi_master_if, i[num_clients]), - static_const_size_t num_clients, - out_buffered_port_32_t sclk, - NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), - NULLABLE_RESOURCE(in_buffered_port_32_t, miso), - out_port p_ss, - static_const_size_t num_slaves, - NULLABLE_RESOURCE(clock, clk)); - /** Task that implements the SPI proctocol in master mode that is connected to a multiple slaves on the bus. @@ -220,10 +208,22 @@ void spi_master( of the slave. Multiple slaves may be supported by specifying, for example, a 4-bit port. Please specify mapping of bits to slaves using - i.set_ss_port_bit() + i.set_ss_port_bit(). \param num_slaves The number of slave devices on the bus. - \param clk a clock for the component to use. + \param clk A clock for the component to use. May be set + to null if low speed operation is acceptable. */ +[[distributable]] +void spi_master( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss, + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); + /** * \addtogroup spi_master_async_if @@ -433,14 +433,13 @@ typedef interface spi_slave_callback_if { /** This callback will get called when the master initiates a bus transfer * or when more data is required during a transaction. - * The application must supply the data to transmit to the master. If - * the spi slave component is set to ``SPI_TRANSFER_SIZE_32`` mode then - * this callback will not be called and master_requires_data32() will - * be called instead. Data is transmitted for the least significant bit - * first. If the master completes the transaction before 8 bits are - * transferred the remaining bits are discarded. - * - * \returns the 8-bit value to transmit. + * The application must supply the data to transmit to the master. + * Data is transmitted with the least significant bit + * first. If the master completes the transaction before 8/32 bits ( + * depending on SPI_TRANSFER_SIZE_8 or SPI_TRANSFER_SIZE_32) are + * transferred and the remaining bits are discarded. + * + * \returns the 8-bit or 32-bit value to transmit. */ uint32_t master_requires_data(void); @@ -470,7 +469,7 @@ typedef interface spi_slave_callback_if { } spi_slave_callback_if; #endif - /**@}*/ // END: addtogroup spi_slave_callback_if +/**@}*/ // END: addtogroup spi_slave_callback_if /** This type specifies the transfer size from the SPI slave component diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 9d498a0..d406070 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -28,16 +28,16 @@ void spi_slave(client spi_slave_callback_if spi_i, configure_in_port_strobed_slave(mosi, ss, clk); if(!isnull(miso)){ - configure_out_port_strobed_slave(miso, ss, clk, 0); + set_port_use_on(miso); // Set to Hi-Z (input) and reset port + asm volatile ("setc res[%0], %1"::"r"(miso), "r"(XS1_SETC_BUF_BUFFERS)); // Switch to buffered mode } // note do NOT configure MISO yet. We will leave this as an input so Hi-Z // TODO if(transfer_type == SPI_TRANSFER_SIZE_8){ asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - if(!isnull(miso)){ - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); // Transfer width - } + // Note no MISO setup because we want it to be Hi-Z + // It will get configured at SS event when we start to tx data from slave } start_clock(clk); @@ -55,11 +55,11 @@ void spi_slave(client spi_slave_callback_if spi_i, sync(sclk); int ss_val; - - uint32_t buffer; + // Wait for de-assert ss when pinseq(!ASSERTED) :> ss_val; + while(1){ select { case ss when pinsneq(ss_val) :> ss_val:{ @@ -68,13 +68,14 @@ void spi_slave(client spi_slave_callback_if spi_i, } if(ss_val != ASSERTED){ + if(!isnull(miso)){ + set_port_use_on(miso); // Set to Hi-Z and reset + asm volatile ("setc res[%0], %1"::"r"(miso), "r"(XS1_SETC_BUF_BUFFERS)); // Switch to buffered mode + } unsigned remaining_bits = endin(mosi); uint32_t data; // Make MISO go Hi-Z if SS not asserted. It will switch // to output again on the next out or partout - if(!isnull(miso)){ - // TODO - } mosi :> data; if(remaining_bits){ //FIXME can this be more then tw? data = bitrev(data); @@ -90,20 +91,20 @@ void spi_slave(client spi_slave_callback_if spi_i, // ss_val == ASSERTED if(!isnull(miso)){ uint32_t data = spi_i.master_requires_data(); - - // Enable MISO and set transfer width if SPI_TRANSFER_SIZE_8 - // TODO + // Note port is only configured as buffered input at the moment if(transfer_type == SPI_TRANSFER_SIZE_8){ data = (bitrev(data)>>24); // Send data before clock. Use ref clock to allow port to output in absence of SPI clock if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ + asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); // Transfer width asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); data = data>>1; partout(miso, 7, data); } else { + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); // Attach to SPI clock partout(miso, 8, data); } } else { @@ -116,6 +117,7 @@ void spi_slave(client spi_slave_callback_if spi_i, data = data>>1; partout(miso, 31, data); } else { + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); // Attach to SPI clock miso <: data; } } diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 59314ac..b663fe6 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -11,7 +11,6 @@ add_subdirectory(spi_master_sync_shutdown) add_subdirectory(spi_slave_benchmark) add_subdirectory(spi_slave_rx_tx) add_subdirectory(spi_slave_shutdown) -add_subdirectory(spi_slave_ss_deassert) add_subdirectory(spi_master_async_rx_tx) add_subdirectory(spi_master_async_multi_client) add_subdirectory(spi_master_async_multi_device) diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py index c67156e..5f308f4 100644 --- a/tests/spi_slave_checker.py +++ b/tests/spi_slave_checker.py @@ -66,6 +66,7 @@ def run(self): initial_clock_delay = int(self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) * nanosecond_ticks) print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") + # drive initial values while slave starts up for the first time xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 1) @@ -74,7 +75,13 @@ def run(self): time_trigger += 10 * microsecond_ticks self.wait_until(time_trigger) - + # check MISO isn't driving + miso_driving = xsi.is_port_driving(self._miso_port) + if miso_driving: + print(f"Error: MISO still driving before ss assert") + + + xsi.drive_port_pins(self._setup_resp_port, 0) # This port also doubles as tester ready to report xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 0) @@ -119,7 +126,7 @@ def run(self): if expected_miso_enabled: if rx_byte != rx_data[byte_count]: error = 1 - print(f"tester rx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") + print(f"Error: tester MISO got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") rx_byte = 0 byte_count = byte_count + 1 if byte_count*8 < expected_num_bits: @@ -129,15 +136,33 @@ def run(self): if bit_count and expected_miso_enabled: if rx_byte != rx_data[byte_count]>>(8-bit_count): error = 1 - print(f"sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count}") + print(f"Error: MISO sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") time_trigger += half_clock self.wait_until(time_trigger) + # Deassert SS xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 1) - - self.wait_for_port_pins_change([self._setup_strobe_port]) + ss_deasserted_time = time_trigger + + # Test MISO is disabled + count_nanoseconds = 0 + max_nanoseconds = 2000 # This is quite lax because, in the test master_supplied_data() does a lot of processing and delays MISO being de-asserted + # We typically see times of 150ns or less + miso_driving = xsi.is_port_driving(self._miso_port) + while miso_driving and count_nanoseconds < max_nanoseconds: + miso_driving = xsi.is_port_driving(self._miso_port) + time_trigger += nanosecond_ticks + self.wait_until(time_trigger) + count_nanoseconds += 1 + if miso_driving: + print(f"Error: MISO still driving {max_nanoseconds}ns after ss deassert, at time: {xsi.get_time() / nanosecond_ticks}ns") + # print(f"MISO deasserted at {(time_trigger - ss_deasserted_time) / nanosecond_ticks}ns after SS, at time: {xsi.get_time() / nanosecond_ticks}ns") + + # Report back to DUT + xsi.drive_port_pins(self._setup_resp_port, 1) # Tester ready to report + self.wait_for_port_pins_change([self._setup_strobe_port]) # Wait for DUT to read xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 1) xsi.drive_port_pins(self._setup_resp_port, error) diff --git a/tests/spi_slave_ss_deassert/CMakeLists.txt b/tests/spi_slave_ss_deassert/CMakeLists.txt deleted file mode 100644 index be78943..0000000 --- a/tests/spi_slave_ss_deassert/CMakeLists.txt +++ /dev/null @@ -1,61 +0,0 @@ -cmake_minimum_required(VERSION 3.21) -include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) - -# Get JSON lists -file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) - -# Get individual fields from params_json -string(JSON arch_list GET ${params_json} arch) -string(JSON spi_mode_list GET ${params_json} SPI_MODE) -string(JSON transfer_size_list GET ${params_json} TRANSFER_SIZE) - -string(JSON arch_list_len LENGTH ${arch_list}) -string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) -string(JSON transfer_size_list_len LENGTH ${transfer_size_list}) - -# Subtract one off each of the lengths because RANGE includes last element -math(EXPR arch_list_len "${arch_list_len} - 1") -math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") -math(EXPR transfer_size_list_len "${transfer_size_list_len} - 1") - - -set(APP_PCA_ENABLE ON) -set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) -include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) - - -foreach(i RANGE 0 ${arch_list_len}) - string(JSON arch GET ${arch_list} ${i}) - if(arch STREQUAL "xs3") - set(target "XK-EVK-XU316") - elseif(arch STREQUAL "xs2") - set(target "XCORE-200-EXPLORER") - endif() - foreach(j RANGE 0 ${spi_mode_list_len}) - string(JSON spi_mode GET ${spi_mode_list} ${j}) - - foreach(j RANGE 0 ${transfer_size_list_len}) - string(JSON transfer_size GET ${transfer_size_list} ${j}) - - - set(config ${spi_mode}_${transfer_size}_${arch}) - message(STATUS "building config ${config}") - - project(spi_slave_ss_deassert) - set(APP_HW_TARGET ${target}) - - set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} - -DSPI_MODE=${spi_mode} - -DTRANSFER_SIZE=${transfer_size} - -O2 - -g - -Wno-reinterpret-alignment) - set(APP_INCLUDES src ../spi_slave_tester_common) - - XMOS_REGISTER_APP() - - unset(APP_COMPILER_FLAGS_${config}) - unset(CONFIG_COMPILER_FLAGS) - endforeach() - endforeach() -endforeach() diff --git a/tests/spi_slave_ss_deassert/config.xscope b/tests/spi_slave_ss_deassert/config.xscope deleted file mode 100644 index 1ba0f11..0000000 --- a/tests/spi_slave_ss_deassert/config.xscope +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc b/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc deleted file mode 100644 index 3718571..0000000 --- a/tests/spi_slave_ss_deassert/src/spi_slave_ss_deassert.xc +++ /dev/null @@ -1,173 +0,0 @@ -// Copyright 2015-2025 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include -#include "spi.h" -#include "common.h" - -out buffered port:32 p_miso = XS1_PORT_1A; -in port p_ss = XS1_PORT_1B; -in port p_sclk = XS1_PORT_1C; -in buffered port:32 p_mosi = XS1_PORT_1D; -clock cb = XS1_CLKBLK_1; - -out port setup_strobe_port = XS1_PORT_1E; -out port setup_data_port = XS1_PORT_16B; -in port setup_resp_port = XS1_PORT_1F; - -#define KBPS 1000 -#define BURNT_THREADS 6 -#define MOSI_ENABLED 1 -#define MISO_ENABLED 1 - - -#if (TRANSFER_SIZE == 8) -#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_8 -#elif (TRANSFER_SIZE == 32) -#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_32 -#else -#error Invalid transfer size given -#endif - - -// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits - -[[combinable]] -void app(server interface spi_slave_callback_if spi_i, - int mosi_enabled, int miso_enabled){ - - unsigned bpt = 0; - spi_transfer_type_t tt = SPI_TRANSFER_SIZE; - switch(tt){ - case SPI_TRANSFER_SIZE_8:bpt = 8;break; - case SPI_TRANSFER_SIZE_32:bpt = 32;break; - } - - - unsigned num_bits = NUMBER_OF_TEST_BYTES*8; - - //First check a multi byte transfer - printf("Send initial settings\n"); - // printf("%u\n", num_bits); - - broadcast_settings(setup_strobe_port, setup_data_port, - SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); - - unsigned rx_byte_no = 0; - unsigned tx_byte_no = 0; - while(1){ - select { - case spi_i.master_requires_data() -> uint32_t r:{ - // printf("master_requires_data\n"); - if(tx_byte_no < NUMBER_OF_TEST_BYTES){ - switch(tt){ - case SPI_TRANSFER_SIZE_8: - r = tx_data[tx_byte_no]; - tx_byte_no++; - break; - case SPI_TRANSFER_SIZE_32: - r = (tx_data[tx_byte_no+3]<<0) - | (tx_data[tx_byte_no+2]<<8) - | (tx_data[tx_byte_no+1]<<16) - | (tx_data[tx_byte_no+0]<<24); - tx_byte_no+=4; - break; - } - } - if(!miso_enabled){ - printf("Error: master cannot require data when miso is not enabled\n"); - _Exit(1); - } - break; - } - case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ - // printf("master_supplied_data\n"); - for(unsigned i=0; i> (valid_bits - 8))&0xff; - if(rx_data[rx_byte_no] != d){ - printf("Error: Expected %02x from master but got %02x for transfer of %d\n", - rx_data[rx_byte_no], d, num_bits); - _Exit(1); - } - rx_byte_no++; - datum <<= 8; - } - - if(valid_bits < 8){ - datum <<= (8-valid_bits); - } else - datum >>= (valid_bits-8); - datum &= 0xff; - - if(valid_bits&0x7){ - uint32_t d =(rx_data[rx_byte_no]>>(8-(valid_bits&0x7)))<<(8-(valid_bits&0x7)); - if(datum != d){ - printf("Error: Expected %02x from master but got %02x for transfer of %d\n", - d, datum, num_bits); - _Exit(1); - } - } - break; - } - - case spi_i.master_ends_transaction():{ - // printf("master_ends_transaction\n"); - //Then check all sub word transfers - if(num_bits == NUMBER_OF_TEST_BYTES*8){ - num_bits = 0; - } - if(num_bits == bpt){ - printf("Test completed\n"); - _Exit(0); - } - num_bits++; - - int r = request_response(setup_strobe_port, setup_resp_port); - - if(r){ - printf("Error: Master Rx error\n"); - _Exit(1); - } - if(num_bits > bpt){ - printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); - _Exit(1); - } - - - broadcast_settings(setup_strobe_port, setup_data_port, - SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); - rx_byte_no = 0; - tx_byte_no = 0; - break; - } - } - } -} - -static void load(static const unsigned num_threads){ - switch(num_threads){ - case 3: par {par(int i=0;i<3;i++) while(1);}break; - case 6: par {par(int i=0;i<6;i++) while(1);}break; - case 7: par {par(int i=0;i<7;i++) while(1);}break; - } -} -#define MOSI_ENABLED 1 - -#if MISO_ENABLED -#define MISO p_miso -#else -#define MISO null -#endif - -int main(){ - interface spi_slave_callback_if i; - par { - - spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); - app(i, MOSI_ENABLED, MISO_ENABLED); - load(BURNT_THREADS); - } - return 0; -} diff --git a/tests/spi_slave_ss_deassert/test_params.json b/tests/spi_slave_ss_deassert/test_params.json deleted file mode 100644 index 842de12..0000000 --- a/tests/spi_slave_ss_deassert/test_params.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "SPI_MODE": [0, 1, 2, 3], - "TRANSFER_SIZE": [8, 32], - "arch": ["xs2", "xs3"] -} diff --git a/tests/spi_slave_tester_common/common.h b/tests/spi_slave_tester_common/common.h index 06d8232..2a5714c 100644 --- a/tests/spi_slave_tester_common/common.h +++ b/tests/spi_slave_tester_common/common.h @@ -55,6 +55,8 @@ static int request_response( in port setup_resp_port ){ int r; + setup_resp_port when pinseq(1) :> r; // Wait for ACK from tester first + setup_strobe_port <: 1; // Twice to make sure we are not too fast setup_strobe_port <: 1; setup_strobe_port <: 0; diff --git a/tests/test_slave_ss_deassert.py b/tests/test_slave_ss_deassert.py deleted file mode 100644 index 90a81a8..0000000 --- a/tests/test_slave_ss_deassert.py +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright 2015-2025 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -from pathlib import Path -import Pyxsim -import pytest -from spi_slave_checker import SPISlaveChecker -from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output - -appname = "spi_slave_ss_deassert" -test_params_file = Path(__file__).parent / f"{appname}/test_params.json" - -def do_test(capfd, spi_mode, transfer_size, arch, id): - id_string = f"{spi_mode}_{transfer_size}_{arch}" - filepath = Path(__file__).resolve().parent - binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" - assert binary.exists() - - pytest.xfail("This test is work in progress") - - checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - "tile[0]:XS1_PORT_1B", - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") - - with open(filepath/f"expected/slave.expect") as exp: - expected = exp.read().splitlines() - expected = expected[:3 + transfer_size] + expected[-1:] - - tester = Pyxsim.testers.ComparisonTester(expected, - regexp = True, - ordered = True) - - Pyxsim.run_on_simulator_( - binary, - # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], - do_xe_prebuild = False, - simthreads = [checker], - capfd=capfd - ) - - output = print_expected_vs_output(expected, capfd) - assert tester.run(output) - -@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) -def test_slave_ss_deassert(capfd, params, request): - do_test(capfd, *params, request.node.callspec.id) From 95330a94434578b155bca8d862cef077baa56f4c Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 6 Aug 2025 17:03:28 +0100 Subject: [PATCH 43/57] Hi-z MISO if SS not asserted +test, update slave benchmark, imrpove error reporting in tests --- CHANGELOG.rst | 3 +- doc/rst/lib_spi.rst | 17 ++- lib_spi/src/spi_slave.xc | 10 +- tests/spi_slave_benchmark/CMakeLists.txt | 2 +- .../src/spi_slave_benchmark.xc | 102 +++++++++++------- tests/spi_slave_checker.py | 25 +++-- tests/spi_slave_tester_common/common.h | 10 +- tests/test_slave_benchmark.py | 4 +- 8 files changed, 106 insertions(+), 67 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index e22128a..534587c 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -10,8 +10,7 @@ lib_spi change log * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments * ADDED: Array transfer method for SPI master sync - * ADDED: SPI slave MISO goes Hi-Z when SS is deasserted supporting - multiple slaves on a single external master + * RESOLVED: SPI slave MISO now goes Hi-Z when SS is deasserted * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 * RESOLVED: SPI slave swapping of SPI modes 0 and 1 * RESOLVED: Non-funcional tests diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 231874b..b4417fe 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -163,9 +163,8 @@ timings can be seen in :numref:`spi_master_sync_timings`. Asynchronous SPI master clock speeds ==================================== -The asynchronous SPI master is limited only by the clock divider on the -clock block. This means that for the 100MHz reference clock, -the asynchronous master can output a clock at up to 100MHz, port timing and hardware permitting. +The asynchronous SPI master uses the same transport layer as the SPI master using a clock block +and so achieves similar performance. .. list-table:: SPI master timings (asynchronous) :header-rows: 1 @@ -174,7 +173,7 @@ the asynchronous master can output a clock at up to 100MHz, port timing and hard - MISO enabled - MOSI enabled - Max kbps (62.5 MHz core) - - Max kbps (125 MHz core) + - Max kbps (100 MHz core) * - 1 - x - x @@ -186,12 +185,12 @@ the asynchronous master can output a clock at up to 100MHz, port timing and hard MISO port timing ================ -Port timing is affected by chip pad and PCB delays. For clock, slave-select and MOSI all of the delays will be broadly matched. -This means port timing adjustment is normally not required even up to the fastest support SPI clock rates. +Port timing is affected by chip pad and PCB delays. For the clock, slave-select and MOSI signals, all of the delays will be broadly matched. +This means port timing adjustment is normally not required even up to the fastest supported SPI clock rates. -For MISO, there will be a 'round trip delay' starting with the clock edge and finishing at the xCORE's input port. -Since this delay will mean the xCORE will be sampling early, it may be necessary to delay the sampling of the MISO -pin to capture within the required window, particularly if the SPI clock is above 20 MHz. +For the MISO signal, there will be a 'round trip delay' starting with the clock edge output and finishing at the xCORE's input port. +The presence of this delay will mean the xCORE may sample too early since data signal will arrive later. +It may be necessary to delay the sampling of the MISO pin to capture within the required window, particularly if the SPI clock is above 20 MHz. Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the API section which exposes the controls available for optimising setup and hold capture. diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index d406070..7d6f5ec 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -35,7 +35,7 @@ void spi_slave(client spi_slave_callback_if spi_i, // note do NOT configure MISO yet. We will leave this as an input so Hi-Z // TODO if(transfer_type == SPI_TRANSFER_SIZE_8){ - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); + // asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); // Note no MISO setup because we want it to be Hi-Z // It will get configured at SS event when we start to tx data from slave } @@ -68,6 +68,8 @@ void spi_slave(client spi_slave_callback_if spi_i, } if(ss_val != ASSERTED){ + // Make MISO go Hi-Z if SS not asserted. It will switch + // to output again on the next out or partout if(!isnull(miso)){ set_port_use_on(miso); // Set to Hi-Z and reset asm volatile ("setc res[%0], %1"::"r"(miso), "r"(XS1_SETC_BUF_BUFFERS)); // Switch to buffered mode @@ -97,7 +99,6 @@ void spi_slave(client spi_slave_callback_if spi_i, data = (bitrev(data)>>24); // Send data before clock. Use ref clock to allow port to output in absence of SPI clock if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); // Transfer width asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); partout(miso, 1, data); asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); @@ -128,8 +129,11 @@ void spi_slave(client spi_slave_callback_if spi_i, } else { buffer = bitrev(buffer); } - } + } // !isnull(miso) clearbuf(mosi); + if(transfer_type == SPI_TRANSFER_SIZE_8){ + asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); // Transfer width + } break; } // case ss diff --git a/tests/spi_slave_benchmark/CMakeLists.txt b/tests/spi_slave_benchmark/CMakeLists.txt index 22c6706..1db2ba9 100644 --- a/tests/spi_slave_benchmark/CMakeLists.txt +++ b/tests/spi_slave_benchmark/CMakeLists.txt @@ -63,7 +63,7 @@ foreach(i RANGE 0 ${arch_list_len}) -DBURNT_THREADS=${BURNT_THREADS} -DMISO_ENABLED=${MISO_ENABLED} -DSPI_MODE=${SPI_MODE} - -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_${SPI_TRANSFER_SIZE} + -DTRANSFER_SIZE=${SPI_TRANSFER_SIZE} -O2 -g -Wno-reinterpret-alignment) diff --git a/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc index 95d67da..da97c27 100644 --- a/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc +++ b/tests/spi_slave_benchmark/src/spi_slave_benchmark.xc @@ -18,10 +18,10 @@ out port setup_data_port = XS1_PORT_16B; in port setup_resp_port = XS1_PORT_1F; -#if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) -#define BITS_PER_TRANSFER 8 -#elif (TRANSFER_SIZE == SPI_TRANSFER_SIZE_32) -#define BITS_PER_TRANSFER 32 +#if (TRANSFER_SIZE == 8) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_8 +#elif (TRANSFER_SIZE == 32) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_32 #else #error Invalid transfer size given #endif @@ -36,7 +36,7 @@ void app(server interface spi_slave_callback_if spi_i, (const void*)rx_data; // Remove warning of unused var unsigned bpt = 0; - spi_transfer_type_t tt = TRANSFER_SIZE; + spi_transfer_type_t tt = SPI_TRANSFER_SIZE; switch(tt){ case SPI_TRANSFER_SIZE_8:bpt = 8;break; case SPI_TRANSFER_SIZE_32:bpt = 32;break; @@ -46,11 +46,15 @@ void app(server interface spi_slave_callback_if spi_i, unsigned cd_max = 40000; unsigned cd_min = 0; unsigned cd = (cd_max + cd_min)/2; + unsigned cd_last_good = cd_max; - unsigned kbps_max = 250000; + // SPI speed + unsigned kbps_max = 100000; unsigned kbps_min = 0; unsigned kbps = (kbps_max + kbps_min)/2; -// unsigned kbps = 7692; + unsigned kbps_last_good = kbps_min; + + int found_solution = 0; int finding_speed = 1; @@ -86,41 +90,47 @@ void app(server interface spi_slave_callback_if spi_i, case spi_i.master_requires_data() -> uint32_t r:{ switch(tt){ - case SPI_TRANSFER_SIZE_8: - tx_count &= 0xf; - r = tx_data_8[tx_count++]; - break; - case SPI_TRANSFER_SIZE_32: - tx_count &= 0x3; - r = tx_data_32[tx_count++]; - break; - default: - __builtin_unreachable(); - break; + case SPI_TRANSFER_SIZE_8: + tx_count &= 0xf; + r = tx_data_8[tx_count++]; + break; + case SPI_TRANSFER_SIZE_32: + tx_count &= 0x3; + r = tx_data_32[tx_count++]; + break; + default: + __builtin_unreachable(); + break; } break; } case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ switch(tt){ - case SPI_TRANSFER_SIZE_8: - rx_count &= 0xf; - if(datum != rx_data_8[rx_count]) - error=1; - break; - case SPI_TRANSFER_SIZE_32: - rx_count &= 0x3; - if(datum != rx_data_32[rx_count]) - error=1; - break; - default: - __builtin_unreachable(); - break; + case SPI_TRANSFER_SIZE_8: + rx_count &= 0xf; + if(datum != rx_data_8[rx_count]){ + error=1; + printf("Error in receiving slave 8 MOSI, expected: 0x%x got: 0x%x\n", rx_data_8[rx_count], datum); + } + break; + case SPI_TRANSFER_SIZE_32: + rx_count &= 0x3; + if(datum != rx_data_32[rx_count]){ + error=1; + printf("Error in receiving slave 32 MOSI, expected: 0x%x got: 0x%x\n", rx_data_32[rx_count], datum); + } + break; + default: + __builtin_unreachable(); + break; } rx_count++; - if(valid_bits != bpt) + if(valid_bits != bpt){ error = 1; + printf("Error in receiving slave bpt expected: %d got: %d\n", bpt, valid_bits); + } break; } @@ -128,6 +138,13 @@ void app(server interface spi_slave_callback_if spi_i, error |= request_response(setup_strobe_port, setup_resp_port); + if(!error){ + found_solution = 1; + cd_last_good = cd; + kbps_last_good = kbps; + } + + // First do speed if(finding_speed){ if(error == 1) kbps_max = kbps; @@ -137,7 +154,7 @@ void app(server interface spi_slave_callback_if spi_i, unsigned next_kbps = (kbps_max + kbps_min)/2; if(next_kbps == kbps){ rep_count++; - if(rep_count == 8){ + if(rep_count == 4){ finding_speed = 0; rep_count = 0; } @@ -159,9 +176,14 @@ void app(server interface spi_slave_callback_if spi_i, unsigned next_cd = (cd_max + cd_min)/2; if(next_cd == cd){ rep_count++; - if(rep_count == 8){ - printf("RESULT: %d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps); - _Exit(1); + if(rep_count == 4){ + if(found_solution){ + printf("RESULT: %d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd_last_good, kbps_last_good); + _Exit(0); + } else { + printf("ERROR! Run did not find a workable setting\n"); + _Exit(-1); + } } } else{ @@ -176,8 +198,8 @@ void app(server interface spi_slave_callback_if spi_i, } } - - // printf("broadcast_NEW settings\n"); + // printf("error from host: %d\n", error); + // printf("broadcast_NEW settings mode: %d mosi_enabled %d miso_enabled %d, num_bits %d kbps %d cd: %u\n", SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); error = 0; @@ -211,11 +233,11 @@ int main(){ #if COMBINED == 1 [[combine]] par { - spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, SPI_TRANSFER_SIZE); app(i, MOSI_ENABLED, MISO_ENABLED); } #else - spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, SPI_TRANSFER_SIZE); app(i, MOSI_ENABLED, MISO_ENABLED); #endif load(BURNT_THREADS); diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py index 5f308f4..1390d8b 100644 --- a/tests/spi_slave_checker.py +++ b/tests/spi_slave_checker.py @@ -63,9 +63,9 @@ def run(self): expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - initial_clock_delay = int(self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) * nanosecond_ticks) + initial_clock_delay = int(self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port)) print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") - + initial_clock_delay = initial_clock_delay * nanosecond_ticks # drive initial values while slave starts up for the first time xsi.drive_port_pins(self._sck_port, expected_cpol) @@ -81,7 +81,7 @@ def run(self): print(f"Error: MISO still driving before ss assert") - xsi.drive_port_pins(self._setup_resp_port, 0) # This port also doubles as tester ready to report + xsi.drive_port_pins(self._setup_resp_port, 0) # This port also doubles as tester ready to report signal xsi.drive_port_pins(self._sck_port, expected_cpol) xsi.drive_port_pins(self._ss_port, 0) @@ -126,7 +126,7 @@ def run(self): if expected_miso_enabled: if rx_byte != rx_data[byte_count]: error = 1 - print(f"Error: tester MISO got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") + print(f"Error: tester MISO got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} byte_count:{byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") rx_byte = 0 byte_count = byte_count + 1 if byte_count*8 < expected_num_bits: @@ -157,14 +157,21 @@ def run(self): self.wait_until(time_trigger) count_nanoseconds += 1 if miso_driving: + error = 1 print(f"Error: MISO still driving {max_nanoseconds}ns after ss deassert, at time: {xsi.get_time() / nanosecond_ticks}ns") # print(f"MISO deasserted at {(time_trigger - ss_deasserted_time) / nanosecond_ticks}ns after SS, at time: {xsi.get_time() / nanosecond_ticks}ns") + # Report back to DUT - xsi.drive_port_pins(self._setup_resp_port, 1) # Tester ready to report - self.wait_for_port_pins_change([self._setup_strobe_port]) # Wait for DUT to read - xsi.drive_port_pins(self._sck_port, expected_cpol) - xsi.drive_port_pins(self._ss_port, 1) + if xsi.sample_port_pins(self._setup_strobe_port) != 0: + print("Error - setup_strobe_port not 0 at end of test") + error = 1 + # setup strobe (trigger to DUT) is low so DUT not requested yet + + # This section corresponds to request_response() in the DUT + xsi.drive_port_pins(self._setup_resp_port, 1) # Tester ready to report + self.wait_for_port_pins_change([self._setup_strobe_port]) # Wait for DUT to ready read, sends 1 xsi.drive_port_pins(self._setup_resp_port, error) + self.wait_for_port_pins_change([self._setup_strobe_port]) # wait for it to go low again + - self.wait_for_port_pins_change([self._setup_strobe_port]) diff --git a/tests/spi_slave_tester_common/common.h b/tests/spi_slave_tester_common/common.h index 2a5714c..7caa8b6 100644 --- a/tests/spi_slave_tester_common/common.h +++ b/tests/spi_slave_tester_common/common.h @@ -3,6 +3,8 @@ #ifndef COMMON_SLAVE_H_ #define COMMON_SLAVE_H_ +#include + static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ switch(mode){ case SPI_MODE_0:cpol = 0; cpha= 0; break; @@ -57,11 +59,17 @@ static int request_response( int r; setup_resp_port when pinseq(1) :> r; // Wait for ACK from tester first - setup_strobe_port <: 1; // Twice to make sure we are not too fast + setup_strobe_port <: 1; // Repeat to make sure we are not too fast + setup_strobe_port <: 1; setup_strobe_port <: 1; + setup_strobe_port <: 1; + setup_strobe_port <: 0; setup_strobe_port <: 0; setup_strobe_port <: 0; + setup_strobe_port <: 0; + setup_resp_port :> r; + return r; } diff --git a/tests/test_slave_benchmark.py b/tests/test_slave_benchmark.py index 21203ea..b7c8fa0 100644 --- a/tests/test_slave_benchmark.py +++ b/tests/test_slave_benchmark.py @@ -29,8 +29,8 @@ def run(self, output): if any(skip in line for skip in ignore_list): continue if "RESULT:" in line: - result_clock_delay_ns = line.split(' ')[-1] - result_kbps = line.split(' ')[-2] + result_kbps = line.split(' ')[-1] + result_clock_delay_ns = line.split(' ')[-2] self.result["CLK_DLY_NS"] = result_clock_delay_ns self.result["KBPS"] = result_kbps From 0a56e1e9d5c8033347441535fdf146446c3ca5e0 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 7 Aug 2025 14:27:45 +0100 Subject: [PATCH 44/57] Documentation refresh --- CHANGELOG.rst | 9 +- Jenkinsfile | 4 +- doc/images/Makefile | 25 - doc/images/spi_master_async_state.dot | 19 - doc/images/spi_master_async_state.svg | 65 -- doc/images/spi_master_sync_state.dot | 14 - doc/images/spi_master_sync_state.svg | 40 - doc/images/wavedrom_mode0.js | 14 +- doc/images/wavedrom_mode0.png | Bin 19070 -> 0 bytes doc/images/wavedrom_mode1.js | 15 +- doc/images/wavedrom_mode1.png | Bin 19051 -> 0 bytes doc/images/wavedrom_mode2.js | 14 +- doc/images/wavedrom_mode2.png | Bin 19114 -> 0 bytes doc/images/wavedrom_mode3.js | 14 +- doc/images/wavedrom_mode3.png | Bin 19026 -> 0 bytes doc/rst/lib_spi.rst | 782 +++++++++++------- examples/AN00160_using_SPI_master/src/main.xc | 20 +- examples/AN00161_using_SPI_slave/src/main.xc | 14 +- lib_spi/api/spi.h | 457 +--------- lib_spi/api/spi_master_async.h | 195 +++++ lib_spi/api/spi_master_sync.h | 167 ++++ lib_spi/api/spi_slave.h | 95 +++ lib_spi/src/spi_fwk.h | 2 +- lib_spi/src/spi_master.c | 2 +- lib_spi/src/spi_master_async.xc | 18 +- lib_spi/src/spi_master_sync.xc | 14 +- lib_spi/src/spi_slave.xc | 6 - tests/helpers.py | 3 +- tests/requirements.txt | 1 + .../src/spi_master_async_multi_client.xc | 4 +- .../src/spi_master_async_rx_tx.xc | 10 +- .../src/spi_master_async_shutdown.xc | 8 +- tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc | 12 +- .../src/spi_slave_shutdown.xc | 14 +- tests/spi_slave_tester_common/common.h | 2 +- 35 files changed, 1055 insertions(+), 1004 deletions(-) delete mode 100644 doc/images/Makefile delete mode 100644 doc/images/spi_master_async_state.dot delete mode 100644 doc/images/spi_master_async_state.svg delete mode 100644 doc/images/spi_master_sync_state.dot delete mode 100644 doc/images/spi_master_sync_state.svg delete mode 100644 doc/images/wavedrom_mode0.png delete mode 100644 doc/images/wavedrom_mode1.png delete mode 100644 doc/images/wavedrom_mode2.png delete mode 100644 doc/images/wavedrom_mode3.png create mode 100644 lib_spi/api/spi_master_async.h create mode 100644 lib_spi/api/spi_master_sync.h create mode 100644 lib_spi/api/spi_slave.h diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 534587c..30174e0 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -10,10 +10,11 @@ lib_spi change log * ADDED: Shutdown method for SPI slave * ADDED: SPI master optional MISO and SS timing adjustments * ADDED: Array transfer method for SPI master sync - * RESOLVED: SPI slave MISO now goes Hi-Z when SS is deasserted - * RESOLVED: SPI master (all) swapping of SPI modes 0 and 1 - * RESOLVED: SPI slave swapping of SPI modes 0 and 1 - * RESOLVED: Non-funcional tests + * FIXED: SPI slave MISO now goes Hi-Z when SS is deasserted + * FIXED: SPI master (all) swapping of SPI modes 0 and 1 + * FIXED: SPI slave swapping of SPI modes 0 and 1 + * FIXED: Non-functional tests + * CHANGED: State diagrams and wavedrom now rendered by xmosdoc * REMOVED: Support for XS1 devices 3.4.0 diff --git a/Jenkinsfile b/Jenkinsfile index 2ce8cc8..4a6e559 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -2,6 +2,8 @@ @Library('xmos_jenkins_shared_library@v0.41.0') _ +getApproval() + def clone_test_deps() { dir("${WORKSPACE}") { sh "git clone git@github.com:xmos/test_support" @@ -9,8 +11,6 @@ def clone_test_deps() { } } -getApproval() - pipeline { agent { label 'x86_64 && linux' diff --git a/doc/images/Makefile b/doc/images/Makefile deleted file mode 100644 index e5306e8..0000000 --- a/doc/images/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -ODGS = $(wildcard *.odg) -PDFS = $(ODGS:.odg=.pdf) - -all: $(PDFS) - @echo PDFs created - -_uncropped: - mkdir _uncropped - -_uncropped/%.pdf: %.odg | _uncropped - soffice -env:UserInstallation=file:///home/$(USER)/.libreoffice-alt --headless --convert-to pdf $< --outdir _uncropped - -%.pdf: _uncropped/%.pdf - pdfcrop $< $@ - -wavedrom: - WaveDromEditor source wavedrom_mode0.js png wavedrom_mode0.png - WaveDromEditor source wavedrom_mode1.js png wavedrom_mode1.png - WaveDromEditor source wavedrom_mode2.js png wavedrom_mode2.png - WaveDromEditor source wavedrom_mode3.js png wavedrom_mode3.png - -clean: - -rm $(PDFS) - -rm _uncropped/*.pdf - -rmdir _uncropped diff --git a/doc/images/spi_master_async_state.dot b/doc/images/spi_master_async_state.dot deleted file mode 100644 index 182edad..0000000 --- a/doc/images/spi_master_async_state.dot +++ /dev/null @@ -1,19 +0,0 @@ -digraph g { - begin_transaction -> init_transfer_array_8 - begin_transaction -> init_transfer_array_32 - - init_transfer_array_8 -> transfer_complete - transfer_complete -> retrieve_transfer_buffers_8 - retrieve_transfer_buffers_8 -> end_transaction - - init_transfer_array_32 -> transfer_complete - transfer_complete -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_32 -> end_transaction - - retrieve_transfer_buffers_32 -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_32 -> retrieve_transfer_buffers_8 - retrieve_transfer_buffers_8 -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_8 -> retrieve_transfer_buffers_8 - - end_transaction -> begin_transaction -} diff --git a/doc/images/spi_master_async_state.svg b/doc/images/spi_master_async_state.svg deleted file mode 100644 index 94f32c7..0000000 --- a/doc/images/spi_master_async_state.svg +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - -begin_transaction - -init_transfer_array_8 - - - - -init_transfer_array_32 - - - - -transfer_complete - - - - - - - -retrieve_transfer_buffers_8 - - - - -retrieve_transfer_buffers_32 - - - - - - - -end_transaction - - - - - - - - - - - - - - - - - - - - - diff --git a/doc/images/spi_master_sync_state.dot b/doc/images/spi_master_sync_state.dot deleted file mode 100644 index 0c309a5..0000000 --- a/doc/images/spi_master_sync_state.dot +++ /dev/null @@ -1,14 +0,0 @@ -digraph g { - begin_transaction -> transfer8 - begin_transaction -> transfer32 - - transfer8 -> transfer8 - transfer8 -> transfer32 - transfer32 -> transfer8 - transfer32 -> transfer32 - - transfer32 -> end_transaction - transfer32 -> end_transaction - - end_transaction -> begin_transaction -} diff --git a/doc/images/spi_master_sync_state.svg b/doc/images/spi_master_sync_state.svg deleted file mode 100644 index 925ca16..0000000 --- a/doc/images/spi_master_sync_state.svg +++ /dev/null @@ -1,40 +0,0 @@ - - - - -begin_transaction - -transfer8 - - - - -transfer32 - - - - - - - - - - - - - - - - -end_transaction - - - - - - - - - - - diff --git a/doc/images/wavedrom_mode0.js b/doc/images/wavedrom_mode0.js index 3459572..d01932f 100644 --- a/doc/images/wavedrom_mode0.js +++ b/doc/images/wavedrom_mode0.js @@ -1,9 +1,9 @@ -{signal: [ - {name: 'CLK', wave: '0...10101|010...', node: '...B'}, - {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, - {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, - { node: '.a.b........c..d'} +{ signal: [ + {name: 'CLK', wave: '0...10101|010...', node: '....B......C......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'], 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'CLK', wave: '0..101010|10....', node: '...B'}, -{name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, -{name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, -{name: 'SS', wave: '10.......|..1..0', node: '.A..........C..D..'}, -{ node: '.a.b........c..d'} ], -edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] +{ signal: [ + {name: 'CLK', wave: '0..101010|10....', node: '....B......C......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'], node: '...................' }, + {name: 'SS', wave: '10.......|...1.0', node: '.A...........D.E..'}, + { node: '.a..b......c.d.e.' } +], + edge: [ 'A|a','B|b','C|c','D|d', 'E|e' ,'a<->b t1','c<->d t2', 'd<->e t3' ] } \ No newline at end of file diff --git a/doc/images/wavedrom_mode1.png b/doc/images/wavedrom_mode1.png deleted file mode 100644 index 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z8{$aJk_v-(JneMwvA5~hrcSq)zxR}Ma*gL7`vK(pYNjF}I77^n1HTN2v*Jxb-JdJ; z5dCR?bz^BqJqH9HIp0K!7u*c^b`x2`q>4bhzRr3jw^mPI@}qAs3k|Ay&1j$~f1t1* zg4O~f843FRe{KI)bvx&X2#I68((T*tRdJW!DP#wZ1z7p~2Nt-u1lBw3aar|Sq-D{f zMJC@~JqEfDyeaADQQ(L?_YICMm-nq&wd%WjuaxOVUB4{g-@mZ{)a#zA z$@}-$SCH{>Zx3(X|K{FaYc>CQXMPnf^?!eBt9J9Mtc!c&zGZ$|)%MRExaKnV!UD&R z{{C>c1^K|kKpMC*E`s`gT{3@#cXPi0ZpSu!%U}Pa*{D1Ncx=p%v-x$+|Np)JpZAyB zZ>DnEd@j$K=NA5!$#~A3cz&MkId+F`!Hli^Ec-jQ&1zQN&))Lq?q%RwXyz2)oC>hN zxXMWA@2l187Xh~wF#cxM*~R$#sQ*)bi;Jn<8o<+S0%7Av<-mOvpP0U-P2KzGKCq>K z4;Tn8uC80-TyC6$XZPZwq6u^7_KIqU9e7xC%LW6ED`R1}*?e1}->_{{8iJ`S!T);!*34 z{kxvGy;=9k`%6o^FZb|W2G-zWQjtmApSS(o#rUl;>|4c}wQIKm_p4jmT)m@VCUwzl z<3y*W;JWIJ>wy!0XJ<@0w@Yg0{wu4`$?p6QER}VuIO0n#0QV9gPVGTGEQoL058%FQ zas5NZ?9mKeY`~HTxZo061HsPuL0YEh4OyB9+f{vs6F5FH1L#ZG=|Z4&i&7lG0UKa# zAhqbQa}ca*hMq|j{0G)f=s5~qnYfJYQ2P|LE#A;=;qMZ$J-3@9?z!pODThZoa837Y#{8-uWM3wU+`_ or `IO timings for xCORE200 `_ document. +During any transfer of data, the master will assert the *SS* +line and then output a series of transitions on the *SCLK* +wire. During this time, the slave will drive data to be sampled by the +master and the master will drive data to be sampled by the slave. At +the end of the transfer, the *SS* is de-asserted. +If the slave select line is not driven high then the slave should +ignore any transitions on the other lines. |newpage| @@ -225,31 +195,21 @@ The master component of this library supports multiple slaves on unique slave select wires. The bit of the port used for each device is configurable and so multiple slaves may share the same select bit if needed. -SPI slave timings -================= -The logical core running the SPI slave task will wait for the slave -select line to assert and then begin processing the transaction. At -this point it will call the ``master_requires_data`` callback to -application code. The time taken for the application to perform this -call will affect how long the logical core has to resume processing -SPI data. This will affect the minimum allowable time between slave -select changing and data transfer from the master (*t1*). -The user of the library will need to determine this -time based on their application. +Disabling master data lines +=========================== -After slave select is de-asserted the SPI slave task will call the -``master_ends_transaction`` callback. The time the application takes -to process this will affect the minimum allowable inter-transmission -gap between transactions (*t2*). The user of the library will also need to -determine this time based on their application. +The *MOSI* and *MISO* parameters of the ``spi_master`` task are +optional. So in the top-level ``par`` statement the function can be +called with ``null`` instead of a port e.g. + +.. code-block:: C + + spi_master(i_spi, 1, p_sclk, null, p_miso , p_ss, 1, clk_spi); -If the SPI slave task is combined will other tasks running on the same -logical core then the other task may process an event delaying the -time it takes for the SPI slave task to react to events. This will add -these delays to the minimum times for both *t1* and *t2*. The library -user will need to take these into account in determining the timing -restrictions on the master. + +Similarly, the *MOSI* parameter of the ``spi_master_async`` task is +optional (but the *MISO* port must be provided). |newpage| @@ -260,8 +220,7 @@ Connecting to the xCORE SPI slave The SPI wires need to be connected to the xCORE device as shown in :numref:`spi_slave_xcore_connect`. The signals can be connected to any -one bit ports on the device provide they do not overlap any other used -ports and are all on the same tile. +one bit ports on the device. .. _spi_slave_xcore_connect: @@ -271,11 +230,19 @@ ports and are all on the same tile. SPI slave connection to the xCORE device The slave will only send and receive data when the slave select is -driven high. +driven high. Additionally the *MISO* line is set to high impedance +when not in use. If the *MISO* line is not required then it need not be connected. The *MOSI* line must always be connected. +Disabling slave data lines +========================== + +The ``spi_slave`` task has an optional *MISO* parameter (but the +*MOSI* port must be supplied). + + |newpage| ************ @@ -304,22 +271,24 @@ connect via an interface connection using the ``spi_master_if`` interface type: SPI master task diagram For example, the following code instantiates an SPI master component -and connect to it:: - - out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss = XS1_PORT_1B; - out buffered port:22 p_sclk = XS1_PORT_1C; - out buffered port:32 p_mosi = XS1_PORT_1D; - clock clk_spi = XS1_CLKBLK_1; - - int main(void) { - spi_master_if i_spi[1]; - par { - spi_master(i_spi, 1, p_sclk, p_mosi, p_miso , p_ss, 1, clk_spi); - my_application(i_spi[0]); - } - return 0; - } +and connect to it. + +.. code-block:: C + + out buffered port:32 p_miso = XS1_PORT_1A; + out port p_ss = XS1_PORT_1B; + out buffered port:22 p_sclk = XS1_PORT_1C; + out buffered port:32 p_mosi = XS1_PORT_1D; + clock clk_spi = XS1_CLKBLK_1; + + int main(void) { + spi_master_if i_spi[1]; + par { + spi_master(i_spi, 1, p_sclk, p_mosi, p_miso , p_ss, 1, clk_spi); + my_application(i_spi[0]); + } + return 0; + } Note that the connection is an array of interfaces, so several tasks can connect to the same component instance. The slave select ports are @@ -333,16 +302,19 @@ of the SPI bus is increased (see :numref:`spi_master_sync_timings`). If block is used. The application can use the client end of the interface connection to -perform SPI bus operations e.g.:: +perform SPI bus operations e.g. + +.. code-block:: C + + void my_application(client spi_master_if spi) { + uint8_t val; + printf("Doing one byte transfer. Sending 0x22.\n"); + spi.begin_transaction(0, 100, SPI_MODE_0); + val = spi.transfer8(0x22); + spi.end_transaction(1000); + printf("Read data %d from the bus.\n", val); + } - void my_application(client spi_master_if spi) { - uint8_t val; - printf("Doing one byte transfer. Sending 0x22.\n"); - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0x22); - spi.end_transaction(1000); - printf("Read data %d from the bus.\n", val); - } Here, ``begin_transaction`` selects the device ``0`` and asserts its slave select line. The application can then transfer data to and from @@ -353,9 +325,9 @@ Operations such as ``spi.transfer8`` will block until the operation is completed on the bus. More information on interfaces and tasks can be be found in the `XMOS Programming Guide `_. By default the -SPI synchronous master mode component does not use any logical cores of its +SPI synchronous master mode component does not use any xCORE threads of its own. It is a *distributed* task which means it will perform its -function on the logical core of the application task connected to +function on the xCORE thread of the application task connected to it (provided the application task is on the same tile). Synchronous master usage state machine @@ -367,10 +339,32 @@ If this sequence is not followed then the behaviour is undefined. .. _spi_master_usage_state_machine: -.. figure:: ../images/spi_master_sync_state.* - :width: 40% +.. uml:: + :width: 60% + :caption: SPI master use state machine (synchronous) + + @startuml + title SPI master use state machine (synchronous) + + [*] --> begin_transaction - SPI master use state machine + begin_transaction --> transfer8 + begin_transaction --> transfer32 + transfer8 --> transfer8 + transfer8 --> transfer32 + transfer8 --> end_transaction + transfer32 --> transfer8 + transfer32 --> transfer32 + transfer32 --> end_transaction + end_transaction --> begin_transaction + begin_transaction --> end_transaction + + begin_transaction --> [*] : shutdown + transfer8 --> [*] : shutdown + transfer32 --> [*] : shutdown + end_transaction --> [*] : shutdown + + @enduml |newpage| @@ -380,33 +374,37 @@ SPI master asynchronous operation The synchronous API will block your application until the bus operation is complete. In cases where the application cannot afford to -wait for this long the asynchronous API can be used. +wait for this long, the asynchronous API can be used. The asynchronous API offloads operations to another task. Calls are provided to initiate reads and writes and notifications are provided when the operation completes. This API requires more management in the application but can provide much more efficient operation. + It is particularly suitable for applications where the SPI bus is being used for continuous data transfer. Setting up an asynchronous SPI master component is done in the same -manner as the synchronous component:: +manner as the synchronous component. - out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss = XS1_PORT_1B; - out buffered port:22 p_sclk = XS1_PORT_1C; - out buffered port:32 p_mosi = XS1_PORT_1D; +.. code-block:: C - clock cb = XS1_CLKBLK_1; + out buffered port:32 p_miso = XS1_PORT_1A; + out port p_ss = XS1_PORT_1B; + out buffered port:22 p_sclk = XS1_PORT_1C; + out buffered port:32 p_mosi = XS1_PORT_1D; + + clock cb = XS1_CLKBLK_1; + + int main(void) { + spi_master_async_if i_spi[1]; + par { + spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + my_application(i_spi[0]); + } + return 0; + } - int main(void) { - spi_master_async_if i_spi[1]; - par { - spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - my_application(i_spi[0]); - } - return 0; - } |newpage| @@ -415,35 +413,38 @@ operations to the component. This is done by moving pointers to the SPI slave task to transfer and then retrieving pointers when the operation is complete. For example, the following code repeatedly calculates 100 bytes to send over the bus and handles 100 -bytes coming back from the slave:: - - void my_application(client spi_master_async_if spi) { - uint8_t outdata[100]; - uint8_t indata[100]; - uint8_t * movable buf_in = indata; - uint8_t * movable buf_out = outdata; - - // create and send initial data - fill_buffer_with_data(outdata); - spi.begin_transaction(0, 1000, SPI_MODE_0); - spi.init_transfer_array_8(move(buf_in), move(buf_out), 100); - while (1) { - select { - case spi.transfer_complete(): - spi.retrieve_transfer_buffers_8(buf_in, buf_out); - spi.end_transaction(); - - // Handle the data that has come in - handle_incoming_data(buf_in); - // Calculate the next set of data to go - fill_buffer_with_data(buf_out); - - spi.begin_transaction(0, 100, SPI_MODE_0); - spi.init_transfer_array_8(move(buf_in), move(buf_out)); - break; - } - } - } +bytes coming back from the slave. + +.. code-block:: C + + void my_application(client spi_master_async_if spi) { + uint8_t outdata[100]; + uint8_t indata[100]; + uint8_t * movable buf_in = indata; + uint8_t * movable buf_out = outdata; + + // create and send initial data + fill_buffer_with_data(outdata); + spi.begin_transaction(0, 1000, SPI_MODE_0); + spi.init_transfer_array_8(move(buf_in), move(buf_out), 100); + while (1) { + select { + case spi.transfer_complete(): + spi.retrieve_transfer_buffers_8(buf_in, buf_out); + spi.end_transaction(); + + // Handle the data that has come in + handle_incoming_data(buf_in); + // Calculate the next set of data to go + fill_buffer_with_data(buf_out); + + spi.begin_transaction(0, 100, SPI_MODE_0); + spi.init_transfer_array_8(move(buf_in), move(buf_out)); + break; + } + } + } + The SPI asynchronous task is combinable so can be run on a logical core with other tasks (including the application task it is connected to). @@ -466,25 +467,47 @@ Asynchronous master usage state machine ....................................... The function calls made on the SPI master asynchronous interface must follow the -sequence shown by the state machine in -:numref:`spi_master_usage_state_machine_async`. +sequence shown by the state machine in :numref:`spi_master_usage_state_machine_async`. If this sequence is not followed then the behaviour is undefined. .. _spi_master_usage_state_machine_async: -.. figure:: ../images/spi_master_async_state.* +.. uml:: + :caption: SPI master use state machine (asynchronous) :width: 60% - SPI master use state machine (asynchronous) + @startuml + title SPI master use state machine (asynchronous) + + [*] --> begin_transaction + begin_transaction --> init_transfer_array_8 + begin_transaction --> init_transfer_array_32 + init_transfer_array_8 --> transfer_complete + init_transfer_array_32 --> transfer_complete + transfer_complete --> retrieve_transfer_buffers_8 + transfer_complete --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_8 --> retrieve_transfer_buffers_8 + retrieve_transfer_buffers_8 --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_8 --> end_transaction + retrieve_transfer_buffers_32 --> retrieve_transfer_buffers_8 + retrieve_transfer_buffers_32 --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_32 --> end_transaction + end_transaction --> begin_transaction + begin_transaction --> end_transaction + end_transaction --> [*] : shutdown + + @enduml + + Master inter-transaction gap ============================ For both synchronous and asynchronous modes the ``end_transaction`` requires a -slave select deassert time. This parameter will provide a minimum deassert time between +slave select de-assert time. This parameter will provide a minimum de-assert time between two transaction on the same slave select. In the case where a ``begin_transaction`` asserting the slave select would violate the previous ``end_transaction`` then the -``begin_transaction`` will block until the slave select deassert time has been +``begin_transaction`` will block until the slave select de-assert time has been satisfied. |newpage| @@ -503,26 +526,30 @@ connection. SPI slave task diagram For example, the following code instantiates an SPI slave component -and connect to it:: - - out buffered port:32 p_miso = XS1_PORT_1E; - in port p_ss = XS1_PORT_1F; - in port p_sclk = XS1_PORT_1G; - in buffered port:32 p_mosi = XS1_PORT_1H; - clock cb = XS1_CLKBLK_1; - - int main(void) { - interface spi_slave_callback_if i_spi; - par { - spi_slave(i_spi, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, - SPI_TRANSFER_SIZE_8); - my_application(i_spi); - } - return 0; - } +and connect to it. + +.. code-block:: C + + out buffered port:32 p_miso = XS1_PORT_1E; + in port p_ss = XS1_PORT_1F; + in port p_sclk = XS1_PORT_1G; + in buffered port:32 p_mosi = XS1_PORT_1H; + clock cb = XS1_CLKBLK_1; + + int main(void) { + interface spi_slave_callback_if i_spi; + par { + spi_slave(i_spi, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, + SPI_TRANSFER_SIZE_8); + my_application(i_spi); + } + return 0; + } + When a slave component is instantiated the mode and transfer size -needs to be specified. +needs to be specified. If you wish to change mode or width, you can +shutdown the component and re-start it. |newpage| @@ -531,66 +558,214 @@ connection. This means it can "callback" to the application to respond to requests from the bus master. For example, the following code snippet shows part of an application that responds to SPI transactions where the first word is a command to read or write command and -subsequent transfers either provide or consume data:: - - while (1) { - uint32_t command = 0; - size_t index = 0; - select { - case spi.master_requires_data() -> uint32_t data: - if (command == 0) { - // Not got the command yet. This will be the - // first word of the transaction. - data = 0; - } else if (command == READ_COMMAND) { - data = get_read_data_item(index); - index++; - } else { - data = 0; - } - break; - case spi.master_supplied_data(uint32_t data, uint32_t valid_bits): - if (command == 0) { - command = data; - } else if (command == WRITE_COMMAND) { - handle_write_data_item(data, index); - index++; - } - break; - case spi.master_ends_transaction(): - // The master has de-asserted slave select. - command = 0; - index = 0; - break; - } - } +subsequent transfers either provide or consume data. + + +.. code-block:: C + + while (1) { + uint32_t command = 0; + size_t index = 0; + select { + case spi.master_requires_data() -> uint32_t data: + if (command == 0) { + // Not got the command yet. This will be the + // first word of the transaction. + data = 0; + } else if (command == READ_COMMAND) { + data = get_read_data_item(index); + index++; + } else { + data = 0; + } + break; + case spi.master_supplied_data(uint32_t data, uint32_t valid_bits): + if (command == 0) { + command = data; + } else if (command == WRITE_COMMAND) { + handle_write_data_item(data, index); + index++; + } + break; + case spi.master_ends_transaction(): + // The master has de-asserted slave select. + command = 0; + index = 0; + break; + } + } + .. note:: The time taken to handle the callbacks will determine the - timing requirements of the SPI slave. See application note AN00161 for - more details on different ways of working with the SPI slave component. + timing requirements of the SPI slave and so should be kept as short as possible. + See application note AN00161 for more details on different ways of working with the SPI slave component. |newpage| -******************** -Disabling data lines -******************** -The *MOSI* and *MISO* parameters of the ``spi_master`` task are -optional. So in the top-level ``par`` statement the function can be -called with ``null`` instead of a port e.g.:: +********************************* +SPI master timing characteristics +********************************* - spi_master(i_spi, 1, p_sclk, null, p_miso , p_ss, 1, clk_spi); +Synchronous SPI master clock speeds +=================================== -Similarly, the *MOSI* parameter of the ``spi_master_async`` task is -optional (but the *MISO* port must be provided). +The maximum speed that the SPI bus can be driven depends on whether a +clock block is used, the speed of the xCORE thread that the SPI code +is running on and where both the *MISO* and *MOSI* lines are used. The +timings can be seen in :numref:`spi_master_sync_timings`. + +.. _spi_master_sync_timings: + +.. list-table:: SPI master timings (synchronous) + :header-rows: 1 + + * - Clock blocks + - MOSI enabled + - MISO enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 0 + - 1 + - 0 + - 2500 + - 3500 + * - 0 + - 1 + - 1 + - 1200 + - 1300 + * - 1 + - 1 + - 0 + - 62500 + - 75000 + * - 1 + - 1 + - 1 + - 62500 + - 75000 + + +Asynchronous SPI master clock speeds +==================================== + +The asynchronous SPI master uses the same transport layer as the SPI master using a clock block +and so achieves similar performance. + +.. list-table:: SPI master timings (asynchronous) + :header-rows: 1 + + * - Clock blocks + - MISO enabled + - MOSI enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 1 + - x + - x + - 62500 + - 75000 + +.. _miso_port_timing: + +MISO port timing +================ + +Port timing is affected by chip pad and PCB delays. For the clock, slave-select and MOSI signals, all of the delays will be broadly matched. +This means port timing adjustment is normally not required even up to the fastest supported SPI clock rates. + +For the MISO signal, there will be a 'round trip delay' starting with the clock edge output and finishing at the xCORE's input port. +The presence of this delay will mean the xCORE may sample too early since data signal will arrive later. +It may be necessary to delay the sampling of the MISO pin to capture within the required window, particularly if the SPI clock is above 20 MHz. + +Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the :ref:`API section` `spi_master_sync_timings()` method which exposes the controls available for optimising setup and hold capture. + +For details on how to calculate and adjust round-trip port timing, please consult the `IO timings for xcore.ai `_ or `IO timings for xCORE200 `_ document. + +|newpage| + +******************************** +SPI slave timing characteristics +******************************** + +The xCORE thread running the SPI slave task will wait for the slave +select line to assert and then begin processing the transaction. At +this point it will call the ``master_requires_data`` callback to +application code. The time taken for the application to perform this +call will affect how long the xCORE thread has to resume processing +SPI data. This will affect the minimum allowable time between slave +select changing and data transfer from the master (*t1*). + +The user of the library will need to determine this time based on their application. + +After slave select is de-asserted the SPI slave task will call the +``master_ends_transaction`` callback. The time the application takes +to process this will affect the minimum allowable inter-transmission +gap between transactions (*t2*). The user of the library will also need to +determine this time based on their application. + +If the SPI slave task is combined will other tasks running on the same +xCORE thread then the other task may process an event delaying the +time it takes for the SPI slave task to react to events. This will add +these delays to the minimum times for both *t1* and *t2*. The library +user will need to take these into account in determining the timing +restrictions on the master. + +.. note:: + + The time taken to handle the callbacks will determine the + timing requirements of the SPI slave, and so must be kept as short as possible. + + +Throughput for SPI slave versus mode and MOSI usage is shown in the following table. + +.. list-table:: SPI slave timings + :header-rows: 1 + + * - SPI Mode + - MOSI enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 0 + - 0 + - 40000 + - 62500 + * - 1 + - 0 + - 40000 + - 62500 + * - 2 + - 0 + - 40000 + - 62500 + * - 3 + - 0 + - 40000 + - 62500 + * - 0 + - 1 + - 7000 + - 10000 + * - 1 + - 1 + - 7000 + - 10000 + * - 2 + - 1 + - 7000 + - 10000 + * - 3 + - 1 + - 7000 + - 10000 -The ``spi_slave`` task has an optional *MISO* parameter (but the -*MOSI* port must be supplied). |newpage| + ******** Examples ******** @@ -606,7 +781,7 @@ attention should be paid to the section `Installation of required third-party to `_. The application uses the `XMOS` build and dependency system, `xcommon-cmake `_. `xcommon-cmake` -is bundled with the `XMOS` XTC tools. +is bundled with the `XMOS` XTC tools. It runs on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_. To configure the build, run the following from an XTC command prompt: @@ -618,12 +793,20 @@ To configure the build, run the following from an XTC command prompt: Any missing dependencies will be downloaded by the build system at this configure step. + Finally, the application binaries can be built using ``xmake``: .. code-block:: console xmake -j -C build +Multiple build profiles are included and will be built as follows: + +* ASYNC - Example of using the `asynchronous` SPI master +* SYNC - Example of using the `synchronous` SPI master with clock-block (high performance) +* SYNC_NO_CLKBLK - Example of using the `synchronous` SPI master without clock-block (low performance / low resource usage) + + Running ======= @@ -637,7 +820,7 @@ command: As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: Sending SPI traffic - 2005400 + 5400 Done. @@ -693,6 +876,11 @@ Each of the SPI implementations use a number of `xcore` resources which include The number of pins is reduced if either of the data lines are not required. +|newpage| + + +.. _api_section: + ************* API Reference ************* @@ -727,23 +915,32 @@ Creating an SPI master instance .. doxygenfunction:: spi_master - .. doxygenfunction:: spi_master_async + |newpage| SPI master interface ..................... +.. c:namespace-push:: spi_master_if + .. doxygengroup:: spi_master_if +.. c:namespace-pop:: + + |newpage| SPI master asynchronous interface ................................. +.. c:namespace-push:: spi_master_async_if + .. doxygengroup:: spi_master_async_if +.. c:namespace-pop:: + |newpage| Slave API @@ -754,7 +951,7 @@ All SPI slave functions can be accessed via the ``spi.h`` header:: #include You will also have to add ``lib_spi`` to the -``LIB_DEPENDENT_MODULES`` field of your application CMakefile. +``APP_DEPENDENT_MODULES`` field of your application CMakefile. Creating an SPI slave instance .............................. @@ -770,8 +967,9 @@ Creating an SPI slave instance The SPI slave interface API ........................... -.. doxygengroup:: spi_slave_callback_if - +.. c:namespace-push:: slave +.. doxygengroup:: spi_slave_callback_if +.. c:namespace-pop:: diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index f872897..bc53599 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -13,7 +13,11 @@ in buffered port:32 p_miso = WIFI_MISO; out buffered port:32 p_mosi = WIFI_MOSI; out port p_rstn = WIFI_WUP_RST_N; -clock clk = on tile[0]: XS1_CLKBLK_1; +clock clk = on tile[0]: XS1_CLKBLK_1; + +#define RESET_DEASSERT 0x02 +#define POST_RESET_DELAY_MICROSECONDS 1000 +#define SPI_SPEED_KBPS 1000 /* This application function sends some traffic as SPI master using * the synchronous interface. It reads the config register (address 0) @@ -23,12 +27,12 @@ void app(client spi_master_if spi) uint8_t val; printstrln("Sending SPI traffic"); - p_rstn <: 0x2; //Take out of reset and wait - delay_microseconds(1000); + p_rstn <: RESET_DEASSERT; //Take out of reset and wait + delay_microseconds(POST_RESET_DELAY_MICROSECONDS); spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 - spi.begin_transaction(0, 1000, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); uint32_t reg_addr = 0; // Read reg 0 uint32_t read_cmd = 0x8000; // Read @@ -53,11 +57,11 @@ void async_app(client spi_master_async_if spi) printstrln("Sending aynch SPI traffic"); - p_rstn <: 0x2; //Take out of reset and wait - delay_microseconds(1000); + p_rstn <: RESET_DEASSERT; //Take out of reset and wait + delay_microseconds(POST_RESET_DELAY_MICROSECONDS); spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 - spi.begin_transaction(0, 1000, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); // Build command uint32_t reg_addr = 0; // Read reg 0 @@ -94,7 +98,7 @@ void async_app(client spi_master_async_if spi) break; } - spi.begin_transaction(0, 1000, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); uint32_t inbuffer32[1] = {0}; uint32_t outbuffer32[1] = {0}; // Dummy for read reg diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/AN00161_using_SPI_slave/src/main.xc index 9799e3f..d09315a 100644 --- a/examples/AN00161_using_SPI_slave/src/main.xc +++ b/examples/AN00161_using_SPI_slave/src/main.xc @@ -29,7 +29,9 @@ typedef interface reg_if { void set_reg(uint8_t regnum, uint8_t value); } reg_if; -#define NUM_REG 5 +#define SPI_SPEED_KBPS 1000 +#define NUM_REG 5 +#define SPI_SS_DELAY_10NS_TICKS 100 // 1 microsecond enum reg_state_t { WRITE_REG = 0, @@ -144,21 +146,21 @@ void app(client reg_if reg) { */ void tester(client spi_master_if spi) { - delay_microseconds(45); + delay_microseconds(45); // Wait for slave to init uint8_t val; - spi.begin_transaction(0, 100, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(READ_REG); // READ command spi.transfer8(0); // REGISTER 0 val = spi.transfer8(0); // DATA - spi.end_transaction(100); + spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); printstr("SPI MASTER: Read register 0: 0x"); printhexln(val); - spi.begin_transaction(0, 100, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(WRITE_REG); // WRITE command spi.transfer8(1); // REGISTER 1 spi.transfer8(0xac); // DATA - spi.end_transaction(100); + spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); printstr("SPI MASTER: Set register 1 to 0xAC\n"); } diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index e3f5154..2309a99 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -15,15 +15,9 @@ extern "C" { #define static_const_size_t static const size_t #define out_port out port #define in_port in port -#define async_master_shutdown shutdown -#define async_master_send_stop_bit send_stop_bit -#define async_master_read read -#define async_master_write write -#define slave_void slave void #define static_const_size_t static const size_t #define static_const_spi_mode_t static const spi_mode_t #define static_const_spi_transfer_type_t static const spi_transfer_type_t -#define static_const_spi_transfer_type_t static const spi_transfer_type_t #define uint32_t_movable_ptr_t uint32_t * movable #define uint8_t_movable_ptr_t uint8_t * movable #endif @@ -39,7 +33,7 @@ typedef enum spi_mode_t { /** This type contains timing settings for SS assert to clock delay and last * clock to SS de-assert delay. The unit is reference timer ticks which is - * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us, * over which the setting will overflow back to zero */ typedef struct spi_master_ss_clock_timing_t { uint32_t cs_to_clk_delay_ticks; @@ -47,11 +41,11 @@ typedef struct spi_master_ss_clock_timing_t { } spi_master_ss_clock_timing_t; -/** This type contains timing settings for capturing the MISO pin. +/** This type contains timing settings for capturing the MISO pin for SPI master. * When the SPI clock is above 20MHz it is usually necessary to delay the * sampling of the MISO pin. These settings can be coarse grained using * miso_sample_delay setting which increments in SPI half clocks or - * fine grained in units of core clock (eg. 600MHz) using the + * fine grained in units of core clock (eg. 600 MHz -> 1.66 ns) using the * miso_pad_delay setting. * * See the following document for details on xcore.ai port timing: @@ -62,447 +56,8 @@ typedef struct spi_master_miso_capture_timing_t { } spi_master_miso_capture_timing_t; -/** This interface allows clients to interact with SPI master task. */ -#ifndef __DOXYGEN__ -typedef interface spi_master_if { -#endif - - /** - * \addtogroup spi_master_if - * @{ - */ - - /** Begin a transaction. - * - * This will start a transaction on the bus. During a transaction, no - * other client to the SPI component can send or receive data. If - * another client is currently using the component then this call - * will block until the bus is released. - * - * \param device_index the index of the slave device to interact with. - * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ). When using the version - * with clockblock, the minimum speed is 100 kHz. - * \param mode The mode of spi transfers during this transaction. - */ - [[guarded]] - void begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode); - - /** End a transaction. - * - * This ends a transaction on the bus and releases the component to other - * clients. - * - * \param ss_deassert_time The minimum time in reference clock ticks between - * assertions of the selected slave select. This - * time will be ignored if the next transaction is - * to a different slave select. - */ - void end_transaction(unsigned ss_deassert_time); - - /** Transfer a byte over the spi bus. - * - * This function will transmit and receive 8 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first. - * - * \param data the data to transmit the MOSI port. - * - * \returns the data read in from the MISO port. - */ - uint8_t transfer8(uint8_t data); - - /** Transfer a 32-bit word over the spi bus. - * - * This function will transmit and receive 32 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first and - * most significant byte first (big endian) - * - * \param data the data to transmit the MOSI port. - * - * \returns the data read in from the MISO port. - */ - uint32_t transfer32(uint32_t data); - - /** Transfer an array of bytes over the SPI interface. - * - * This function will transmit and receive 32 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first in byte - * order in memory. Note that XMOS uses little endian and so 32b data etc. - * may need byteswap() first. - * - * \param data_out Reference to data to transmit the MOSI port. May be null - * if only a read is needed. - * \param data_in Reference to data to receive from the MISO port. May be - * null if only a write is needed. - * \param num_bytes Constant value of the size of the array to be transferred. - * - */ - void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static_const_size_t num_bytes); - - /** Sets the bit of port which is used for slave select (> 1b port type only) - * and only for spi_master. spi_master sets all bits in each port high/low - * - * The default value (if this is not called) is the bit number is equal to - * the device_index (device 0-> bit 0, device 1-> bit 1 etc.). - * - * \param device_index The index of the device for which the port bit is to be set. - * \param ss_port_bit Which bit number in the port to use for slave select. - */ - void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); - - /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz - * it is likely that some capture delays will need to be introduced to ensure - * setup and hold times are met. - * These settings only affect the fast SPI master which uses a clock block. - * - * See the following document for details on xcore.ai port timing: - * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html - * - * \param device_index The index of the device for which the MISO timing is to be set. - * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with - * the desired settings. - */ - void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); - - /** Configures the timing settings for SS assert to clock delay, and last - * clock to SS de-assert delay. The unit is reference timer ticks which is - * nominally 10 ns. The maximum setting is 65535 which equates to 655 us - * over which the setting will overflow back to zero. - * These settings only affect the fast SPI master which uses a clock block. - * - * \param device_index The index of the device for which the SS timing is to be set. - * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with - * the desired settings. - */ - void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); - - /** Shut down the SPI master interface server. - */ - void shutdown(void); - -#ifndef __DOXYGEN__ -} spi_master_if; -#endif - -/**@}*/ // END: addtogroup spi_master_if - -/** Task that implements the SPI proctocol in master mode that is - connected to a multiple slaves on the bus. - - Each slave must be connected to using the same SPI mode. - - You can access different slave devices over the interface connection - using the device_index parameter of the interface functions. - The task will allocate the device indices in the order of the supplied - array of slave select ports. - - \param i an array of interface connection to the - clients of the task. - \param num_clients the number of clients connected to the task. - \param clk a clock block used by the task. - \param sclk the SPI clock port. - \param mosi the SPI MOSI (master out, slave in) port. - \param miso the SPI MISO (master in, slave out) port. - \param p_ss A port connected to the slave select signals - of the slave. Multiple slaves may be supported - by specifying, for example, a 4-bit port. - Please specify mapping of bits to slaves using - i.set_ss_port_bit(). - \param num_slaves The number of slave devices on the bus. - \param clk A clock for the component to use. May be set - to null if low speed operation is acceptable. -*/ -[[distributable]] -void spi_master( - SERVER_INTERFACE(spi_master_if, i[num_clients]), - static_const_size_t num_clients, - out_buffered_port_32_t sclk, - NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), - NULLABLE_RESOURCE(in_buffered_port_32_t, miso), - out_port p_ss, - static_const_size_t num_slaves, - NULLABLE_RESOURCE(clock, clk)); - - -/** - * \addtogroup spi_master_async_if - * @{ - */ - -/** Asynchronous interface to an SPI component. - * - * This interface allows programs to offload SPI bus transfers to another - * task. An asynchronous notification occurs when the transfer is complete. - */ -#ifndef __DOXYGEN__ -typedef interface spi_master_async_if { -#endif - /** Begin a transaction. - * - * This will start a transaction on the bus. During a transaction, no - * other client to the SPI component can send or receive data. If - * another client is currently using the component then this call - * will block until the bus is released. - * - * \param device_index the index of the slave device to interact with. - * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ). The minimum speed is 100 kHz. - * \param mode The mode of spi transfers during this transaction - */ - void begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode); - - /** End a transaction. - * - * This ends a transaction on the bus and releases the component to other - * clients. - * - * \param ss_deassert_time The minimum time in reference clock ticks between - * assertions of the selected slave select. This - * time will be ignored if the next transaction is - * to a different slave select. - */ - void end_transaction(unsigned ss_deassert_time); - - /** Initialize Transfer an array of bytes over the spi bus. - * - * This function will initialize a transmit of 8 bit data - * over the SPI bus. - * - * \param inbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to fill with data. If this - * parameter is NULL then the incoming data of the transfer - * will be discarded. - * \param outbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to with data to transmit. - * If this parameter is NULL then the outgoing data of the - * transfer will consist of undefined values. - * \param nbytes The number of bytes to transfer over the bus. - */ - void init_transfer_array_8(uint8_t_movable_ptr_t inbuf, - uint8_t_movable_ptr_t outbuf, - size_t nbytes); - - /** Initialize Transfer an array of bytes over the spi bus. - * - * This function will initialize a transmit of 32 bit data - * over the SPI bus. - * - * \param inbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to fill with data. If this - * parameter is NULL then the incoming data of the transfer - * will be discarded. - * \param outbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to with data to transmit. - * If this parameter is NULL then the outgoing data of the - * transfer will consist of undefined values. - * \param nwords The number of words to transfer over the bus. - */ - void init_transfer_array_32(uint32_t_movable_ptr_t inbuf, - uint32_t_movable_ptr_t outbuf, - size_t nwords); - - /** Transfer completed notification. - * - * This notification occurs when a transfer is completed. - */ - [[notification]] - slave void transfer_complete(void); - - /** Retrieve transfer buffers. - * - * This function should be called after the transfer_complete() notification - * and will return the buffers given to the other task by - * init_transfer_array_8(). - * - * \param inbuf A movable pointer that will be set to the buffer - * pointer that was filled during the transfer. - * \param outbuf A movable pointer that will be set to the buffer - * pointer that was transmitted during the transfer. - */ - [[clears_notification]] - void retrieve_transfer_buffers_8(REFERENCE_PARAM(uint8_t_movable_ptr_t, inbuf), - REFERENCE_PARAM(uint8_t_movable_ptr_t, outbuf)); - - - /** Retrieve transfer buffers. - * - * This function should be called after the transfer_complete() notification - * and will return the buffers given to the other task by - * init_transfer_array_32(). - * - * \param inbuf A movable pointer that will be set to the buffer - * pointer that was filled during the transfer. - * \param outbuf A movable pointer that will be set to the buffer - * pointer that was transmitted during the transfer. - */ - [[clears_notification]] - void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), - REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); - - /** Sets the bit of port which is used for slave select (> 1b port type only) - * and only for spi_master. spi_master sets all bits in each port high/low - * - * The default value (if this is not called) is the bit number is equal to - * the device_index (0->0, 1->1 etc.). - * - * \param device_index The index of the device for which the port bit is to be set. - * \param ss_port_bit Which bit number in the port to use for slave select. - */ - void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); - - /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz - * it is likely that some capture delays will need to be introduced to ensure - * setup and hold times are met. - * - * See the following document for details on xcore.ai port timing: - * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html - * - * \param device_index The index of the device for which the MISO timing is to be set. - * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with - * the desired settings. - */ - void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); - - /** Configures the timing settings for SS assert to clock delay, and last - * clock to SS de-assert delay. The unit is reference timer ticks which is - * nominally 10 ns. The maximum setting is 65535 which equates to 655 us - * over which the setting will overflow back to zero. - * - * \param device_index The index of the device for which the SS timing is to be set. - * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with - * the desired settings. - */ - void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); - - /** Shut down the SPI master interface server. - */ - void shutdown(void); - - /**@}*/ // END: addtogroup spi_master_async_if - -#ifndef __DOXYGEN__ -} spi_master_async_if; -#endif - -/** SPI master component for asynchronous API. - * - * This component implements SPI and allows a client to connect using the - * asynchronous SPI master interface. - * - * \param i an array of interface connection to the - * clients of the task. - * \param num_clients the number of clients connected to the task. - * \param sclk the SPI clock port. - * \param mosi the SPI MOSI (master out, slave in) port. - * \param miso the SPI MISO (master in, slave out) port. - * \param p_ss a port of any width which outputs the slave select signals - * \param num_slaves The number of slave devices on the bus. - * \param clk a clock block for the component to use. - */ -[[combinable]] -void spi_master_async( - SERVER_INTERFACE(spi_master_async_if, i[num_clients]), - static_const_size_t num_clients, - out_buffered_port_32_t sclk, - NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), - in_buffered_port_32_t miso, - out_port p_ss, - static_const_size_t num_slaves, - clock clk); - -/**** SLAVE ****/ - -/** - * \addtogroup spi_slave_callback_if - * @{ - */ - -/** This interface allows clients to interact with SPI slave tasks by - * completing callbacks that show how to handle data. - */ -#ifndef __DOXYGEN__ -typedef interface spi_slave_callback_if { -#endif - - /** This callback will get called when the master de-asserts on the slave - * select line to end a transaction. - */ - void master_ends_transaction(void); - - /** This callback will get called when the master initiates a bus transfer - * or when more data is required during a transaction. - * The application must supply the data to transmit to the master. - * Data is transmitted with the least significant bit - * first. If the master completes the transaction before 8/32 bits ( - * depending on SPI_TRANSFER_SIZE_8 or SPI_TRANSFER_SIZE_32) are - * transferred and the remaining bits are discarded. - * - * \returns the 8-bit or 32-bit value to transmit. - */ - uint32_t master_requires_data(void); - - /** This callback will get called after a transfer. It will occur after - * every 8 bits transferred if the slave component is set to - * ``SPI_TRANSFER_SIZE_8``. If the component is set to - * ``SPI_TRANSFER_SIZE_32`` then it will occur if the master ends the - * transaction before 32 bits are transferred. - * - * \param datum the data received from the master. - * \param valid_bits the number of valid bits of data received from the master. - */ - void master_supplied_data(uint32_t datum, uint32_t valid_bits); - - /** Request shut down the SPI slave interface client. - */ - [[notification]] - slave void request_shutdown(void); - - /** Acknowledgment that the SPI slave task has been shutdown. - */ - [[clears_notification]] - [[guarded]] - void shutdown_complete(void); - -#ifndef __DOXYGEN__ -} spi_slave_callback_if; -#endif - -/**@}*/ // END: addtogroup spi_slave_callback_if - - -/** This type specifies the transfer size from the SPI slave component - to the application */ -typedef enum spi_transfer_type_t { - SPI_TRANSFER_SIZE_8, ///< Transfers should by 8-bit. - SPI_TRANSFER_SIZE_32 ///< Transfers should be 32-bit. -} spi_transfer_type_t; - -/** SPI slave component. - * - * This function implements an SPI slave bus. - * - * \param spi_i The interface to connect to the user of the component. - * The component acts as the client and will make callbacks to - * the application. - * \param p_sclk the SPI clock port. - * \param p_mosi the SPI MOSI (master out, slave in) port. - * \param p_miso the SPI MISO (master in, slave out) port. - * \param p_ss the SPI SS (slave select) port. - * \param clk clock to be used by the component. - * \param mode the SPI mode of the bus. - * \param transfer_type the type of transfer the slave will perform: either - * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. - */ - [[combinable]] - void spi_slave(CLIENT_INTERFACE(spi_slave_callback_if, spi_i), - in_port p_sclk, - in_buffered_port_32_t p_mosi, - NULLABLE_RESOURCE(out_buffered_port_32_t, p_miso), - in_port p_ss, - clock clk, - static_const_spi_mode_t mode, - static_const_spi_transfer_type_t transfer_type); +#include "spi_master_sync.h" +#include "spi_master_async.h" +#include "spi_slave.h" #endif // _spi_h_ diff --git a/lib_spi/api/spi_master_async.h b/lib_spi/api/spi_master_async.h new file mode 100644 index 0000000..fd06bc9 --- /dev/null +++ b/lib_spi/api/spi_master_async.h @@ -0,0 +1,195 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + + +/** +* @defgroup spi_master_async_if +* Methods for asynchronous SPI master interface. +* @{ +*/ + +/** Asynchronous interface to an SPI component. + * + * This interface allows programs to offload SPI bus transfers to another + * task. An asynchronous notification occurs when the transfer is complete. + */ +#ifndef __DOXYGEN__ +typedef interface spi_master_async_if { +#endif + /** @fn void master_async::begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode) + * Begin a transaction. + * + * This will start a transaction on the bus. During a transaction, no + * other client to the SPI component can send or receive data. If + * another client is currently using the component then this call + * will block until the bus is released. + * + * \param device_index The index of the slave device to interact with. + * \param speed_in_khz The speed that the SPI bus should run at during + * the transaction (in kHZ). The minimum speed is 100 kHz. + * \param mode The mode of spi transfers during this transaction + */ + void begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode); + + /** @fn void master_async::end_transaction(unsigned ss_deassert_time) + * End a transaction. + * + * This ends a transaction on the bus and releases the component to other + * clients. + * + * \param ss_deassert_time The minimum time in reference clock ticks between + * assertions of the selected slave select. This + * time will be ignored if the next transaction is + * to a different slave select. + */ + void end_transaction(unsigned ss_deassert_time); + + /** Initialize Transfer an array of bytes over the SPI bus. + * + * This function will initialize a transmit of 8 bit data + * over the SPI bus. + * + * \param inbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to fill with data. If this + * parameter is NULL then the incoming data of the transfer + * will be discarded. + * \param outbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to with data to transmit. + * If this parameter is NULL then the outgoing data of the + * transfer will consist of undefined values. + * \param nbytes The number of bytes to transfer over the bus. + */ + void init_transfer_array_8(uint8_t_movable_ptr_t inbuf, + uint8_t_movable_ptr_t outbuf, + size_t nbytes); + + /** Initialize Transfer an array of bytes over the SPI bus. + * + * This function will initialize a transmit of 32 bit data + * over the SPI bus. + * + * \param inbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to fill with data. If this + * parameter is NULL then the incoming data of the transfer + * will be discarded. + * \param outbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to with data to transmit. + * If this parameter is NULL then the outgoing data of the + * transfer will consist of undefined values. + * \param nwords The number of words to transfer over the bus. + */ + void init_transfer_array_32(uint32_t_movable_ptr_t inbuf, + uint32_t_movable_ptr_t outbuf, + size_t nwords); + + /** Transfer completed notification. + * + * This notification occurs when a transfer is completed. + */ + [[notification]] + slave void transfer_complete(void); + + /** Retrieve transfer buffers. + * + * This function should be called after the transfer_complete() notification + * and will return the buffers given to the other task by + * init_transfer_array_8(). + * + * \param inbuf A movable pointer that will be set to the buffer + * pointer that was filled during the transfer. + * \param outbuf A movable pointer that will be set to the buffer + * pointer that was transmitted during the transfer. + */ + [[clears_notification]] + void retrieve_transfer_buffers_8(REFERENCE_PARAM(uint8_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint8_t_movable_ptr_t, outbuf)); + + + /** Retrieve transfer buffers. + * + * This function should be called after the transfer_complete() notification + * and will return the buffers given to the other task by + * init_transfer_array_32(). + * + * \param inbuf A movable pointer that will be set to the buffer + * pointer that was filled during the transfer. + * \param outbuf A movable pointer that will be set to the buffer + * pointer that was transmitted during the transfer. + */ + [[clears_notification]] + void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is the bit number is equal to + * the device_index (0->0, 1->1 etc.). + * + * \param device_index The index of the device for which the port bit is to be set. + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); + + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); + + /** Shut down the SPI master interface server. Must be done after all transactions are complete + * to avoid leaving moveable pointers in the wrong place. + */ + void shutdown(void); + +/**@}*/ // end spi_master_async_if + +#ifndef __DOXYGEN__ +} spi_master_async_if; +#endif + +/** SPI master component for asynchronous API. + * + * This component implements SPI and allows a client to connect using the + * asynchronous SPI master interface. + * + * \param i an array of interface connection to the + * clients of the task. + * \param num_clients the number of clients connected to the task. + * \param sclk the SPI clock port. + * \param mosi the SPI MOSI (master out, slave in) port. + * \param miso the SPI MISO (master in, slave out) port. + * \param p_ss a port of any width which outputs the slave select signals + * \param num_slaves The number of slave devices on the bus. + * \param clk a clock block for the component to use. + */ +[[combinable]] +void spi_master_async( + SERVER_INTERFACE(spi_master_async_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + in_buffered_port_32_t miso, + out_port p_ss, + static_const_size_t num_slaves, + clock clk); diff --git a/lib_spi/api/spi_master_sync.h b/lib_spi/api/spi_master_sync.h new file mode 100644 index 0000000..0fa62ed --- /dev/null +++ b/lib_spi/api/spi_master_sync.h @@ -0,0 +1,167 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + + +/** This interface allows clients to interact with SPI master task. */ +#ifndef __DOXYGEN__ +typedef interface spi_master_if { +#endif + + /** + * @defgroup spi_master_if + * Methods for synchronous SPI master interface. + * @{ + */ + + /** Begin a transaction. + * + * This will start a transaction on the bus. During a transaction, no + * other client to the SPI component can send or receive data. If + * another client is currently using the component then this call + * will block until the bus is released. + * + * \param device_index The index of the slave device to interact with. + * \param speed_in_khz The speed that the SPI bus should run at during + * the transaction (in kHZ). When using the version + * with clockblock, the minimum speed is 100 kHz. + * \param mode The mode of spi transfers during this transaction. + */ + [[guarded]] + void begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode); + + /** @fn void master_sync::end_transaction(unsigned ss_deassert_time) + * End a transaction. + * + * This ends a transaction on the bus and releases the component to other + * clients. + * + * \param ss_deassert_time The minimum time in reference clock ticks between + * assertions of the selected slave select. This + * time will be ignored if the next transaction is + * to a different slave select. + */ + void end_transaction(unsigned ss_deassert_time); + + /** Transfer a byte over the SPI bus. + * + * This function will transmit and receive 8 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first. + * + * \param data The data to transmit the MOSI port. + * + * \returns The data read in from the MISO port. + */ + uint8_t transfer8(uint8_t data); + + /** Transfer a 32-bit word over the SPI bus. + * + * This function will transmit and receive 32 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first and + * most significant byte first (big endian) + * + * \param data The data to transmit the MOSI port. + * + * \returns The data read in from the MISO port. + */ + uint32_t transfer32(uint32_t data); + + /** Transfer an array of bytes over the SPI interface. + * + * This function will transmit and receive 32 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first in byte + * order in memory. Note that XMOS uses little endian and so 32b data etc. + * may need byteswap() first. + * + * \param data_out Reference to data to transmit the MOSI port. May be null + * if only a read is needed. + * \param data_in Reference to data to receive from the MISO port. May be + * null if only a write is needed. + * \param num_bytes Constant value of the size of the array to be transferred. + * + */ + void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static_const_size_t num_bytes); + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is the bit number is equal to + * the device_index (device 0-> bit 0, device 1-> bit 1 etc.). + * + * \param device_index The index of the device for which the port bit is to be set. + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); + + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * These settings only affect the fast SPI master which uses a clock block. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * These settings only affect the fast SPI master which uses a clock block. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); + + /** Shut down the SPI master interface server. + */ + void shutdown(void); + +#ifndef __DOXYGEN__ +} spi_master_if; +#endif + +/**@}*/ // end spi_master_if + +/** Task that implements the SPI proctocol in master mode that is + connected to a multiple slaves on the bus. + + Each slave must be connected to using the same SPI mode. + + You can access different slave devices over the interface connection + using the device_index parameter of the interface functions. + The task will allocate the device indices in the order of the supplied + array of slave select ports. + + \param i An array of interface connection to the + clients of the task. + \param num_clients The number of clients connected to the task. + \param clk a clock block used by the task. + \param sclk The SPI clock port. + \param mosi The SPI MOSI (master out, slave in) port. + \param miso The SPI MISO (master in, slave out) port. + \param p_ss A port connected to the slave select signals + of the slave. Multiple slaves may be supported + by specifying, for example, a 4-bit port. + Please specify mapping of bits to slaves using + i.set_ss_port_bit(). + \param num_slaves The number of slave devices on the bus. + \param clk A clock for the component to use. May be set + to null if low speed operation is acceptable. +*/ +[[distributable]] +void spi_master( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss, + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); diff --git a/lib_spi/api/spi_slave.h b/lib_spi/api/spi_slave.h new file mode 100644 index 0000000..b5da542 --- /dev/null +++ b/lib_spi/api/spi_slave.h @@ -0,0 +1,95 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + +/** +* @defgroup spi_slave_callback_if +* Methods for SPI slave interface. +* @{ +*/ + + +/** This interface allows clients to interact with SPI slave tasks by + * completing callbacks that show how to handle data. + */ +#ifndef __DOXYGEN__ +typedef interface spi_slave_callback_if { +#endif + + /** This callback will get called when the master de-asserts on the slave + * select line to end a transaction. + */ + void master_ends_transaction(void); + + /** This callback will get called when the master initiates a bus transfer + * or when more data is required during a transaction. + * The application must supply the data to transmit to the master. + * Data is transmitted with the least significant bit + * first. If the master completes the transaction before 8/32 bits ( + * depending on SPI_TRANSFER_SIZE_8 or SPI_TRANSFER_SIZE_32) are + * transferred and the remaining bits are discarded. + * + * \returns the 8-bit or 32-bit value to transmit. + */ + uint32_t master_requires_data(void); + + /** This callback will get called after a transfer. It will occur after + * every 8 bits transferred if the slave component is set to + * ``SPI_TRANSFER_SIZE_8``. If the component is set to + * ``SPI_TRANSFER_SIZE_32`` then it will occur if the master ends the + * transaction before 32 bits are transferred. + * + * \param datum the data received from the master. + * \param valid_bits the number of valid bits of data received from the master. + */ + void master_supplied_data(uint32_t datum, uint32_t valid_bits); + + /** Request shut down the SPI slave interface client. + */ + [[notification]] + slave void request_shutdown(void); + + /** Acknowledgment that the SPI slave task has been shutdown. + */ + [[clears_notification]] + [[guarded]] + void shutdown_complete(void); + +#ifndef __DOXYGEN__ +} spi_slave_callback_if; +#endif + +/**@}*/ // END: addtogroup spi_slave_callback_if + + +/** This type specifies the transfer size from the SPI slave component + to the application */ +typedef enum spi_transfer_type_t { + SPI_TRANSFER_SIZE_8, ///< Transfers should be 8-bit. + SPI_TRANSFER_SIZE_32 ///< Transfers should be 32-bit. +} spi_transfer_type_t; + +/** SPI slave component. + * + * This function implements an SPI slave bus. + * + * \param spi_i The interface to connect to the user of the component. + * The component acts as the client and will make callbacks to + * the application. + * \param p_sclk The SPI clock port. + * \param p_mosi The SPI MOSI (master out, slave in) port. + * \param p_miso The SPI MISO (master in, slave out) port. + * \param p_ss The SPI SS (slave select) port. + * \param clk Clock to be used by the component. + * \param mode The SPI mode of the bus. + * \param transfer_type The type of transfer the slave will perform: either + * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. + */ + [[combinable]] + void spi_slave(CLIENT_INTERFACE(spi_slave_callback_if, spi_i), + in_port p_sclk, + in_buffered_port_32_t p_mosi, + NULLABLE_RESOURCE(out_buffered_port_32_t, p_miso), + in_port p_ss, + clock clk, + static_const_spi_mode_t mode, + static_const_spi_transfer_type_t transfer_type); diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h index 03d6865..45b6e68 100644 --- a/lib_spi/src/spi_fwk.h +++ b/lib_spi/src/spi_fwk.h @@ -117,7 +117,7 @@ typedef struct { typedef struct { spi_master_t *spi_master_ctx; spi_master_source_clock_t source_clock; - int clock_divisor; + uint32_t clock_divisor; spi_master_sample_delay_t miso_sample_delay; uint32_t miso_pad_delay; uint32_t miso_initial_trigger_delay; diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c index f4c67e2..c21ab27 100644 --- a/lib_spi/src/spi_master.c +++ b/lib_spi/src/spi_master.c @@ -65,7 +65,7 @@ inline uint32_t load_data_out( uint32_t tmp; uint32_t word_out; - tmp = data_out[0] << 8; + tmp = (uint32_t)data_out[0] << 8; if (len > 1) { tmp |= data_out[1]; } diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index e785b6f..18ba614 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -22,7 +22,8 @@ typedef struct { uint32_t * movable buffer_rx; } transaction_request; -#define NBYTES_UNASSIGNED (-1) + +#define NBYTES_UNASSIGNED 0xffffffff // Can be made using mkmsk quickly [[combinable]] @@ -61,7 +62,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], unsafe{ spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)sclk, (port_t)mosi, (port_t)miso); - for(int i = 0; i < num_slaves; i++){ + for(size_t i = 0; i < num_slaves; i++){ device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; @@ -72,7 +73,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) uint8_t ss_port_bit[SPI_MAX_DEVICES]; - for(int i = 0; i < SPI_MAX_DEVICES; i++){ + for(size_t i = 0; i < SPI_MAX_DEVICES; i++){ ss_port_bit[i] = i; } @@ -139,11 +140,10 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], case i[int x].init_transfer_array_8(uint8_t * movable inbuf, uint8_t * movable outbuf, size_t nbytes) :{ - // if(dbg) printstr("init_transfer_array_8 "); if(dbg) printintln(nbytes); if(x != active_client){ // Just buffer it - unsigned index; - for(unsigned j=0;j bpt){ printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); - flush_print(); + delay_after_print(); _Exit(1); } diff --git a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc index b4cba01..ae4e99e 100644 --- a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc +++ b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc @@ -71,7 +71,7 @@ void app(server interface spi_slave_callback_if spi_i, } if(!miso_enabled){ printf("Error: master cannot require data when miso is not enabled\n"); - flush_print(); + delay_after_print(); _Exit(1); } break; @@ -83,7 +83,7 @@ void app(server interface spi_slave_callback_if spi_i, if(rx_data[rx_byte_no] != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", rx_data[rx_byte_no], d, num_bits); - flush_print(); + delay_after_print(); _Exit(1); } rx_byte_no++; @@ -101,7 +101,7 @@ void app(server interface spi_slave_callback_if spi_i, if(datum != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", d, datum, num_bits); - flush_print(); + delay_after_print(); _Exit(1); } } @@ -118,7 +118,7 @@ void app(server interface spi_slave_callback_if spi_i, int r = request_response(setup_strobe_port, setup_resp_port); if(r){ printf("Error: Master Rx error\n"); - flush_print(); + delay_after_print(); _Exit(1); } spi_i.request_shutdown(); @@ -130,12 +130,12 @@ void app(server interface spi_slave_callback_if spi_i, if(r){ printf("Error: Master Rx error\n"); - flush_print(); + delay_after_print(); _Exit(1); } if(num_bits > bpt){ printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); - flush_print(); + delay_after_print(); _Exit(1); } @@ -149,7 +149,7 @@ void app(server interface spi_slave_callback_if spi_i, case spi_i.shutdown_complete(): printf("Test completed\n"); - flush_print(); + delay_after_print(); return; break; } diff --git a/tests/spi_slave_tester_common/common.h b/tests/spi_slave_tester_common/common.h index 7caa8b6..0de6dc3 100644 --- a/tests/spi_slave_tester_common/common.h +++ b/tests/spi_slave_tester_common/common.h @@ -74,7 +74,7 @@ static int request_response( } -void flush_print(void){ +void delay_after_print(void){ delay_microseconds(10); } From 6afb730c3c7b796664544eb7d2f7e60ba535f574 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 11 Aug 2025 08:06:31 +0100 Subject: [PATCH 45/57] Fix https://github.com/xmos/lib_spi/issues/68 --- CHANGELOG.rst | 1 + examples/AN00160_using_SPI_master/src/main.xc | 17 ++-- lib_spi/src/spi_master_async.xc | 77 +++++++++++-------- lib_spi/src/spi_master_shared.xc | 1 - lib_spi/src/spi_master_sync.xc | 43 +++++++---- tests/spi_slave_checker.py | 2 +- 6 files changed, 82 insertions(+), 59 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 30174e0..24e79e7 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -13,6 +13,7 @@ lib_spi change log * FIXED: SPI slave MISO now goes Hi-Z when SS is deasserted * FIXED: SPI master (all) swapping of SPI modes 0 and 1 * FIXED: SPI slave swapping of SPI modes 0 and 1 + * FIXED: Passing NULL ptr to SPI asynch throws exception * FIXED: Non-functional tests * CHANGED: State diagrams and wavedrom now rendered by xmosdoc * REMOVED: Support for XS1 devices diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index bc53599..6a217a3 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -34,7 +34,7 @@ void app(client spi_master_if spi) spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); - uint32_t reg_addr = 0; // Read reg 0 + uint32_t reg_addr = 0; // Read reg 0 CONFIG register uint32_t read_cmd = 0x8000; // Read uint32_t num_16b_words = 2; // 32b uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command @@ -64,19 +64,16 @@ void async_app(client spi_master_async_if spi) spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); // Build command - uint32_t reg_addr = 0; // Read reg 0 + uint32_t reg_addr = 0; // Read reg 0 CONFIG register uint32_t read_cmd = 0x8000; uint32_t num_16b_words = 2; uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command - uint8_t inbuffer[2]; // Dummy for write command uint8_t outbuffer[2]; - - // memcpy(outbuffer, &command, sizeof(command)); outbuffer[0] = (command >> 8) & 0xff; // MSB first outbuffer[1] = command & 0xff; - uint8_t * movable inbuf = inbuffer; + uint8_t * movable inbuf = NULL; // We do not care about the read data for the cmd write uint8_t * movable outbuf = outbuffer; @@ -101,19 +98,19 @@ void async_app(client spi_master_async_if spi) spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); uint32_t inbuffer32[1] = {0}; - uint32_t outbuffer32[1] = {0}; // Dummy for read reg uint32_t * movable inbuf32 = inbuffer32; - uint32_t * movable outbuf32 = outbuffer32; + uint32_t * movable outbuf32 = NULL; // We do not care what is written during reg reads spi.init_transfer_array_32(move(inbuf32), - move(outbuf32), + null, 1); select { case spi.transfer_complete(): // Once the transfer is complete, we can retrieve the // buffers back into the inbuf and outbuf pointer variables - spi.retrieve_transfer_buffers_32(inbuf32, outbuf32); + spi.retrieve_transfer_buffers_32(inbuf32, + outbuf32); break; } diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc index 18ba614..6cc6055 100644 --- a/lib_spi/src/spi_master_async.xc +++ b/lib_spi/src/spi_master_async.xc @@ -9,17 +9,16 @@ #include "spi.h" #include "spi_master_shared.h" -#define SPI_MAX_DEVICES 32 //Used to size the array of which bit in the SS port maps to which device typedef struct { - unsigned client_id; - unsigned device_index; - unsigned speed_in_khz; - spi_mode_t mode; - size_t buffer_nbytes; - unsigned buffer_transfer_width; - uint32_t * movable buffer_tx; - uint32_t * movable buffer_rx; + unsigned client_id; + unsigned device_index; + unsigned speed_in_khz; + spi_mode_t mode; + size_t buffer_nbytes; + unsigned buffer_transfer_width; + uint32_t * movable buffer_tx; + uint32_t * movable buffer_rx; } transaction_request; @@ -37,7 +36,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], clock cb){ //These buffer are for the transaction requests - transaction_request tr_buffer[num_clients]; ///FIXME num_clients + transaction_request tr_buffer[num_clients]; unsigned tr_tail = 0; unsigned tr_fill = 0; @@ -72,8 +71,8 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], } // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) - uint8_t ss_port_bit[SPI_MAX_DEVICES]; - for(size_t i = 0; i < SPI_MAX_DEVICES; i++){ + uint8_t ss_port_bit[num_slaves]; + for(size_t i = 0; i < num_slaves; i++){ ss_port_bit[i] = i; } @@ -81,8 +80,8 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], p_ss <: 0xffffffff; // TMP MISO vals - uint8_t r8; - uint32_t r32; + uint8_t read8; + uint32_t read32; // Use as way of implementing a default case. Setting the default_case_time to the current time makes an event happen immediately // This is used for subsequent SPI transfers after the first during a transaction @@ -96,7 +95,7 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], //if doing a transaction then buffer this one if(currently_performing_a_transaction){ //Note, the tr_fill should never exceed num_clients if the calling protocol is respected - unsigned index = (tr_tail + tr_fill)%num_clients; //FIXME div? + unsigned index = (tr_tail + tr_fill)%num_clients; tr_buffer[index].device_index = device_index; tr_buffer[index].speed_in_khz = speed_in_khz; tr_buffer[index].mode = mode; @@ -166,7 +165,11 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], i[x].transfer_complete(); } else { buffer_transfer_width = 8; - spi_master_transfer(&spi_dev[active_device], (uint8_t*movable)&buffer_tx[0], &r8, 1); + uint8_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = ((uint8_t*movable)buffer_tx)[0]; + } + spi_master_transfer(&spi_dev[active_device], &mosi_data, &read8, 1); tmr :> default_case_time; default_case_enabled = 1; } @@ -202,9 +205,11 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], i[x].transfer_complete(); } else { buffer_transfer_width = 32; - uint32_t data = byterev(buffer_tx[0]); - // uint32_t data = buffer_tx[0]; - spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); + uint32_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = byterev(buffer_tx[0]); + } + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&mosi_data, (uint8_t*)&read32, 4); tmr :> default_case_time; default_case_enabled = 1; } @@ -214,31 +219,35 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], // This case handles the input from the last transfer case default_case_enabled => tmr when timerafter(default_case_time) :> int _:{ - //put the data into the correct array and send the next data if need be + //put the data into the correct array and send the next data if needs be if(buffer_transfer_width == 8){ - uint32_t data = byterev((uint32_t)r8<<24); // TODO - this is just r8!??? - ((uint8_t*movable)buffer_rx)[buffer_current_index] = (uint8_t)data; + uint32_t data = (uint32_t)read8; + if(buffer_rx != NULL){ + ((uint8_t*movable)buffer_rx)[buffer_current_index] = (uint8_t)data; + } buffer_current_index++; if((buffer_current_index*sizeof(uint8_t)) == buffer_nbytes){ default_case_enabled = 0; buffer_current_index = 0; i[active_client].transfer_complete(); } else { - spi_master_transfer(&spi_dev[active_device], &((uint8_t*movable)buffer_tx)[buffer_current_index], &r8, 1); + spi_master_transfer(&spi_dev[active_device], &((uint8_t*movable)buffer_tx)[buffer_current_index], &read8, 1); tmr :> default_case_time; default_case_enabled = 1; } } else { - uint32_t data = byterev(r32); - buffer_rx[buffer_current_index] = data; + uint32_t data = byterev(read32); + if(buffer_rx != NULL){ + buffer_rx[buffer_current_index] = data; + } buffer_current_index++; if((buffer_current_index*sizeof(uint32_t)) == buffer_nbytes){ default_case_enabled = 0; buffer_current_index = 0; i[active_client].transfer_complete(); } else { - uint32_t data = byterev(buffer_tx[buffer_current_index]); - spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); + uint32_t mosi_data = byterev(buffer_tx[buffer_current_index]); + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&mosi_data, (uint8_t*)&read32, 4); tmr :> default_case_time; default_case_enabled = 1; } @@ -297,13 +306,19 @@ void spi_master_async(server interface spi_master_async_if i[num_clients], buffer_rx = move(tr_buffer[index].buffer_rx); buffer_transfer_width = tr_buffer[index].buffer_transfer_width; if(buffer_transfer_width == 8){ - spi_master_transfer(&spi_dev[active_device], (uint8_t*movable)&buffer_tx[0], &r8, 1); + uint8_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = ((uint8_t*movable)buffer_tx)[0]; + } + spi_master_transfer(&spi_dev[active_device], &mosi_data, &read8, 1); tmr :> default_case_time; default_case_enabled = 1; } else { - uint32_t data = byterev(buffer_tx[0]); - // uint32_t data = buffer_tx[0]; - spi_master_transfer(&spi_dev[active_device], (uint8_t *)&data, (uint8_t*)&r32, 4); + uint32_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = byterev(buffer_tx[0]); + } + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&mosi_data, (uint8_t*)&read32, 4); tmr :> default_case_time; default_case_enabled = 1; } diff --git a/lib_spi/src/spi_master_shared.xc b/lib_spi/src/spi_master_shared.xc index 1a8e8b7..6abd528 100644 --- a/lib_spi/src/spi_master_shared.xc +++ b/lib_spi/src/spi_master_shared.xc @@ -4,7 +4,6 @@ #include #include -//TODO DEL these #include #include #include diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc index d0f70d7..1e0479b 100644 --- a/lib_spi/src/spi_master_sync.xc +++ b/lib_spi/src/spi_master_sync.xc @@ -16,9 +16,9 @@ [[distributable]] void spi_master(server interface spi_master_if i[num_clients], static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, + out buffered port:32 p_sclk, + out buffered port:32 ?p_mosi, + in buffered port:32 ?p_miso, out port p_ss, // Note only one SS port supported - individual bits in port may be used for different devices however static const size_t num_slaves, clock ?cb){ @@ -39,7 +39,7 @@ void spi_master(server interface spi_master_if i[num_clients], if(!isnull(cb)){ unsafe{ - spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)sclk, (port_t)mosi, (port_t)miso); + spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)p_sclk, (port_t)p_mosi, (port_t)p_miso); // Set default timings for(int i = 0; i < num_slaves; i++){ device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; @@ -50,9 +50,20 @@ void spi_master(server interface spi_master_if i[num_clients], } } } else { + unsafe{ + set_port_clock(p_ss, (clock)XS1_CLKBLK_REF); + set_port_clock(p_sclk, (clock)XS1_CLKBLK_REF); + if(!isnull(p_miso)){ + set_port_clock(p_miso, (clock)XS1_CLKBLK_REF); + } + if(!isnull(p_mosi)){ + set_port_clock(p_mosi, (clock)XS1_CLKBLK_REF); + } + } // Initial SS bit pattern - deselected p_ss <: 0xffffffff; sync(p_ss); + } int accepting_new_transactions = 1; @@ -81,8 +92,8 @@ void spi_master(server interface spi_master_if i[num_clients], if(isnull(cb)){ // Set the expected clock idle state on the clock port - partout(sclk, 1, cpol); - sync(sclk); + partout(p_sclk, 1, cpol); + sync(p_sclk); unsigned ss_port_val = ~(1 << ss_port_bit[current_device]); p_ss <: ss_port_val; @@ -133,7 +144,7 @@ void spi_master(server interface spi_master_if i[num_clients], case i[int x].transfer8(uint8_t data)-> uint8_t r :{ if(isnull(cb)){ - r = transfer8_sync_zero_clkblk(sclk, mosi, miso, data, clkblkless_period_ticks, cpol, cpha); + r = transfer8_sync_zero_clkblk(p_sclk, p_mosi, p_miso, data, clkblkless_period_ticks, cpol, cpha); } else { spi_master_transfer(&spi_dev[current_device], (uint8_t *)&data, &r, 1); } @@ -143,7 +154,7 @@ void spi_master(server interface spi_master_if i[num_clients], case i[int x].transfer32(uint32_t data) -> uint32_t r:{ if(isnull(cb)){ - r = transfer32_sync_zero_clkblk(sclk, mosi, miso, data, clkblkless_period_ticks, cpol, cpha); + r = transfer32_sync_zero_clkblk(p_sclk, p_mosi, p_miso, data, clkblkless_period_ticks, cpol, cpha); } else { // For 32b words, we need to swap to big endian (standard for SPI) from little endian (XMOS) // This means we transmit the MSByte first @@ -160,11 +171,11 @@ void spi_master(server interface spi_master_if i[num_clients], if(isnull(cb)){ for(int n = 0; n < num_bytes; n++){ uint8_t send; - if(!isnull(mosi)){ + if(!isnull(p_mosi)){ send = data_out[n]; } - uint8_t recv = transfer8_sync_zero_clkblk(sclk, mosi, miso, send, clkblkless_period_ticks, cpol, cpha); - if(!isnull(miso)){ + uint8_t recv = transfer8_sync_zero_clkblk(p_sclk, p_mosi, p_miso, send, clkblkless_period_ticks, cpol, cpha); + if(!isnull(p_miso)){ data_in[n] = recv; } } @@ -209,13 +220,13 @@ void spi_master(server interface spi_master_if i[num_clients], case i[int x].shutdown(void):{ p_ss <: 0xffffffff; // If using XC, then we need to enable/init which is how XC does it - if (!isnull(mosi)) { - set_port_use_on(mosi); + if (!isnull(p_mosi)) { + set_port_use_on(p_mosi); } - if (!isnull(miso)) { - set_port_use_on(miso); + if (!isnull(p_miso)) { + set_port_use_on(p_miso); } - set_port_use_on(sclk); + set_port_use_on(p_sclk); if(!isnull(cb)){ set_clock_on(cb); } diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py index 1390d8b..65f5479 100644 --- a/tests/spi_slave_checker.py +++ b/tests/spi_slave_checker.py @@ -11,7 +11,7 @@ class SPISlaveChecker(px.SimThread): """" - This simulator thread will act as SPI slave and check any transactions + This simulator thread will act as SPI master and check any transactions caused by the master. """ def __init__(self, From 447cd8ef00674643e59e4ef208bf995f2ce491e4 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 11 Aug 2025 16:30:48 +0100 Subject: [PATCH 46/57] Review 2 Doxy groups fix --- Jenkinsfile | 8 +++++++- examples/AN00160_using_SPI_master/src/main.xc | 6 ++++-- lib_spi/api/spi_master_async.h | 13 +++++++------ lib_spi/api/spi_slave.h | 15 ++++++++------- lib_spi/src/spi_master.c | 2 +- lib_spi/src/spi_master_shared.xc | 1 - tests/requirements.txt | 2 +- 7 files changed, 28 insertions(+), 19 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 4a6e559..6c1797a 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -110,7 +110,13 @@ pipeline { archiveSandbox(REPO_NAME) } } - } + + stage('🚀 Release') { + steps { + triggerRelease() + } + } + } // stages post { cleanup { xcoreCleanSandbox() diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index 6a217a3..ee07ff7 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -37,7 +37,8 @@ void app(client spi_master_if spi) uint32_t reg_addr = 0; // Read reg 0 CONFIG register uint32_t read_cmd = 0x8000; // Read uint32_t num_16b_words = 2; // 32b - uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command + uint32_t word_to_byte_shift = 2; + uint32_t command = read_cmd | num_16b_words | (reg_addr >> word_to_byte_shift); //Do read command val = spi.transfer8(command >> 8);// MSB first val = spi.transfer8(command & 0xff); uint32_t reg; @@ -67,7 +68,8 @@ void async_app(client spi_master_async_if spi) uint32_t reg_addr = 0; // Read reg 0 CONFIG register uint32_t read_cmd = 0x8000; uint32_t num_16b_words = 2; - uint32_t command = read_cmd | num_16b_words | (reg_addr << 12); //Do read command + uint32_t word_to_byte_shift = 2; + uint32_t command = read_cmd | num_16b_words | (reg_addr >> word_to_byte_shift); //Do read command uint8_t outbuffer[2]; outbuffer[0] = (command >> 8) & 0xff; // MSB first diff --git a/lib_spi/api/spi_master_async.h b/lib_spi/api/spi_master_async.h index fd06bc9..51c75ac 100644 --- a/lib_spi/api/spi_master_async.h +++ b/lib_spi/api/spi_master_async.h @@ -2,12 +2,6 @@ // This Software is subject to the terms of the XMOS Public Licence: Version 1. -/** -* @defgroup spi_master_async_if -* Methods for asynchronous SPI master interface. -* @{ -*/ - /** Asynchronous interface to an SPI component. * * This interface allows programs to offload SPI bus transfers to another @@ -16,6 +10,13 @@ #ifndef __DOXYGEN__ typedef interface spi_master_async_if { #endif + + /** + * @defgroup spi_master_async_if + * Methods for asynchronous SPI master interface. + * @{ + */ + /** @fn void master_async::begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode) * Begin a transaction. diff --git a/lib_spi/api/spi_slave.h b/lib_spi/api/spi_slave.h index b5da542..2a21a77 100644 --- a/lib_spi/api/spi_slave.h +++ b/lib_spi/api/spi_slave.h @@ -1,12 +1,6 @@ // Copyright 2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. -/** -* @defgroup spi_slave_callback_if -* Methods for SPI slave interface. -* @{ -*/ - /** This interface allows clients to interact with SPI slave tasks by * completing callbacks that show how to handle data. @@ -15,6 +9,13 @@ typedef interface spi_slave_callback_if { #endif + /** + * @defgroup spi_slave_callback_if + * Methods for SPI slave interface. + * @{ + */ + + /** This callback will get called when the master de-asserts on the slave * select line to end a transaction. */ @@ -58,7 +59,7 @@ typedef interface spi_slave_callback_if { } spi_slave_callback_if; #endif -/**@}*/ // END: addtogroup spi_slave_callback_if +/**@}*/ // end: spi_slave_callback_if /** This type specifies the transfer size from the SPI slave component diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c index c21ab27..81ef8a4 100644 --- a/lib_spi/src/spi_master.c +++ b/lib_spi/src/spi_master.c @@ -137,7 +137,7 @@ void spi_master_transfer( data_out += 2; } if (do_input) { - port_set_trigger_time(spi->miso_port, start_time + (tw - 2) + dev->miso_initial_trigger_delay); /* don't ask. port timing is weird */ + port_set_trigger_time(spi->miso_port, start_time + (tw - 2) + dev->miso_initial_trigger_delay); } clock_start(spi->clock_block); diff --git a/lib_spi/src/spi_master_shared.xc b/lib_spi/src/spi_master_shared.xc index 6abd528..5901a55 100644 --- a/lib_spi/src/spi_master_shared.xc +++ b/lib_spi/src/spi_master_shared.xc @@ -28,7 +28,6 @@ uint8_t transfer8_sync_zero_clkblk( for(unsigned i=0;i<8;i++){ partout_timed(sclk, 1, c, time); c>>=1; - //sclk @ time <:>> c; if(!isnull(mosi)){ partout_timed(mosi, 1, data>>7, time); diff --git a/tests/requirements.txt b/tests/requirements.txt index 11b9c0d..4effb9b 100644 --- a/tests/requirements.txt +++ b/tests/requirements.txt @@ -35,4 +35,4 @@ filelock==3.18.0 # of its own setup.py file, then this list must include an entry for that # setup.py file, e.g., '-e .' or '-e ./python' (without the quotes). --e ./../../test_support +-e git+ssh://git@github.com/xmos/test_support.git@v2.0.0#egg=test_support From 1f04248287aa59a24ddfa2d207f17a8d7e34daae Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 11 Aug 2025 17:05:02 +0100 Subject: [PATCH 47/57] Clarify register access in AN00160 --- Jenkinsfile | 8 -------- examples/AN00160_using_SPI_master/src/main.xc | 14 ++++++++------ 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 6c1797a..d18c99e 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,13 +4,6 @@ getApproval() -def clone_test_deps() { - dir("${WORKSPACE}") { - sh "git clone git@github.com:xmos/test_support" - sh "git -C test_support checkout v2.0.0" - } -} - pipeline { agent { label 'x86_64 && linux' @@ -85,7 +78,6 @@ pipeline { { steps { withTools(params.TOOLS_VERSION) { - clone_test_deps() dir("${REPO_NAME}/tests") { createVenv(reqFile: "requirements.txt") xcoreBuild() diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc index ee07ff7..40f1013 100644 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ b/examples/AN00160_using_SPI_master/src/main.xc @@ -35,12 +35,14 @@ void app(client spi_master_if spi) spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); uint32_t reg_addr = 0; // Read reg 0 CONFIG register - uint32_t read_cmd = 0x8000; // Read - uint32_t num_16b_words = 2; // 32b - uint32_t word_to_byte_shift = 2; - uint32_t command = read_cmd | num_16b_words | (reg_addr >> word_to_byte_shift); //Do read command + uint32_t read_cmd = 0x8000; + uint32_t num_16b_words = 2; + uint32_t reg_addr_shift = 12; + uint32_t command = read_cmd | num_16b_words | (reg_addr << reg_addr_shift); //Do read command + val = spi.transfer8(command >> 8);// MSB first val = spi.transfer8(command & 0xff); + uint32_t reg; reg = spi.transfer32(0x00); //Read result spi.end_transaction(0); @@ -68,8 +70,8 @@ void async_app(client spi_master_async_if spi) uint32_t reg_addr = 0; // Read reg 0 CONFIG register uint32_t read_cmd = 0x8000; uint32_t num_16b_words = 2; - uint32_t word_to_byte_shift = 2; - uint32_t command = read_cmd | num_16b_words | (reg_addr >> word_to_byte_shift); //Do read command + uint32_t reg_addr_shift = 12; + uint32_t command = read_cmd | num_16b_words | (reg_addr << reg_addr_shift); //Do read command uint8_t outbuffer[2]; outbuffer[0] = (command >> 8) & 0xff; // MSB first From 1482611c2b3fa90bfca102e33bd13f45ec07d278 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 13 Aug 2025 12:42:12 +0100 Subject: [PATCH 48/57] Initial doc convert for spi master example --- doc/exclude_patterns.inc | 4 +- .../spi_slave_example_block_diagram.png | Bin 0 -> 160270 bytes doc/rst/lib_spi.rst | 349 +++++++++++++++++- examples/AN00160_using_SPI_master/README.rst | 46 --- .../doc/rst/AN00160.rst | 266 ------------- .../doc/rst/images/block_diagram.odg | Bin 18906 -> 0 bytes .../doc/rst/images/block_diagram.pdf | Bin 26106 -> 0 bytes .../doc/rst/images/run_config_sim.png | Bin 121580 -> 0 bytes .../doc/rst/images/task_diag.odg | Bin 12566 -> 0 bytes .../doc/rst/images/task_diag.pdf | Bin 19961 -> 0 bytes .../doc/rst/images/vcd1.png | Bin 213200 -> 0 bytes .../doc/rst/images/vcd2.png | Bin 229593 -> 0 bytes examples/AN00161_using_SPI_slave/README.rst | 44 --- .../doc/rst/images/Makefile | 19 - .../doc/rst/images/run_config_trace.png | Bin 113567 -> 0 bytes .../AN00161_using_SPI_slave/doc/rst/xdoc.conf | 2 - examples/CMakeLists.txt | 6 +- .../CMakeLists.txt | 4 +- .../LICENSE.rst | 0 examples/app_spi_master/README.rst | 16 + .../config.xscope | 0 .../src/main.xc | 0 .../CMakeLists.txt | 0 .../LICENSE.rst | 0 examples/app_spi_slave/README.rst | 16 + .../config.xscope | 0 .../doc/rst/AN00161.rst | 0 .../doc/rst/images/.~lock.task_diag.odg# | 1 + .../doc/rst/images/Makefile | 0 .../doc/rst/images/block_diagram.odg | Bin .../doc/rst/images/block_diagram.pdf | Bin .../doc/rst/images/run_config_loopback.png | Bin .../doc/rst/images/run_config_sim.png | Bin .../doc/rst/images/run_config_trace.png | Bin .../doc/rst/images/task_diag.odg | Bin .../doc/rst/images/task_diag.pdf | Bin .../doc/rst/xdoc.conf | 0 .../src/main.xc | 0 38 files changed, 386 insertions(+), 387 deletions(-) create mode 100644 doc/images/spi_slave_example_block_diagram.png delete mode 100644 examples/AN00160_using_SPI_master/README.rst delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/AN00160.rst delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.odg delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.pdf delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/run_config_sim.png delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/task_diag.odg delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/task_diag.pdf delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/vcd1.png delete mode 100644 examples/AN00160_using_SPI_master/doc/rst/images/vcd2.png delete mode 100644 examples/AN00161_using_SPI_slave/README.rst delete mode 100644 examples/AN00161_using_SPI_slave/doc/rst/images/Makefile delete mode 100644 examples/AN00161_using_SPI_slave/doc/rst/images/run_config_trace.png delete mode 100644 examples/AN00161_using_SPI_slave/doc/rst/xdoc.conf rename examples/{AN00160_using_SPI_master => app_spi_master}/CMakeLists.txt (85%) rename examples/{AN00160_using_SPI_master => app_spi_master}/LICENSE.rst (100%) create mode 100644 examples/app_spi_master/README.rst rename examples/{AN00160_using_SPI_master => app_spi_master}/config.xscope (100%) rename examples/{AN00160_using_SPI_master => app_spi_master}/src/main.xc (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/CMakeLists.txt (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/LICENSE.rst (100%) create mode 100644 examples/app_spi_slave/README.rst rename examples/{AN00161_using_SPI_slave => app_spi_slave}/config.xscope (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/AN00161.rst (100%) create mode 100644 examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# rename examples/{AN00160_using_SPI_master => app_spi_slave}/doc/rst/images/Makefile (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/block_diagram.odg (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/block_diagram.pdf (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/run_config_loopback.png (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/run_config_sim.png (100%) rename examples/{AN00160_using_SPI_master => app_spi_slave}/doc/rst/images/run_config_trace.png (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/task_diag.odg (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/doc/rst/images/task_diag.pdf (100%) rename examples/{AN00160_using_SPI_master => app_spi_slave}/doc/rst/xdoc.conf (100%) rename examples/{AN00161_using_SPI_slave => app_spi_slave}/src/main.xc (100%) diff --git a/doc/exclude_patterns.inc b/doc/exclude_patterns.inc index d4616be..a36136a 100644 --- a/doc/exclude_patterns.inc +++ b/doc/exclude_patterns.inc @@ -6,5 +6,5 @@ #TODO remove these **index* **resource_usage_summary* -**AN00160* -**AN00161* +**app_spi_master* +**app_spi_slave* diff --git a/doc/images/spi_slave_example_block_diagram.png b/doc/images/spi_slave_example_block_diagram.png new file mode 100644 index 0000000000000000000000000000000000000000..8b17d425fb0f32a01622fb077c3a6e84d722ce27 GIT binary patch literal 160270 zcmbSz1z1#R`!~C;x}xZ+AkrWT(jp~|Al==d(k-0>Sb!ifNVn9`okNX^NJ$PbbcaKC z4e>pLpsw$Gz1RQx&R)CAc{t~ZyYJt9AKoa)iR0lC%k=j- zFv6o}+lGVl$15`t5d}#R5z1$FHpXU_MmRWkLm(mi5_LkP_4>;7N?N1~loQaTxu=8# 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zn~L>84SHFc!|v9H>odOL^F1}u6LFRVD2LU3&rUkYFMb?q>H5LAGlG-i+*mRUheJDy z$_Hk^ccrT6w-5nT@)C%}x+knaTxzL|fu6w$J}_dLzB|(Z)AS>j$&Eu(6zS5_LxHo^ zK<@!fnuwz_R!o6%fev~SGGLPluYlb!9y60+?UZR!frl`>^gFqIyCuNx^&1NCa7T4& z6#|8hQI;w$P)Z4=rN;PxF6YJqBp>(ao^Jd8wCm>O{+@BVNmQHOYS>Bv=uX@ZFrs46 tulg=%_`ZGylF%A*e|RUttR}d*za1T4lr+SFU>dHP*Y&OyUAg_>{{Xygri}mq literal 0 HcmV?d00001 diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 72b5119..65275e6 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -770,8 +770,41 @@ Throughput for SPI slave versus mode and MOSI usage is shown in the following ta Examples ******** +Various examples are provided to demonstrate the use of `lib_spi`. The SPI master examples are run on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_ using the WFM200 WiFi device as as simple SPI slave and the SPI slave example is run under the simulator with an instantiation of SPI master (from `lib_spi`) to act as the test device. + +SPI Master Example +================== + +The example uses the XMOS SPI library to perform some bus transactions as SPI master. + +The application consists of two tasks: + + - A task that drives the SPI bus + + - An application task that connects to the SPI task + +These tasks communicate via the use of xC interfaces. Note that for the SPI `synchronous` cases, even though +the SPI master and app are separate tasks, the compiler is able to `distribute` the SPI master so that the +application only uses a single hardware thread. + +:numref:`spi_master_example` shows the task and communication structure of the application. + +.. _spi_master_example: + +.. uml:: + :width: 60% + :caption: Task diagram of SPI master example + + @startuml + left to right direction + circle app + circle SPI_master + app --> SPI_master : spi_master_if\nor\nspi_master_async_if + @enduml + + Building -======== +........ The following section assumes that the `XMOS XTC tools `_ has been downloaded and installed (see `README` for required version). @@ -788,7 +821,7 @@ To configure the build, run the following from an XTC command prompt: .. code-block:: console cd examples - cd AN00160_using_SPI_master + cd app_spi_master cmake -G "Unix Makefiles" -B build Any missing dependencies will be downloaded by the build system at this configure step. @@ -806,11 +839,13 @@ Multiple build profiles are included and will be built as follows: * SYNC - Example of using the `synchronous` SPI master with clock-block (high performance) * SYNC_NO_CLKBLK - Example of using the `synchronous` SPI master without clock-block (low performance / low resource usage) +The build profiles are guarded by the defines `SPI_USE_ASYNC=1` for specifying the asynchronous SPI master and `CLKBLK=null` +when using the synchronous SPI master which determines which underlying SPI master transport to use. Running -======= +....... -To run the application return to the ``/examples/AN00160_using_SPI_master`` directory and run the following +To run the application return to the ``/examples/app_spi_master`` directory and run the following command: .. code-block:: console @@ -823,9 +858,315 @@ As application runs that reads a value from the SPI connected WiFi chip and prin 5400 Done. +The value `5400` represents bits 15 to 0 of the default value of the CONFIG register of the WFM200. + +Likewise, the following two commands should yield the same console output: + +.. code-block:: console + + xrun --xscope bin/SYNC/app_spi_master_SYNC_NO_CLKBLK.xe + xrun --xscope bin/SYNC/app_spi_master_ASYNC.xe + + +|newpage| + + +SPI Slave Example +================= + +The example in this application note uses the XMOS SPI library to +act as SPI slave. It maintains a register file which can be read and +written by the internal application *or* by the master on the SPI bus. +To show the bus functioning the demo application also has a tester +component connected to an SPI master bus which is connected (in +simulation) to the the SPI slave. This allows the generation of +traffic to show the the communication functioning. + +The application consists of five tasks: + + - A task that controls the SPI slave ports + + - A task that implements the register file handling calls from the + SPI slave component and the application + + - An application task that connects to the register file task + + - A task that controls the SPI master ports used for testing + + - A tester task that outputs commands to the SPI master task + +:numref:`spi_slave_example_block` shows the task and communication structure of the application. + +.. _spi_slave_example_block: + +.. figure:: ../images/spi_slave_example_block_diagram.png + :scale: 60% + :align: center + + Block diagram of SPI slave application example + + +These tasks communicate via the use of xC interfaces. :numref:`spi_slave_example_task` shows +the task and communication structure of the application. + +.. _spi_slave_example_task: + +.. uml:: + :width: 60% + :caption: Task diagram of SPI slave example + + @startuml + circle tester + circle SPI_master + circle app + circle reg_file + circle SPI_slave + + ' Force layout order with hidden links + SPI_master -[#transparent]-> SPI_slave + + ' Actual displayed nodes + tester -r-> SPI_master : spi_master_if + SPI_slave -r-> reg_file : spi_slave_callback_if + app -l-> reg_file : reg_if + @enduml + + +Declaring ports +............... + +The SPI library connects to external pins via xCORE ports. In +``main.xc`` these are declared as variables of type ``port`` at the +start of the file: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: p_sclk + :end-at: clock + +Note that there is also a clock declaration since the slave needs to +use an internal clock as well as ports inside the xCORE device. + +How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will +depend on the exact device being used. See the device datasheet for details. + +This application also has an SPI master interface on different ports: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: p_test_sclk + :end-at: p_test_mosi + +|newpage| + +The application main() function +............................... + +Below is the source code for the main function of this application, +which is taken from the source file ``main.xc`` + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: int main + +Looking at this in a more detail you can see the following: + + - The par functionality describes running five separate tasks in + parallel; three are for the main application and two are for the + tester. + + - The ``spi_slave`` task controls the application + SPI bus and takes the ports it will use as arguments. + + - The ``reg_file`` task is connected to the ``app`` task and the + ``spi_slave`` task. + + - The ``spi_slave`` task has an argument for the mode is expects - + in this case Mode 0 (see the SPI library user guide for more + details on modes) + + - The ``spi_slave`` task also has an argument + ``SPI_TRANSFER_SIZE_8`` which specifies the size of data chunk it + will use when making callbacks to the application. + + - The ``spi_master`` task controls the test SPI bus and takes + different ports to the SPI slave bus as arguments. For details on + using SPI master see application note AN00160. + + +The reg_file() function +....................... + +The ``reg_file`` function is the main logic of this example. It will +respond to calls from the application and the SPI slave bus whilst +maintaining a set of register values. + +The function is marked as ``[[distributable]]`` which means it only +responds to calls from other tasks. The main reason for this is so +that the ``reg_file`` task itself does not need a logical core of its +own it can use the logical core of the task that calls it. See the +XMOS programming guide for details of distributable tasks. + +The function takes two arguments, the interface connections to the +application task and the SPI slave task: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: [[distributable]] + :end-at: { + +The ``reg_if`` interface has been defined in ``main.xc`` earlier. It +defines the functions that the app may call in the ``reg_file`` tasks: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: interface + :end-at: } + +In this case we have two functions - one for reading a register value +and one for writing a register value. + +The ``reg_file`` function first declares its state - an array to hold +register value, a state variable to hold what stage of an SPI +transaction it is in and the currently addressed register by the SPI bus. + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: This array holds + :end-at: addr = 0 + +The state variable is just an integer from the following ``enum`` type +defined earlier in the file: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: enum + :end-at: } + +The implemented protocol on the SPI bus is as follows: + + * The master will start a transaction (assert slave select) + * It will then send a byte of either a 0 for a write or a + 1 for a read. + * It will then send the address of the register to read/write + * It will then send or receive the value of the register |newpage| +To implement the protocol logic the ``reg_file`` tasks must continually react +to events from the SPI slave tasks keeping track of its state, +updating registers and supplying the correct outputs. This is done via +a ``while (1)`` loop with an xC ``select`` statement inside it. A +``select`` statement will wait and then react to various events or +calls from different tasks - see the XMOS programming guide for more details. + +The following cases in the main loop of the function handle this: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: while (1) + :end-before: respond to the application + +We can see that the slave will always send the value of the currently +addressed register on every data transfer (this is allowable in the +described protocol). + +When the SPI master supplies some data to the slave then what happens +depends on the current state - either the state variable is updated, +the currently addressed register is updated or a register value is +updated. This state machine will implement the previously described +protocol. + +|newpage| + +The main select also needs to react to request from the +application. The following cases implement this: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: respond to the application + :end-before: } + +The app() function +.................. + +The ``app`` task represents a sample application tasks that uses the +register file. In this demo, it doesn't do much - it simple sets one +register and repeatedly polls the value of another register and prints +out its value: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: app( + :end-before: tester + +Note that the ``debug_printf`` function comes from the +``debug_print.h`` header supplied by ``lib_logging``. It is a low +memory debug printing function that will print out messages to the +console in the xTIMEcomposer (either using JTAG or xSCOPE to +communicate to the host via the debug adaptor). + +The tester() function +..................... + +The tester function will send some test data to the SPI master +bus. It does this using the SPI master interface to communicate with +the SPI master task: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :start-at: tester( + :end-before: main + + + +Building +........ + +The following section assumes that the `XMOS XTC tools `_ has +been downloaded and installed (see `README` for required version). + +Installation instructions can be found `here `_. Particular +attention should be paid to the section `Installation of required third-party tools +`_. + +The application uses the `XMOS` build and dependency system, `xcommon-cmake `_. `xcommon-cmake` +is bundled with the `XMOS` XTC tools. It runs on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_. + +To configure the build, run the following from an XTC command prompt: + +.. code-block:: console + + cd examples + cd app_spi_slave + cmake -G "Unix Makefiles" -B build + +Any missing dependencies will be downloaded by the build system at this configure step. + + +Finally, the application binaries can be built using ``xmake``: + +.. code-block:: console + + xmake -j -C build + + +Running +....... + +To run the application return to the ``/examples/app_spi_slave`` directory and run the following +command: + +.. code-block:: console + + xrun --xscope bin/SYNC/app_spi_slave.xe + +As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: + + Sending SPI traffic + 5400 + Done. + +The value `5400` represents bits 15 to 0 of the default value of the CONFIG register of the WFM200. + +Likewise, the following two commands should yield the same console output: + +.. code-block:: console + + xrun --xscope bin/SYNC/app_spi_master_SYNC_NO_CLKBLK.xe + xrun --xscope bin/SYNC/app_spi_master_ASYNC.xe + + +|newpage| ************** Resource Usage diff --git a/examples/AN00160_using_SPI_master/README.rst b/examples/AN00160_using_SPI_master/README.rst deleted file mode 100644 index 39f206a..0000000 --- a/examples/AN00160_using_SPI_master/README.rst +++ /dev/null @@ -1,46 +0,0 @@ -How to use the SPI library as SPI master -======================================== - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE drive an SPI bus as SPI master. The application is the simplest -example of setting up the library and performing a couple of -transactions. The code can then be run in simulation to see the -outputted waveforms. - -The note covers both the synchronous and asynchronous use of the SPI -master components provided from the library. - -Required tools and libraries -............................ - -* xTIMEcomposer Tools - Version 14.0 -* XMOS SPI library - Version 3.0.0 - -Required hardware -................. - -This application note is designed to run in simulation so requires no -XMOS hardware. - -Prerequisites -............. - - - This document assumes familiarity with the XMOS xCORE - architecture, the SPI bus protocol, the XMOS tool chain and the xC - language. Documentation related to these aspects which are not - specific to this application note are linked to in the references appendix. - - - For descriptions of XMOS related terms found in this document - please see the XMOS Glossary [#]_. - - - For the full API listing of the XMOS SPI Device Library please see - the library user guide [#]_. - - .. [#] http://www.xmos.com/published/glossary - - .. [#] http://www.xmos.com/support/libraries/lib_spi - - diff --git a/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst b/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst deleted file mode 100644 index 6708d25..0000000 --- a/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst +++ /dev/null @@ -1,266 +0,0 @@ -.. include:: ../../README.rst - -|newpage| - -Overview --------- - -Introduction -............ - -The XMOS SPI library is a library that provides -software defined, industry-standard, SPI (serial peripheral interface) -components that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. - -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. - -The library includes features such as SPI master and SPI slave modes, -supported speeds of up to 100 Mbit, multiple slave device support and -support for all configurations of clock polarity and phase. - -Block diagram -............. - -.. figure:: images/block_diagram.* - :scale: 100% - :align: center - - Block diagram of SPI master application example - -SPI master example ------------------- - -The example in this application note uses the XMOS SPI library to -perform some bus transactions as SPI master. The binary is then run in -simulation so the user can see the waveform output in the VCD tracing -perspective in the xTIMEcomposer. - -The application consists of two tasks: - - - A task that drives the SPI bus - - - An application task that connects to the SPI task - -These tasks communicate via the use of xC interfaces. - -The following diagram shows the task and communication structure of -the application. - -.. figure:: images/task_diag.* - - Task diagram of SPI master example - -Makefile additions for this example -................................... - -To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: - - USED_MODULES = ... lib_spi - -You can then access the SPI functions in your source code via the -spi.h header file:: - - #include - -Declaring ports -............... - -The SPI library connects to external pins via xCORE ports. In -``main.xc`` these are declared as variables of type ``port`` at the -start of the file: - -.. literalinclude:: main.xc - :start-on: p_sclk - :end-on: p_mosi - -Note that the slave select declaration (``p_ss``) is an array of -ports. This is what the SPI library expects since there may be many -slave select lines for multiple devices. - -How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will -depend on the exact device being used. See the device datasheet for details. - -|newpage| - -The application main() function -............................... - -Below is the source code for the main function of this application, -which is taken from the source file ``main.xc`` - -.. literalinclude:: main.xc - :start-on: int main - :end-before: Uncomment - -Looking at this in more detail you can see the following: - - - The par functionality describes running two separate tasks in parallel - - - The ``spi_master`` task drives the SPI bus and takes the ports it - will use as arguments. - - - The ``app`` task communicates to the ``spi_master`` task via the - shared interface argument ``i_spi``. This is an array since the - SPI master task could connect to many other tasks in parallel. - -The app() function -.................. - -The ``app`` function uses its interface connection to the SPI master -task to perform SPI transactions. It performs two transactions (each -transaction will assert the slave select line, transfer some data and then -de-assert the slave select line). The functions in the SPI master -interface can be found in the SPI library user guide. - -.. literalinclude:: main.xc - :start-on: void app - :end-before: This application function - -Note that when ``begin_transaction`` is called the device is selected -by the first argument. In this case it is ``0``, so the zero-th -element of the ``p_ss`` array will be used for the slave select -line. This is the method that is used to communiate with multiple SPI -slave devices. The speed and mode of the SPI protocol is also set at -in the ``begin_transaction`` call. - -|newpage| - -Setting up the run configuration for the application -.................................................... - -To run the application binary in the simulator, first the application -must be built by pressing the :menuitem:`Build` button in the -xTIMEcomposer. This will create the ``AN00160_using_SPI_master.xe`` -binary in the ``bin`` folder of the project. The xTIMEcomposer may -have to import the SPI library if you do not already have it in your -workspace; this will occur automatically on build. - -Then a *Run Configuration* needs to be set up. This can be done by -selecting the :menuitem:`Run,Run Configurations..` menu. You can -create a new run configuration by right clicking on the -:menuitem:`xCORE application` group in the left hand pane and -:menuitem:`new`. However, in this example a run configuration has -already been created for you. - -Looking at this run configuration, you can see the simulator has been -selected under :menuitem:`Device Options:`: - -.. image:: images/run_config_sim.png - :width: 70% - :align: center - -|newpage| - -In the :menuitem:`Simulator` tab of the run configuration. The -:menuitem:`Enable signal tracing` check box has been enabled and a -:menuitem:`Tile Trace Option` has been added to trace the ports on -tile[0]: - -.. image:: images/run_config_trace.png - :width: 70% - :align: center - -|newpage| - -Running the application -....................... - -By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit -Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` -button in the run configuration dialog, the program -will run. In the console window you will get this output:: - - Sending SPI traffic - Done. - -After this it will immediately swith the the VCD tracing perspective -(since signal tracing was enabled in the run configuration). In this -perspective you can drag ports from within the tree in the -:menuitem:`Signals` pane on the left hand side to the -:menuitem:`Waves` pane on the right: - -.. image:: images/vcd1.png - :width: 70% - :align: center - -By dragging in the four ports used by the application (1I, 1J, 1K and -1L) you can see that the application has driven the correct SPI -signal. Note that you need to expand each port and drag in just the -port value, the other traces (such as ``tile[0]_XS1_PORT_1J_inuse``) -just show the internal port state and are not so interesting here. - -.. image:: images/vcd2.png - :width: 70% - :align: center - -|newpage| - -Using the asynchronous interface -................................ - -There is an alternative ``main()`` function in the program to try: - -.. literalinclude:: main.xc - :start-on: Uncomment - -By uncommenting this main (and commenting out the original main) the -application will use the ``spi_master_async`` task instead of the -synchronous ``spi_master`` task. This task still drives the SPI bus -but runs on a separate logical core and will drive the bus in parallel -to your application. This way your application can overlap processing -with communication. - -The ``async_app()`` function performs the same function as the -``app()`` function using the asynchronous interface. The big -difference is that pointers have to be passed to the SPI task that -point to the buffers to send from/receive into. These need to be -*movable* pointers (see the xC programing guide for more information) -that can be passed to another task: - -.. literalinclude:: main.xc - :start-on: async_app - :end-on: outbuf - -|newpage| - -Once the pointers have been initialized they can be passed and later -retrieved from the SPI master task: - -.. literalinclude:: main.xc - :start-on: traffic (async) - :end-on: end_transaction - -|appendix| -|newpage| - -References ----------- - -.. nopoints:: - - * XMOS Tools User Guide - - http://www.xmos.com/published/xtimecomposer-user-guide - - * XMOS xCORE Programming Guide - - http://www.xmos.com/published/xmos-programming-guide - - * XMOS SPI Library - - http://www.xmos.com/support/libraries/lib_spi - -|newpage| - -Full source code listing ------------------------- - -.. literalinclude:: main.xc - :largelisting: - -|newpage| - diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.odg 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The application provides a register -file that can be read and written by the internal application and by -the SPI master using a simple command set. The code is -run in simulation with an SPI master output looped-back onto the SPI -slave input to show the bus functioning. - -Required tools and libraries -............................ - -* xTIMEcomposer Tools - Version 14.0 -* XMOS SPI library - Version 3.0.0 - -Required hardware -................. - -This application note is designed to run in simulation so requires no -XMOS hardware. - -Prerequisites -............. - - - This document assumes familiarity with the XMOS xCORE - architecture, the SPI bus protocol, the XMOS tool chain and the xC - language. Documentation related to these aspects which are not - specific to this application note are linked to in the references appendix. - - - For descriptions of XMOS related terms found in this document - please see the XMOS Glossary [#]_. - - - For the full API listing of the XMOS SPI Device Library please see - the library user guide [#]_. - - .. [#] http://www.xmos.com/published/glossary - - .. [#] http://www.xmos.com/support/libraries/lib_spi - - diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile b/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile deleted file mode 100644 index fddcef8..0000000 --- a/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -ODGS = $(wildcard *.odg) -PDFS = $(ODGS:.odg=.pdf) - -all: $(PDFS) - @echo PDFs created - -_uncropped: - mkdir _uncropped - -_uncropped/%.pdf: %.odg | _uncropped - soffice -env:UserInstallation=file:///home/$(USER)/.libreoffice-alt --headless --convert-to pdf $< --outdir _uncropped - -%.pdf: _uncropped/%.pdf - pdfcrop $< $@ - -clean: - -rm $(PDFS) - -rm _uncropped/*.pdf - -rmdir _uncropped diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/run_config_trace.png b/examples/AN00161_using_SPI_slave/doc/rst/images/run_config_trace.png deleted file mode 100644 index e474960ebb7719cc16857960e03c4e21caf7a480..0000000000000000000000000000000000000000 GIT binary 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The application is the simplest +example of setting up the library and performing a couple of +transactions. + +The note covers both the synchronous and asynchronous use of the SPI +master components provided from the library. + +Please refer to the main `lib_spi` documentation examples section +for setup, building and running of this example. \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master/config.xscope b/examples/app_spi_master/config.xscope similarity index 100% rename from examples/AN00160_using_SPI_master/config.xscope rename to examples/app_spi_master/config.xscope diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/app_spi_master/src/main.xc similarity index 100% rename from examples/AN00160_using_SPI_master/src/main.xc rename to examples/app_spi_master/src/main.xc diff --git a/examples/AN00161_using_SPI_slave/CMakeLists.txt b/examples/app_spi_slave/CMakeLists.txt similarity index 100% rename from examples/AN00161_using_SPI_slave/CMakeLists.txt rename to examples/app_spi_slave/CMakeLists.txt diff --git a/examples/AN00161_using_SPI_slave/LICENSE.rst b/examples/app_spi_slave/LICENSE.rst similarity index 100% rename from examples/AN00161_using_SPI_slave/LICENSE.rst rename to examples/app_spi_slave/LICENSE.rst diff --git a/examples/app_spi_slave/README.rst b/examples/app_spi_slave/README.rst new file mode 100644 index 0000000..6f35c1d --- /dev/null +++ b/examples/app_spi_slave/README.rst @@ -0,0 +1,16 @@ +How to use the SPI library as SPI master +======================================== + +Summary +------- + +This application note shows how to use the SPI library to make the +xCORE drive an SPI bus as SPI master. The application is the simplest +example of setting up the library and performing a couple of +transactions. + +The note covers both the synchronous and asynchronous use of the SPI +master components provided from the library. + +Please refer to the main `lib_spi` documentation examples section +for setup, building and running of this example. \ No newline at end of file diff --git a/examples/AN00161_using_SPI_slave/config.xscope b/examples/app_spi_slave/config.xscope similarity index 100% rename from examples/AN00161_using_SPI_slave/config.xscope rename to examples/app_spi_slave/config.xscope diff --git a/examples/AN00161_using_SPI_slave/doc/rst/AN00161.rst b/examples/app_spi_slave/doc/rst/AN00161.rst similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/AN00161.rst rename to examples/app_spi_slave/doc/rst/AN00161.rst diff --git a/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# b/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# new file mode 100644 index 0000000..d51b26f --- /dev/null +++ b/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# @@ -0,0 +1 @@ +,ed,ed-zenbook,13.08.2025 11:38,file:///home/ed/.config/libreoffice/4; \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/Makefile b/examples/app_spi_slave/doc/rst/images/Makefile similarity index 100% rename from examples/AN00160_using_SPI_master/doc/rst/images/Makefile rename to examples/app_spi_slave/doc/rst/images/Makefile diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/block_diagram.odg b/examples/app_spi_slave/doc/rst/images/block_diagram.odg similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/block_diagram.odg rename to examples/app_spi_slave/doc/rst/images/block_diagram.odg diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/block_diagram.pdf b/examples/app_spi_slave/doc/rst/images/block_diagram.pdf similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/block_diagram.pdf rename to examples/app_spi_slave/doc/rst/images/block_diagram.pdf diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/run_config_loopback.png b/examples/app_spi_slave/doc/rst/images/run_config_loopback.png similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/run_config_loopback.png rename to examples/app_spi_slave/doc/rst/images/run_config_loopback.png diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/run_config_sim.png b/examples/app_spi_slave/doc/rst/images/run_config_sim.png similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/run_config_sim.png rename to examples/app_spi_slave/doc/rst/images/run_config_sim.png diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/run_config_trace.png b/examples/app_spi_slave/doc/rst/images/run_config_trace.png similarity index 100% rename from examples/AN00160_using_SPI_master/doc/rst/images/run_config_trace.png rename to examples/app_spi_slave/doc/rst/images/run_config_trace.png diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.odg b/examples/app_spi_slave/doc/rst/images/task_diag.odg similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.odg rename to examples/app_spi_slave/doc/rst/images/task_diag.odg diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.pdf b/examples/app_spi_slave/doc/rst/images/task_diag.pdf similarity index 100% rename from examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.pdf rename to examples/app_spi_slave/doc/rst/images/task_diag.pdf diff --git a/examples/AN00160_using_SPI_master/doc/rst/xdoc.conf b/examples/app_spi_slave/doc/rst/xdoc.conf similarity index 100% rename from examples/AN00160_using_SPI_master/doc/rst/xdoc.conf rename to examples/app_spi_slave/doc/rst/xdoc.conf diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/app_spi_slave/src/main.xc similarity index 100% rename from examples/AN00161_using_SPI_slave/src/main.xc rename to examples/app_spi_slave/src/main.xc From 15800dfaeb1235395c5dcfb99956f2fa284a6703 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 13 Aug 2025 17:16:03 +0100 Subject: [PATCH 49/57] Update spi_slave example FIx changelog --- .gitignore | 1 + CHANGELOG.rst | 3 + doc/images/spi_slave_simulation.png | Bin 0 -> 78982 bytes doc/rst/lib_spi.rst | 227 ++++++++--- examples/app_spi_master/CMakeLists.txt | 2 +- examples/app_spi_master/README.rst | 2 +- examples/app_spi_master/src/main.xc | 6 +- examples/app_spi_slave/CMakeLists.txt | 3 +- examples/app_spi_slave/README.rst | 14 +- examples/app_spi_slave/doc/rst/AN00161.rst | 382 ------------------ .../doc/rst/images/.~lock.task_diag.odg# | 1 - .../app_spi_slave/doc/rst/images/Makefile | 19 - .../doc/rst/images/block_diagram.odg | Bin 23125 -> 0 bytes .../doc/rst/images/block_diagram.pdf | Bin 25606 -> 0 bytes .../doc/rst/images/run_config_loopback.png | Bin 127477 -> 0 bytes .../doc/rst/images/run_config_sim.png | Bin 121442 -> 0 bytes .../doc/rst/images/run_config_trace.png | Bin 113567 -> 0 bytes .../doc/rst/images/task_diag.odg | Bin 15904 -> 0 bytes .../doc/rst/images/task_diag.pdf | Bin 23103 -> 0 bytes examples/app_spi_slave/doc/rst/xdoc.conf | 2 - examples/app_spi_slave/simulate_cmd.txt | 1 + examples/app_spi_slave/src/main.xc | 25 +- examples/deps.cmake | 3 +- 23 files changed, 215 insertions(+), 476 deletions(-) create mode 100644 doc/images/spi_slave_simulation.png delete mode 100644 examples/app_spi_slave/doc/rst/AN00161.rst delete mode 100644 examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# delete mode 100644 examples/app_spi_slave/doc/rst/images/Makefile delete mode 100644 examples/app_spi_slave/doc/rst/images/block_diagram.odg delete mode 100644 examples/app_spi_slave/doc/rst/images/block_diagram.pdf delete mode 100644 examples/app_spi_slave/doc/rst/images/run_config_loopback.png delete mode 100644 examples/app_spi_slave/doc/rst/images/run_config_sim.png delete mode 100644 examples/app_spi_slave/doc/rst/images/run_config_trace.png delete mode 100644 examples/app_spi_slave/doc/rst/images/task_diag.odg delete mode 100644 examples/app_spi_slave/doc/rst/images/task_diag.pdf delete mode 100644 examples/app_spi_slave/doc/rst/xdoc.conf create mode 100644 examples/app_spi_slave/simulate_cmd.txt diff --git a/.gitignore b/.gitignore index e0c142d..b7fafa1 100644 --- a/.gitignore +++ b/.gitignore @@ -30,3 +30,4 @@ build/ __gen *tests/logs/* *.gtkw +*.xmt diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 24e79e7..bed6c0c 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -12,10 +12,13 @@ lib_spi change log * ADDED: Array transfer method for SPI master sync * FIXED: SPI slave MISO now goes Hi-Z when SS is deasserted * FIXED: SPI master (all) swapping of SPI modes 0 and 1 + * FIXED: SPI master async non-functional SPI modes 1 and 2 * FIXED: SPI slave swapping of SPI modes 0 and 1 * FIXED: Passing NULL ptr to SPI asynch throws exception * FIXED: Non-functional tests * CHANGED: State diagrams and wavedrom now rendered by xmosdoc + * CHANGED: Examples AN00160 and AN00161 now integrated into main document as + app_spi_master and app_spi_slave examples * REMOVED: Support for XS1 devices 3.4.0 diff --git a/doc/images/spi_slave_simulation.png b/doc/images/spi_slave_simulation.png new file mode 100644 index 0000000000000000000000000000000000000000..52ceb2dd3ff0b1a57f97ccc76fb936cce405ca50 GIT binary patch literal 78982 zcmb4qbzD^6yDo|%A|cYP($d`^QX3E?#CXUJkCetjw$&)+ie~2ncTxBt?al+`tEm zu5L=o*KM%l7DWXrfsceQ8QxU~jCv}{(_40DFn*|aan+vw7Kw8+XQ%C{t@P3U5be3J zSjxwrLFn(Cp6<4MZMe9Q`20C7nIbmmc-!5LbZAguyQSc3!!g(~zCD3k`^9LxUyyPg zi@}cx!C_##-bZ=tfY+ap-~IPnSF-f9vy(P-)lN=Ltv6l3lZKw2f{F?$ zy!#u_Tv=I3x%ArB_&cS{v@=Pujp68wKEKcfC2yc}k4cq&-TW9kn)Jjd-MGU4=rrK< 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The SPI master examples are run on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_ using the WFM200 WiFi device as a simple SPI slave. The application consists of two tasks: @@ -802,6 +803,86 @@ application only uses a single hardware thread. app --> SPI_master : spi_master_if\nor\nspi_master_async_if @enduml +Declaring ports +............... + +The SPI library connects to external pins via xCORE ports. In +``main.xc`` these are declared as variables of type ``port`` at the +start of the file: + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: p_sclk + :end-at: p_mosi + +.. note:: + + The slave select declaration is for a mulit-bit port. The pin in this + port that will be used as SPI SS set by ``spi.set_ss_port_bit(0, 1);`` + +How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will +depend on the exact device being used. See the device datasheet for details. + +|newpage| + +The application main() function +............................... + +Below is the source code for the main function of this application, +which is taken from the source file ``main.xc`` + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-after: // SPI async main + :end-before: // end async main + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-after: // SPI sync main + :end-before: // end sync main + +Looking at this in more detail you can see the following: + + - The par functionality describes running two separate tasks in parallel + + - The ``spi_master`` or ``spi_master_async`` task drives the SPI bus and takes the ports it + will use as arguments. + + - The ``app`` or ``app_async`` task communicates to the SPI master task via the + shared interface argument ``i_spi`` or ``i_spi_async``. This is an array since the + SPI master task could connect to many other tasks (clients) in parallel. + +The app() function +.................. + +The ``app`` function uses its interface connection to the SPI master +task to perform SPI transactions. It performs two transactions (each +transaction will assert the slave select line, transfer some data and then +de-assert the slave select line). The functions in the SPI master +interface can be found in the SPI library user guide. + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: void app + :end-at: spi.shutdown + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: void async_app + :end-at: spi.shutdown + + +.. note:: + + When ``begin_transaction`` is called the SPI device selected is determined + by the first argument. In this case it is ``0``. + This is the method that is used to communiate with multiple SPI + slave devices. The speed and mode of the SPI protocol is also set at + in the ``begin_transaction`` call. + +|newpage| + + Building ........ @@ -874,6 +955,9 @@ Likewise, the following two commands should yield the same console output: SPI Slave Example ================= +Introduction +............ + The example in this application note uses the XMOS SPI library to act as SPI slave. It maintains a register file which can be read and written by the internal application *or* by the master on the SPI bus. @@ -900,7 +984,7 @@ The application consists of five tasks: .. _spi_slave_example_block: .. figure:: ../images/spi_slave_example_block_diagram.png - :scale: 60% + :scale: 50% :align: center Block diagram of SPI slave application example @@ -940,11 +1024,13 @@ The SPI library connects to external pins via xCORE ports. In start of the file: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: p_sclk - :end-at: clock + :language: c + :start-at: p_sclk + :end-at: clock -Note that there is also a clock declaration since the slave needs to -use an internal clock as well as ports inside the xCORE device. +.. note:: + + There is also a clock declaration since the slave needs to use an internal clock as well as ports inside the xCORE device. How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will depend on the exact device being used. See the device datasheet for details. @@ -952,8 +1038,9 @@ depend on the exact device being used. See the device datasheet for details. This application also has an SPI master interface on different ports: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: p_test_sclk - :end-at: p_test_mosi + :language: c + :start-at: p_test_sclk + :end-at: p_test_mosi |newpage| @@ -964,7 +1051,8 @@ Below is the source code for the main function of this application, which is taken from the source file ``main.xc`` .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: int main + :language: c + :start-at: int main Looking at this in a more detail you can see the following: @@ -978,7 +1066,7 @@ Looking at this in a more detail you can see the following: - The ``reg_file`` task is connected to the ``app`` task and the ``spi_slave`` task. - - The ``spi_slave`` task has an argument for the mode is expects - + - The ``spi_slave`` task has an argument for the mode it expects - in this case Mode 0 (see the SPI library user guide for more details on modes) @@ -998,25 +1086,28 @@ The ``reg_file`` function is the main logic of this example. It will respond to calls from the application and the SPI slave bus whilst maintaining a set of register values. -The function is marked as ``[[distributable]]`` which means it only -responds to calls from other tasks. The main reason for this is so -that the ``reg_file`` task itself does not need a logical core of its -own it can use the logical core of the task that calls it. See the +The function is marked as ``[[distributable]]`` which means it can only +responds to calls from other tasks, rather than resource events. +The main reason for this is so +that the ``reg_file`` task itself does not need a hardware thread of its +own it can use the hardware thread of the task that calls it. See the XMOS programming guide for details of distributable tasks. The function takes two arguments, the interface connections to the application task and the SPI slave task: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: [[distributable]] - :end-at: { + :language: c + :start-at: [[distributable]] + :end-at: { The ``reg_if`` interface has been defined in ``main.xc`` earlier. It defines the functions that the app may call in the ``reg_file`` tasks: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: interface - :end-at: } + :language: c + :start-at: interface + :end-at: } In this case we have two functions - one for reading a register value and one for writing a register value. @@ -1026,15 +1117,17 @@ register value, a state variable to hold what stage of an SPI transaction it is in and the currently addressed register by the SPI bus. .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: This array holds - :end-at: addr = 0 + :language: c + :start-at: This array holds + :end-at: addr = 0 The state variable is just an integer from the following ``enum`` type defined earlier in the file: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: enum - :end-at: } + :language: c + :start-at: enum + :end-at: } The implemented protocol on the SPI bus is as follows: @@ -1049,13 +1142,14 @@ The implemented protocol on the SPI bus is as follows: To implement the protocol logic the ``reg_file`` tasks must continually react to events from the SPI slave tasks keeping track of its state, updating registers and supplying the correct outputs. This is done via -a ``while (1)`` loop with an xC ``select`` statement inside it. A +a ``while(1)`` loop with an xC ``select`` statement inside it. A ``select`` statement will wait and then react to various events or calls from different tasks - see the XMOS programming guide for more details. The following cases in the main loop of the function handle this: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c :start-at: while (1) :end-before: respond to the application @@ -1075,26 +1169,30 @@ The main select also needs to react to request from the application. The following cases implement this: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: respond to the application - :end-before: } + :language: c + :start-at: respond to the application + :end-before: } The app() function .................. -The ``app`` task represents a sample application tasks that uses the +The ``app`` task represents a sample application task that uses the register file. In this demo, it doesn't do much - it simple sets one register and repeatedly polls the value of another register and prints out its value: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: app( - :end-before: tester + :language: c + :start-at: app( + :end-before: tester -Note that the ``debug_printf`` function comes from the -``debug_print.h`` header supplied by ``lib_logging``. It is a low -memory debug printing function that will print out messages to the -console in the xTIMEcomposer (either using JTAG or xSCOPE to -communicate to the host via the debug adaptor). + +.. note:: + + The ``debug_printf`` function comes from the ``debug_print.h`` header supplied by ``lib_logging``. It is a low + memory debug printing function that will print out messages to the + console in the xTIMEcomposer (either using JTAG or xSCOPE to + communicate to the host via the debug adaptor). The tester() function ..................... @@ -1104,8 +1202,9 @@ bus. It does this using the SPI master interface to communicate with the SPI master task: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc - :start-at: tester( - :end-before: main + :language: c + :start-at: tester( + :end-before: main @@ -1143,28 +1242,54 @@ Finally, the application binaries can be built using ``xmake``: Running ....... -To run the application return to the ``/examples/app_spi_slave`` directory and run the following -command: +To run the application return to the ``/examples/app_spi_slave`` directory and run the following command: .. code-block:: console - xrun --xscope bin/SYNC/app_spi_slave.xe + xsim --xscope '-offline trace.xmt' bin/app_spi_slave.xe \ + --trace-plugin VcdPlugin.dll '-tile tile[0] -o trace.vcd -xe bin/app_spi_slave.xe \ + -ports -functions -cores -instructions' --plugin LoopbackPort.dll \ + '-port tile[0] XS1_PORT_1I 1 0 -port tile[0] XS1_PORT_1E 1 0 \ + -port tile[0] XS1_PORT_1J 1 0 -port tile[0] XS1_PORT_1F 1 0 \ + -port tile[0] XS1_PORT_1K 1 0 -port tile[0] XS1_PORT_1G 1 0 \ + -port tile[0] XS1_PORT_1L 1 0 -port tile[0] XS1_PORT_1H 1 0' + +.. note:: + + This command line is provided as a file in the ``/examples/app_spi_slave`` directory under the filename ``simulate_cmd.txt``. + You can rename this file to ``simulate_cmd.sh`` or ``simulate_cmd.bat`` and run it directly, depending on your host OS. As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: - Sending SPI traffic - 5400 - Done. + APP: Set register 0 to 0xED + APP: Register 0 is 0xED, Register 1 is 0x0 + APP: Register 0 is 0xED, Register 1 is 0x0 + SPI MASTER: Read register 0: 0xED + APP: Register 0 is 0xED, Register 1 is 0x0 + SPI MASTER: Set register 1 to 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC -The value `5400` represents bits 15 to 0 of the default value of the CONFIG register of the WFM200. +Both registers were initialised to 0x00 so you can see the successful application side write to register 0 of value 0xED, followed by the +SPI master read of that register shortly afterwards. You can also see that the SPI master writes to register 1 with the value of 0xAC +which is then successfully read by the application. -Likewise, the following two commands should yield the same console output: +Next, you can also view the simulation in a VCD (Voltage Change Description) viewer such as ``gtkwave`` by running the following command: .. code-block:: console - xrun --xscope bin/SYNC/app_spi_master_SYNC_NO_CLKBLK.xe - xrun --xscope bin/SYNC/app_spi_master_ASYNC.xe + gtkwave slave_simulation.gtkw + +This will view the four SPI lines and zoom into the section where the SPI transactions occur as can be seen in numref:`spi_slave_simulation`. + +.. _spi_slave_simulation: + +.. figure:: ../images/spi_slave_simulation.png + :scale: 80% + :align: center + VCD waveform trace for SPI slave with registers simulation |newpage| diff --git a/examples/app_spi_master/CMakeLists.txt b/examples/app_spi_master/CMakeLists.txt index 6aa2f78..8742cfb 100644 --- a/examples/app_spi_master/CMakeLists.txt +++ b/examples/app_spi_master/CMakeLists.txt @@ -37,4 +37,4 @@ set(APP_COMPILER_FLAGS_ASYNC -DSPI_USE_ASYNC=1) -XMOS_REGISTER_APP() \ No newline at end of file +XMOS_REGISTER_APP() diff --git a/examples/app_spi_master/README.rst b/examples/app_spi_master/README.rst index 6f35c1d..ccda44f 100644 --- a/examples/app_spi_master/README.rst +++ b/examples/app_spi_master/README.rst @@ -5,7 +5,7 @@ Summary ------- This application note shows how to use the SPI library to make the -xCORE drive an SPI bus as SPI master. The application is the simplest +xCORE drive a SPI bus as SPI master. The application is the simplest example of setting up the library and performing a couple of transactions. diff --git a/examples/app_spi_master/src/main.xc b/examples/app_spi_master/src/main.xc index 40f1013..d2a419d 100644 --- a/examples/app_spi_master/src/main.xc +++ b/examples/app_spi_master/src/main.xc @@ -126,7 +126,7 @@ void async_app(client spi_master_async_if spi) #if SPI_USE_ASYNC - +// SPI async main int main(void) { interface spi_master_async_if i_spi_async[1]; par { @@ -139,12 +139,15 @@ int main(void) { } return 0; } +// end async main #else // SYNC + #ifndef CLKBLK #define CLKBLK clk #endif +// SPI sync main int main(void) { interface spi_master_if i_spi[1]; par { @@ -153,5 +156,6 @@ int main(void) { } return 0; } +// end sync main #endif /*SPI_USE_ASYNC*/ diff --git a/examples/app_spi_slave/CMakeLists.txt b/examples/app_spi_slave/CMakeLists.txt index 42bc5a0..0f62b1f 100644 --- a/examples/app_spi_slave/CMakeLists.txt +++ b/examples/app_spi_slave/CMakeLists.txt @@ -21,6 +21,7 @@ set( -report -Wall -Werror + -DDEBUG_PRINT_ENABLE=1 ) -XMOS_REGISTER_APP() \ No newline at end of file +XMOS_REGISTER_APP() diff --git a/examples/app_spi_slave/README.rst b/examples/app_spi_slave/README.rst index 6f35c1d..e4c6dca 100644 --- a/examples/app_spi_slave/README.rst +++ b/examples/app_spi_slave/README.rst @@ -1,16 +1,14 @@ -How to use the SPI library as SPI master -======================================== +How to use the SPI library as SPI slave +======================================= Summary ------- This application note shows how to use the SPI library to make the -xCORE drive an SPI bus as SPI master. The application is the simplest -example of setting up the library and performing a couple of -transactions. - -The note covers both the synchronous and asynchronous use of the SPI -master components provided from the library. +xCORE drive a SPI bus as SPI slave. The application implements +a SPI slave (driven by a test SPI master) as well as a +register set, similar to commercially available SPI devices, +which can be modified by the external master. Please refer to the main `lib_spi` documentation examples section for setup, building and running of this example. \ No newline at end of file diff --git a/examples/app_spi_slave/doc/rst/AN00161.rst b/examples/app_spi_slave/doc/rst/AN00161.rst deleted file mode 100644 index f8447de..0000000 --- a/examples/app_spi_slave/doc/rst/AN00161.rst +++ /dev/null @@ -1,382 +0,0 @@ -.. include:: ../../README.rst - -|newpage| - -Overview --------- - -Introduction -............ - -The XMOS SPI library is a library that provides -software defined, industry-standard, SPI (serial peripheral interface) -components that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. - -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. - -The library includes features such as SPI master and SPI slave modes, -supported speeds of up to 100 Mbit, multiple slave device support and -support for all configurations of clock polarity and phase. - -Block diagram -............. - -.. figure:: images/block_diagram.* - :scale: 100% - :align: center - - Block diagram of SPI slave application example - -SPI slave example ------------------- - -The example in this application note uses the XMOS SPI library to -act as SPI slave. It maintains a register file which can be read and -written by the internal application *or* by the master on the SPI bus. -To show the bus functioning the demo application also has a tester -component connected to an SPI master bus which is connected (in -simulation) to the the SPI slave. This allows the generation of -traffic to show the the communication functioning. - -The application consists of five tasks: - - - A task that controls the SPI slave ports - - - A task that implements the register file handling calls from the - SPI slave component and the application - - - An application task that connects to the register file task - - - A task that controls the SPI master ports used for testing - - - A tester task that outputs commands to the SPI master task - -These tasks communicate via the use of xC interfaces. - -The following diagram shows the task and communication structure of -the application. - -.. figure:: images/task_diag.* - - Task diagram of SPI slave example - -The SPI slave task communicates via the ``spi_slave_callback_if`` -which the SPI library defines as a set of callbacks a slave will make -to the application to handle communication occuring on the SPI -bus. - -The application also needs to communicate with the register file task -to get or set register values. To do this we define a custom -communication software interface (``reg_if``). - -|newpage| - -Makefile additions for this example -................................... - -To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: - - USED_MODULES = ... lib_spi - -You can then access the SPI functions in your source code via the -spi.h header file:: - - #include - -The example also uses the XMOS debug printing library -(``lib_logging``). This provides handy debug printing functions:: - - USED_MODULES = ... lib_logging - -Declaring ports -............... - -The SPI library connects to external pins via xCORE ports. In -``main.xc`` these are declared as variables of type ``port`` at the -start of the file: - -.. literalinclude:: main.xc - :start-on: p_sclk - :end-on: clock - -Note that there is also a clock declaration since the slave needs to -use an internal clock as well as ports inside the xCORE device. - -How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will -depend on the exact device being used. See the device datasheet for details. - -This application also has an SPI master interface on different ports: - -.. literalinclude:: main.xc - :start-on: p_test_sclk - :end-on: p_test_mosi - -|newpage| - -The application main() function -............................... - -Below is the source code for the main function of this application, -which is taken from the source file ``main.xc`` - -.. literalinclude:: main.xc - :start-on: int main - -Looking at this in a more detail you can see the following: - - - The par functionality describes running five separate tasks in - parallel; three are for the main application and two are for the - tester. - - - The ``spi_slave`` task controls the application - SPI bus and takes the ports it will use as arguments. - - - The ``reg_file`` task is connected to the ``app`` task and the - ``spi_slave`` task. - - - The ``spi_slave`` task has an argument for the mode is expects - - in this case Mode 0 (see the SPI library user guide for more - details on modes) - - - The ``spi_slave`` task also has an argument - ``SPI_TRANSFER_SIZE_8`` which specifies the size of data chunk it - will use when making callbacks to the application. - - - The ``spi_master`` task controls the test SPI bus and takes - different ports to the SPI slave bus as arguments. For details on - using SPI master see application note AN00160. - - -The reg_file() function -....................... - -The ``reg_file`` function is the main logic of this example. It will -respond to calls from the application and the SPI slave bus whilst -maintaining a set of register values. - -The function is marked as ``[[distributable]]`` which means it only -responds to calls from other tasks. The main reason for this is so -that the ``reg_file`` task itself does not need a logical core of its -own it can use the logical core of the task that calls it. See the -XMOS programming guide for details of distributable tasks. - -The function takes two arguments, the interface connections to the -application task and the SPI slave task: - -.. literalinclude:: main.xc - :start-on: [[distributable]] - :end-on: { - -The ``reg_if`` interface has been defined in ``main.xc`` earlier. It -defines the functions that the app may call in the ``reg_file`` tasks: - -.. literalinclude:: main.xc - :start-on: interface - :end-on: } - -In this case we have two functions - one for reading a register value -and one for writing a register value. - -The ``reg_file`` function first declares its state - an array to hold -register value, a state variable to hold what stage of an SPI -transaction it is in and the currently addressed register by the SPI bus. - -.. literalinclude:: main.xc - :start-on: This array holds - :end-on: addr = 0 - -The state variable is just an integer from the following ``enum`` type -defined earlier in the file: - -.. literalinclude:: main.xc - :start-on: enum - :end-on: } - -The implemented protocol on the SPI bus is as follows: - - * The master will start a transaction (assert slave select) - * It will then send a byte of either a 0 for a write or a - 1 for a read. - * It will then send the address of the register to read/write - * It will then send or receive the value of the register - -|newpage| - -To implement the protocol logic the ``reg_file`` tasks must continually react -to events from the SPI slave tasks keeping track of its state, -updating registers and supplying the correct outputs. This is done via -a ``while (1)`` loop with an xC ``select`` statement inside it. A -``select`` statement will wait and then react to various events or -calls from different tasks - see the XMOS programming guide for more details. - -The following cases in the main loop of the function handle this: - -.. literalinclude:: main.xc - :start-on: while (1) - :end-before: respond to the application - -We can see that the slave will always send the value of the currently -addressed register on every data transfer (this is allowable in the -described protocol). - -When the SPI master supplies some data to the slave then what happens -depends on the current state - either the state variable is updated, -the currently addressed register is updated or a register value is -updated. This state machine will implement the previously described -protocol. - -|newpage| - -The main select also needs to react to request from the -application. The following cases implement this: - -.. literalinclude:: main.xc - :start-on: respond to the application - :end-before: } - -The app() function -.................. - -The ``app`` task represents a sample application tasks that uses the -register file. In this demo, it doesn't do much - it simple sets one -register and repeatedly polls the value of another register and prints -out its value: - -.. literalinclude:: main.xc - :start-on: app( - :end-before: tester - -Note that the ``debug_printf`` function comes from the -``debug_print.h`` header supplied by ``lib_logging``. It is a low -memory debug printing function that will print out messages to the -console in the xTIMEcomposer (either using JTAG or xSCOPE to -communicate to the host via the debug adaptor). - -The tester() function -..................... - -The tester function will send some test data to the SPI master -bus. It does this using the SPI master interface to communicate with -the SPI master task: - -.. literalinclude:: main.xc - :start-on: tester( - :end-before: main - - -|newpage| - - -Setting up the run configuration for the application -.................................................... - -To run the application binary in the simulator, first the application -must be built by pressing the :menuitem:`Build` button in the -xTIMEcomposer. This will create the ``AN00161_using_SPI_slave.xe`` -binary in the ``bin`` folder of the project. The xTIMEcomposer may -have to import the SPI library if you do not already have it in your -workspace; this will occur automatically on build. - -Then a *Run Configuration* needs to be set up. This can be done by -selecting the :menuitem:`Run,Run Configurations..` menu. You can -create a new run configuration by right clicking on the -:menuitem:`xCORE application` group in the left hand pane and -:menuitem:`new`. However, in this example a run configuration has -already been created for you. - -Looking at this run configuration, you can see the simulator has been -selected under :menuitem:`Device Options:`: - -.. image:: images/run_config_sim.png - :width: 70% - :align: center - -|newpage| - -In the :menuitem:`Loopback` tab of the :menuitem:`Simulator` tab of -the run configuration. The -:menuitem:`Enable pin connections` check box has been enabled and four -loopback connections have been added connecting the SPI master ports -to the corresponding SPI slave ports: - -.. image:: images/run_config_loopback.png - :width: 70% - :align: center - -|newpage| - -Running the application -....................... - -By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit -Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` -button in the run configuration dialog, the program -will run. In the console window you will get this output:: - - APP: Set register 1 to 0xFE - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - SPI MASTER: Read register 0: 0xFE - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - SPI MASTER: Set register 1 to 0xAC - APP: Register 1 is 0xAC - APP: Register 1 is 0xAC - APP: Register 1 is 0xAC - ... - -You can terminate the program by clicking the :menuitem:`Terminate` -button in the Console window (the red square). - -The console shows the debug print output from the application and tester. You -can see that the SPI bus can read registers that the application has -set and the application can read registers that the SPI bus has set. - -|appendix| -|newpage| - -References ----------- - -.. nopoints:: - - * XMOS Tools User Guide - - http://www.xmos.com/published/xtimecomposer-user-guide - - * XMOS xCORE Programming Guide - - http://www.xmos.com/published/xmos-programming-guide - - * XMOS SPI Library - - http://www.xmos.com/support/libraries/lib_spi - -|newpage| - -Full source code listing ------------------------- - -.. literalinclude:: main.xc - :largelisting: - -|newpage| - diff --git a/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# b/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# deleted file mode 100644 index d51b26f..0000000 --- a/examples/app_spi_slave/doc/rst/images/.~lock.task_diag.odg# +++ /dev/null @@ -1 +0,0 @@ -,ed,ed-zenbook,13.08.2025 11:38,file:///home/ed/.config/libreoffice/4; \ No newline at end of file diff --git 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zVoq%wM;@2D2B#Re!C9xH2O%9pJ?!q&Zzt=-MP4_Euk_04PJc~c*nexY2Hr)uh`sw! zy0w>XK~(GPVKitmbDZJd`2a6xo@w>J98g_YI2Q+00s;Wm_8+C_Hy$S_1Qq-p{OeJc zCZLI;&79p`FLYH4U%)~FB63z#t${?BGuU>Oxa>2MW7*0+<&dd8yc00)pF5Z|tv$0>9|E zzhugq0XmqA4N&i*i(fSC|Ca)^v!7G)GXpSG|77pL0OYD=rFQ}3LihyWfa&^M%mV}A z-bV(LWTbl z^FW&cG#wgHtw8*mc9@Hm1x#cY7vN3+s$O7&7qT$u=T^SBkOLXqfk?{(hsyHu2pK3` zK@cV_FQ^~@5fG4;gDFTuVFC&gp#R;(=;A(g_b@|y{M;K*C;|Y4IXL9+DUkjjL*bFv diff --git a/examples/app_spi_slave/doc/rst/xdoc.conf b/examples/app_spi_slave/doc/rst/xdoc.conf deleted file mode 100644 index 37460ab..0000000 --- a/examples/app_spi_slave/doc/rst/xdoc.conf +++ /dev/null @@ -1,2 +0,0 @@ -XMOSNEWSTYLE=1 -SOURCE_INCLUDE_DIRS=../../src \ No newline at end of file diff --git a/examples/app_spi_slave/simulate_cmd.txt b/examples/app_spi_slave/simulate_cmd.txt new file mode 100644 index 0000000..45283fa --- /dev/null +++ b/examples/app_spi_slave/simulate_cmd.txt @@ -0,0 +1 @@ +xsim --xscope '-offline trace.xmt' bin/app_spi_slave.xe --trace-plugin VcdPlugin.dll '-tile tile[0] -o trace.vcd -xe bin/app_spi_slave.xe -ports -functions -cores -instructions' --plugin LoopbackPort.dll '-port tile[0] XS1_PORT_1I 1 0 -port tile[0] XS1_PORT_1E 1 0 -port tile[0] XS1_PORT_1J 1 0 -port tile[0] XS1_PORT_1F 1 0 -port tile[0] XS1_PORT_1K 1 0 -port tile[0] XS1_PORT_1G 1 0 -port tile[0] XS1_PORT_1L 1 0 -port tile[0] XS1_PORT_1H 1 0' diff --git a/examples/app_spi_slave/src/main.xc b/examples/app_spi_slave/src/main.xc index d09315a..068dbee 100644 --- a/examples/app_spi_slave/src/main.xc +++ b/examples/app_spi_slave/src/main.xc @@ -5,6 +5,7 @@ #include #include #include +#include #include "spi.h" @@ -21,6 +22,9 @@ out buffered port:32 p_test_sclk = on tile[0]: XS1_PORT_1I; out port p_test_ss = on tile[0]: XS1_PORT_1J; in buffered port:32 p_test_miso = on tile[0]: XS1_PORT_1K; out buffered port:32 p_test_mosi = on tile[0]: XS1_PORT_1L; +// Clock used specifically for the test SPI master component. +clock cb_test = on tile[0]: XS1_CLKBLK_2; + /* Interface to communicate between the register file tasks and the application. */ @@ -130,12 +134,15 @@ void reg_file(server spi_slave_callback_if i_spi, * to the reg_file tasks to get/set registers. */ void app(client reg_if reg) { - reg.set_reg(0, 0xfe); - printstr("APP: Set register 1 to 0xFE\n"); + uint8_t set_reg_data = 0xed; + reg.set_reg(0, set_reg_data); + debug_printf("APP: Set register %u to 0x%x\n", 0, set_reg_data); while (1) { + uint8_t reg_data_read[2]; delay_microseconds(20); - printstr("APP: Register 1 is 0x"); - printhexln(reg.get_reg(1)); + reg_data_read[0] = reg.get_reg(0); + reg_data_read[1] = reg.get_reg(1); + debug_printf("APP: Register %d is 0x%x, Register %d is 0x%x\n", 0, reg_data_read[0], 1, reg_data_read[1]); } } @@ -146,15 +153,14 @@ void app(client reg_if reg) { */ void tester(client spi_master_if spi) { - delay_microseconds(45); // Wait for slave to init + delay_microseconds(50); // Wait for slave to init uint8_t val; spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(READ_REG); // READ command spi.transfer8(0); // REGISTER 0 val = spi.transfer8(0); // DATA spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); - printstr("SPI MASTER: Read register 0: 0x"); - printhexln(val); + debug_printf("SPI MASTER: Read register 0: 0x%x\n", val); spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(WRITE_REG); // WRITE command @@ -162,6 +168,9 @@ void tester(client spi_master_if spi) spi.transfer8(0xac); // DATA spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); printstr("SPI MASTER: Set register 1 to 0xAC\n"); + + delay_microseconds(100); + _Exit(0); } int main(void) { @@ -180,7 +189,7 @@ int main(void) { on tile[0]: tester(i_spi_master[0]); on tile[0]: spi_master(i_spi_master, 1, p_test_sclk, p_test_mosi, p_test_miso, p_test_ss, - 1, null); + 1, cb_test); } return 0; } diff --git a/examples/deps.cmake b/examples/deps.cmake index e0f172e..81867d5 100644 --- a/examples/deps.cmake +++ b/examples/deps.cmake @@ -1,2 +1,3 @@ # Common dependencies for examples -set(APP_DEPENDENT_MODULES "lib_spi") +set(APP_DEPENDENT_MODULES "lib_spi" + "lib_logging(3.3.2)") From a30eba74ff037c180e56d38e35ad553caf14287c Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 14 Aug 2025 12:02:36 +0100 Subject: [PATCH 50/57] Fix diagram rendering --- doc/rst/lib_spi.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 1954ba0..ceff893 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -984,7 +984,7 @@ The application consists of five tasks: .. _spi_slave_example_block: .. figure:: ../images/spi_slave_example_block_diagram.png - :scale: 50% + :width: 90% :align: center Block diagram of SPI slave application example @@ -1281,12 +1281,12 @@ Next, you can also view the simulation in a VCD (Voltage Change Description) vie gtkwave slave_simulation.gtkw -This will view the four SPI lines and zoom into the section where the SPI transactions occur as can be seen in numref:`spi_slave_simulation`. +This will view the four SPI lines and zoom into the section where the SPI transactions occur as can be seen in :numref:`spi_slave_simulation`. .. _spi_slave_simulation: .. figure:: ../images/spi_slave_simulation.png - :scale: 80% + :width: 100% :align: center VCD waveform trace for SPI slave with registers simulation From 3670d8e7a2b74375abd54c3e23e291ceba8c3b68 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 14 Aug 2025 17:15:21 +0100 Subject: [PATCH 51/57] Remove unneeded license files and .rst review feedback --- doc/rst/lib_spi.rst | 72 ++++++++++++------------- examples/app_spi_master/LICENSE.rst | 84 ----------------------------- examples/app_spi_master/README.rst | 16 ------ examples/app_spi_slave/LICENSE.rst | 84 ----------------------------- examples/app_spi_slave/README.rst | 14 ----- 5 files changed, 36 insertions(+), 234 deletions(-) delete mode 100644 examples/app_spi_master/LICENSE.rst delete mode 100644 examples/app_spi_master/README.rst delete mode 100644 examples/app_spi_slave/LICENSE.rst delete mode 100644 examples/app_spi_slave/README.rst diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index ceff893..56e8240 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -199,7 +199,7 @@ and so multiple slaves may share the same select bit if needed. Disabling master data lines =========================== -The *MOSI* and *MISO* parameters of the ``spi_master`` task are +The *MOSI* and *MISO* parameters of the ``spi_master()`` task are optional. So in the top-level ``par`` statement the function can be called with ``null`` instead of a port e.g. @@ -208,7 +208,7 @@ called with ``null`` instead of a port e.g. spi_master(i_spi, 1, p_sclk, null, p_miso , p_ss, 1, clk_spi); -Similarly, the *MOSI* parameter of the ``spi_master_async`` task is +Similarly, the *MOSI* parameter of the ``spi_master_async()`` task is optional (but the *MISO* port must be provided). |newpage| @@ -239,7 +239,7 @@ If the *MISO* line is not required then it need not be connected. The Disabling slave data lines ========================== -The ``spi_slave`` task has an optional *MISO* parameter (but the +The ``spi_slave()`` task has an optional *MISO* parameter (but the *MOSI* port must be supplied). @@ -295,7 +295,7 @@ and connect to it. also an array since the same SPI data lines can connect to several devices via different slave lines. -The final parameter of the ``spi_master`` task is an optional clock +The final parameter of the ``spi_master()`` task is an optional clock block. If the clock block is supplied then the maximum transfer rate of the SPI bus is increased (see :numref:`spi_master_sync_timings`). If ``null`` is supplied instead then the performance is lower but no clock @@ -845,17 +845,17 @@ Looking at this in more detail you can see the following: - The par functionality describes running two separate tasks in parallel - - The ``spi_master`` or ``spi_master_async`` task drives the SPI bus and takes the ports it + - The ``spi_master()`` or ``spi_master_async()`` task drives the SPI bus and takes the ports it will use as arguments. - - The ``app`` or ``app_async`` task communicates to the SPI master task via the + - The ``app()`` or ``app_async()`` task communicates to the SPI master task via the shared interface argument ``i_spi`` or ``i_spi_async``. This is an array since the SPI master task could connect to many other tasks (clients) in parallel. -The app() function -.................. +The app() task +.............. -The ``app`` function uses its interface connection to the SPI master +The ``app()`` task uses its interface connection to the SPI master task to perform SPI transactions. It performs two transactions (each transaction will assert the slave select line, transfer some data and then de-assert the slave select line). The functions in the SPI master @@ -955,16 +955,16 @@ Likewise, the following two commands should yield the same console output: SPI Slave Example ================= -Introduction -............ +Overview +........ The example in this application note uses the XMOS SPI library to act as SPI slave. It maintains a register file which can be read and written by the internal application *or* by the master on the SPI bus. To show the bus functioning the demo application also has a tester component connected to an SPI master bus which is connected (in -simulation) to the the SPI slave. This allows the generation of -traffic to show the the communication functioning. +simulation) to the the SPI slave, using the simulator loopback plug-in. +This allows generation of SPI traffic to show the communication functioning. The application consists of five tasks: @@ -1060,36 +1060,36 @@ Looking at this in a more detail you can see the following: parallel; three are for the main application and two are for the tester. - - The ``spi_slave`` task controls the application + - The ``spi_slave()`` task controls the application SPI bus and takes the ports it will use as arguments. - - The ``reg_file`` task is connected to the ``app`` task and the - ``spi_slave`` task. + - The ``reg_file()`` task is connected to the ``app()`` task and the + ``spi_slave()`` task. - - The ``spi_slave`` task has an argument for the mode it expects - + - The ``spi_slave()`` task has an argument for the mode it expects - in this case Mode 0 (see the SPI library user guide for more details on modes) - - The ``spi_slave`` task also has an argument + - The ``spi_slave()`` task also has an argument ``SPI_TRANSFER_SIZE_8`` which specifies the size of data chunk it will use when making callbacks to the application. - - The ``spi_master`` task controls the test SPI bus and takes + - The ``spi_master()`` task controls the test SPI bus and takes different ports to the SPI slave bus as arguments. For details on using SPI master see application note AN00160. -The reg_file() function -....................... +The reg_file() task +................... -The ``reg_file`` function is the main logic of this example. It will +The ``reg_file()`` task is the main logic of this example. It will respond to calls from the application and the SPI slave bus whilst maintaining a set of register values. -The function is marked as ``[[distributable]]`` which means it can only +The task is marked as ``[[distributable]]`` which means it can only responds to calls from other tasks, rather than resource events. The main reason for this is so -that the ``reg_file`` task itself does not need a hardware thread of its +that the ``reg_file()`` task itself does not need a hardware thread of its own it can use the hardware thread of the task that calls it. See the XMOS programming guide for details of distributable tasks. @@ -1102,7 +1102,7 @@ application task and the SPI slave task: :end-at: { The ``reg_if`` interface has been defined in ``main.xc`` earlier. It -defines the functions that the app may call in the ``reg_file`` tasks: +defines the functions that the app may call in the ``reg_file()`` tasks: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc :language: c @@ -1112,7 +1112,7 @@ defines the functions that the app may call in the ``reg_file`` tasks: In this case we have two functions - one for reading a register value and one for writing a register value. -The ``reg_file`` function first declares its state - an array to hold +The ``reg_file()`` task first declares its state - an array to hold register value, a state variable to hold what stage of an SPI transaction it is in and the currently addressed register by the SPI bus. @@ -1139,7 +1139,7 @@ The implemented protocol on the SPI bus is as follows: |newpage| -To implement the protocol logic the ``reg_file`` tasks must continually react +To implement the protocol logic the ``reg_file()`` task must continually react to events from the SPI slave tasks keeping track of its state, updating registers and supplying the correct outputs. This is done via a ``while(1)`` loop with an xC ``select`` statement inside it. A @@ -1165,7 +1165,7 @@ protocol. |newpage| -The main select also needs to react to request from the +The main ``select`` statement also needs to react to request from the application. The following cases implement this: .. literalinclude:: ../../examples/app_spi_slave/src/main.xc @@ -1173,10 +1173,10 @@ application. The following cases implement this: :start-at: respond to the application :end-before: } -The app() function -.................. +The app() task +.............. -The ``app`` task represents a sample application task that uses the +The ``app()`` task represents a sample application task that uses the register file. In this demo, it doesn't do much - it simple sets one register and repeatedly polls the value of another register and prints out its value: @@ -1194,10 +1194,10 @@ out its value: console in the xTIMEcomposer (either using JTAG or xSCOPE to communicate to the host via the debug adaptor). -The tester() function -..................... +The tester() task +................. -The tester function will send some test data to the SPI master +The tester task will send some test data to the SPI master bus. It does this using the SPI master interface to communicate with the SPI master task: @@ -1275,13 +1275,13 @@ Both registers were initialised to 0x00 so you can see the successful applicatio SPI master read of that register shortly afterwards. You can also see that the SPI master writes to register 1 with the value of 0xAC which is then successfully read by the application. -Next, you can also view the simulation in a VCD (Voltage Change Description) viewer such as ``gtkwave`` by running the following command: +If you wish, you can also view the simulation in a VCD (Voltage Change Description) viewer, such as ``gtkwave``, by running the following command: .. code-block:: console gtkwave slave_simulation.gtkw -This will view the four SPI lines and zoom into the section where the SPI transactions occur as can be seen in :numref:`spi_slave_simulation`. +This will show the four SPI lines and zoom into the section where the SPI transactions occur, as can be seen in :numref:`spi_slave_simulation`. .. _spi_slave_simulation: diff --git a/examples/app_spi_master/LICENSE.rst b/examples/app_spi_master/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/examples/app_spi_master/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. Definitions** - -**“Applicable Patent Rights”** means: (a) where XMOS is the grantor of the rights, (i) claims of patents that are now or in future owned by or assigned to XMOS and (ii) that cover subject matter contained in the Software, but only to the extent it is necessary to use, reproduce or distribute the Software without infringement; and (b) where you are the grantor of the rights, (i) claims of patents that are now or in future owned by or assigned to you and (ii) that cover the subject matter contained in your Derivatives, taken alone or in combination with the Software. - -**“Compiled Code”** means any compiled, binary, machine readable or executable version of the Source Code. - -**“Contributor”** means any person or entity that creates or contributes to the creation of Derivatives. - -**“Derivatives”** means any addition to, deletion from and/or change to the substance, structure of the Software, any previous Derivatives, the combination of the Derivatives and the Software and/or any respective portions thereof. - -**“Source Code”** means the human readable code that is suitable for making modifications but excluding any Compiled Code. - -**“Software”** means the software and associated documentation files which XMOS makes available and which contain a notice identifying the software as original XMOS software and referring to the software being subject to the terms of this XMOS Public Licence. - -This Licence refers to XMOS Software and does not relate to any XMOS hardware or devices which are protected by intellectual property rights (including patent and trade marks) which may be sold to you under a separate agreement. - - -**2. Licence** - -**Permitted Uses, Conditions and Restrictions.** Subject to the conditions below, XMOS grants you a worldwide, royalty free, non-exclusive licence, to the extent of any Patent Rights to do the following: - -2.1 **Unmodified Software.** You may use, copy, display, publish, distribute and make available unmodified copies of the Software: - -2.1.1 for personal or academic, non-commercial purposes; or - -2.1.2 for commercial purposes provided the Software is at all times used on a device designed, licensed or developed by XMOS and, provided that in each instance (2.1.1 and 2.1.2): - -(a) you must retain and reproduce in all copies of the Software the copyright and proprietary notices and disclaimers of XMOS as they appear in the Software, and keep intact all notices and disclaimers in the Software files that refer to this Licence; and - -(b) you must include a copy of this Licence with every copy of the Software and documentation you publish, distribute and make available and you may not offer or impose any terms on such Software that alter or restrict this Licence or the intent of such Licence, except as permitted below (Additional Terms). - -The licence above does not include any Compiled Code which XMOS may make available under a separate support and licence agreement. - -2.2 **Derivatives.** You may create and modify Derivatives and use, copy, display, publish, distribute and make available Derivatives: - -2.2.1 for personal or academic, non-commercial purposes; or - -2.2.2 for commercial purposes, provided the Derivatives are at all times used on a device designed, licensed or developed by XMOS and, provided that in each instance (2.2.1 and 2.2.2): - -(a) you must comply with the terms of clause 2.1 with respect to the Derivatives; - -(b) you must copy (to the extent it doesn’t already exist) the notice below in each file of the Derivatives, and ensure all the modified files carry prominent notices stating that you have changed the files and the date of any change; and - -(c) if you sublicence, distribute or otherwise make the Software and/or the Derivatives available for commercial purposes, you must provide that the Software and Derivatives are at all times used on a device designed, licensed or developed by XMOS. - -Without limitation to these terms and clause 3 below, the Source Code and Compiled Code to your Derivatives may at your discretion (but without obligation) be released, copied, displayed, published, distributed and made available; and if you elect to do so, it must be under the terms of this Licence including the terms of the licence at clauses 2.2.1, 2.2.2 and clause 3 below. - -2.3 **Distribution of Executable Versions.** If you distribute or make available Derivatives, you must include a prominent notice in the code itself as well as in all related documentation, stating that the Source Code of the Software from which the Derivatives are based is available under the terms of this Licence, with information on how and where to obtain such Source Code. - -**3. Your Grant of Rights.** In consideration and as a condition to this Licence, you grant to any person or entity receiving or distributing any Derivatives, a non-exclusive, royalty free, perpetual, irrevocable license under your Applicable Patent Rights and all other intellectual property rights owned or controlled by you, to use, copy, display, publish, distribute and make available your Derivatives of the same scope and extent as XMOS’s licence under clause 2.2 above. - -**4. Combined Products.** You may create a combined product by combining Software, Derivatives and other code not covered by this Licence as a single application or product. In such instance, you must comply with the requirements of this Licence for any portion of the Software and/or Derivatives. - -**5. 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Only XMOS shall have the right to modify these terms. - -**7. IPR and Ownership** -Any rights, including all intellectual property rights and all trademarks not expressly granted herein are reserved in full by the authors or copyright holders. Any requests for additional permissions by XMOS including any rights to use XMOS trademarks, should be made (without obligation) to XMOS at **support@xmos.com** - -Nothing herein shall limit any rights that XMOS is otherwise entitled to under the doctrines of patent exhaustion, implied license, or legal estoppel. Neither the name of the authors, the copyright holders or any contributors may be used to endorse or promote any Derivatives from this Software without specific written permission. Any attempt to deal with the Software which does not comply with this Licence shall be void and shall automatically terminate any rights granted under this licence (including any licence of any intellectual property rights granted herein). -Subject to the licences granted under this Licence any Contributor retains all rights, title and interest in and to any Derivatives made by Contributor subject to the underlying rights of XMOS in the Software. XMOS shall retain all rights, title and interest in the Software and any Derivatives made by XMOS (“XMOS Derivatives”). XMOS Derivatives will not automatically be subject to this Licence and XMOS shall be entitled to licence such rights on any terms (without obligation) as it sees fit. - -**8. Termination** - -8.1 This Licence will automatically terminate immediately, without notice to you, if: - -(a) you fail to comply with the terms of this Licence; and/or - -(b) you directly or indirectly commence any action for patent or intellectual property right infringement against XMOS, or any parent, group, affiliate or subsidiary of XMOS; provided XMOS did not first commence an action or patent infringement against you in that instance; and/or - -(c) the terms of this Licence are held by any court of competent jurisdiction to be unenforceable in whole or in part. - -**9. Critical Applications.** Unless XMOS has agreed in writing with you an agreement specifically governing use of the Goods in military, aerospace, automotive or medically related functions (collectively and individually hereinafter referred to as "Special Use"), any permitted use of the Software excludes Special Use. Notwithstanding any agreement between XMOS and you for Special Use, Special Use shall be at your own risk, and you shall fully indemnify XMOS against any damages, losses, costs and claims (direct and indirect) arising out of any Special Use. - -**10. NO WARRANTY OR SUPPORT.** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL XMOS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, WARRANTY, CIVIL TORT (INCLUDING NEGLIGENCE), PRODUCTS LIABILITY OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE INCLUDING GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES AND NOT WITHSTANDING THE FAILURE OF ESSENTIAL PURPOSE. IN SOME JURISDICTIONS PARTIES ARE UNABLE TO LIMIT LIABILTY IN THIS WAY, IF THIS APPLIES TO YOUR JURISDICTION THIS LIABILITY CLAUSE ABOVE MAY NOT APPLY. NOTWITHSTANDING THE ABOVE, IN NO EVENT SHALL XMOS’s TOTAL LIABILITY TO YOU FOR ALL DAMAGES, LOSS OR OTHERWISE EXCEED $50. - -**11. Governing Law and Jurisdiction.** This Licence constitutes the entire agreement between the parties with respect to the subject matter hereof. The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/examples/app_spi_master/README.rst b/examples/app_spi_master/README.rst deleted file mode 100644 index ccda44f..0000000 --- a/examples/app_spi_master/README.rst +++ /dev/null @@ -1,16 +0,0 @@ -How to use the SPI library as SPI master -======================================== - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE drive a SPI bus as SPI master. The application is the simplest -example of setting up the library and performing a couple of -transactions. - -The note covers both the synchronous and asynchronous use of the SPI -master components provided from the library. - -Please refer to the main `lib_spi` documentation examples section -for setup, building and running of this example. \ No newline at end of file diff --git a/examples/app_spi_slave/LICENSE.rst b/examples/app_spi_slave/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/examples/app_spi_slave/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. Definitions** - -**“Applicable Patent Rights”** means: (a) where XMOS is the grantor of the rights, (i) claims of patents that are now or in future owned by or assigned to XMOS and (ii) that cover subject matter contained in the Software, but only to the extent it is necessary to use, reproduce or distribute the Software without infringement; and (b) where you are the grantor of the rights, (i) claims of patents that are now or in future owned by or assigned to you and (ii) that cover the subject matter contained in your Derivatives, taken alone or in combination with the Software. - -**“Compiled Code”** means any compiled, binary, machine readable or executable version of the Source Code. - -**“Contributor”** means any person or entity that creates or contributes to the creation of Derivatives. - -**“Derivatives”** means any addition to, deletion from and/or change to the substance, structure of the Software, any previous Derivatives, the combination of the Derivatives and the Software and/or any respective portions thereof. - -**“Source Code”** means the human readable code that is suitable for making modifications but excluding any Compiled Code. - -**“Software”** means the software and associated documentation files which XMOS makes available and which contain a notice identifying the software as original XMOS software and referring to the software being subject to the terms of this XMOS Public Licence. - -This Licence refers to XMOS Software and does not relate to any XMOS hardware or devices which are protected by intellectual property rights (including patent and trade marks) which may be sold to you under a separate agreement. - - -**2. Licence** - -**Permitted Uses, Conditions and Restrictions.** Subject to the conditions below, XMOS grants you a worldwide, royalty free, non-exclusive licence, to the extent of any Patent Rights to do the following: - -2.1 **Unmodified Software.** You may use, copy, display, publish, distribute and make available unmodified copies of the Software: - -2.1.1 for personal or academic, non-commercial purposes; or - -2.1.2 for commercial purposes provided the Software is at all times used on a device designed, licensed or developed by XMOS and, provided that in each instance (2.1.1 and 2.1.2): - -(a) you must retain and reproduce in all copies of the Software the copyright and proprietary notices and disclaimers of XMOS as they appear in the Software, and keep intact all notices and disclaimers in the Software files that refer to this Licence; and - -(b) you must include a copy of this Licence with every copy of the Software and documentation you publish, distribute and make available and you may not offer or impose any terms on such Software that alter or restrict this Licence or the intent of such Licence, except as permitted below (Additional Terms). - -The licence above does not include any Compiled Code which XMOS may make available under a separate support and licence agreement. - -2.2 **Derivatives.** You may create and modify Derivatives and use, copy, display, publish, distribute and make available Derivatives: - -2.2.1 for personal or academic, non-commercial purposes; or - -2.2.2 for commercial purposes, provided the Derivatives are at all times used on a device designed, licensed or developed by XMOS and, provided that in each instance (2.2.1 and 2.2.2): - -(a) you must comply with the terms of clause 2.1 with respect to the Derivatives; - -(b) you must copy (to the extent it doesn’t already exist) the notice below in each file of the Derivatives, and ensure all the modified files carry prominent notices stating that you have changed the files and the date of any change; and - -(c) if you sublicence, distribute or otherwise make the Software and/or the Derivatives available for commercial purposes, you must provide that the Software and Derivatives are at all times used on a device designed, licensed or developed by XMOS. - -Without limitation to these terms and clause 3 below, the Source Code and Compiled Code to your Derivatives may at your discretion (but without obligation) be released, copied, displayed, published, distributed and made available; and if you elect to do so, it must be under the terms of this Licence including the terms of the licence at clauses 2.2.1, 2.2.2 and clause 3 below. - -2.3 **Distribution of Executable Versions.** If you distribute or make available Derivatives, you must include a prominent notice in the code itself as well as in all related documentation, stating that the Source Code of the Software from which the Derivatives are based is available under the terms of this Licence, with information on how and where to obtain such Source Code. - -**3. Your Grant of Rights.** In consideration and as a condition to this Licence, you grant to any person or entity receiving or distributing any Derivatives, a non-exclusive, royalty free, perpetual, irrevocable license under your Applicable Patent Rights and all other intellectual property rights owned or controlled by you, to use, copy, display, publish, distribute and make available your Derivatives of the same scope and extent as XMOS’s licence under clause 2.2 above. - -**4. Combined Products.** You may create a combined product by combining Software, Derivatives and other code not covered by this Licence as a single application or product. In such instance, you must comply with the requirements of this Licence for any portion of the Software and/or Derivatives. - -**5. Additional Terms.** You may choose to offer, and to charge a fee for, warranty, support, indemnity or liability obligations and/or other rights consistent with the term of this Licence (“Additional Terms”) to any legitimate recipients of the Software and/or Derivatives. The terms on which you provide such Additional Terms are on your sole responsibility and you shall indemnify, defend and hold XMOS harmless against any claims asserted against XMOS. - -**6. New Versions.** XMOS may publish revised and/or new versions of this Licence from time to time to accommodate changes to the Licence terms, new versions, updates and bug fixes of the Software. Each version will be given a distinguishing version number. Once Software has been published under a particular version of this Licence, you may continue to use it under the terms of that version. You may also choose to use the latest version of the Software under any subsequent version published by XMOS. Only XMOS shall have the right to modify these terms. - -**7. IPR and Ownership** -Any rights, including all intellectual property rights and all trademarks not expressly granted herein are reserved in full by the authors or copyright holders. Any requests for additional permissions by XMOS including any rights to use XMOS trademarks, should be made (without obligation) to XMOS at **support@xmos.com** - -Nothing herein shall limit any rights that XMOS is otherwise entitled to under the doctrines of patent exhaustion, implied license, or legal estoppel. Neither the name of the authors, the copyright holders or any contributors may be used to endorse or promote any Derivatives from this Software without specific written permission. Any attempt to deal with the Software which does not comply with this Licence shall be void and shall automatically terminate any rights granted under this licence (including any licence of any intellectual property rights granted herein). -Subject to the licences granted under this Licence any Contributor retains all rights, title and interest in and to any Derivatives made by Contributor subject to the underlying rights of XMOS in the Software. XMOS shall retain all rights, title and interest in the Software and any Derivatives made by XMOS (“XMOS Derivatives”). XMOS Derivatives will not automatically be subject to this Licence and XMOS shall be entitled to licence such rights on any terms (without obligation) as it sees fit. - -**8. Termination** - -8.1 This Licence will automatically terminate immediately, without notice to you, if: - -(a) you fail to comply with the terms of this Licence; and/or - -(b) you directly or indirectly commence any action for patent or intellectual property right infringement against XMOS, or any parent, group, affiliate or subsidiary of XMOS; provided XMOS did not first commence an action or patent infringement against you in that instance; and/or - -(c) the terms of this Licence are held by any court of competent jurisdiction to be unenforceable in whole or in part. - -**9. Critical Applications.** Unless XMOS has agreed in writing with you an agreement specifically governing use of the Goods in military, aerospace, automotive or medically related functions (collectively and individually hereinafter referred to as "Special Use"), any permitted use of the Software excludes Special Use. Notwithstanding any agreement between XMOS and you for Special Use, Special Use shall be at your own risk, and you shall fully indemnify XMOS against any damages, losses, costs and claims (direct and indirect) arising out of any Special Use. - -**10. NO WARRANTY OR SUPPORT.** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL XMOS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, WARRANTY, CIVIL TORT (INCLUDING NEGLIGENCE), PRODUCTS LIABILITY OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE INCLUDING GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES AND NOT WITHSTANDING THE FAILURE OF ESSENTIAL PURPOSE. IN SOME JURISDICTIONS PARTIES ARE UNABLE TO LIMIT LIABILTY IN THIS WAY, IF THIS APPLIES TO YOUR JURISDICTION THIS LIABILITY CLAUSE ABOVE MAY NOT APPLY. NOTWITHSTANDING THE ABOVE, IN NO EVENT SHALL XMOS’s TOTAL LIABILITY TO YOU FOR ALL DAMAGES, LOSS OR OTHERWISE EXCEED $50. - -**11. Governing Law and Jurisdiction.** This Licence constitutes the entire agreement between the parties with respect to the subject matter hereof. The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/examples/app_spi_slave/README.rst b/examples/app_spi_slave/README.rst deleted file mode 100644 index e4c6dca..0000000 --- a/examples/app_spi_slave/README.rst +++ /dev/null @@ -1,14 +0,0 @@ -How to use the SPI library as SPI slave -======================================= - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE drive a SPI bus as SPI slave. The application implements -a SPI slave (driven by a test SPI master) as well as a -register set, similar to commercially available SPI devices, -which can be modified by the external master. - -Please refer to the main `lib_spi` documentation examples section -for setup, building and running of this example. \ No newline at end of file From 3389170c1988f9e0715845224c41fa21825d97f6 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 18 Aug 2025 15:15:18 +0100 Subject: [PATCH 52/57] Fix release stage in Jenkins --- Jenkinsfile | 137 +++++++++++++++++++++++++++------------------------- 1 file changed, 71 insertions(+), 66 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index d18c99e..5e53151 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -5,14 +5,8 @@ getApproval() pipeline { - agent { - label 'x86_64 && linux' - } - options { - buildDiscarder(xmosDiscardBuildSettings()) - skipDefaultCheckout() - timestamps() - } + agent none + parameters { choice(name: 'TEST_LEVEL', choices: ['smoke', 'default', 'extended'], description: 'The level of test coverage to run' @@ -34,74 +28,90 @@ pipeline { ) } + options { + buildDiscarder(xmosDiscardBuildSettings()) + skipDefaultCheckout() + timestamps() + } + stages { - stage('Checkout & build examples') { - steps { - println "Stage running on ${env.NODE_NAME}" + stage('🏗️ Build and test') { + agent { + label 'x86_64 && linux && documentation' + } - script { - def (server, user, repo) = extractFromScmUrl() - env.REPO_NAME = repo - } + stages { + stage('Checkout') { + steps { + println "Stage running on ${env.NODE_NAME}" + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo + } - dir("${REPO_NAME}") { - checkoutScmShallow() + dir(REPO_NAME){ + checkoutScmShallow() + } + } + } - dir("examples") { - withTools(params.TOOLS_VERSION) { + stage('Examples build') { + steps { + dir("${REPO_NAME}/examples") { xcoreBuild() } } } - } - } - stage('Library checks') { - steps { - warnError("Library checks failed") - { - runRepoChecks("${WORKSPACE}/${REPO_NAME}") + stage('Repo checks') { + steps { + warnError("Repo checks failed") + { + runRepoChecks("${WORKSPACE}/${REPO_NAME}") + } + } } - } - } - stage('Documentation') { - steps { - dir(REPO_NAME) { - buildDocs() + stage('Doc build') { + steps { + dir(REPO_NAME) { + buildDocs() + } + } } - } - } - - - stage('Tests') - { - steps { - withTools(params.TOOLS_VERSION) { - dir("${REPO_NAME}/tests") { - createVenv(reqFile: "requirements.txt") - xcoreBuild() - withVenv{ - runPytest("--numprocesses=auto --testlevel=${params.TEST_LEVEL}") + + stage('Tests') { + steps { + withTools(params.TOOLS_VERSION) { + dir("${REPO_NAME}/tests") { + createVenv(reqFile: "requirements.txt") + xcoreBuild() + withVenv{ + runPytest("--numprocesses=auto --testlevel=${params.TEST_LEVEL}") + } + } // dir + } // withTools + } // steps + post { + always { + archiveArtifacts artifacts: "${REPO_NAME}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true } - } // dir - } // withTools - } // steps - post - { - always{ - archiveArtifacts artifacts: "${REPO_NAME}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true + } } - } - } - stage("Archive") - { - steps - { - archiveSandbox(REPO_NAME) + stage("Archive sandbox") { + steps { + archiveSandbox(REPO_NAME) + } + } + } // stages + + post { + cleanup { + xcoreCleanSandbox() + } } - } + } // stage build and test stage('🚀 Release') { steps { @@ -109,9 +119,4 @@ pipeline { } } } // stages - post { - cleanup { - xcoreCleanSandbox() - } - } -} +} // pipeline From d41ef8fe4b283a038fe5f5523e03d8438b34c221 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 18 Aug 2025 15:27:27 +0100 Subject: [PATCH 53/57] Remove mention of AN00160 and AN00161 from readme (now in main docs) --- README.rst | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/README.rst b/README.rst index 393b24a..ad5c63d 100644 --- a/README.rst +++ b/README.rst @@ -57,8 +57,7 @@ Required libraries (dependencies) Related application notes ************************* -* AN00160 - How to communicate as SPI master -* AN00161 - How to communicate as SPI slave +Please see `examples` section of user guide for SPI slave and SPI master examples. ******* From 9dd2d725b81be2731db72b31822eb449e67e5f74 Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Tue, 19 Aug 2025 17:51:10 +0100 Subject: [PATCH 54/57] Update CD part numbers in settings.yml --- settings.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/settings.yml b/settings.yml index 110d6f4..e9f5f3c 100644 --- a/settings.yml +++ b/settings.yml @@ -11,7 +11,7 @@ documentation: linkcheck_ignore_regex: [''] latex_toc_depth: 3 latex_secnum_depth: 3 - cognidox_part_number: XM-015352-UG + cognidox_part_number: XM-006232-UG doxygen_projects: lib_spi: doxyfile_path: doc/Doxyfile.inc @@ -24,4 +24,4 @@ documentation: pdf_filename: '{{lib_name}}_v{{version}}_readme' pdf_short: yes software: - cognidox_part_number: XM-012540-SM + cognidox_part_number: XM-007474-SM From 9771ce4e5115ef5cdce0556bc31b0e2364861e9c Mon Sep 17 00:00:00 2001 From: Ross Owen Date: Fri, 29 Aug 2025 12:07:39 +0100 Subject: [PATCH 55/57] Update Jenkins shared library version to 0.42.0 --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 5e53151..161b69c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,6 +1,6 @@ // This file relates to internal XMOS infrastructure and should be ignored by external users -@Library('xmos_jenkins_shared_library@v0.41.0') _ +@Library('xmos_jenkins_shared_library@v0.42.0') _ getApproval() From afa7aa7bc05fc3e91e9303278cace54942410460 Mon Sep 17 00:00:00 2001 From: Ed Date: Mon, 8 Sep 2025 14:34:13 +0100 Subject: [PATCH 56/57] Document updates following TB review --- doc/rst/lib_spi.rst | 58 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index 56e8240..e8e707a 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -9,9 +9,9 @@ Introduction SPI is a four-wire hardware bi-directional serial interface. This library provides a software defined, industry-standard, SPI (serial peripheral interface) component that allows you to control an SPI bus via the -xCORE GPIO ports. +``xcore`` GPIO ports. -The SPI bus can be used by multiple tasks within the xCORE device +The SPI bus can be used by multiple tasks within the ``xcore`` device and (each addressing the same or different slaves) and is compatible with other slave devices on the same bus. @@ -33,7 +33,7 @@ This component is the standard SPI master and is simplest to use. The `synchrono means that calls to this component block until the transaction has completed. The component server may be placed on the same or a different tile from the client. If placed on the same tile, the task may be `distributed` by the compiler which means it gets turned into a function -call and consequently does not consume an xCORE thread. +call and consequently does not consume an ``xcore`` thread. Multiple clients are supported and are arbitrated by the component. Multiple devices are also supported by means of individual slave select bits within a port. @@ -45,7 +45,7 @@ This component offers buffering functionality over the `synchronous` SPI master. The `asynchronous` feature means that calls to this component can be non-blocking and SPI transfers may be queued. The component server may be placed on the same or a different tile from the client. -Due to the buffering logic, the `asynchronous` version always consumes an xCORE thread. +Due to the buffering logic, the `asynchronous` version always consumes an ``xcore`` thread. Multiple clients are supported and are arbitrated by the component. Multiple devices are also supported by means of individual slave select bits within a port. @@ -53,7 +53,7 @@ supported by means of individual slave select bits within a port. SPI Slave ========= -The SPI slave component task always runs in its own xCORE thread because it needs to be +The SPI slave component task always runs in its own ``xcore`` thread because it needs to be responsive to the external master requests. It offers a single slave device with basic 8 or 32 bit transfer support. It provides callbacks for when the slave needs data to transmit or has received data, as @@ -86,7 +86,7 @@ relative to the clock. The timings are given by: * - *MAX CLOCK RATE* - This is the maximum clock rate supported by the configuration. -The setup and hold timings are inherited from the underlying xCORE +The setup and hold timings are inherited from the underlying ``xcore`` device. For details on these timing please refer to the device datasheet. When operating above 20 Mbps please also see the :ref:`MISO port timing` section. @@ -171,11 +171,11 @@ ignore any transitions on the other lines. |newpage| -********************************** -Connecting to the xCORE SPI master -********************************** +************************************** +Connecting to the ``xcore`` SPI master +************************************** -The SPI wires need to be connected to the xCORE device as shown in +The SPI wires need to be connected to the ``xcore`` device as shown in :numref:`spi_master_xcore_connect`. The signals can be connected to any one bit ports, with the exception of slave select which may be any width port. All ports must be on the same tile. @@ -185,7 +185,7 @@ port. All ports must be on the same tile. .. figure:: ../images/spi_master_connect.* :width: 40% - SPI master connection to the xCORE device + SPI master connection to the ``xcore`` device If only one data direction is required then the *MOSI* or *MISO* line need not be connected. However, **asynchronous mode is only supported @@ -214,11 +214,11 @@ optional (but the *MISO* port must be provided). |newpage| -********************************* -Connecting to the xCORE SPI slave -********************************* +************************************* +Connecting to the ``xcore`` SPI slave +************************************* -The SPI wires need to be connected to the xCORE device as shown in +The SPI wires need to be connected to the ``xcore`` device as shown in :numref:`spi_slave_xcore_connect`. The signals can be connected to any one bit ports on the device. @@ -227,7 +227,7 @@ one bit ports on the device. .. figure:: ../images/spi_slave_connect.* :width: 40% - SPI slave connection to the xCORE device + SPI slave connection to the ``xcore`` device The slave will only send and receive data when the slave select is driven high. Additionally the *MISO* line is set to high impedance @@ -325,9 +325,9 @@ Operations such as ``spi.transfer8`` will block until the operation is completed on the bus. More information on interfaces and tasks can be be found in the `XMOS Programming Guide `_. By default the -SPI synchronous master mode component does not use any xCORE threads of its +SPI synchronous master mode component does not use any ``xcore`` threads of its own. It is a *distributed* task which means it will perform its -function on the xCORE thread of the application task connected to +function on the ``xcore`` thread of the application task connected to it (provided the application task is on the same tile). Synchronous master usage state machine @@ -600,7 +600,7 @@ subsequent transfers either provide or consume data. The time taken to handle the callbacks will determine the timing requirements of the SPI slave and so should be kept as short as possible. - See application note AN00161 for more details on different ways of working with the SPI slave component. + See the SPI slave example in ``examples/app_spi_slave`` for more details on different ways of working with the SPI slave component. |newpage| @@ -613,7 +613,7 @@ Synchronous SPI master clock speeds =================================== The maximum speed that the SPI bus can be driven depends on whether a -clock block is used, the speed of the xCORE thread that the SPI code +clock block is used, the speed of the ``xcore`` thread that the SPI code is running on and where both the *MISO* and *MOSI* lines are used. The timings can be seen in :numref:`spi_master_sync_timings`. @@ -677,8 +677,8 @@ MISO port timing Port timing is affected by chip pad and PCB delays. For the clock, slave-select and MOSI signals, all of the delays will be broadly matched. This means port timing adjustment is normally not required even up to the fastest supported SPI clock rates. -For the MISO signal, there will be a 'round trip delay' starting with the clock edge output and finishing at the xCORE's input port. -The presence of this delay will mean the xCORE may sample too early since data signal will arrive later. +For the MISO signal, there will be a 'round trip delay' starting with the clock edge output and finishing at the ``xcore``'s input port. +The presence of this delay will mean the ``xcore`` may sample too early since data signal will arrive later. It may be necessary to delay the sampling of the MISO pin to capture within the required window, particularly if the SPI clock is above 20 MHz. Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the :ref:`API section` `spi_master_sync_timings()` method which exposes the controls available for optimising setup and hold capture. @@ -691,11 +691,11 @@ For details on how to calculate and adjust round-trip port timing, please consul SPI slave timing characteristics ******************************** -The xCORE thread running the SPI slave task will wait for the slave +The ``xcore`` thread running the SPI slave task will wait for the slave select line to assert and then begin processing the transaction. At this point it will call the ``master_requires_data`` callback to application code. The time taken for the application to perform this -call will affect how long the xCORE thread has to resume processing +call will affect how long the ``xcore`` thread has to resume processing SPI data. This will affect the minimum allowable time between slave select changing and data transfer from the master (*t1*). @@ -708,7 +708,7 @@ gap between transactions (*t2*). The user of the library will also need to determine this time based on their application. If the SPI slave task is combined will other tasks running on the same -xCORE thread then the other task may process an event delaying the +``xcore`` thread then the other task may process an event delaying the time it takes for the SPI slave task to react to events. This will add these delays to the minimum times for both *t1* and *t2*. The library user will need to take these into account in determining the timing @@ -806,7 +806,7 @@ application only uses a single hardware thread. Declaring ports ............... -The SPI library connects to external pins via xCORE ports. In +The SPI library connects to external pins via ``xcore`` ports. In ``main.xc`` these are declared as variables of type ``port`` at the start of the file: @@ -1019,7 +1019,7 @@ the task and communication structure of the application. Declaring ports ............... -The SPI library connects to external pins via xCORE ports. In +The SPI library connects to external pins via ``xcore`` ports. In ``main.xc`` these are declared as variables of type ``port`` at the start of the file: @@ -1030,7 +1030,7 @@ start of the file: .. note:: - There is also a clock declaration since the slave needs to use an internal clock as well as ports inside the xCORE device. + There is also a clock declaration since the slave needs to use an internal clock as well as ports inside the ``xcore`` device. How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will depend on the exact device being used. See the device datasheet for details. @@ -1191,7 +1191,7 @@ out its value: The ``debug_printf`` function comes from the ``debug_print.h`` header supplied by ``lib_logging``. It is a low memory debug printing function that will print out messages to the - console in the xTIMEcomposer (either using JTAG or xSCOPE to + console (either using JTAG or xSCOPE to communicate to the host via the debug adaptor). The tester() task From d737ab6018d76abdbcf9eab9766e26cc0b41811d Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 10 Sep 2025 09:32:46 +0100 Subject: [PATCH 57/57] Patch UML issue --- doc/rst/lib_spi.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst index e8e707a..f0dc94f 100644 --- a/doc/rst/lib_spi.rst +++ b/doc/rst/lib_spi.rst @@ -1005,10 +1005,10 @@ the task and communication structure of the application. circle app circle reg_file circle SPI_slave - + ' Force layout order with hidden links - SPI_master -[#transparent]-> SPI_slave - + SPI_master -[hidden]-> SPI_slave + ' Actual displayed nodes tester -r-> SPI_master : spi_master_if SPI_slave -r-> reg_file : spi_slave_callback_if